Calculation method, device, chip, electronic device, and storage medium

Abstract

To provide an operation method, a device, a chip, electronic equipment, and a storage medium that actualize an insensitive operation to convert floating-point data into fixed-point data, and save labor costs and computing resources.SOLUTION: A method comprises: acquiring a plurality of first fixed points and a plurality of first indexes, and a plurality of second fixed points and a plurality of second indexes based upon a plurality of first floating points of a first vector and a plurality of second floating points of a second vector input to an operation unit; acquiring values of fixed point products of respective first fixed points among the plurality of first fixed points and second fixed points corresponding thereto and corresponding indexes of the fixed point products; acquiring an internal product calculation result of the fixed points of the first vector and second vector based upon the indexes of the fixed point products; and acquiring an internal product calculation result of a floating point of a floating point data format based upon the internal product calculation result of the fixed points.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to the field of computer technology, in particular to the field of chip technology and artificial intelligence, and in particular to a computing method, an apparatus, a chip, an electronic device, a computer-readable storage medium and a computer program product. [Background technology]

[0002] With the development of artificial intelligence technology, more and more applications have achieved much better results than traditional algorithms based on artificial intelligence technology. Deep learning is the core technology of current artificial intelligence technology. Deep learning is a data-intensive and computation-intensive algorithm, and is also an algorithm that is undergoing rapid iterative development.

[0003] Traditional general-purpose processing devices such as CPU, GPU, DSP, etc. are designed for general-purpose computing tasks, and have shortcomings such as low computing performance and low efficiency when processing deep learning applications, so they cannot effectively support large-scale deployment of deep learning algorithms in scenarios such as data centers. ASIC / FPGA-based dedicated deep learning acceleration devices deeply customize the hardware structure for the computing characteristics of deep learning, and can achieve higher computing performance and computing efficiency than traditional devices such as CPU, GPU, DSP, etc.

[0004] The approaches described in this section are not necessarily approaches that have been previously contemplated or adopted. Unless otherwise noted, any approach described in this section should not be considered prior art by its inclusion in this section alone. Similarly, unless otherwise noted, any problem addressed in this section should not be considered an admission of prior art. Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure provides a computing method, an apparatus, a chip, an electronic device, a computer readable storage medium and a computer program product. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, there is provided a calculation method executed by a calculation device, the method including: obtaining, based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers of a second vector input to the calculation device, a plurality of first fixed-point numbers and a plurality of first exponents expressed in binary corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents expressed in binary corresponding to the plurality of second floating-point numbers, wherein the plurality of first floating-point numbers correspond one-to-one to the plurality of second floating-point numbers, and each fixed-point number among the plurality of first fixed-point numbers and the plurality of second fixed-point numbers has a sign bit and a first exponent; obtaining a fixed-point product value and a corresponding fixed-point product exponent between each first fixed-point number among the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number; obtaining a fixed-point dot product calculation result between the first vector and the second vector based on a fixed-point product exponent corresponding to each fixed-point product value among the plurality of fixed-point product values ​​corresponding respectively to the plurality of first fixed-point numbers; and obtaining a floating-point dot product calculation result in a floating-point data format corresponding to the fixed-point dot product calculation result based on the fixed-point dot product calculation result.

[0007] According to one aspect of the present disclosure, there is provided a computation method executed by a computing device, the method including: obtaining a first matrix and a second matrix, where the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the vector lengths of the row vectors and the column vectors are the same; and by the above computation method executed by the computing device for calculating a vector inner product, respectively obtaining inner product results of each row vector in the first matrix and each column vector in the second matrix, and obtaining an inner product result matrix of the first matrix and the second matrix.

[0008] According to another aspect of the present disclosure, there is provided a computing device, the computing device being configured to obtain, based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers of a second vector input to the computing device, a plurality of first fixed-point numbers and a plurality of first exponents expressed in binary corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents expressed in binary corresponding to the plurality of second floating-point numbers, where the plurality of first floating-point numbers correspond one-to-one to the plurality of second floating-point numbers, and each fixed-point number among the plurality of first fixed-point numbers and the plurality of second fixed-point numbers includes a sign bit and a first predetermined number of fixed-point numeric bits. the multiplier configured to obtain a fixed-point product value between each first fixed-point number among the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number and a corresponding fixed-point product exponent; a second acquisition unit configured to obtain a fixed-point dot product calculation result between a first vector and a second vector based on a fixed-point product exponent corresponding to each fixed-point product value among the plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers respectively; and a third acquisition unit configured to obtain a floating-point dot product calculation result in a floating-point data format corresponding to the fixed-point dot product calculation result based on the fixed-point dot product calculation result.

[0009] According to another aspect of the present disclosure, there is provided a computing device, the computing device including: a fourth acquisition unit configured to acquire a first matrix and a second matrix, where the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the vector lengths of the row vectors and the column vectors are the same; and a fifth acquisition unit configured to acquire, by the above-mentioned computing method executed in the computing device for calculating vector dot products, dot product results of each row vector in the first matrix and each column vector in the second matrix, respectively, and acquire an dot product result matrix of the first matrix and the second matrix.

[0010] According to another aspect of the present disclosure, a chip is provided, the chip including at least one of the above arithmetic unit for computing vector dot products and the above arithmetic unit for computing matrix dot products.

[0011] According to another aspect of the present disclosure, there is provided an electronic device, the electronic device including the above chip.

[0012] According to another aspect of the present disclosure, there is provided an electronic device including at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the computational method of calculating a vector dot product described above or the computational method of calculating a matrix dot product described above.

[0013] According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium having stored thereon computer instructions for causing a computer to execute the above-described method of calculating a vector dot product or the above-described method of calculating a matrix dot product.

[0014] According to another aspect of the present disclosure, there is provided a computer program product including a computer program which, when executed by a processor, realizes the above-described method for calculating a vector dot product or the above-described method for calculating a matrix dot product. Effect of the Invention

[0015] According to one or more embodiments of the present disclosure, floating-point data input into the computing device can be converted into fixed-point data through internal computation of the computing device, and related computations can be completed based on the fixed-point data, thereby realizing the insensitivity operation of converting floating-point data into fixed-point data, thereby saving labor costs and computing resources.

[0016] It should be understood that the contents described in this section are not intended to identify key or important features of the embodiments of the present disclosure, and are not intended to limit the scope of protection of the present disclosure. Other features of the present disclosure will be readily understood from the following description. [Brief description of the drawings]

[0017] The drawings illustratively illustrate the examples, constitute a part of the specification, and together with the written description of the specification, serve to explain exemplary embodiments of the examples. The illustrated examples are for illustrative purposes only and are not intended to limit the scope of the claims. In all the drawings, the same reference numerals refer to similar, but not necessarily identical, elements. [Figure 1] 4 is a flowchart illustrating a computing method performed by a computing device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a block diagram of a vector multiplication device according to an embodiment of the present disclosure. [Diagram 3] 13 is a flowchart of obtaining a plurality of first fixed-point numbers and a plurality of first exponents and a plurality of second fixed-point numbers and a plurality of second exponents according to an embodiment of the present disclosure. [Figure 4] 1 is a flowchart of obtaining fixed-point product values ​​corresponding to a plurality of first fixed-point numbers and corresponding fixed-point product exponents according to an embodiment of the present disclosure. [Diagram 5] FIG. 11 is a block diagram illustrating a vector multiplication device according to another embodiment of the present disclosure. [Figure 6] 1 illustrates a flowchart of a computation method performed by a computation device for computing matrix multiplication according to an embodiment of the present disclosure. [Figure 7] FIG. 1 is a configuration block diagram of a matrix multiplication device according to an embodiment of the present disclosure. [Figure 8] FIG. 1 shows a block diagram of a calculation device for calculating a vector inner product according to an embodiment of the present disclosure. [Figure 9] FIG. 2 shows a block diagram of a calculation device used for calculating matrix multiplication according to an embodiment of the present disclosure. [Figure 10]FIG. 1 illustrates a structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, exemplary embodiments of the present disclosure will be described in conjunction with the drawings. In order to facilitate understanding, various details of the embodiments of the present disclosure are included therein, but they should be considered as merely exemplary. Therefore, as can be recognized by those skilled in the art, various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for clarity and conciseness, the following description omits descriptions of known functions and structures.

[0019] In this application, unless otherwise specified, the terms "first," "second," and the like, used to describe various elements are not intended to limit the location, timing, or importance of these elements. Such terms are used only to distinguish one element from another. In some instances, a first element and a second element may refer to the same instance of an element, or in some cases, may refer to different instances based on the contextual description.

[0020] The terms used in the description of various examples of the present disclosure are intended only to describe particular examples and are not intended to be limiting. Unless otherwise clearly indicated by the context, an element may be one or more, unless specifically limited in number. It should be noted that the term "and / or" as used in the present disclosure covers any and all possible combinations of the listed items.

[0021] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0022] The core operation of deep learning algorithms is the matrix multiplication operation. The mainstream language models (e.g., BERT, ERNIE, etc.) all contain a large number of matrix multiplications, and the mainstream machine vision models (e.g., RESNET, MASK-RCNN, YOLO, SSD, etc. networks) contain a large number of convolution operations, but the convolution operations are usually realized by transforming them into matrix operations.

[0023] Deep learning networks all perform matrix multiplication operations based on data in single-precision floating-point format (i.e., float format). With the development of deep learning, those skilled in the art have discovered that for matrix multiplication operations and convolution operations, fixed-point precision, for example, signed 16-bit fixed-point data, can be used to significantly reduce the area and power consumption realized by the hardware, obtain better performance / power consumption ratio and performance / area ratio, and ensure no obvious loss in precision.

[0024] In the related art, the matrix multiplication operation in the deep learning network can be completed by a matrix multiplication device in the deep learning chip. The matrix multiplication device supports fixed-point operation, but those skilled in the art need to use an independent device to convert the floating-point precision data into fixed-point data through fixed-point conversion, and then input the fixed-point data into the matrix multiplication device for operation.

[0025] An embodiment of the present disclosure provides a computing method executed by a computing device, which converts floating-point data input to the computing device into fixed-point data through internal computation of the computing device, and then performs vector multiplication or matrix multiplication computation based on the fixed-point data to realize an insensitivity operation of converting floating-point data into fixed-point data, thereby saving labor costs and computing resources.

[0026] According to an embodiment of the present disclosure, as shown in FIG. 1, there is provided a computing method executed by a computing device, the computing method including: obtaining, based on a plurality of first floating-point numbers of a first vector and a plurality of second floating-point numbers of a second vector input to the computing device, a plurality of first fixed-point numbers and a plurality of first exponents expressed in binary corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents expressed in binary corresponding to the plurality of second floating-point numbers, wherein the plurality of first floating-point numbers correspond one-to-one to the plurality of second floating-point numbers, and each fixed-point number among the plurality of first fixed-point numbers and the plurality of second fixed-point numbers has a sign bit and a first predetermined number of fixed-point bits. The method may include a step S101 of acquiring a fixed-point product value of each first fixed-point number among the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number and a corresponding fixed-point product exponent, a step S103 of acquiring a fixed-point dot product calculation result between a first vector and a second vector based on a fixed-point product exponent corresponding to each fixed-point product value among a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers respectively, and a step S104 of acquiring a floating-point dot product calculation result in a floating-point data format corresponding to the fixed-point dot product calculation result based on the fixed-point dot product calculation result.

[0027] In this way, the floating-point data input to the arithmetic device is converted into fixed-point data through internal calculations of the arithmetic device, and related calculations are completed based on the fixed-point data, thereby realizing the insensitivity operation of converting floating-point data into fixed-point data, and saving labor costs and computing resources.

[0028] FIG. 2 is a block diagram of a vector multiplication device according to an embodiment of the present disclosure.

[0029] 2 may be a single arithmetic unit disposed on a chip, and the above arithmetic method may be realized by the vector multiplication unit 200. Specifically, the vector multiplication unit 200 includes a data extraction module 210, a fixed-point multiplication module 220, an exponent comparison module 230, a shift module 240, an adder 250, and an inverse fixed-point conversion module 260.

[0030] According to the IEEE 754 standard, one single-precision floating-point data is represented as {S,E,M}, where S is a 1-bit sign bit, E is an 8-bit exponent bit, and M is a 23-bit floating-point value bit. The actual value of this floating-point data can be calculated by the following formula: N=(-1) S x1.M x2 (E-127)

[0031] In some embodiments, first, a first vector A{a[0], a[1], ..., a[k-1]} and a second vector B{b[0], b[1], ..., b[k-1]} are input in parallel to a data extraction module 210 in the vector multiplication device 200, where k is a positive integer greater than 2. Each first floating-point number a[i] in the first vector A and each second floating-point number b[i] in the second vector B are single-precision floating-point data (where i ∈ [0, k-1]), and the storage format thereof is as described above.

[0032] In some embodiments, the data extraction module 210 may first process each first floating-point number a[k-1] and each second floating-point number b[k-1] and convert them into a first fixed-point number and a second fixed-point number, respectively.

[0033] In some embodiments, as shown in FIG. 3 , obtaining a plurality of first fixed-point numbers and a plurality of first exponents expressed in binary corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents expressed in binary corresponding to the plurality of second floating-point numbers, includes extracting, for each floating-point number among the plurality of first floating-point numbers and the plurality of second floating-point numbers, a sign bit, an exponent bit, and a floating-point value bit of the floating-point number. wherein the floating-point number is represented by a binary number in step S301; a second predetermined number of most significant numerical bits are extracted from the floating-point number in step S302; a fixed-point number corresponding to the floating-point number is determined based on the most significant numerical bits and a sign bit of the floating-point number in step S303; and an exponent corresponding to the floating-point number is determined based on the exponent bits of the floating-point number in step S304.

[0034] This allows input floating-point numbers to be converted to fixed-point numbers using only the arithmetic device of the present disclosure, thereby making the conversion of floating-point data to fixed-point data insensitive, improving the user experience, and saving computational resources as no additional resources are required for fixed-point processing of the data.

[0035] First, the data extraction module 210 extracts in parallel the sign bit, the exponent bit and the floating-point value bit of each first floating-point number a[i] and each second floating-point number b[i], respectively, where the sign bit is denoted as a[i]

[31] and b[i]

[31] , the exponent bits are denoted as a[i][30:23] and b[i][30:23], respectively, and the floating-point value bits are denoted as a[i][22:0] and b[i][22:0], respectively.

[0036] Then, for each of the floating-point value bits therein, a second predetermined number of most significant bits are extracted.

[0037] In some embodiments, the first fixed-point number and the second fixed-point number to be converted may be 16-bit fixed-point data, and the second predetermined number may be 14-bit accordingly, i.e., the most significant 14-bit data is extracted for a[i][22:0] and b[i][22:0], respectively, and the resulting most significant numeric bits are a[i][22:9] and b[i][22:9], respectively.

[0038] In some embodiments, a fixed-point number corresponding to each floating-point number can be obtained by using the most significant bits and the sign bit according to the following formula:

[0039]

number

[0040] Here, a.us[i] and b.us[i] represent the first fixed-point number and the second fixed-point number corresponding to the first floating-point number a[i] and the second fixed-point number b[i], respectively, and among them, 1'b0 in the 2-bit data added before a[i][22:9] and b[i][22:9] is the sign bit, and 1'b1 is used to fill in the integer before the omitted decimal point when the floating-point data is stored.

[0041] The first exponent ae[i] and the second exponent be[i] corresponding to the first fixed-point number a.us[i] and the second fixed-point number b.us[i], respectively, can be obtained based on the following formula:

[0042]

number

[0043] In some embodiments, as shown in FIG. 4 , obtaining a fixed-point product value between each first fixed-point number among the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number and a corresponding exponent of the fixed-point product includes: a step S401 of obtaining a plurality of first complements corresponding to the plurality of first fixed-point numbers and a plurality of second complements corresponding to the plurality of second fixed-point numbers; a step S402 of calculating a product of each first complement among the plurality of first complements and a second complement corresponding to the first complement to obtain a fixed-point product value; and a step S403 of calculating a sum of a first exponent corresponding to each first fixed-point number among the plurality of first fixed-point numbers and a second exponent corresponding to the second fixed-point number corresponding to the first fixed-point number to obtain an exponent of the fixed-point product.

[0044] This allows the sign bit to also participate in the operation by converting the fixed-point number to its complement and performing subsequent operations, eliminating the need to perform calculations on the sign bit alone and saving computational resources.

[0045] In some embodiments, based on the sign bits a[i]

[31] and b[i]

[31] corresponding to the first floating-point number a[i] and the second floating-point number b[i], respectively, the first complement as[i] and the second complement bs[i] corresponding to the first fixed-point number a.us[i] and the second fixed-point number b.us[i], respectively, can be obtained by the following formula:

[0046]

number

[0047] In this way, for each first floating-point number a[i] in the first vector A and each second floating-point number b[i] in the second vector B, the data extraction module 210 correspondingly obtains each first fixed-point number a.us[i] and its complement as[i] and each second fixed-point number b.us[i] and its complement bs[i], which are transmitted by the data extraction module 210 to the fixed-point multiplication module 220. At the same time, the data extraction module can transmit each first exponent ae[i] and each second exponent be[i] to the exponent comparison module 230.

[0048] In some embodiments, the fixed-point multiplication module 220 may include a fixed-point multiplication sub-module of k sets of 16-bit fixed-point data, and the input data of the fixed-point multiplication module 220 may be each first fixed-point number a.us[i] and each second fixed-point number b.us[i], and the corresponding first fixed-point number and second fixed-point number are multiplied to obtain a corresponding fixed-point product value, and the sign of the fixed-point product value needs to be determined by the sign bit of the first floating-point number and the second floating-point number corresponding to the first fixed-point number and the second fixed-point number.

[0049] In some embodiments, the fixed-point multiplication module 220 may include a fixed-point multiplication sub-module of k sets of 16-bit fixed-point data, and the input data of the fixed-point multiplication module 220 may be a first complement as[i] corresponding to each first fixed-point number and a second complement bs[i] corresponding to each second fixed-point number, and obtain a fixed-point product value m[i] by respectively multiplying the corresponding first complement as[i] and second complement bs[i] for each pair, and the specific formula is as follows:

[0050]

number

[0051] Here, the number of bits of each fixed-point product value m[i] is 32 bits.

[0052] At the same time, the exponent comparison module 230 may accordingly obtain the fixed-point product exponent ab.e[i] corresponding to each fixed-point product value m[i], and the specific formula is as follows:

[0053]

number

[0054] Since the exponents corresponding to each fixed-point product value are different, before adding each fixed-point product value, it is necessary to unify each fixed-point product value into the same numerical range. For example, if the numerical bits of two fixed-point products are both 1001, but the numerical values ​​corresponding to their exponents are 2 and -2, respectively, their actual values ​​are 100.1 and 0.01001, respectively (that is, by shifting and aligning the values ​​of these two fixed-point products with the exponent 0 as the base, these two fixed-point products are unified into the same numerical range), and then the result obtained by performing the addition calculation is the correct one.

[0055] In the related art, generally, before inputting data, the maximum value in each vector is first obtained, and then the numerical range of each data in the vector is unified according to the maximum value, which leads to a large loss of precision again after the data is converted to fixed-point data.

[0056] In some embodiments, obtaining a fixed-point dot product calculation result between the first vector and the second vector based on a fixed-point product exponent corresponding to each fixed-point product value among the multiple fixed-point product values ​​corresponding to the multiple first fixed-point numbers, respectively, includes: arithmetically shifting the fixed-point product value based on a fixed-point product exponent corresponding to each fixed-point product value among the multiple fixed-point product values ​​corresponding to the multiple first fixed-point numbers, respectively; and summing the multiple arithmetically shifted fixed-point product values ​​corresponding to the multiple first fixed-point numbers, thereby obtaining a fixed-point dot product calculation result between the first vector and the second vector.

[0057] In this way, after obtaining the value of each fixed-point product, and before calculating the fixed-point inner product calculation result, the value of each fixed-point product is shifted, thereby unifying the numerical range of each fixed-point product value, thereby reducing the loss of data precision and improving the accuracy of calculation compared to the method in the related art.

[0058] In some embodiments, the value of each fixed-point product and the exponent of each fixed-point product are input correspondingly to the shift module 240, so that the value of each fixed-point product is arithmetically shifted according to the exponent of the corresponding fixed-point product, and the value of each fixed-point product can be aligned to the same numerical range, and then the aligned fixed-point product value is input to the adder 250, thereby obtaining the fixed-point dot product calculation result of the first vector and the second vector.

[0059] In some embodiments, arithmetically shifting the fixed-point product value based on a fixed-point product exponent corresponding to each fixed-point product value among a plurality of fixed-point product values ​​corresponding to a plurality of first fixed-point numbers respectively includes: determining a first fixed-point product exponent among a plurality of fixed-point product exponents corresponding to the plurality of first fixed-point numbers; obtaining an arithmetic shift value corresponding to each fixed-point product value among the plurality of fixed-point product values ​​based on each fixed-point product exponent among the plurality of fixed-point product exponents and the first fixed-point product exponent; and arithmetically shifting the fixed-point product value based on the arithmetic shift value corresponding to each fixed-point product value among the plurality of fixed-point product values.

[0060] In some embodiments, the exponent of a first fixed-point product among all the exponents of the fixed-point products is determined as a reference for arithmetic shifting, and the shift distance corresponding to each fixed-point product value can be determined by calculating the difference between the exponents of the other fixed-point products and the exponent of the first fixed-point product, which can further simplify the calculation, improve the calculation efficiency, and save the calculation resources.

[0061] In some embodiments, determining a first fixed-point product exponent among the multiple fixed-point product exponents corresponding to the multiple first fixed-point numbers includes obtaining a fixed-point product exponent having a maximum numerical value among the multiple fixed-point product exponents corresponding to the multiple first fixed-point numbers as the first fixed-point product exponent, and obtaining an arithmetic shift value corresponding to each fixed-point product value among the multiple fixed-point product values ​​based on the exponent of each fixed-point product among the multiple fixed-point product exponents and the exponent of the first fixed-point product includes calculating a difference between the exponent of the first fixed-point product and the exponent of each fixed-point product among the multiple fixed-point product exponents as an arithmetic shift value corresponding to the fixed-point product value corresponding to the exponent of the fixed-point product.

[0062] Therefore, by determining the base exponent, which is the exponent of the first fixed-point product, as the maximum exponent among all exponents, it is possible to prevent data with large actual values ​​from losing a lot of precision and ensure the accuracy of the calculation.

[0063] In some embodiments, first, the exponent comparison module 230 can obtain the maximum exponent in all the fixed-point product exponents ab.e[i] as the first fixed-point product exponent ab.e.max, and the specific formula is as follows:

[0064]

number

[0065] Then, obtain each arithmetic shift value sft[i] by calculating the difference between the exponent ab.e.max of the first fixed-point product and the exponent ab.e[i] of each fixed-point product, and the specific formula is as follows:

[0066]

number

[0067] Each arithmetic shift value sft[i] output by the exponent comparison module 230 and each fixed-point multiplication value m[i] output by the fixed-point multiplication module 220 are input to the shift module 240, and the shift module 240 performs an arithmetic right shift process on each fixed-point multiplication value m[i] according to the corresponding arithmetic shift value sft[i] to obtain a corresponding arithmetic shifted fixed-point product value ms[i], the specific formula is as follows:

[0068]

number

[0069] In some embodiments, each arithmetically shifted fixed-point product value ms[i] output by the shift module 240 is input to the adder 250, and the adder 250 sums up the arithmetically shifted fixed-point product values ​​to obtain the fixed-point inner product calculation result si of the first vector A and the second vector B, and the specific formula is as follows:

[0070]

number

[0071] Here, the fixed-point inner product calculation result si is signed fixed-point data having a bit number of (32+j) bits, where j is determined by the following formula.

[0072]

number

[0073] Here, ceiling(x) is a function for rounding up the data. Therefore, by setting more bits for the fixed-point dot product calculation result si, data overflow during the summation process can be prevented.

[0074] In some embodiments, based on the fixed-point dot product calculation result, obtaining a floating-point dot product calculation result in a floating-point data format corresponding to the fixed-point dot product calculation result can be processed by the inverse fixed-point module 260.

[0075] The adder 250 transmits the fixed-point inner product calculation result si to the inverse fixed-point conversion module 260, which first converts the fixed-point inner product calculation result si into equivalent floating-point format data sf.

[0076] At the same time, the exponent comparison module 230 transmits the exponent ab.e.max of the first fixed-point product to the inverse fixed-point conversion module 260, and the inverse fixed-point conversion module 260 converts the exponent ab.e.max of the first fixed-point product into exponent data df in floating-point format, and the specific formula is as follows:

[0077]

number

[0078] Then, the floating-point multiplier in the inverse fixed-point module 260 calculates the product of sf and df to obtain the floating-point inner product calculation result res of the floating-point data format of the first vector and the second vector, and the specific formula is as follows:

[0079]

number

[0080] In some embodiments, the computing device can calculate the dot product of two vectors of a first predetermined length in one computing cycle, and for a third vector and a fourth vector whose lengths are the same and both are greater than the first predetermined length, the method further includes: dividing the third vector and the fourth vector into a plurality of first vectors and a plurality of second vectors respectively based on the first predetermined length, where the plurality of first vectors correspond one-to-one to the plurality of second vectors; respectively calculating floating-point dot product calculation results of the plurality of sets of corresponding first vectors and second vectors; and calculating a sum of the floating-point dot product calculation results of the plurality of sets of corresponding first vectors and second vectors, thereby obtaining the dot product calculation result of the third vector and the fourth vector.

[0081] Therefore, by dividing the input vector, inputting each of the divided vectors to the calculation device in different calculation cycles, and then accumulating the results obtained in each calculation cycle, it is possible to realize a larger-scale inner product calculation of vectors.

[0082] FIG. 5 is a block diagram showing a vector multiplication device according to another embodiment of the present disclosure.

[0083] 5 may be a single arithmetic unit disposed on a chip, and the above arithmetic method can be realized by the vector multiplication unit 500. Specifically, the vector multiplication unit 500 includes a data extraction module 510, a fixed-point multiplication module 520, an exponent comparison module 530, a shift module 540, an adder 550, a fixed-point inverse module 560, and an accumulating module 570.

[0084] Here, the operations for modules 510 to 560 in vector multiplication device 500 are similar to the operations for modules 210 to 260 in vector multiplication device 200 described above, and therefore detailed description thereof will be omitted here.

[0085] In some embodiments, the data extraction module 510 sequentially extracts a first vector and a second vector of a first predetermined length for the third vector and the fourth vector input to the vector multiplication device 500 during each calculation cycle, and obtains a floating-point dot product calculation result of the first vector and the second vector during the calculation cycle, and stores the result in the accumulating module 570. After obtaining each floating-point dot product calculation result, the accumulating module 570 can calculate a sum of all the floating-point dot product calculation results to obtain the floating-point format dot product calculation result of the third vector and the fourth vector.

[0086] In some embodiments, a calculation method performed by a calculation device for calculating matrix multiplication is provided, which includes, as shown in FIG. 6 , step S601 of obtaining a first matrix and a second matrix, where the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the vector lengths of the row vectors and the column vectors are the same; and step S602 of respectively obtaining dot product results of each row vector in the first matrix and each column vector in the second matrix through the above-mentioned calculation method for calculating vector dot products, thereby obtaining a dot product result matrix of the first matrix and the second matrix.

[0087] FIG. 7 is a configuration block diagram of a matrix multiplication device according to an embodiment of the present disclosure.

[0088] In some embodiments, the vector multiplication unit as shown in FIG. 7 may be a single arithmetic unit located on a chip, and the above arithmetic method for calculating matrix multiplication may be implemented by the vector multiplication unit.

[0089] Here, the first matrix includes m row vectors A(0), A(1), ..., A(m-1), and the second matrix includes n column vectors B(0), B(1), ..., B(n-1). The matrix multiplication device as shown in Fig. 7 includes m x n vector multiplication devices, each of which may be the vector multiplication device 200 of Fig. 2 or the vector multiplication device 500 as shown in Fig. 5, and each vector multiplication device calculates the vector inner product of the row vector A and the column vector B according to the above-mentioned calculation method of calculating the vector inner product, and further obtains the calculation result of each vector multiplication device to obtain the inner product result matrix of the first matrix and the second matrix.

[0090] In some embodiments, as shown in FIG. 8, a calculation device 800 is provided, the device including a first acquisition unit configured to acquire, based on a first vector of a plurality of first floating-point numbers and a second vector of a plurality of second floating-point numbers input to the calculation device, a first fixed-point number and a first exponent expressed in binary corresponding to the first floating-point numbers, and a second fixed-point number and a second exponent expressed in binary corresponding to the second floating-point numbers, where the first floating-point numbers have a one-to-one correspondence with the second floating-point numbers, and each fixed-point number among the first fixed-point number and the second fixed-point number includes a sign bit and a first predetermined number of fixed-point numeric bits. The input / output circuit may include a multiplier 820 configured to obtain a fixed-point product value between each first fixed-point number among the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number and a corresponding fixed-point product exponent; a second obtaining unit 830 configured to obtain a fixed-point dot product calculation result between a first vector and a second vector based on a fixed-point product exponent corresponding to each fixed-point product value among the plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers respectively; and a third obtaining unit 840 configured to obtain a floating-point dot product calculation result in a floating-point data format corresponding to the fixed-point dot product calculation result based on the fixed-point dot product calculation result.

[0091] Here, the operations performed on units 810 to 840 in the arithmetic device 800 are similar to the operations in steps S101 to S104 in the arithmetic method executed by the arithmetic device described above, and detailed description thereof will be omitted here.

[0092] In some embodiments, the second obtaining unit may include: a shifter configured to arithmetically shift a fixed-point product value based on a fixed-point product exponent corresponding to each fixed-point product value among a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, respectively; and an adder configured to sum the plurality of arithmetically shifted fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, thereby obtaining a fixed-point dot product calculation result of the first vector and the second vector.

[0093] In some embodiments, the shifter may include a determining module configured to determine a first fixed-point product exponent among a plurality of fixed-point product exponents corresponding to a plurality of first fixed-point numbers; an obtaining module configured to obtain an arithmetic shift value corresponding to each fixed-point product value among the plurality of fixed-point product values ​​based on each fixed-point product exponent among the plurality of fixed-point product exponents and the first fixed-point product exponent; and a shift module configured to arithmetically shift the fixed-point product value based on the arithmetic shift value corresponding to each fixed-point product value among the plurality of fixed-point product values.

[0094] In some embodiments, the determination module can be configured to obtain an exponent of a fixed-point product having a maximum numerical value among a plurality of fixed-point product exponents corresponding to a plurality of first fixed-point numbers as an exponent of a first fixed-point product, and in this case, the obtaining module can be configured to calculate a difference between the exponent of the first fixed-point product and an exponent of each fixed-point product among the plurality of fixed-point product exponents as an arithmetic shift value corresponding to the value of the fixed-point product corresponding to the exponent of the fixed-point product.

[0095] In some embodiments, the first obtaining unit may be configured to perform an operation for each floating-point number among the plurality of first floating-point numbers and the plurality of second floating-point numbers, extracting a sign bit, an exponent bit and a floating-point value bit in the floating-point number, where the floating-point number is configured to be expressed by a binary number, a second extraction subunit configured to extract a second predetermined number of most significant numerical bits among the floating-point value bits, a first determination subunit configured to determine a fixed-point number corresponding to the floating-point number based on the significant numerical bits, and a second determination subunit configured to determine an exponent corresponding to the floating-point number based on the exponent bits of the floating-point number.

[0096] According to some embodiments, the multiplier may include an obtaining subunit configured to obtain a plurality of first complements corresponding to the plurality of first fixed-point numbers and a plurality of second complements corresponding to the plurality of second fixed-point numbers based on a sign bit of a plurality of first floating-point numbers corresponding to the plurality of first fixed-point numbers, respectively, and a sign bit of a plurality of second floating-point numbers corresponding to the plurality of second fixed-point numbers, respectively; a first calculation subunit configured to calculate a product of each first complement of the plurality of first complements and a second complement corresponding to the first complement, thereby obtaining a fixed-point product value; and a second calculation subunit configured to calculate a sum of a first exponent corresponding to each first fixed-point number of the plurality of first fixed-point numbers and a second exponent corresponding to the second fixed-point number corresponding to the first fixed-point number, thereby obtaining an exponent of the fixed-point product.

[0097] In some embodiments, the above-mentioned arithmetic device can calculate the dot product of two vectors of a first predetermined length in one calculation cycle, and for a third vector and a fourth vector whose lengths are the same and both are greater than the first predetermined length, the above-mentioned arithmetic device can further include: a division unit configured to divide the third vector and the fourth vector into a plurality of first vectors and a plurality of second vectors respectively based on the first predetermined length, where the plurality of first vectors correspond one-to-one to the plurality of second vectors; a first calculation unit configured to respectively calculate floating-point dot product calculation results of the plurality of sets of corresponding first vectors and second vectors; and a second calculation unit configured to calculate a sum of the floating-point dot product calculation results of the plurality of sets of corresponding first vectors and second vectors to obtain the dot product calculation result of the third vector and the fourth vector.

[0098] In some embodiments, as shown in FIG. 9 , a calculation device 900 is further provided, which includes: a fourth obtaining unit 910 configured to obtain a first matrix and a second matrix, where the first matrix includes a first number of row vectors, the second matrix includes a second number of column vectors, and the vector lengths of the row vectors and the column vectors are the same; and a fifth obtaining unit 920 configured to obtain, by the above-mentioned calculation method executed in the calculation device for calculating vector dot products, respectively, dot product results of each row vector in the first matrix and each column vector in the second matrix, and obtain an dot product result matrix of the first matrix and the second matrix.

[0099] Here, the operations for units 910 to 920 in the arithmetic device 900 are similar to the operations in steps S601 to S602 in the arithmetic method executed by the arithmetic device for calculating the matrix multiplication described above, and detailed description thereof will be omitted here.

[0100] In some embodiments, a chip is provided, the chip including at least one of the above arithmetic units for computing vector dot products and the above arithmetic units for computing matrix dot products.

[0101] In some embodiments, an electronic device is provided, the electronic device including the chip described above.

[0102] In some embodiments, an electronic device is provided that includes at least one processor and a memory communicatively coupled to the at least one processor, where the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the method of calculating a vector dot product as described above or the method of calculating a matrix dot product as described above.

[0103] In some embodiments, a non-transitory computer-readable storage medium is provided that stores computer instructions for causing a computer to execute the above-described method of calculating a vector dot product or the above-described method of calculating a matrix dot product.

[0104] In some embodiments, a computer program product is provided that includes a computer program, which when executed by a processor, implements the method for computing vector dot products as described above or the method for computing matrix dot products as described above.

[0105] According to embodiments of the present disclosure, an electronic device, a readable storage medium, and a computer program product are further provided.

[0106] With reference to FIG. 10, a structural block diagram of an electronic device 1000 that can be used as a server or client of the present disclosure, which is an example of a hardware device applicable to various aspects of the present disclosure, will now be described. The electronic device may represent various forms of digital electronic computing devices, such as laptop computers, desktop computers, stages, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may further represent various forms of mobile devices, such as personal digital processing, mobile phones, smartphones, wearable devices, and other similar computing devices. The components, their connections, and their functions shown herein are merely exemplary and do not limit the implementation of the present disclosure as described and / or claimed herein.

[0107] 10, the electronic device 1000 includes a computing unit 1001, which can perform various suitable operations and processes according to a computer program stored in a read-only memory (ROM) 1002 or loaded from a storage unit 1008 into a random access memory (RAM) 1003. The RAM 1003 may further store various programs and data necessary for operating the electronic device 1000. The computing unit 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0108] The components in the electronic device 1000 are connected to an I / O interface 1005, and include an input unit 1006, an output unit 1007, a storage unit 1008, and a communication unit 1009. The input unit 1006 may be any type of device capable of inputting information to the electronic device 1000, and the input unit 1006 may generate input numeric or character information and key signal inputs related to user settings and / or function control of the electronic device, and may include, but is not limited to, a mouse, a keyboard, a touch screen, a trackboard, a trackball, a control lever, a microphone, and / or a remote control. The output unit 1007 may be any type of device capable of presenting information, and may include, but is not limited to, a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 1008 may include, but is not limited to, a magnetic disk, an optical disk. The communication unit 1009 enables the electronic device 1000 to exchange information / data with other devices via a computer network, e.g., the Internet, and / or various telecommunication networks, and may include, but is not limited to, a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, e.g., a Bluetooth device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0109] The computing unit 1001 may be various general-purpose and / or special-purpose processing assemblies having processing and computing capabilities. Some examples of the computing unit 1001 may include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units for executing machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1001 performs each of the methods and processes described above, such as the above-mentioned method for calculating vector dot products or the above-mentioned method for calculating matrix dot products. For example, in some embodiments, the above-mentioned method for calculating vector dot products or the above-mentioned method for calculating matrix dot products may be implemented as a computer software program tangibly embodied in a machine-readable medium such as the storage unit 1008. In some embodiments, parts or all of the computer program may be loaded and / or installed in the electronic device 1000 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded into the RAM 1003 and executed by the computing unit 1001, it can perform one or more steps of the above-mentioned method for calculating vector dot products or the above-mentioned method for calculating matrix dot products described above. Alternatively, in other embodiments, the computing unit 1001 is configured to perform the above-mentioned method for calculating vector dot products or the above-mentioned method for calculating matrix dot products in any other suitable manner (e.g., using firmware).

[0110] Various embodiments of the systems and techniques described herein may be implemented in digital electronic circuitry systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), software hardware, firmware, software, and / or combinations thereof. These various embodiments may be embodied in one or more computer programs that may be executed and / or interpreted by a programmable system that includes at least one programmable processor, which may be a special purpose or general purpose programmable processor, and may include receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0111] The program code implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer or other programmable data processing apparatus, such that when executed by the processor or controller, the program code performs the functions / operations specified in the flowcharts and / or block diagrams. The program code may be entirely executed on a machine, partly executed on a machine, partly executed on a machine and partly executed on a remote machine as a separate software package, or entirely executed on a remote machine or server.

[0112] In the context of this disclosure, a machine-readable medium may be a tangible medium, which may include or store a program for use in or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the above. More specific examples of machine-readable storage media include an electrical connection with one or more leads, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0113] To provide for interaction with a user, a computer may implement the systems and techniques described herein and include a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user, and a keyboard and pointing device (e.g., a mouse or trackball) through which the user may provide input to the computer. Other types of devices may also be provided for providing interaction with a user. For example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or haptic feedback), and may receive input from the user in any form (including audio input, speech input, or tactile input).

[0114] The systems and techniques described herein may be implemented in a computing system including backstage components (e.g., as a data server), middleware components (e.g., an application server), front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with embodiments of the systems and techniques), or any combination of backstage components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communications network). Examples of communications networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0115] The computer system may include a client side and a server. The client side and the server are generally remote from each other and usually interact with each other via a communication network. The relationship between the client side and the server is generated by executing computer programs having a client side-server relationship with each other on corresponding computers. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0116] It should be understood that the various forms of flows described above may be used to rearrange, add, or remove steps, for example, the steps described in this disclosure may be performed in parallel, sequentially, or in a different order, and the present disclosure is not limited thereto, as long as the technical solutions disclosed in this disclosure achieve the desired results.

[0117] Although the embodiments or examples of the present disclosure have been described with reference to the drawings, it should be understood that the above methods, systems, and devices are merely exemplary embodiments or examples, and the scope of the present invention is not limited by these embodiments or examples, but only by the scope of the claims and their equivalents after grant. Various elements of the embodiments or examples may be omitted or replaced by their equivalent elements. It should be noted that each step may be performed in a different order from the order described in this disclosure. Furthermore, various elements of the embodiments or examples may be combined in various ways. It is important to note that with the evolution of technology, many elements described herein may be replaced by equivalent elements that appear later in this disclosure.

Claims

1. A computing method executed by a computing device, comprising: obtaining a first matrix and a second matrix, the first matrix including a first number of row vectors, the second matrix including a second number of column vectors, and the row vectors and the column vectors having the same vector length; Each row vector in the first matrix and each column vector in the second matrix are determined as a first vector and a second vector, respectively, and an inner product calculation process is performed on the first vector and the second vector to obtain an inner product result between each row vector in the first matrix and each column vector in the second matrix, wherein the inner product calculation process on the first vector and the second vector includes: obtaining a plurality of first fixed-point numbers and a plurality of first exponents, which correspond to the plurality of first floating-point numbers, expressed in binary, and a plurality of second fixed-point numbers and a plurality of second exponents, which correspond to the plurality of second floating-point numbers, expressed in binary, based on the plurality of first floating-point numbers of the first vector and the plurality of second floating-point numbers of the second vector input to the arithmetic unit, where the plurality of first floating-point numbers correspond to the plurality of second floating-point numbers in a one-to-one relationship, and each fixed-point number among the plurality of first fixed-point numbers and the plurality of second fixed-point numbers includes a sign bit and a first predetermined number of fixed-point numeric bits; obtaining a fixed-point product value of each first fixed-point number of the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number and a corresponding fixed-point product exponent; obtaining a fixed-point inner product calculation result between the first vector and the second vector based on a fixed-point product exponent corresponding to each fixed-point product value among a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, respectively; obtaining a floating-point dot product calculation result in a floating-point data format corresponding to the fixed-point dot product calculation result based on the fixed-point dot product calculation result; obtaining an inner product result matrix of the first matrix and the second matrix based on the inner product result of each row vector in the first matrix and each column vector in the second matrix.

2. obtaining a fixed-point inner product calculation result between the first vector and the second vector based on a fixed-point product exponent corresponding to each fixed-point product value among a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, respectively, arithmetically shifting a fixed-point product value based on a fixed-point product exponent corresponding to each fixed-point product value among a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, respectively; and summing a plurality of arithmetically shifted fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, thereby obtaining a fixed-point dot product result of the first vector and the second vector.

3. arithmetically shifting the fixed-point product value based on a fixed-point product exponent corresponding to each fixed-point product value among a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, respectively, includes: determining a first fixed-point product exponent among a plurality of fixed-point product exponents corresponding to the plurality of first fixed-point numbers; obtaining an arithmetic shift value corresponding to each fixed-point product value among the plurality of fixed-point product values ​​based on an exponent of each fixed-point product among the plurality of fixed-point product exponents and an exponent of the first fixed-point product; 3. The method of claim 2, further comprising arithmetically shifting each fixed-point product value of the plurality of fixed-point product values ​​based on an arithmetic shift value corresponding to the each fixed-point product value of the plurality of fixed-point product values.

4. determining a first fixed-point product exponent among a plurality of fixed-point product exponents corresponding to the plurality of first fixed-point numbers includes obtaining a fixed-point product exponent having a maximum value among a plurality of fixed-point product exponents corresponding to the plurality of first fixed-point numbers as a first fixed-point product exponent; and 4. The method of claim 3, wherein obtaining an arithmetic shift value corresponding to each fixed-point product value among the plurality of fixed-point product values ​​based on an exponent of each fixed-point product among the plurality of fixed-point product exponents and an exponent of the first fixed-point product includes: calculating a difference between an exponent of the first fixed-point product and an exponent of each fixed-point product among the plurality of fixed-point product exponents as an arithmetic shift value corresponding to the fixed-point product value corresponding to the exponent of the fixed-point product.

5. Obtaining a plurality of first fixed-point numbers and a plurality of first exponents expressed in binary corresponding to the plurality of first floating-point numbers, and a plurality of second fixed-point numbers and a plurality of second exponents expressed in binary corresponding to the plurality of second floating-point numbers, includes: for each floating point number of the first plurality of floating point numbers and the second plurality of floating point numbers, extracting a sign bit, an exponent bit, and a floating-point value bit from the floating-point number, where the floating-point number is represented by a binary number; extracting a second predetermined number of most significant bits from the most significant bits of the floating-point value as most significant bits of the floating-point value; determining a fixed-point number corresponding to the floating-point number based on the most significant bits; and determining an exponent corresponding to the floating-point number based on exponent bits of the floating-point number.

6. Obtaining a fixed-point product value and a corresponding fixed-point product exponent of each first fixed-point number of the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number includes: obtaining a plurality of first complements corresponding to the plurality of first fixed-point numbers and a plurality of second complements corresponding to the plurality of second fixed-point numbers based on sign bits of a plurality of first floating-point numbers corresponding to the plurality of first fixed-point numbers, respectively, and sign bits of a plurality of second floating-point numbers corresponding to the plurality of second fixed-point numbers, respectively; calculating a product of each first complement of the plurality of first complements with a corresponding second complement of the first complement to obtain a fixed-point product value; 6. The method of claim 5, further comprising: calculating a sum of a first exponent corresponding to each first fixed-point number of the plurality of first fixed-point numbers and a second exponent corresponding to a second fixed-point number corresponding to the first fixed-point number to obtain an exponent of the fixed-point product.

7. The computing device is capable of calculating an inner product of two vectors of a first predetermined length in one computing cycle, and for a third vector and a fourth vector, both of which have the same length and are greater than the first predetermined length, the method includes: Dividing the third vector and the fourth vector into a plurality of first vectors and a plurality of second vectors, respectively, based on the first predetermined length, where the plurality of first vectors have a one-to-one correspondence with the plurality of second vectors; Calculating floating-point dot products of a plurality of corresponding pairs of first and second vectors, respectively; 2. The method of claim 1, further comprising: calculating a sum of floating-point dot products of the sets of corresponding first and second vectors to obtain a dot product of the third and fourth vectors.

8. 1. A computing device, comprising: a fourth acquisition unit configured to acquire a first matrix and a second matrix, the first matrix including a first number of row vectors, the second matrix including a second number of column vectors, and the row vectors and the column vectors have the same vector length; a fifth obtaining unit configured to determine each row vector in the first matrix and each column vector in the second matrix as a first vector and a second vector, respectively, perform an inner product calculation process for the first vector and the second vector to obtain inner product results between each row vector in the first matrix and each column vector in the second matrix, and obtain an inner product result matrix of the first matrix and the second matrix based on the inner product results between each row vector in the first matrix and each column vector in the second matrix; The inner product calculation process for the first vector and the second vector includes: a first acquisition unit configured to acquire, based on the first floating-point numbers of the first vector and the second floating-point numbers of the second vector input to the arithmetic device, a first fixed-point number and a first exponent corresponding to the first floating-point numbers and expressed in binary, and a second fixed-point number and a second exponent corresponding to the second floating-point numbers and expressed in binary, where the first floating-point numbers correspond one-to-one to the second floating-point numbers, and each fixed-point number among the first fixed-point numbers and the second fixed-point numbers includes a sign bit and a first predetermined number of fixed-point numeric bits; a multiplier configured to obtain a fixed-point product value of each first fixed-point number of the plurality of first fixed-point numbers and a second fixed-point number corresponding to the first fixed-point number and a corresponding fixed-point product exponent; a second obtaining unit configured to obtain a fixed-point inner product calculation result between the first vector and the second vector according to a fixed-point product exponent corresponding to each fixed-point product value among a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, respectively; a third obtaining unit configured to obtain, based on the fixed-point dot product calculation result, a floating-point dot product calculation result in a floating-point data format corresponding to the fixed-point dot product calculation result; An apparatus implemented based on the above.

9. The second acquisition unit includes: a shifter configured to arithmetically shift a fixed-point product value based on a fixed-point product exponent corresponding to each fixed-point product value among a plurality of fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, respectively; and an adder configured to sum a plurality of arithmetically shifted fixed-point product values ​​corresponding to the plurality of first fixed-point numbers, thereby obtaining a fixed-point dot product result of the first vector and the second vector.

10. The shifter is a determining module configured to determine a first fixed-point product exponent among a plurality of fixed-point product exponents corresponding to the plurality of first fixed-point numbers; an obtaining module configured to obtain an arithmetic shift value corresponding to each fixed-point product value among the plurality of fixed-point product values ​​based on an exponent of each fixed-point product among the plurality of fixed-point product exponents and an exponent of the first fixed-point product; and a shift module configured to arithmetically shift each fixed-point product value among the plurality of fixed-point product values ​​based on an arithmetic shift value corresponding to the each fixed-point product value.

11. The determination module is configured to obtain a fixed-point product exponent having a maximum value among a plurality of fixed-point product exponents corresponding to the plurality of first fixed-point numbers as a first fixed-point product exponent; 11. The apparatus of claim 10, wherein the retrieval module is configured to calculate a difference between an exponent of the first fixed-point product and an exponent of each fixed-point product among the plurality of fixed-point product exponents as an arithmetic shift value corresponding to a fixed-point product value corresponding to the fixed-point product exponent.

12. The first acquisition unit, for each floating-point number of the plurality of first floating-point numbers and the plurality of second floating-point numbers, a first extraction subunit for extracting a sign bit, an exponent bit and a floating-point value bit in the floating-point number, the floating-point number being configured to be represented by a binary number; a second extraction subunit configured to extract a second predetermined number of most significant bits from the most significant bits of the floating-point value as the most significant bits of the floating-point value; a first determination subunit configured to determine a fixed-point number corresponding to the floating-point number based on the most significant bits; The apparatus of claim 11 , configured to perform the operation with a second determination subunit configured to determine an exponent corresponding to the floating-point number based on exponent bits of the floating-point number.

13. The multiplier comprises: an acquiring subunit configured to acquire a plurality of first complements corresponding to the plurality of first fixed-point numbers and a plurality of second complements corresponding to the plurality of second fixed-point numbers based on sign bits of a plurality of first floating-point numbers corresponding to the plurality of first fixed-point numbers, respectively, and sign bits of a plurality of second floating-point numbers corresponding to the plurality of second fixed-point numbers, respectively; a first calculation subunit configured to calculate a product of each first complement of the plurality of first complements and a corresponding second complement of the first complement to obtain a fixed-point product value; and a second calculation subunit configured to calculate a sum of a first exponent corresponding to each first fixed-point number of the plurality of first fixed-point numbers and a second exponent corresponding to a second fixed-point number corresponding to the first fixed-point number to obtain an exponent of the fixed-point product.

14. The computing device is capable of calculating the inner product of two vectors of a first predetermined length in one computing cycle, and for a third vector and a fourth vector whose vector lengths are the same and both are greater than the first predetermined length, the device: a splitting unit configured to split the third vector and the fourth vector into a plurality of first vectors and a plurality of second vectors, respectively, based on the first predetermined length, where the plurality of first vectors have a one-to-one correspondence with the plurality of second vectors; a first calculation unit configured to calculate floating-point dot product results of a plurality of sets of corresponding first and second vectors, respectively; 9. The apparatus of claim 8, further comprising: a second calculation unit configured to calculate a sum of floating-point dot product results of the sets of corresponding first and second vectors to obtain a dot product result of the third and fourth vectors.

15. A chip comprising a device described in any one of claims 8 to 14.

16. An electronic device comprising the chip of claim 15.

17. An electronic device, At least one processor; a memory communicatively coupled to the at least one processor; An electronic device, wherein the memory stores instructions executable by the at least one processor, and the instructions, when executed by the at least one processor, enable the at least one processor to perform the method according to any one of claims 1 to 7.

18. A non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to carry out the method according to any one of claims 1 to 7.

19. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 7.

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