Semiconductor device and electronic device

Abstract

To provide a semiconductor device capable of performing calculations with low power consumption.SOLUTION: A semiconductor device comprises first and second circuits, a first amplifying circuit, first to fourth switches, and a capacity. The first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacity via the first switch, and the second wiring is electrically connected to the first terminal of the capacity via the third switch. Moreover, the first terminal of the capacity is electrically connected to a first terminal of the second switch, and a second terminal of the capacity is electrically connected to the first amplifying circuit via the fourth switch. Currents according to the result of product-sum operation flow in each of the first and second wirings, and each of the currents is converted into potential by the first and second circuits. The difference of the converted potential is held in the capacity, and moreover, the difference is inputted to the first amplifying circuit and is outputted as the potential according to an arithmetic result.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and testing methods thereof. [Background technology]

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using SRAM (Static Random Access Memory). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-patent document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In an artificial neural network, a calculation is performed in which the connection strength (sometimes called a weighting coefficient) of a synapse connecting two neurons is multiplied by the signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, the connection strength of each synapse between a plurality of first neurons in a first layer and one of the second neurons in a second layer must be multiplied by each signal input from a plurality of first neurons in the first layer to one of the second neurons in the second layer and then added together (a multiply-and-add operation). The number of connection strengths and the number of parameters representing the signals are determined depending on the scale of the artificial neural network. In other words, the greater the number of layers and neurons in an artificial neural network, the greater the number of circuits corresponding to "neurons" and "synapses," and the greater the amount of calculation required.

[0007] For example, neural network operations include not only product-sum operations but also activation function operations, etc. In activation function operations, the larger the scale of the artificial neural network, the higher the power consumption tends to be.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device or the like in which a hierarchical artificial neural network is built.An object of one embodiment of the present invention is to provide a semiconductor device or the like with low power consumption.An object of one embodiment of the present invention is to provide a novel semiconductor device or the like.An object of one embodiment of the present invention is to provide an electronic device including the semiconductor device.

[0009] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] (1) One embodiment of the present invention is a semiconductor device including a cell and a first circuit, the first circuit including a first capacitance, a first input terminal, and a second input terminal, the cell being electrically connected to the first input terminal via a first wiring and electrically connected to the second input terminal via a second wiring, the cell having a function of retaining first data and a function of causing a first current corresponding to the first data and the second data to flow between the cell and the first wiring and a second current corresponding to the first data and the second data to flow between the cell and the second wiring when second data is input to the cell, and the first capacitance having a function of retaining a differential voltage between a first potential corresponding to the first current and a second potential corresponding to the second current.

[0011] (2) Another embodiment of the present invention is a semiconductor device having the above-described structure (1), in which the first circuit includes a second circuit, and the second circuit has a function of obtaining a differential voltage and outputting a signal according to the differential voltage.

[0012] (3) Alternatively, in one aspect of the present invention, in the configuration (2) above, the first circuit has a first current-voltage conversion circuit, a second current-voltage conversion circuit, a first switch, a second switch, a third switch, and a fourth switch, the first input terminal is electrically connected to a first terminal of the first switch and a first terminal of the first current-voltage conversion circuit, the second terminal of the first switch is electrically connected to a first terminal of the second switch and a first terminal of the first capacitor, the second input terminal is electrically connected to a first terminal of the third switch and a first terminal of the second current-voltage conversion circuit, The second terminal of the third switch is electrically connected to the first terminal of the fourth switch and the second terminal of the first capacitor, the second terminal of the fourth switch is electrically connected to the first terminal of the second circuit, the first current-voltage conversion circuit has a function of setting the potential of the first terminal of the first current-voltage conversion circuit to a first potential in accordance with a first current input to the first terminal of the first current-voltage conversion circuit, and the second current-voltage conversion circuit has a function of setting the potential of the first terminal of the second current-voltage conversion circuit to a second potential in accordance with a second current input to the first terminal of the second current-voltage conversion circuit.

[0013] (4) Alternatively, one embodiment of the present invention is a semiconductor device having the configuration of (3), in which the second terminal of the second switch is electrically connected to a third wiring that provides a reference potential, and the first circuit has a function of turning on the first switch and the third switch and turning off the second switch and the fourth switch to set the first terminal of the first capacitance to a first potential and the second terminal of the first capacitance to a second potential, a function of turning off the first switch, the third switch, and the fourth switch and turning on the second switch to change the first terminal of the first capacitance from the first potential to the reference potential, thereby changing the second potential of the second terminal of the first capacitance to a third potential by capacitive coupling, and a function of turning off the first switch, the second switch, and the third switch and turning on the fourth switch to input a third potential corresponding to the differential voltage to the first terminal of the second circuit.

[0014] (5) Alternatively, one embodiment of the present invention is a semiconductor device including a cell and a first circuit. The first circuit includes a first capacitance, a second capacitance, a first input terminal, and a second input terminal. The cell is electrically connected to the first input terminal through a first wiring and electrically connected to the second input terminal through a second wiring. The cell has a function of retaining first data and a function of causing a first current corresponding to the first data and the second data to flow between the cell and the first wiring and a second current corresponding to the first data and the second data to flow between the cell and the second wiring when second data is input to the cell. The first capacitance has a function of retaining a first differential voltage between a first potential corresponding to the first current and a second potential corresponding to the second current. The second capacitance has a function of retaining a second differential voltage between the first potential corresponding to the first current and the second potential corresponding to the second current.

[0015] (6) Alternatively, one embodiment of the present invention is a semiconductor device having the configuration of (5) above, in which the first circuit includes a second circuit and a third circuit, the second circuit has a function of acquiring a first differential voltage based on the potential of a first terminal of the first capacitance and outputting a first signal corresponding to the first differential voltage, and the third circuit has a function of acquiring a second differential voltage based on the potential of a second terminal of the second capacitance and outputting a second signal corresponding to the second differential voltage.

[0016] (7) Alternatively, according to one aspect of the present invention, in the configuration of (6) above, the first circuit includes a first current-voltage conversion circuit, a second current-voltage conversion circuit, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch, the first input terminal is electrically connected to a first terminal of the first switch, a first terminal of the fifth switch, and a first terminal of the first current-voltage conversion circuit, the second terminal of the first switch is electrically connected to a first terminal of the second switch and a first terminal of the first capacitance, the second terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and a first terminal of the second capacitance, and the second input terminal is electrically connected to a first terminal of the third switch, a first terminal of the seventh switch, and a first terminal of the second current-voltage conversion circuit. a second terminal of the third switch electrically connected to a first terminal of the fourth switch and a second terminal of the first capacitor; a second terminal of the seventh switch electrically connected to a first terminal of the eighth switch and a second terminal of the second capacitor; a second terminal of the fourth switch electrically connected to a first terminal of the second circuit; and a second terminal of the sixth switch electrically connected to a first terminal of the third circuit. The first current-voltage conversion circuit has a function of setting the potential of the first terminal of the first current-voltage conversion circuit to a first potential in accordance with a first current input to the first terminal of the first current-voltage conversion circuit. The second current-voltage conversion circuit has a function of setting the potential of the first terminal of the second current-voltage conversion circuit to a second potential in accordance with a second current input to the first terminal of the second current-voltage conversion circuit.

[0017] (8) Alternatively, according to one aspect of the present invention, in the configuration of (7) above, the second terminal of the second switch is electrically connected to a third wiring that provides a reference potential, and the second terminal of the eighth switch is electrically connected to the third wiring that provides the reference potential, and the first circuit has a function of turning on the first switch and the third switch and turning off the second switch and the fourth switch to set the first terminal of the first capacitance to a first potential and the second terminal of the first capacitance to a second potential, turning on the fifth switch and the seventh switch and turning off the sixth switch and the eighth switch to set the first terminal of the second capacitance to the first potential and the second terminal of the second capacitance to the second potential, and a function of turning off the first switch, the third switch, and the fourth switch and turning on the second switch to set the first terminal of the first capacitance from the first potential to the reference potential. a function of changing the second terminal of the second capacitance from the second potential to a reference potential by capacitive coupling, thereby changing the second potential of the second terminal of the first capacitance to a third potential; a function of changing the first potential of the first terminal of the first capacitance to a fourth potential by capacitive coupling, thereby changing the second terminal of the second capacitance from the second potential to a reference potential by turning the fifth switch, the sixth switch, and the seventh switch to an off state and the eighth switch to an on state; a function of inputting a third potential corresponding to the first differential voltage to the first terminal of the second circuit by turning the first switch, the second switch, and the third switch to an off state and the fourth switch to an on state; and a function of inputting a fourth potential corresponding to the second differential voltage to the first terminal of the third circuit by turning the fifth switch, the seventh switch, and the eighth switch to an off state and the sixth switch to an on state.

[0018] (9) Alternatively, according to one aspect of the present invention, in any one of the configurations (1) to (8) above, the cell includes a first cell and a second cell, the first cell is electrically connected to the first wiring, the second wiring, the first input wiring, and the second input wiring, the second cell is electrically connected to the first wiring, the second wiring, the first input wiring, and the second input wiring, each of the first input wiring and the second input wiring has a function of applying a potential according to second data, and the first cell has a function of causing a first current to flow through the first wiring when a first input potential is input to the first input wiring and a second input potential is input to the second input wiring, and a function of causing a second current to flow through the second wiring when a second input potential is input to the first input wiring and the first input potential is input to the second input wiring. and a function of bringing the first cell and the first wiring and the first cell and the second wiring into a non-conductive state when a second input potential is input to the first input wiring and the second input potential is input to the second input wiring, and the second cell has a function of passing a second current through the second wiring when the first input potential is input to the first input wiring and the second input potential is input to the second input wiring, a function of passing a first current through the first wiring when the second input potential is input to the first input wiring and the first input potential is input to the second input wiring, and a function of bringing the second cell and the first wiring and the second cell and the second wiring into a non-conductive state when the second input potential is input to the first input wiring and the second input potential is input to the second input wiring.

[0019] (10) Alternatively, in one aspect of the present invention, in the configuration of (9) above, the first cell has a first transistor, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, and a third capacitor; the second cell has a second transistor, a thirteenth switch, a fourteenth switch, a fifteenth switch, a sixteenth switch, and a fourth capacitor; a first terminal of the first transistor is electrically connected to a first terminal of the ninth switch, a first terminal of the tenth switch, and a first terminal of the eleventh switch; a gate of the first transistor is electrically connected to a first terminal of the third capacitor and a first terminal of the twelfth switch; a second terminal of the ninth switch is electrically connected to a second terminal of the twelfth switch; a second terminal of the tenth switch is electrically connected to the first wiring; and a control terminal of the tenth switch is connected to the first input wiring. a gate of the second transistor electrically connected to a first terminal of the fourth capacitor and a first terminal of the sixteenth switch; a second terminal of the eleventh switch electrically connected to the second wiring; a control terminal of the eleventh switch electrically connected to the second input wiring; a first terminal of the second transistor electrically connected to a first terminal of the thirteenth switch, a first terminal of the fourteenth switch, and a first terminal of the fifteenth switch; a gate of the second transistor electrically connected to a first terminal of the fourth capacitor and a first terminal of the sixteenth switch; a second terminal of the thirteenth switch electrically connected to the second terminal of the sixteenth switch; a second terminal of the fourteenth switch electrically connected to the second wiring; a control terminal of the fourteenth switch electrically connected to the first input wiring; a second terminal of the fifteenth switch electrically connected to the first wiring; and a control terminal of the fifteenth switch electrically connected to the second input wiring.

[0020] (11) Alternatively, one embodiment of the present invention is a semiconductor device having the above-described configuration (10), in which the 12th switch includes a third transistor, and the third transistor includes a metal oxide in a channel formation region thereof; and the 16th switch includes a fourth transistor, and the fourth transistor includes a metal oxide in a channel formation region thereof.

[0021] (12) Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (11) above and a housing, in which the semiconductor device performs a neural network operation.

[0022] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0023] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0024] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0025] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0026] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0027] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0028] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0029] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0030] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also parasitic capacitance appearing between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," and the like. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0031] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0032] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0033] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0034] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0035] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the orientation of each component. Therefore, the terms are not limited to those used in the specification, but can be rephrased appropriately depending on the situation. For example, the expression "an insulator located on the upper surface of a conductor" can be rephrased as "an insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0037] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0039] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0040] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0041] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main components constituting a semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause, for example, the formation of density of states (DOS) in the semiconductor, a decrease in carrier mobility, or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

[0042] In this specification and the like, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0043] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0045] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0046] According to one embodiment of the present invention, a semiconductor device or the like in which a hierarchical artificial neural network is constructed can be provided. According to another embodiment of the present invention, a semiconductor device or the like with low power consumption can be provided. According to another embodiment of the present invention, a novel semiconductor device or the like can be provided. According to another embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0047] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0048] [Figure 1] 1A and 1B are diagrams illustrating a hierarchical neural network. [Figure 2] FIG. 2A is a circuit diagram showing an example of the configuration of a semiconductor device, and FIGS. 2B and 2C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 3] 3A to 3C are circuit diagrams showing examples of the configuration and operation of a semiconductor device. [Figure 4] 4A and 4B are circuit diagrams showing an example of the configuration and operation of a semiconductor device. [Figure 5] FIG. 5 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 6] 6A to 6C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 7] 7A to 7C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 9] FIG. 9 is a timing chart illustrating an example of the operation of the semiconductor device. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 11] 11A and 11B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 12] FIG. 12 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 13] 13A to 13D are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 14] 14A to 14C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 15] FIG. 15 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 16] FIG. 16 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 18] 18A and 18B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 19] 19A to 19E are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 20]20A to 20C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 21] 21A and 21B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 22] 22A and 22B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 23] 23A to 23C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 24] 24A to 24C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 25] 25A to 25C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 26] 26A to 26C are timing charts illustrating an example of the operation of the semiconductor device. [Figure 27] 27A and 27B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 28] 28A and 28B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 29] 29A to 29C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 30] 30A to 30C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 31] 31A to 31C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 32] 32A and 32B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 33] FIG. 33 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 34] FIG. 34 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 35] 35A to 35C are cross-sectional views illustrating examples of the configuration of a semiconductor device. [Figure 36]36A and 36B are cross-sectional views illustrating examples of the structure of a transistor. [Figure 37] FIG. 37 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 38] 38A and 38B are cross-sectional views illustrating examples of the structure of a transistor. [Figure 39] FIG. 39 is a schematic cross-sectional view illustrating a configuration example of a semiconductor device. [Figure 40] FIG. 40A is a top view showing an example of the configuration of a capacitor, and FIGS. 40B and 40C are cross-sectional perspective views showing an example of the configuration of a capacitor. [Figure 41] FIG. 41A is a top view showing an example of the configuration of a capacitor, FIG. 41B is a cross-sectional view showing the example of the configuration of a capacitor, and FIG. 41C is a cross-sectional perspective view showing the example of the configuration of a capacitor. [Figure 42] FIG. 42A is a diagram illustrating the classification of IGZO crystal structures, FIG. 42B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 42C is a diagram illustrating the micro-electron beam diffraction pattern of crystalline IGZO. [Figure 43] FIG. 43A is a perspective view showing an example of a semiconductor wafer, FIG. 43B is a perspective view showing an example of a chip, and FIGS. 43C and 43D are perspective views showing an example of an electronic component. [Figure 44] FIG. 44 is a perspective view showing an example of an electronic device. [Figure 45] 45A to 45C are perspective views showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0049] In an artificial neural network (hereafter referred to as a neural network), the strength of synaptic connections can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining connection strengths is sometimes called "learning."

[0050] Furthermore, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), new information can be output based on the connection strengths. In this way, the process of outputting new information based on the provided information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0051] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are sometimes called "deep neural networks" (DNNs), and machine learning using deep neural networks is sometimes called "deep learning."

[0052] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. Furthermore, when a metal oxide is referred to as an OS FET or an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0053] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0054] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0055] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0056] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0057] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0058] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0059] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m,n]” may be added to the symbol.

[0060] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0061] In addition, regarding this specification and the like, when In:Ga:Zn = 4:2:3 or in its vicinity, with respect to the total number of atoms, when In is 4, Ga is 1 or more and 3 or less (1 ≤ Ga ≤ 3), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, when In:Ga:Zn = 5:1:6 or in its vicinity, with respect to the total number of atoms, when In is 5, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also, when In:Ga:Zn = 1:1:1 or in its vicinity, with respect to the total number of atoms, when In is 1, Ga is greater than 0.1 and 2 or less (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and 2 or less (0.1 < Zn ≤ 2). Also, when In:Ga:Zn = 5:1:3 or in its vicinity, with respect to the total number of atoms, when In is 5, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, when In:Ga:Zn = 10:1:3 or in its vicinity, with respect to the total number of atoms, when In is 10, Ga is 0.5 or more and 1.5 or less (0.5 ≤ Ga ≤ 1.5), and Zn is 2 or more and 4.1 or less (2 ≤ Zn ≤ 4.1). Also, when In:Zn = 2:1 or in its vicinity, with respect to the total number of atoms, when In is 1, Zn is greater than 0.25 and 0.75 or less (0.25 < Zn ≤ 0.75). Also, when In:Zn = 5:1 or in its vicinity, with respect to the total number of atoms, when In is 1, Zn is greater than 0.12 and 0.25 or less (0.12 < Zn ≤ 0.25). Also, when In:Zn = 10:1 or in its vicinity, with respect to the total number of atoms, when In is 1, Zn is greater than 0.07 and 0.12 or less (0.07 < Zn ≤ 0.12).

[0062] (Embodiment 1) In this embodiment, an arithmetic circuit that performs neural network operations, which is a semiconductor device according to one aspect of the present invention, will be described.

[0063] <Hierarchical neural network> First, a hierarchical neural network will be described. A hierarchical neural network, for example, has one input layer, one or more intermediate layers (hidden layers), and one output layer, for a total of three or more layers. The hierarchical neural network 100 shown in FIG. 1A is an example of such a network, and the neural network 100 has layers 1 through R (where R can be an integer equal to or greater than four). In particular, the first layer corresponds to the input layer, the R layer corresponds to the output layer, and the other layers correspond to intermediate layers. Note that FIG. 1A illustrates layers (k-1) and k (where k is an integer equal to or greater than three and equal to or less than R-1) as intermediate layers, and does not illustrate the other intermediate layers.

[0064] Each layer of neural network 100 has one or more neurons. In FIG. 1A, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is an integer equal to or greater than 1), and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 (k) Neuron N n (k) (where n is an integer greater than or equal to 1), and the Rth layer has neurons N1 (R) Neuron N q (R) (where q is an integer equal to or greater than 1).

[0065] In addition, in Figure 1A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R)In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j (k) (where j is an integer between 1 and n) are also shown, and other neurons are omitted from the illustration.

[0066] Next, we will explain the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output at each neuron. j (k) Focus on.

[0067] Figure 1B shows the k-th layer neuron N j (k) and neuron N j (k) and the signal input to neuron N j (k) 10 shows the signal output from the

[0068] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) The output signal z1 (k-1) ~z m (k-1) But neuron N j (k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is output as an output signal to each neuron in the (k+1)th layer (not shown).

[0069] The degree of signal transmission for a signal input from a neuron in the previous layer to a neuron in the next layer is determined by the connection strength (hereinafter referred to as a weighting coefficient) of the synapse connecting those neurons. In the neural network 100, the signal output from a neuron in the previous layer is multiplied by the corresponding weighting coefficient before being input to a neuron in the next layer. If i is an integer between 1 and m, then the (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer neuron N j (k) The signal input to can be expressed by equation (1.1).

[0070]

number

[0071] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) From each of these, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) z m (k-1)is input. At this time, the k-th layer neuron N j (k) The sum of the signals input to j (k) is expressed as equation (1.2).

[0072]

number

[0073] Also, the weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) and the neuron signal z1 (k-1) ~z m (k-1) The result of the sum of products of and can be given a bias. When the bias is b, equation (1.2) can be rewritten as the following equation.

[0074]

number

[0075] Neuron N j (k) u j (k) Depending on j (k) where neuron N j (k) Output signal z from j (k) is defined as follows:

[0076]

number

[0077] The function f(u j (k)) is an activation function in a hierarchical neural network, and can be a step function, a linear ramp function, a sigmoid function, etc. The activation function can be the same for all neurons or different for each layer. In addition, the activation functions of neurons can be the same or different for each layer.

[0078] The signals, weight coefficients w, or biases b output by neurons in each layer may be analog or digital values. Digital values ​​may be, for example, binary or ternary. Values ​​with even larger bit counts may also be used. For example, in the case of analog values, activation functions such as linear ramp functions and sigmoid functions may be used. In the case of binary digital values, step functions that output either -1 or 1, or either 0 or 1 may be used. Furthermore, signals output by neurons in each layer may be ternary or more. For example, activation functions that output three values ​​may be step functions that output either -1, 0, or 1, or step functions that output either 0, 1, or 2. Furthermore, activation functions that output five values ​​may be step functions that output either -2, -1, 0, 1, or 2. By using digital values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to reduce the circuit size, reduce power consumption, or increase the calculation speed, etc. Furthermore, by using analog values ​​for at least one of the signals output by neurons in each layer, the weighting coefficient w, or the bias b, it is possible to improve the accuracy of calculations.

[0079] When an input signal is input to the first layer (input layer), neural network 100 generates an output signal in each layer, from the first layer (input layer) to the last layer (output layer), based on the signal input from the previous layer, using equations (1.1), (1.2) (or (1.3)), and (1.4), and outputs the output signal to the next layer. The signal output from the last layer (output layer) corresponds to the result of calculation by neural network 100.

[0080] <Configuration example 1 of an arithmetic circuit> Here, an example of an arithmetic circuit capable of performing the calculations of Equation (1.2) (or Equation (1.3)) and Equation (1.4) in the above-mentioned neural network 100 will be described. In the arithmetic circuit, as an example, the weight coefficients of the synapse circuits of the neural network 100 can be binary or more digital values ​​or analog values, and the activation function of the neurons can be a step function or the like. In this specification and the like, either the weight coefficients or the values ​​of signals input from neurons in a previous layer to neurons in a next layer (sometimes referred to as calculated values) may be referred to as first data, and the other as second data. The weight coefficients of the synapse circuits of the neural network 100 and the calculated values ​​are not limited to digital values; at least one of them may be an analog value.

[0081] 2A is a semiconductor device having an array part ALP and a circuit AFP. The arithmetic circuit 110 is, for example, a neuron N j (k) The signal input to the neuron N j (k) The signal z output from j (k)However, one embodiment of the present invention is not limited to this. The arithmetic circuit 110 may function as a storage device or a memory circuit, for example. For example, the arithmetic circuit 110 may function as a DRAM, an SRAM, or a flash memory. Alternatively, the arithmetic circuit 110 may function as a circuit that performs calculations within a memory circuit, that is, as an in-memory computing circuit, for example.

[0082] The array unit ALP includes, for example, circuits MP[1,j] to MP[m,j]. The circuit AFP includes, for example, a circuit ACTF[j], which includes a capacitance CRE, a circuit AC, a terminal T1, and a terminal T2.

[0083] Note that the capacitor CRE may be realized using a normal capacitor element, but one embodiment of the present invention is not limited thereto. For example, the capacitor CRE may be realized using a gate capacitance of a transistor as shown in FIG. 2B or FIG. 2C . In this case, the transistor may be an N-channel type or a P-channel type, or both may be used and connected in parallel. Note that in FIGS. 2B and 2C , a transistor CRET is used instead of the capacitor CRE. For example, an OS transistor can be used as the transistor CRET. Note that OS transistors will be described in detail in Embodiment 5. In addition to the OS transistor, for example, a transistor having silicon in a channel formation region (hereinafter referred to as a Si transistor) can be used. As the silicon, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used. In addition, examples of transistors that can be used other than OS transistors and Si transistors include transistors with Ge as an active layer, transistors with compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe as an active layer, transistors with carbon nanotubes as an active layer, and transistors with organic semiconductors as an active layer.

[0084] Each of the circuits MP[1,j] to MP[m,j] is electrically connected to a wiring OL[j] and a wiring OLB[j]. Each of the circuits MP[1,j] to MP[m,j] is electrically connected to a wiring XLS[1] to a wiring XLS[m]. The wiring OL[j] is electrically connected to a terminal T1, which is electrically connected to a first terminal of the capacitor CRE. The wiring OLB[j] is electrically connected to a terminal T2, which is electrically connected to a second terminal of the capacitor CRE. Note that, for example, some element or circuit (e.g., a switch, a transistor, etc.) may be connected between the terminal T1 and the first terminal of the capacitor CRE. Similarly, for example, some element or circuit (e.g., a switch, a transistor, etc.) may be connected between the terminal T2 and the second terminal of the capacitor CRE.

[0085] Each of the wires XLS[1] to XLS[m] is, for example, a neuron N1 (k-1) Neuron N m (k-1) The signal z1 output from (k-1) ~z m (k-1) It has the function of transmitting a potential according to the

[0086] The circuit MP[1,j] is, for example, a neuron N1 (k-1) and neuron N j (k) Weighting coefficient w1 between (k-1) j (k) Similarly, the circuit MP[m,j] has a function of holding the neuron N m (k-1) and neuron N j (k) The weighting factor w between m (k-1) j (k) It has the function of retaining the

[0087] Also, the circuit MP[1,j] is, for example, a neuron N1 (k-1)The signal z1 output from (k-1) (Here, we will call this the second data) and the first data w1 (k-1) j (k) Similarly, the circuit MP[m,j] has a function of outputting the product of m (k-1) The signal z output from m (k-1) (Here, we will call this the second data) and the first data w m (k-1) j (k) It has the function of outputting the product of

[0088] As a specific example, the circuit MP[1,j] is connected to the second data z1 via the wiring XLS[1]. (k-1) By inputting a potential according to the first data w1 (k-1) j (k) and the second data z1 (k-1) In another specific example, the circuit MP[m,j] is similarly supplied with second data z m (k-1) By inputting a potential according to the first data w m (k-1) j (k) and the second data z m (k-1) and outputs information (for example, current, voltage, etc.) according to the product of these values ​​to the wiring OL[j] and / or the wiring OLB[j].

[0089] For this reason, for example, in the wiring OL, information (e.g., current, voltage, etc.) output from each of the circuits MP[1,j] to MP[m,j] is added together. Similarly, for example, in the wiring OLB, information (e.g., current, voltage, etc.) output from each of the circuits MP[1,j] to MP[m,j] is added together. That is, in each of the wirings OL and OLB, the first data w1 (k-1)j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) Information (e.g., current, voltage, etc.) corresponding to the sum of products of the above flows. However, one embodiment of the present invention is not limited to this. For example, information (e.g., current, voltage, etc.) that serves as some reference (e.g., reference, precharge, bias, etc.) may flow in at least one of the wiring OL and the wiring OLB.

[0090] The specific circuit configurations of the circuits MP[1,j] to MP[m,j] will be described later.

[0091] For example, the circuit ACTF[j] acquires information (such as current, voltage, etc.) corresponding to the sum of the products of the first data and the second data from the wiring OL[j] and the wiring OLB[j], and outputs a signal to the neuron N j (k) The signal z output from j (k) Specifically, the circuit AC included in the circuit ACTF[j] generates an output signal z represented by a digital value such as a binary or multi-value or an analog value from the information. j (k) (sometimes referred to as the calculation value) is generated. In other words, the circuit AC is treated as an activation function circuit, for example.

[0092] The circuit AC may be, for example, an analog-to-digital conversion circuit (sometimes called a sense amplifier). Specifically, the circuit AC may, for example, output a signal z j (k) When the result of the sum of products is positive, the output signal z j (k) The input signal may be an analog-to-digital converter that outputs a "positive" digital value as the input signal.

[0093] In this specification and the like, when there is no need to distinguish between the circuits MP[1,j] to MP[m,j], they will be referred to as the circuit MP. Similarly, when there is no need to distinguish between the wirings XLS[1] to XLS[m], they will be referred to as the wiring XLS. Furthermore, the [j] in each of the wirings OL[j] and OLB[j] may be omitted and they may be referred to as the wiring OL and the wiring OLB. Similarly, the [j] in the circuit ACTF[j] may be omitted and they may be referred to as the circuit ACTF.

[0094] <Operation example 1 of the arithmetic circuit> Next, an example of the operation of the circuit ACTF[j] in Fig. 2A will be described. Each of Fig. 3A to Fig. 3C is a circuit diagram showing the sequence of an example of the operation of the circuit ACTF[j].

[0095] 3A shows an example of an operation in which the voltage between the first terminal and the second terminal of the capacitor CRE of the circuit ACTF[j] is initialized to 0 V. Specifically, in the circuit of FIG. 3A, the wiring OL[j] and the wiring OLB[j] are each supplied with an initialization potential, for example, V ini Assume that V is given. ini For example, when a current flows from the wiring OL to the circuit MP, the potential becomes VDD, and when a current flows from the circuit MP to the wiring OL, the potential becomes VSS or GND.

[0096] In FIG. 3B, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) This shows an example of an operation in which information (e.g., current, voltage, charge, etc.) corresponding to the sum of products of the capacitors CRE and CRE is output to the wiring OL[j] and OLB[j], and the circuit ACTF[j] acquires the information. iniis the potential V based on the information input from the circuit MP to the circuit ACTF[j] via the wiring OL[j]. OL and the potential of the second terminal of the capacitor CRE changes to V ini is the potential V based on the information input from the circuit MP to the circuit ACTF[j] via the wiring OLB[j]. OLB At this time, the voltage between the first and second terminals of the capacitance CRE is |V RD |(=|V OLB -V OL |) and this |V RD For example, | corresponds to the difference between the total amount of information flowing through the wiring OL[j] and the total amount of information flowing through the wiring OLB[j]. For example, if the wiring OL[j] is a sum of positive values ​​and the wiring OLB[j] is a sum of negative values, then |V RD | corresponds to the difference between the sum of positive values ​​and the sum of negative values. Therefore, |V RD | corresponds to the result of the sum-of-products operation. That is, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) The sum of products is the voltage |V RD | can be held between the first terminal and the second terminal of the capacitance CRE.

[0097] In FIG. 3C, as an example, the voltage (charge) stored in the capacitor CRE is input to the circuit AC to sense the amount of the voltage (charge) stored in the capacitor CRE. In this case, the potential V OL , and potential V OLB changes significantly depending on the result of the sum of products. Therefore, if this potential is input directly to the AC circuit, there may be disadvantages such as the circuit configuration of the AC circuit becoming complicated or the operating range of the AC circuit becoming smaller. Therefore, as an example, the potential V OL , and potential V OLBEven if the magnitudes of |V RD |(=|V OLB -V OL If the voltages V | are the same, it is desirable that the circuit AC be configured so that the same voltage is input. For example, OL =1, potential V OLB Even in the case of =2, the potential V OL =3, potential V OLB In the case of |V = 4, both RD |=1, and |V RD | will be the same magnitude. Even in such a case, it is desirable to have a configuration in which the same voltage is input to the circuit AC. Therefore, as an example, at least one of the first terminal and the second terminal of the capacitance CRE is set in an electrically floating state, and then a reference potential (here, as an example, GND potential (0V). However, one embodiment of the present invention is not limited to this, and may be VDD potential, precharge potential, potential of (VDD / 2), etc.)) is applied to either the first terminal of the capacitance CRE or the second terminal of the capacitance CRE. Then, the potential of the other of the first terminal of the capacitance CRE or the second terminal of the capacitance CRE becomes |V RD That is, the potential V OL , and potential V OLB Even if the magnitude of |V RD When | is the same, the same potential can be input to the circuit AC. Then, the circuit AC senses the potential of the second terminal of the capacitor CRE, for example, and outputs the voltage V RD signal z according to j (k) That is, in the operation example shown in FIG. 3C, the signal z j (k) will be output.

[0098] Here, a specific example of the above operation will be described.

[0099] First data w1 (k-1) j (k) Or even wm (k-1) j (k) For ease of explanation, each of the second data z1 (k-1) ~z m (k-1) Each of these takes a value of, for example, "+1", "0", or "-1".

[0100] In the operation example of FIG. 3A, the potential V ini is assumed to be precharged to a high level potential.

[0101] Furthermore, in the circuit MP, when the product of the first data and the second data is “+1,” the circuit MP and the wiring OL are in a conductive state, and the circuit MP and the wiring OLB are in a non-conductive state. A current corresponding to “|+1|” flows from the wiring OL to the circuit MP. Furthermore, in the circuit MP, when the product of the first data and the second data is “−1,” the circuit MP and the wiring OL are in a non-conductive state, and the circuit MP and the wiring OLB are in a conductive state. A current corresponding to “|−1|” (i.e., a current having the same magnitude as the current corresponding to “|+1|”) flows from the wiring OLB to the circuit MP. Furthermore, in the circuit MP, when the product of the first data and the second data is “0,” the circuit MP and the wiring OL and the circuit MP and the wiring OLB are in a non-conductive state. In other words, a current having a magnitude equal to the positive sum flows through the wiring OL, and a current having a magnitude equal to the absolute value of the negative sum flows through the wiring OLB.

[0102] At this time, in the operation example of FIG. 3B, the potential V OL The magnitude of the potential V is determined by the number of circuits MP in which the product of the first data and the second data is "+1." Specifically, the greater the number of circuits MP in which the product of the first data and the second data is "+1," the greater the total amount of current flowing from the wiring OL to the circuits MP[1,j] to MP[m,j]. iniSince the total current flowing through the circuits MP[1,j] to MP[m,j] is precharged, the potential V ini In other words, the more circuits MP where the product of the first data and the second data is "+1", the greater the voltage drop from the potential V OL will be lower.

[0103] Similarly, the potential V OLB The magnitude of the potential V is determined by the number of circuits MP in which the product of the first data and the second data is "-1." Specifically, the greater the number of circuits MP in which the product of the first data and the second data is "-1," the greater the total amount of current flowing from the wiring OLB to the circuits MP[1,j] to MP[m,j]. ini Since the total current flowing through the circuits MP[1,j] to MP[m,j] is precharged, the potential V ini In other words, the more circuits MP where the product of the first data and the second data is "-1", the greater the voltage drop from the potential V OLB will be lower.

[0104] From the above, when the number of circuits MP where the product of the first data and the second data is "+1" is greater than the number of circuits MP where the product of the first data and the second data is "-1", the potential V of the first terminal of the capacitance CRE OL is the potential V of the second terminal of the capacitance CRE OLB That is, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the sum of the products is positive, the potential V OL is the potential V OLBFurthermore, when the number of circuits MP where the product of the first data and the second data is "-1" is greater than the number of circuits MP where the product of the first data and the second data is "+1", the potential V OL is the potential V of the second terminal of the capacitance CRE OLB That is, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the sum of the products is negative, the potential V OL is the potential V OLB It will be higher than.

[0105] Furthermore, when the number of circuits MP in which the product of the first data and the second data is “+1” is equal to the number of circuits MP in which the product of the first data and the second data is “−1”, or when the product of the first data and the second data is “0” in all of the circuits MP[1,j] to MP[m,j], the potential V OL is the potential V of the second terminal of the capacitance CRE OLB That is, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the sum of the products is "0", the potential V OL and potential V OLB Furthermore, when the product of the first data and the second data is "0" in all cases, the potential V OL and potential V OLB is the potential V ini It will remain as it is.

[0106] In addition, the first data w1 (k-1) j (k) Or even wm (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) The larger the absolute value of the sum of the products, the greater the potential V OL and potential V OLB The potential difference (absolute value of the voltage between the first terminal and the second terminal of the first capacitance) becomes large.

[0107] In the above example, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) In the above description, the first data w1 is, for example, one of "+1", "0", and "-1". However, the operation of the semiconductor device according to one embodiment of the present invention is not limited to this. For example, (k-1) j (k) Or even w m (k-1) j (k) The value that can be taken by may be multi-valued, more than three values ​​such as "+2", "+1", "0", "-1", "-2", etc., or may be binary, such as "+1" and "-1". The amount of current flowing between the circuit MP[1,j] to the circuit MP[m,j] and the wiring OL and / or the wiring OLB is calculated based on the first data w1 (k-1) j (k) Or even w m (k-1) j (k) It is sufficient to determine the value depending on the result of multiplying the first data w1 by the second data. (k-1) j (k) Or even w m (k-1) j (k) Each of these takes one of "+2", "+1", "0", "-1", and "-2", and the second data z1 (k-1) ~z m (k-1)Here, when the product of the first data and the second data is "+1", the circuit MP and the wiring OL are in a conductive state, and the circuit MP and the wiring OLB are in a non-conductive state. Then, the amount of current I flows from the wiring OL to the circuit MP. ut In addition, when the product of the first data and the second data is "+2" in the circuit MP, the circuit MP and the wiring OL are in a conductive state, and the circuit MP and the wiring OLB are in a non-conductive state. Then, a current of 2×I flows from the wiring OL to the circuit MP. ut Furthermore, when the product of the first data and the second data is "-1", the circuit MP and the wiring OL are in a non-conductive state, and the circuit MP and the wiring OLB are in a conductive state. Then, a current of I ut It is sufficient to assume that a current of 2×I flows from the wiring OLB to the circuit MP. When the product of the first data and the second data is “−2”, the circuit MP and the wiring OL are in a non-conductive state, and the circuit MP and the wiring OLB are in a conductive state. ut When the product of the first data and the second data is "0", a non-conductive state is established between the circuit MP and the wiring OL, and a non-conductive state is established between the circuit MP and the wiring OLB.

[0108] As described above, by performing the operation example of FIG. 3B, the voltage between the first terminal and the second terminal of the first capacitor is set to the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) The potential V OL and potential V OLB potential difference (voltage |V RD |).

[0109] After that, as shown in the operation example shown in FIG. 3C, for example, the second terminal of the capacitor CRE is set to an electrically floating state (the first terminal of the capacitor CRE may also be set to an electrically floating state), and then the potential of the first terminal of the capacitor CRE is set to the GND potential, thereby setting the potential of the second terminal of the capacitor CRE to V RD First data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) If the sum of the products is positive, the potential V of the second terminal of the capacitance CRE RD becomes a positive potential, and the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) If the sum of the products is negative, the potential V of the second terminal of the capacitance CRE RD becomes a negative potential. (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the sum of the products is "0", the differential voltage between the first terminal and the second terminal of the capacitance CRE is approximately 0, so the potential V of the second terminal of the capacitance CRE RD becomes the GND potential.

[0110] Then, by sensing the potential of the second terminal of the capacitance CRE using the circuit AC, the voltage V RD Output signal z according to j (k) That is, the potential V of the first terminal of the capacitor CRE can be output. OL and the potential V of the second terminal of the capacitance CRE OLBEven if both are large, or the potential V of the first terminal of the capacitance CRE OL and the potential V of the second terminal of the capacitance CRE OLB Even if and are small, the potential V OL and potential V OLB If the differential voltage between the two is equal in each case, the differential voltage is detected by the capacitance CRE, and the same voltage is input to the circuit AC, and the same result is output as the output signal z j (k) As a result, the potential V OL and potential V OLB Therefore, a more accurate sum-of-products result can be obtained regardless of the magnitude of

[0111] In particular, in the case of a hierarchical neural network, the circuit AC may be an activation function circuit. Depending on the type of activation function, for example, when the result of the sum of the products of the first data and the second data is "0" or less, the output signal z j (k) When the result of the multiplication and accumulation of the first data and the second data is positive, the output signal z j (k) As such a circuit, it is preferable to use, for example, an analog-to-digital conversion circuit (sense amplifier, comparator, etc.) that can sense only positive voltages.

[0112] Although the above example illustrates an example of use in a neural network, one embodiment of the present invention is not limited thereto. For example, the wiring OL may be used to output a signal from a memory cell to be read, and the wiring OLB may be used to output a signal from a reference memory cell, thereby reading information stored in the memory cell. That is, the wiring OL may be used as a DRAM, an SRAM, or a flash memory. For example, the wiring OL may be operated to read multi-valued data. Alternatively, the wiring OL may be used as a circuit that performs calculations within a memory circuit, i.e., an in-memory computing circuit.

[0113] By the way, when the result of the sum of the products of the first data and the second data is "negative", the output signal z j (k) To output a negative multi-value signal, for example, circuit AC can be an analog-to-digital converter capable of sensing both positive and negative voltages. Alternatively, in FIG. 3C, the potential of the first terminal of capacitor CRE can be set to (VDD / 2) rather than GND. In this way, when the sum of the first and second data is zero, circuit AC receives a potential of (VDD / 2). Furthermore, even when the sum of the first and second data is negative, or when the sum is positive, and the absolute value is small, circuit AC receives a positive potential. This allows the use of analog-to-digital converters (sense amplifiers, comparators, etc.) capable of sensing only positive voltages. Furthermore, analog-to-digital converters (sense amplifiers, comparators, etc.) can be simplified when only positive voltages are input. This eliminates the need for a negative power supply, simplifying the power supply circuit. Furthermore, since the input voltage range can be widened, a large margin can be secured against noise, enabling accurate processing.

[0114] In addition, when the result of the sum of the products of the first data and the second data is negative, the output signal z j (k)As a method for outputting a "negative" multi-value as a multiplication result, for example, the arithmetic circuit 110 of FIG. 2A may be replaced with the arithmetic circuit 120 shown in FIG. 4A. In other words, by increasing the number of capacitors CRE, it becomes possible to use an analog-to-digital conversion circuit (such as a sense amplifier or comparator) capable of sensing only positive voltages even when the result of the product-sum operation is "negative." As an example, the arithmetic circuit 120 includes a capacitor CREP, a capacitor CREM, a circuit ACP, and a circuit ACM. A first terminal of the capacitor CREP is electrically connected to a terminal T1, and a second terminal of the capacitor CREP is electrically connected to a terminal T2. A first terminal of the capacitor CREM is electrically connected to the terminal T1, and a second terminal of the capacitor CREM is electrically connected to the terminal T2. Note that, for example, some element or circuit (e.g., a switch, a transistor, etc.) may be connected between the terminal T1 and the first terminal of the capacitor CREP (capacitor CREM). Similarly, for example, some element or circuit (e.g., a switch, transistor, etc.) may be connected between terminal T2 and the second terminal of capacitor CREP (capacitor CREM). Furthermore, similar to circuit AC used in arithmetic circuit 110 of FIG. 2A, circuit ACP and circuit ACM are analog-to-digital conversion circuits (sense amplifiers, comparators, etc.) capable of sensing, for example, positive voltages. It is assumed that each of circuits ACP and ACM is initialized before sensing, and circuit ACP senses the potential of the second terminal of capacitor CREP, and circuit ACM senses the potential of the first terminal of capacitor CREM. In other words, different terminals are used for sensing between capacitors CREP and CREM.

[0115] 4A, the arithmetic circuit 120 changes the potential of the wiring OL to V OL and the potential of the wiring OL is V OLB The voltage between the first and second terminals of the capacitance CREP and the voltage between the first and second terminals of the capacitance CREP are |V RE | can be used.

[0116] Here, as in the operation example of FIG. 4B, the second terminal of the capacitance CREP and the first terminal of the capacitance CREM are each set to an electrically floating state (the first terminal of the capacitance CREP and the second terminal of the capacitance CREM may also be set to an electrically floating state), and then the potentials of the first terminal of the capacitance CREP and the second terminal of the capacitance CREM are set to the GND potential. As a result, the potential of the second terminal of the capacitance CREP becomes V RD The potential of the first terminal of the capacitor CREM becomes -V RD The first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the result of the sum of products is "positive", V RD becomes a potential higher than 0, and the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the result of the sum of products is negative, V RD is a potential lower than 0. In other words, the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the result of the sum of products is "positive", the circuit ACM detects the potential -V RD is negative, no potential is output from the circuit ACM (or zero is output), and the circuit ACP outputs the potential V RD is positive, sensing is performed to transfer the potential V RD In addition, the potential corresponding to the first data w1 (k-1) j (k) Or even wm (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the result of the sum of products is negative, the circuit ACP detects the potential V of the second terminal of the capacitance CREP. RD is negative, no potential is output from the circuit ACP (or zero is output), and the circuit ACM outputs the potential -V RD Since is positive, sensing is performed to transfer the potential V RD The potential corresponding to the first data w1 (k-1) j (k) Or even w m (k-1) j (k) and the second data z1 (k-1) ~z m (k-1) When the result of the sum of products is "0", the potential of the first terminal of the capacitance CREP is the GND potential, so the circuit ACP does not output a potential (or outputs zero), and the potential of the second terminal of the capacitance CREM is the GND potential, so the circuit ACM does not output a potential (or outputs zero).

[0117] Here, by making the potential output from the circuit ACP correspond to multiple "positive" values ​​and the potential output from the circuit ACM correspond to multiple "negative" values, even when an analog-to-digital conversion circuit (sense amplifier, comparator, etc.) that can sense only positive voltages is used, even when the result of the sum of the products of the first data and the second data is "negative," the output signal z j (k)As a result, it is possible to output multiple "negative" values. Note that, although an example in which the circuit AC includes the circuit ACP and the circuit ACM is shown in FIG. 4, one embodiment of the present invention is not limited to this. The circuit ACP and the circuit ACM may be replaced by only the circuit AC, and sensing may be performed twice by the circuit AC. In other words, the operation of the circuit AC may be divided into two times and operated in a time-division manner. This increases the processing time, but allows the circuit scale to be reduced.

[0118] <Configuration example 2 of an arithmetic circuit> Next, a specific example of the circuit configuration of the circuit ACTF[j] will be described. As an example, the circuit ACTF[j] can have the circuit configuration shown in FIG. 5. FIG. 5 shows an example in which a signal z j (k) Specifically, FIG. 5 shows a circuit that generates an output signal z j (k) 5 shows an example of an arithmetic circuit that outputs an activation function circuit ACTF[j]. Therefore, the circuit ACTF[j] can be configured to function as an activation function circuit in a neural network, for example. Note that FIG. 5 also shows the array unit ALP and the circuit AFP to show the electrical connection between the circuit ACTF[j] and the surrounding circuits.

[0119] The circuit ACTF[j] shown in FIG. 5 includes, for example, a switch SWR1, a switch SWR1B, a switch SWR2, a switch SWR2B, a circuit IVTR, a circuit IVTRr, a capacitance CRE, and a circuit AC.

[0120] For example, electrical switches such as analog switches and transistors can be applied as each of the switches SWR1, SWR1B, SWR2, and SWR2B. Note that when a transistor is applied to at least one of the switches SWR1, SWR1B, SWR2, and SWR2B, the transistor can be a transistor that can be used for the transistor CRET. Furthermore, other than electrical switches, mechanical switches may also be applied.

[0121] The circuit IVTR is electrically connected to the terminal T1 and a first terminal of the switch SWR1. The second terminal of the switch SWR1 is electrically connected to a first terminal of the capacitor CRE and a first terminal of the switch SWR2. The second terminal of the switch SWR2 is electrically connected to the wiring VCN3. The circuit IVTRr is electrically connected to the terminal T2 and a first terminal of the switch SWR1B. The second terminal of the switch SWR1B is electrically connected to the second terminal of the capacitor CRE and a first terminal of the switch SWR2B. The second terminal of the switch SWR2B is electrically connected to the terminal mbt1 of the circuit AC.

[0122] The wiring VCN3 functions as a wiring that applies a constant voltage. The constant voltage can be, for example, the ground potential GND or a low-level potential. Alternatively, as one example, it can be VDD (high-level potential).

[0123] The circuit AC has a terminal mbt1 and a terminal mbt2. As described above, the circuit AC may be, for example, an analog-to-digital conversion circuit. The circuit AC shown in FIG. 5 senses the potential applied to the terminal mbt1 and outputs an output signal z corresponding to the potential from the terminal mbt2 as a digital signal. j (k)Therefore, for example, if the circuit AC is an analog-to-digital converter that converts to a 1-bit digital signal, there will be one terminal mbt2, and if the circuit AC is an analog-to-digital converter that converts to a k-bit (k is an integer equal to or greater than 2) digital signal, there will be k terminals mbt2. Note that in FIG. 5, the terminal mbt2 is illustrated as a plurality of terminals. As an example, the circuit AC performs analog-to-digital conversion based on a plurality of predetermined potentials, converts the analog potential (or multi-level digital value) of the terminal mbt1 into a digital signal, and outputs it.

[0124] In particular, when the circuit ACTF[j] in Figure 5 is applied as a circuit for the activation function of a neuron in a hierarchical neural network, for example, if the potential of terminal mbt1 of circuit AC during analog-to-digital conversion is lower than the potential provided by wiring VCN3 (if the result of the sum of the products of the first data and the second data is negative), the circuit for the activation function can be configured to output zero instead of outputting that value, thereby making it possible to operate as a circuit for outputting the value of a step function.

[0125] The circuit IVTR is a circuit having a function of converting the current flowing through the wiring OL[j] into a voltage value (or a charge amount). The circuit IVTRr is a circuit having a function of converting the current flowing through the wiring OLB[j] into a voltage value (or a charge amount), and can have a configuration similar to that of the circuit IVTR. As a result, in the circuit ACTF[j] of FIG. 5, the circuit IVTR can convert the current flowing through the wiring OL[j] into a voltage value (or a charge amount) and provide the voltage value to the first terminal of the switch SWR1, and the circuit IVTRr can convert the current flowing through the wiring OLB[j] into a voltage value (or a charge amount) and provide the voltage value to the first terminal of the switch SWR1B.

[0126] The circuit IVTR (circuit IVTRr) can have, for example, the circuit configuration shown in Figures 6A to 6C. Note that in Figures 6A to 6C, in order to distinguish between the circuit IVTR and the circuit IVTRr, the symbols of the wiring OLB[j], the circuit elements included in the circuit IVTRr, and the like are written in parentheses.

[0127] 6A includes a switch SWR3 (switch SWR3B) and a capacitor CRT (capacitor CRTB). A wiring OL[j] (wiring OLB[j]) is electrically connected to a first terminal of the switch SWR3 (switch SWR3B) and a first terminal of the capacitor CRT (capacitor CRTB). A second terminal of the switch SWR3 (switch SWR3B) is electrically connected to a second terminal of the capacitor CRT (capacitor CRTB) and a wiring VCN4.

[0128] As the switch SWR3 and the switch SWR3B, for example, switches that can be applied in the same manner as the above-mentioned switch SWR1, switch SWR1B, switch SWR2, and switch SWR2B can be used.

[0129] For example, the wiring VCN4 functions as a wiring that applies a constant voltage. The constant voltage can be, for example, a high-level potential, a ground potential, or a low-level potential. For example, the wiring VCN4 may be applied with the same potential as the wiring VSO described later. Alternatively, for example, the wiring VCN4 may be electrically connected to the wiring VSO. In other words, the wiring VCN4 and the wiring VSO may be combined into a single wiring.

[0130] In the circuit IVTR (circuit IVTRr) shown in FIG. 6A, by turning on the switch SWR3 (switch SWR3B), electrical continuity can be established between the wiring OL[j] (wiring OLB[j]) and the wiring VCN4, and the constant voltage of the wiring VCN4 can be applied to the wiring OL[j] (wiring OLB[j]). The operation of applying the constant voltage of the wiring VCN4 to the wiring OL[j] (wiring OLB[j]) corresponds to an initial operation for reading information (current, voltage, etc.) from the circuits MP[1,j] to MP[m,j]. Alternatively, it corresponds to an operation for initializing the charge accumulated in the capacitor CRT (capacitor CRTB). Furthermore, by turning off the switch SWR3 (switch SWR3B), the circuit IVTR (circuit IVTRr) shown in FIG. 6A can charge the first terminal of the capacitor CRT with the amount of current flowing through the wiring OL[j] (wiring OLB[j]). That is, the potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through the wiring OL[j] (wiring OLB[j]).

[0131] Furthermore, the amount of current flowing through the wiring OL[j] (wiring OLB[j]) can be, for example, the sum of the currents flowing between the circuits MP[1,j] to MP[m,j] and the wiring OL[j] (wiring OLB[j]). Therefore, by allowing the current flowing between each of the circuits MP[1,j] to MP[m,j] and the wiring OL[j] (wiring OLB[j]) to flow for a certain period of time, the charge stored in the first terminal of the capacitor CRT is determined by the amount of current flowing through the wiring OL[j] (wiring OLB[j]) and the certain period of time. In other words, the voltage that the circuit IVTRr (circuit IVTRr) applies to the first terminal of the switch SWR1 (switch SWR1B) is determined by the amount of current flowing through each of the circuits MP[1,j] to MP[m,j] and the circuit MP[m,j] and the time.

[0132] Incidentally, when the current flowing through the wiring OL[j] (wiring OLB[j]) is converted into a voltage by the parasitic resistance or parasitic capacitance of the wiring OL[j] (wiring OLB[j]), the circuit IVTR (circuit IVTRr) can have the circuit configuration shown in Fig. 6B. That is, the capacitance CRT (capacitor CRTB) can be omitted from the circuit IVTR (circuit IVTRr) of Fig. 6A.

[0133] 6C includes a switch SWR3 (switch SWR3B) and a resistor RRT (resistor RRTB). The wiring OL[j] (wiring OLB[j]) is electrically connected to a first terminal of the switch SWR3 (switch SWR3B) and a first terminal of the resistor RRT (resistor RRTB). The second terminal of the switch SWR3 (switch SWR3B) is electrically connected to a second terminal of the resistor RRT (resistor RRTB) and a wiring VCN4.

[0134] In the circuit IVTR (circuit IVTRr) shown in FIG. 6C, by turning on the switch SWR3 (switch SWR3B), the wiring OL[j] (wiring OLB[j]) and the wiring VCN4 can be brought into a conductive state, and the constant voltage of the wiring VCN4 can be applied to the wiring OL[j] (wiring OLB[j]). The operation of applying the constant voltage of the wiring VCN4 to the wiring OL[j] (wiring OLB[j]) corresponds to the initial operation for reading information (current, voltage, etc.) from the circuits MP[1,j] to MP[m,j]. In addition, in the circuit IVTR (circuit IVTRr) shown in FIG. 6C, by turning off the switch SWR3 (switch SWR3B), the current flowing in the wiring OL[j] (wiring OLB[j]) flows to the wiring VCN4 via the resistor RRT (resistor RRTB) without passing through the switch SWR3 (switch SWR3B). At this time, a voltage corresponding to the resistance value of the resistor RRT (resistor RRTB) and the amount of current is generated between the first terminal and the second terminal of the resistor RRT (resistor RRTB). That is, the potential of the first terminal of the capacitor CRT is determined according to the amount of current flowing through the wiring OL[j] (wiring OLB[j]) and the resistance value of the resistor RRT (resistor RRTB). Note that the switch SWR3 (switch SWR3B) does not necessarily have to be provided.

[0135] Next, an example of a circuit configuration that is different from the circuit ACTF[j] in FIG. 5 and that can be applied to the circuit ACTF[j] in FIG. 2 will be described.

[0136] The circuit ACTF[j] shown in Fig. 7A is an example of a configuration obtained by modifying the circuit configuration of the circuit ACTF[j] in Fig. 5. Specifically, it differs from the circuit ACTF[j] in Fig. 5 in that the terminal mbt1 of the circuit AC is electrically connected to the second terminal of the switch SWR2, and the wiring VCN3 is electrically connected to the second terminal of the switch SWR2B.

[0137] Furthermore, an example of a circuit configuration that can be applied to the circuit ACTF[j] in Fig. 2 is the circuit ACTF[j] shown in Fig. 7B. The circuit ACTF[j] in Fig. 7B includes a switch SWR2, a switch SWR2B, a switch SWR6, a switch SWR6B, a switch SWR7, a switch SWR7B, a capacitance CRE, a circuit IVTR, a circuit IVTRr, and a circuit AC.

[0138] A first terminal of the switch SWR6 is electrically connected to the terminal T1, and a second terminal of the switch SWR6 is electrically connected to a first terminal of the switch SWR7, a first terminal of the switch SWR2, and a first terminal of the capacitor CRE. A second terminal of the switch SWR7 is electrically connected to the circuit IVTR, and a second terminal of the switch SWR2 is electrically connected to the wiring VCN3. A first terminal of the switch SWR6B is electrically connected to the terminal T2, and a second terminal of the switch SWR6B is electrically connected to a first terminal of the switch SWR7B, a first terminal of the switch SWR2B, and a second terminal of the capacitor CRE. A second terminal of the switch SWR7B is electrically connected to the circuit IVTRr, and a second terminal of the switch SWR2B is electrically connected to the circuit AC.

[0139] As the switches SWR6, SWR6B, SWR7, and SWR7B, for example, switches that can be applied in the same manner as the switches SWR1, SWR1B, SWR2, and SWR2B described above can be used.

[0140] For each of the circuit AC, the circuit IVTR, and the circuit IVTRr, refer to the descriptions of the circuit AC, the circuit IVTR, and the circuit IVTRr included in the circuit ACTF[j] of FIG. 5.

[0141] Also, as a circuit configuration applicable to the circuit ACTF[j] of FIG. 2A, for example, it can be the circuit ACTF[j] shown in FIG. 7C. The circuit ACTF[j] of FIG. 7C is configured not to provide the switch SWR7 and the switch SWR2B to the circuit ACTF[j] of FIG. 7B. That is, in the circuit ACTF[j] of FIG. 7C, the second terminal of the switch SWR6 is electrically connected to the circuit IVTR, and the terminal mbt1 of the circuit AC is electrically connected to the second terminal of the capacitor CRE, the second terminal of the switch SWR6B, and the first terminal of the switch SWR7B.

[0142] By applying any one of the circuits ACTF[j] in FIGS. 7A to 7C to the circuit ACTF[j] of FIG. 2, similar to the circuit ACTF[j] of FIG. 5, as a result corresponding to the sum of products of the first data and the second data, the signal z j (k) can be output.

[0143] <Operation Example 2 of the Arithmetic Circuit> Subsequently, an operation example of the circuit ACTF[j] of FIG. 5 will be described. In the description of this operation example, as an example, the arithmetic circuit 110A shown in FIG. 8 is used. The arithmetic circuit 110A is configured by applying the circuit IVTR (circuit IVTRr) of FIG. 6A as the circuit IVTR and the circuit IVTRr included in the circuit ACTF[j] shown in FIG. 5.

[0144] 8 also illustrates, as an example, wirings SRL1, SRL2-1, SRL2-2, and SRL3 as wirings for switching between the on and off states of switches SWR1, SWR2, SWR3, SWR1B, SWR2B, and SWR3B included in circuit ACTF[J]. Specifically, wiring SRL1 is electrically connected to the control terminal of switch SWR1 and the control terminal of switch SWR1B, wiring SRL2-1 is electrically connected to the control terminal of switch SWR2, wiring SRL2-2 is electrically connected to the control terminal of switch SWR2B, and wiring SRL3 is electrically connected to the control terminal of switch SWR3 and the control terminal of switch SWR3B. Note that, for example, some of switches SWR1, SWR2, SWR3, SWR1B, SWR2B, and SWR3B can be omitted in some cases or depending on the situation. That is, for example, the switches SWR1, SWR2, SWR1B, and SWR2B may be configured in a circuit in which some of these switches are always in the on state. Furthermore, for example, by using other switches, the switches SWR3 and SWR3B may be configured in a circuit in which some of these switches are always in the off state. Alternatively, for example, the connections of the switches SWR1, SWR2, SWR3, SWR1B, SWR2B, and SWR3B may be partially changed. Note that, for example, the wiring SRL1, wiring SRL2-1, wiring SRL2-2, or wiring SRL3 may be partially omitted depending on the situation. For example, the wiring SRL2-1 and wiring SRL2-2 may be combined into a single wiring. Alternatively, for example, the wires SRL1 and SRL2-1 (SRL2-2) may be combined into a single wire by reversing the on / off polarities of the switches SWR1 and SWR2 (switch SWR2B). This allows the switches SWR1 and SWR2 (switch SWR2B) to be alternately turned on and off using a single wire.

[0145] 8 also illustrates a node n4 as the electrical connection point between the first terminal of the switch SWR1, the first terminal of the capacitor CRT, and the first terminal of the switch SWR3, and a node n4r as the electrical connection point between the first terminal of the switch SWR1B, the first terminal of the capacitor CRTB, and the first terminal of the switch SWR3B. Also, a node n5 is illustrated as the electrical connection point between the second terminal of the switch SWR1, the first terminal of the capacitor CRE, and the first terminal of the switch SWR2, and a node n5r is illustrated as the electrical connection point between the second terminal of the switch SWR1B, the second terminal of the capacitor CRE, and the first terminal of the switch SWR2B.

[0146] 9 is a timing chart showing an example of the operation of the circuit ACTF[j] of the arithmetic circuit 110A in FIG. 8. The timing chart shows fluctuations in the potentials of the wirings XLS[1] to XLS[m], the wirings SRL1, SRL2-1, SRL2-2, SRL3, the node n4, the node n4r, the node n5, and the node n5r from time T01 to time T08 and in the vicinity thereof. Note that "high" in FIG. 9 indicates a high-level potential, and "low" indicates a low-level potential.

[0147] In this operation example, each of switches SWR1, SWR2, SWR1B, and SWR2B is turned on when a high-level potential is input to the control terminal, and turned off when a low-level potential is input to the control terminal.

[0148] 9 collectively illustrates the wirings XLS[1] to XLS[m]. In the timing chart of FIG. 9 , the periods during which the second data is input to the wirings XLS[1] to XLS[m] are indicated by hatching.

[0149] In this operation example, it is assumed that a current flows from the wiring OL[j] to the circuit MP, and also from the wiring OLB[j] to the circuit MP. Therefore, it is assumed that a wiring (for example, the wiring VE and wiring VEl described in the second embodiment) that applies VSS (low-level potential) is electrically connected to the circuit MP (not shown in FIG. 8), and the constant voltage applied by the wiring VCN4 is VDD (high-level potential). The amount of current flowing from the wiring OL[j] to the circuit MP and the amount of current flowing from the wiring OLB[j] to the circuit MP are determined by the first data stored in the circuit MP and the second data input from the wiring XLS. The amount of current flowing from the wiring OL[j] to the circuit MP and / or the amount of current flowing from the wiring OLB[j] to the circuit MP may be zero. The constant voltage applied by the wiring VCN3 is assumed to be VSS.

[0150] Before time T01, the circuits MP[1,j] to MP[m,j] are each provided with a weighting coefficient w1 as first data. (k-1) j (k) Or even w m (k-1) j (k) is assumed to be held.

[0151] Before time T01, a low-level potential is input to the wirings XLS[1] to XLS[m], and a low-level potential is input to the wirings SRL1, SRL2-1, SRL2-2, and SRL3. The potentials of the nodes n4, n4r, n5, and n5r are set to VSS.

[0152] Between time T01 and time T02, a high-level potential is input to the wirings SRL1 and SRL3. When a high-level potential is input to the wiring SRL1, the switches SWR1 and SWR1B are turned on, and when a high-level potential is input to the wiring SRL3, the switches SWR3 and SWR3B are turned on.

[0153] Furthermore, between time T01 and time T02, a low-level potential is input to the wirings SRL2-1 and SRL2-2. When a low-level potential is input to the wirings SRL2-1 and SRL2-2, the switches SWR2 and SWR2B are turned off.

[0154] As a result, conduction occurs between the wiring VCN4 and the wiring OL[j], and between the wiring VCN4 and the first terminal of the capacitor CRE. Conduction also occurs between the wiring VCN4 and the wiring OLB[j], between the wiring VCN4 and the second terminal of the capacitor CRE, and between the wiring VCN4 and the terminal mbt1. Conduction also occurs between the wiring VCN3 and the first terminal of the capacitor CRE. Therefore, the potentials of the nodes n4, n4r, n5, and n5r are all VDD.

[0155] Between time T02 and time T03, a low-level potential is input to the wiring SRL3. By inputting a low-level potential to the wiring SRL3, the switches SWR3 and SWR3B are turned off. As a result, there is no conduction between the wiring VCN4 and the wiring OL[j], there is no conduction between the wiring VCN4 and the wiring OLB[j], and the nodes n4, n5, n4r, and n5r are floating.

[0156] Between time T03 and time T04, the neuron signal z1 is sent as second data to each of the circuits MP[1,j] to MP[m,j] of the array unit ALP. (k-1) ~z m (k-1) will be sent.

[0157] As a result, in the circuit MP[i,j], the weight coefficient w i (k-1) j (k) and the neuron's signal z1 (k-1)In response to this, a current flows between one of the wirings OL[j] and OLB[j] and the circuit MC, and a current flows between the other of the wirings OL[j] and OLB[j] and the circuit MCr. Here, the sum of the currents flowing between each of the circuits MP[1,j] to MP[m,j] and the wiring OL[j] is expressed as I out [j], and the sum of the currents flowing between each of the circuits MP[1,j] to MP[m,j] and the wiring OLB[j] is I Bout Let's say [j].

[0158] At this time, the potentials of the nodes n4 and n5 are reduced by the current flowing through the wiring OL[j], and the potentials of the nodes n4r and n5r are reduced by the current flowing through the wiring OLB[j].

[0159] In this example, I Bout I rather than [j] out [j] is assumed to be large. Therefore, the decrease in the potentials of the nodes n4 and n5 from time T03 to time T04 is assumed to be larger than the decrease in the potentials of the nodes n4r and n5r. In the timing chart of FIG. 9, at time T04, the potentials of the nodes n4 and n5 are V Iout The potential V IBout It is said that the level has decreased to

[0160] Also, at time T04, a low-level potential is input to the line SRL1. By inputting a low-level potential to the line SRL1, the switches SWR1 and SWR1B are turned off. As a result, a non-conductive state is established between the first terminal of the capacitor CRE and the line OL[j], and a non-conductive state is established between the second terminal of the capacitor CRE and the line OLB[j]. As a result, the decrease in the potential at the first terminal (node ​​n5) of the capacitor CRE stops, and the decrease in the potential at the second terminal (node ​​n5r) of the capacitor CRE stops. Furthermore, the voltage between the first terminal (node ​​n5) of the capacitor CRE and the second terminal (node ​​n5r) of the capacitor CRE is maintained. Note that the potentials of the nodes n4 and n4r continue to decrease from before time T04.

[0161] Between time T05 and time T06, a low-level potential is input to each of the wirings XLS[1] to XLS[m]. As a result, a neuron signal z1 corresponding to the second data is input to each of the circuits MP[1,j] to MP[m,j] of the array unit ALP. (k-1) ~z m (k-1) As a result, the current flowing from the wiring OL[j] to the circuit MP stops, and the current flowing from the wiring OLB[j] to the circuit MP stops. As a result, the potentials of the nodes n4 and n4r stop decreasing.

[0162] Between time T06 and time T07, a high-level potential is input to the line SRL2-1. When a high-level potential is input to the line SRL2-1, the switch SWR2 is turned on. As a result, conduction is established between the first terminal of the capacitor CRE and the line VCN3, and the potential of the first terminal (node ​​n5) of the capacitor CRE becomes VSS.

[0163] By the way, since the second terminal (node ​​n5r) of the capacitor CRE is in a floating state, the potential of the first terminal (node ​​n5) of the capacitor CRE is V Iout The potential of the second terminal (node ​​n5r) of the capacitor CRE also changes due to capacitive coupling when the potential of the first terminal of the capacitor CRE changes from V to VSS. The amount of change in potential due to capacitive coupling is determined according to the capacitive coupling coefficient. However, for the sake of simplicity, in this specification, it is assumed that the potential of the first terminal of the capacitor CRE is V Iout When the voltage changes from V to VSS, the potential of the second terminal of the capacitor CRE becomes V IBout -(V Iout -VSS) (In the timing chart of Figure 9, V OP In other words, this change in potential corresponds to the case where the capacitive coupling coefficient determined according to the capacitance CRE and the peripheral circuit elements is set to 1.

[0164] Between time T07 and time T08, a high-level potential is input to the line SRL2-2. When a high-level potential is input to the line SRL2-2, the switch SWR2B is turned on. As a result, conduction is established between the second terminal (node ​​n5r) of the capacitor CRE and the terminal mbt1.

[0165] At this time, the terminal mbt1 of the circuit AC is connected to the second terminal (node ​​n5r) of the capacitor CRE, V OP is entered.

[0166] As a result, the circuit AC is at the potential V input to the terminal mbt1. OP As a digital signal corresponding to z j (k) A signal with a value of is output.

[0167] z j (k) is the potential V according to the amount of current flowing through the wiring OL[j] Iout and the potential V according to the amount of current flowing through the wiring OLB[j] IBout The value output is based on the potential difference between V and V. Iout , potential V IBout I out [j] and I Bout It is determined by [j] and the time that the switches SWR1 and SWR2 are in the ON state (the time from time T03 to time T04). out [j] and I Bout [j] is the first data w1 which is the first data held in each of the circuits MP[1,j] to MP[m,j]. (k-1) j (k) Or even w m (k-1) j (k) and the value z1 of the signal which is the second data input to the circuits MP[1,j] to MP[m,j]. (k-1) ~z m (k-1) The result of the multiplication and addition operation of and, that is, u in equation (1.2) j (k) On the other hand, the current is proportional to the potential VIout , potential V IBout Since changes depending on the time period during which the switches SWR1 and SWR2 are in the ON state (the time period from time T03 to time T04), it is preferable that this time period be set appropriately depending on the circuit AC.

[0168] In this example, the current amount I out [j] and I Bout By converting each of [j] into a potential and inputting the potential difference into the AC circuit, z j (k) In other words, by using the circuit AC as a circuit of the activation function in a hierarchical neural network, the value of z j (k) The value of z in equation (1.4) j (k) The potential can be set to a value corresponding to:

[0169] By the way, between time T07 and time T08, when the switch SWR2B is turned on, strictly speaking, taking into account the influence of parasitic resistance and parasitic capacitance, the potential input to the terminal mbt1 is V OP In this case, it is preferable that the circuit AC is designed to appropriately correct the potential input to the terminal mbt1 in consideration of the resistance of the wiring between the second terminal of the capacitor CRE and the terminal mbt1.

[0170] In addition, in the above example, I Bout I rather than [j] out We have explained the case where [j] is large. On the other hand, I out I rather than [j] Bout When [j] is large, at time T04, the potential V Iout The potential of node n5r is V IBoutTherefore, when the switch SWR2 is turned on between time T06 and time T07, the potential of the node n5r becomes lower than VSS due to the capacitive coupling of the capacitor CRE. Then, between time T07 and time T08, a potential lower than VSS is input to the terminal mbt1. At this time, as a configuration of the circuit AC, for example, when the output signal z j (k) This is the activation function f(u in a hierarchical neural network) j (k) ) but u j (k) is equivalent to functioning as a ramp function that outputs 0 when is negative.

[0171] <Configuration example 3 of an arithmetic circuit> Note that one embodiment of the present invention is not limited to the circuit configuration of the circuit ACTF[j] in FIG. 5 included in the arithmetic circuit. For example, the circuit ACTF[j] in FIG. 5 included in the semiconductor device (arithmetic circuit) of one embodiment of the present invention can be changed to the circuit configuration shown in the circuit ACTF[j] in FIG. 10. The circuit ACTF[j] in FIG. 10 includes switches SWR1, SWR1B, SWR2, SWR2B, SWR3, SWR3B, SWR4, SWR4B, loads LE, LEB, operational amplifiers OP, OPB, and a circuit AC. Note that descriptions of parts that overlap with the circuit ACTF[j] shown in FIG. 5 will be omitted.

[0172] The switches SWR3, SWR3B, SWR4, and SWR4B may each be a switch that can be applied in the same manner as the switches SWR1, SWR1B, SWR2, and SWR2B, for example.

[0173] A first terminal of the switch SWR3 is electrically connected to the terminal T1, a first terminal of the switch SWR4, and a first terminal of the load LE. A second terminal of the switch SWR3 is electrically connected to the wiring VCN4. A non-inverting input terminal of the operational amplifier OP is electrically connected to the wiring Vref1L, an inverting input terminal of the operational amplifier OP is electrically connected to the second terminal of the switch SWR4, and an output terminal of the operational amplifier OP is electrically connected to the second terminal of the load LE and the first terminal of the switch SWR1.

[0174] A first terminal of the switch SWR3B is electrically connected to the terminal T2, a first terminal of the switch SWR4B, and a first terminal of the load LEB. A first terminal of the switch SWR3B is electrically connected to the wiring VCN4. A non-inverting input terminal of the operational amplifier OPB is electrically connected to the wiring Vref2L, an inverting input terminal of the operational amplifier OPB is electrically connected to the second terminal of the switch SWR4B, and an output terminal of the operational amplifier OPB is electrically connected to the second terminal of the load LEB and the first terminal of the switch SWR1B.

[0175] The wiring Vref1L and wiring Vref2L function as wirings that supply the same voltage or different voltages. Therefore, the wiring Vref1L and wiring Vref2L can sometimes be combined into one wiring.

[0176] The circuit ACTF[j] in Figure 10 can perform initial operation of applying a constant voltage of the wiring VCN4 to the wiring OL[j] (wiring OLB[j]), similar to Figure 10, by turning on the switch SWR3 (switch SWR3B) and turning off the switch SWR4 (switch SWR4B).

[0177] In the circuit ACTF[j] of FIG. 10, the loads LE and LEB can be, for example, resistors or capacitors. In particular, by using capacitors as the loads LE and LEB, the operational amplifier OP and the load LE, and the operational amplifier OPB and the load LEB, respectively, function as integrating circuits. That is, by turning off the switches SWR3 and SWR3B and turning on the switches SWR4 and SWR4B, charge is stored in the respective capacitors (load LE, load LEB) according to the amount of current flowing through the wiring OL[j] or wiring OLB[j]. That is, the currents flowing from the wirings OL[j] and OLB[j] are converted into voltages by the integrating circuits, and the respective voltages are output from the output terminals of the operational amplifiers OP and OPB.

[0178] By treating the loads LE and LEB as capacitances, the circuit ACTF[j] in Figure 10 can convert the amount of charge flowing through the wiring OL[j] into a voltage value and provide that voltage value to the first terminal of the switch SWR1, and can also convert the amount of charge flowing through the wiring OLB[j] into a voltage value and provide that voltage value to the first terminal of the switch SWR1B.

[0179] Furthermore, the circuit ACTF[j] in Fig. 5 can be changed to the circuit configuration shown in the circuit ACTF[j] in Fig. 11A. The circuit ACTF[j] in Fig. 11A includes a switch SWR3, a switch SWR3B, a switch SWR4, a switch SWR4B, a switch SWR5, a load LEA, a load LEAB, an operational amplifier OPA, and a circuit AC.

[0180] The switches SWR3, SWR3B, SWR4, SWR4B, and SWR5 may each be a switch that can be applied in the same manner as the switches SWR1, SWR1B, SWR2, and SWR2B, for example.

[0181] The first terminal of the switch SWR3 is electrically connected to the terminal T1, the first terminal of the switch SWR4, and the first terminal of the load LEA. The second terminal of the switch SWR3 is electrically connected to the wiring VCN4. The inverting input terminal of the operational amplifier OP is electrically connected to the second terminal of the switch SWR4. The second terminal of the load LEA is electrically connected to the first terminal of the switch SWR5. The first terminal of the switch SWR3B is electrically connected to the terminal T2, the first terminal of the switch SWR4B, and the first terminal of the load LEAB. The second terminal of the switch SWR3B is electrically connected to the wiring VCN4. The non-inverting input terminal of the operational amplifier OP is electrically connected to the second terminal of the switch SWR4B. The second terminal of the load LEAB is electrically connected to the wiring VCN5. The output terminal of the operational amplifier OP is electrically connected to the second terminal of the switch SWR5 and the terminal mbt1 of the circuit AC.

[0182] The wiring VCN5 functions as a wiring that applies a constant voltage, which may be, for example, a ground potential or a low-level potential.

[0183] The circuit ACTF[j] in Figure 11A can perform initial operation of applying a constant voltage of the wiring VCN4 to the wiring OL[j] (wiring OLB[j]), as in Figure 10, by turning on the switch SWR3 (switch SWR3B), turning off the switch SWR4 (switch SWR4B), and turning off the switch SWR5.

[0184] In the circuit ACTF[j] of FIG. 11A, the loads LEA and LEAB can be, for example, resistors or capacitors. When a subtraction circuit is configured using the operational amplifier OPA, the loads LEA and LEAB can be resistors. By using resistors for the loads LEA and LEAB, a voltage corresponding to the difference in current flowing between the first and second terminals of the load LEA and between the first and second terminals of the load LEAB can be output from the output terminal of the operational amplifier OPA. As a result, by turning off the switches SWR3 and SWR3B, turning on the switches SWR4 and SWR4B, and turning on the switch SWR5, a voltage corresponding to the difference in current flowing through the wiring OL[j] and the wiring OLB[j] can be output from the output terminal of the operational amplifier OPA.

[0185] The voltage output from the output terminal of the operational amplifier OPA is input to the input terminal of the circuit AC. This allows the analog voltage output from the output terminal of the operational amplifier OPA to be converted into a digital signal by the circuit AC. The digital signal is then converted into the calculated value z of the neuron signal. j (k) can be output from terminal mbt2 of circuit AC as follows.

[0186] 11A may be modified to form the circuit ACTF[j] shown in FIG. 11B. The circuit ACTF[j] shown in FIG. 11B is the circuit ACTF[j] shown in FIG. 11A, but without the circuit AC. This allows the analog voltage output from the output terminal of the operational amplifier OPA to be converted into the calculated value z of the neuron signal. j (k) It can be said that:

[0187] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0188] (Embodiment 2) In this embodiment, a description will be given of peripheral circuit configurations of the arithmetic circuit 110, the arithmetic circuit 110A, and the arithmetic circuit 120 described in the above embodiment, and an example of operation of the arithmetic circuits.

[0189] <Configuration example 1 of an arithmetic circuit> 12 is a semiconductor device having, as an example, an array section ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP. The arithmetic circuit 130 is a neuron N1 in the k-th layer in FIGS. 1A and 1B. (k) Neuron N n (k) The signal z1 input to (k-1) ~z m (k-1) and neuron N1 (k) Neuron N n (k) The signal z1 output from each (k) ~z n (k) This is a circuit that generates

[0190] Note that the entire arithmetic circuit 130, or a part thereof, may be used for purposes other than neural networks or AI. For example, when performing product-sum operations or matrix operations in graphics calculations or scientific calculations, the entire arithmetic circuit 130, or a part thereof, may be used for the processing. In other words, the entire arithmetic circuit 130, or a part thereof, may be used not only for AI calculations but also for general calculations. Furthermore, for example, the entire arithmetic circuit 130, or a part thereof, may be used for purposes such as a storage device.

[0191] For example, the circuit ILD is electrically connected to wirings IL[1] to IL[n] and ILB[1] to ILB[n]. For example, the circuit WLD is electrically connected to wirings WLS[1] to WLS[m]. For example, the circuit XLD is electrically connected to wirings XLS[1] to XLS[m]. For example, the circuit AFP is electrically connected to wirings OL[1] to OL[n] and OLB[1] to OLB[n].

[0192] <<Array section ALP>> The array unit ALP has, for example, m×n circuits MP. The circuits MP are, for example, arranged in a matrix of m rows and n columns within the array unit ALP. In FIG. 12, the circuit MP located in the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) is represented as circuit MP[i,j]. However, in FIG. 12, the circuit MP[1,1], circuit MP[m,1], circuit MP[i,j], circuit MP[1,n], and circuit MP[m,n] are selectively illustrated.

[0193] As an example, the circuit MP[i,j] is electrically connected to wiring IL[j], wiring ILB[j], wiring WLS[i], wiring XLS[i], wiring OL[j], and wiring OLB[j].

[0194] For example, the circuit MP[i,j] has the same functions as the circuits MP[1,j] to MP[m,j] described in the above embodiment. Furthermore, the circuit MP[i,j] has a function of acquiring a weighting coefficient (first data) held in the circuit MP[i,j] from the wiring IL[j] and the wiring ILB[j]. Note that although FIG. 12 illustrates an example in which the wiring IL[j] and the wiring ILB[j] are provided, one embodiment of the present invention is not limited thereto. Only one of the wiring IL[j] and the wiring ILB[j] may be provided.

[0195] The circuits MP[1,1] to MP[m,n] will be specifically described later.

[0196] <<Circuit XLD>> 12, for example, a neuron N1 (k-1) Neuron N m (k) z1, the calculated value output from (k-1) ~z m (k-1) (It may be called first data or second data. Here, it is called second data.) Specifically, the circuit XLD supplies the neurons N i (k-1) The second data z output from i (k-1) Information (for example, a potential, a current value, or the like) corresponding to the wiring XLS[i] is supplied through the wiring XLS[i]. Note that although the example in which the wiring XLS[i] is provided is shown, one embodiment of the present invention is not limited to this. For example, in the arithmetic circuit 130 in FIG. 12, the wiring XLS[i] may be a plurality of wirings.

[0197] <<Circuit WLD>> For example, the circuit WLD in FIG. 12 has a function of selecting a circuit MP to which information (e.g., a potential, a resistance value, a current value, etc.) corresponding to a weighting coefficient (sometimes referred to as first data or second data; here, referred to as first data) input from the circuit ILD is to be written. For example, when writing information (e.g., a potential, a resistance value, a current value, etc.) to the circuits MP[i,1] to MP[i,n] located in the i-th row of the array portion ALP, the circuit WLD may supply, to the wiring WLS[i], a signal for turning on or off the write switching elements included in the circuits MP[i,1] to MP[i,n] and supply, to the wiring WLS, a potential for turning off the write switching elements included in the circuits MP other than the i-th row. Note that although an example in which the wiring WLS[i] is provided is shown, one embodiment of the present invention is not limited thereto. In addition to the wiring WLS[i], for example, a wiring for transmitting an inverted signal of a signal input to the wiring WLS[i] may be provided separately. That is, the wiring WLS[i] may be replaced with a plurality of wirings. Note that the circuit WLD may be arranged as a separate circuit from the circuit XLD, but one embodiment of the present invention is not limited to this. For example, the circuit WLD may be integrated with the circuit XLD.

[0198] <<Circuit AFP>> The circuit AFP in FIG. 12 includes, for example, circuits ACTF[1] to ACTF[n]. For example, the circuit ACTF[j] described in the above embodiment can be applied to the circuits ACTF[1] to ACTF[n]. As a result, for example, the circuits ACTF[1] to ACTF[n] can generate signals according to the respective pieces of information (e.g., potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j]. For example, the circuits ACTF[1] to ACTF[n] compare the respective pieces of information (e.g., potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j] and generate signals according to the comparison results. The signals are transmitted to the neuron N j (k) The signal z output from j (k)That is, the circuits ACTF[1] to ACTF[n] function as, for example, circuits that perform the calculation of the activation function of the neural network described above.

[0199] <<Circuit MP>> Here, an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 130 will be described.

[0200] FIG. 13A shows an example configuration of a circuit MP[i,j] applicable to the arithmetic circuit 130. The circuit MP[i,j] includes, for example, a circuit MC and a circuit MCr. The circuit MC and the circuit MCr are circuits that calculate the product of first data and second data in the circuit MP. The circuit MC can have the same configuration as the circuit MCr or a different configuration from the circuit MCr. Therefore, the circuit MCr is designated with an "r" in order to distinguish it from the circuit MC. The circuit elements included in the circuit MCr, which will be described later, are also designated with an "r."

[0201] For example, the circuit MC has a holding unit HC, and the circuit MCr has a holding unit HCr. The holding unit HC and the holding unit HCr each have a function of holding information (for example, potential, resistance value, current value, etc.). Note that the first data w set in the circuit MP[i,j] i (k-1) j (k) is determined according to the information (for example, potential, resistance value, current value, etc.) held in each of the holding units HC and HCr. i (k-1) j (k) The wiring OL[j] and the wiring OLB[j] are electrically connected to supply various pieces of information (for example, potential, resistance value, current value, etc.) according to the above.

[0202] 13A, the circuit MP[i,j] is electrically connected to the wiring VE[j] and the wiring VEn[j]. The wiring VE[j] and the wiring VEn[j] function as wirings that supply a constant voltage. In addition, as an example, a current flows from the wiring OL through the circuit MC to the wiring VE[j]. In addition, as an example, a current flows from the wiring OLB through the circuit MCr to the wiring VEn[j].

[0203] The wiring WL[i] shown in FIG. 13A corresponds to the wiring WLS[i] in FIG. 12. The wiring WL[i] is electrically connected to the holding unit HC and the holding unit HCr. The first data w i (k-1) j (k) When writing information (for example, a potential, a resistance value, a current value, etc.) according to the first data w, a predetermined potential is supplied to the wiring WL[i], thereby bringing the wiring OL[j] and the holding unit HC into a conductive state, and bringing the wiring OLB[j] and the holding unit HCr into a conductive state. i (k-1) j (k) By supplying a potential or the like according to the data w, the potential or the like can be input to each of the holding units HC and HCr. After that, a predetermined potential is supplied to the wiring WL[i] to make the wiring IL[j] and the holding unit HC non-conductive, and also to make the wiring ILB[j] and the holding unit HCr non-conductive. Then, the first data w is input to each of the holding units HC and HCr. i (k-1) j (k) Each current according to the above is maintained.

[0204] For example, the first data w i (k-1) j (k) Consider the case where the first data w takes one of the three values ​​"-1", "0", or "1". i (k-1) j (k)When the first data w is "1", for example, a predetermined potential is held in the holding unit HC so that a current corresponding to "1" flows from the wiring IL[j] to the wiring VE[j] via the circuit MC, and a potential V0 is held in the holding unit HCr so that a current does not flow from the wiring ILB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is "-1", for example, the potential V0 is held in the holding unit HC so that no current flows from the wiring IL[j] to the wiring VE[j] via the circuit MC, and a predetermined potential is held in the holding unit HCr so that a current corresponding to "-1" flows from the wiring ILB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is "0", for example, the potential V0 is held in the holding unit HC so that no current flows from the wiring IL[j] to the wiring VE[j] via the circuit MC, and the potential V0 is held in the holding unit HCr so that no current flows from the wiring ILB[j] to the wiring VE[j] via the circuit MCr. Note that the potential V0 can be the potential provided by the wiring VCN in the description of FIG. 14A, which will be described later.

[0205] As another example, the first data w i (k-1) j (k) Let us consider the case where the first data w is an analog value, specifically, a "negative analog value", "0", or a "positive analog value". i (k-1) j (k) is a "positive analog value," for example, a predetermined potential is held in the holding unit HC so that an analog current corresponding to the "positive analog value" flows from the wiring IL[j] to the wiring VE[j] via the circuit MC, and a potential V0 is held in the holding unit HCr so that a current does not flow from the wiring ILB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k)is a "negative analog value," for example, a potential V0 is held in the holding unit HC so that no current flows from the wiring IL[j] to the wiring VE[j] via the circuit MC, and a predetermined potential is held in the holding unit HCr so that an analog current corresponding to the "negative analog value" flows from the wiring ILB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) is "0", for example, the potential V0 is held in the holding unit HC so that no current flows from the wiring IL[j] to the wiring VE[j] via the circuit MC, and the potential V0 is held in the holding unit HCr so that no current flows from the wiring ILB[j] to the wiring VE[j] via the circuit MCr. Note that the potential V0 can be the potential provided by the wiring VCN in the description of FIG. 14A described later, similar to the previous example.

[0206] Furthermore, as an example, the circuit MC has a function of outputting a current, a voltage, etc. corresponding to the information (e.g., potential, resistance value, or current value) held in the holding unit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of outputting a current, a voltage, etc. corresponding to the information (e.g., potential, resistance value, or current value) held in the holding unit HCr to the other of the wiring OL[j] or the wiring OLB[j]. For example, when a first potential is held in the holding unit HC, the circuit MC flows a current having a first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE, and when a second potential is held in the holding unit HC, the circuit MC flows a current having a second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE. Similarly, when a first potential is held in the holding unit HCr, the circuit MCr flows a current having a first current value from the wiring OL[j] or wiring OLB[j] to the wiring VE, and when a second potential is held in the holding unit HCr, the circuit MCr flows a current having a second current value from the wiring OL[j] or wiring OLB[j] to the wiring VE. The magnitudes of the first current value and the second current value are respectively determined by the first data w i (k-1) j (k)The first current value is determined by the value of . As an example, the first current value may be greater than or less than the second current value. Furthermore, as another example, one of the first current value and the second current value may be zero current, i.e., the current value may be 0. Alternatively, the current having the first current value and the current having the second current value may flow in different directions.

[0207] In particular, for example, the first data w i (k-1) j (k) When the first data w takes one of the three values ​​"-1", "0", and "1", it is preferable to configure the circuits MC and MCr so that either the first current value or the second current value becomes zero. i (k-1) j (k) takes an analog value, for example, a "negative analog value," "0," or a "positive analog value," the first current value or the second current value can also take an analog value, for example.

[0208] However, when the current flowing from the wiring OL[j] or the wiring OLB[j] (from the wiring IL[j]) to the wiring VE[j] through the circuit MC is made equal to the current flowing from the wiring OL[j] or the wiring OLB[j] (from the wiring ILB[j]) to the wiring VEn[j] through the circuit MCr, the potential held in the circuit MC may not be equal to the potential held in the circuit MCr because the characteristics of the transistors may vary due to a manufacturing process of the transistors, etc. In the semiconductor device of one embodiment of the present invention, even if the characteristics of the transistors vary, the amount of current flowing from the wiring OL[j] or the wiring OLB[j] (from the wiring IL[j]) to the wiring VE[j] through the circuit MC may be made approximately equal to the amount of current flowing from the wiring OL[j] or the wiring OLB[j] (from the wiring ILB[j]) to the wiring VEn[j] through the circuit MCr.

[0209] In this specification, the current or voltage corresponding to the information (e.g., potential, resistance value, or current value) stored in the storage unit HC or storage unit HCr may be a positive current or voltage, a negative current or voltage, a zero current or zero voltage, or a mixture of positive, negative, and zero.

[0210] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 13A correspond to the wiring XLS[i] in FIG. 12. Note that the second data z i (k-1) For example, the second data z i (k-1) Each potential corresponding to the above is input.

[0211] For example, the circuits MC and MCr transmit the first data w to the wirings OL[j] and OLB[j] in response to a potential or a current input to the wirings X1L[i] and X2L[i]. i (k-1) j (k) and the second data z i (k-1) and outputs a current or potential according to the product of these. As a specific example, the destination of the current output from the circuit MC and the circuit MCr is determined by the potentials of the wiring X1L[i] and the wiring X2L[i]. For example, the circuit MC and the circuit MCr are configured so that the current output from the circuit MC flows to either the wiring OL[j] or the wiring OLB[j], and the current output from the circuit MCr flows to the other wiring OL[j] or the wiring OLB[j]. In other words, the currents output from the circuit MC and the circuit MCr do not flow through the same wiring, but through different wirings. Note that, as an example, there may be cases where no current flows from the circuit MC or the circuit MCr to either the wiring OL[j] or the wiring OLB[j].

[0212] For example, the second data zi (k-1) As an example, consider the case where the second data z i (k-1) is "1", the circuit MP brings the circuit MC and the wiring OL[j] into a conductive state, and brings the circuit MCr and the wiring OLB[j] into a conductive state. i (k-1) is "-1", the circuit MP brings the circuit MC and the wiring OLB[j] into a conductive state, and brings the circuit MCr and the wiring OL[j] into a conductive state. i (k-1) When is "0", in order to prevent the current output by each of the circuits MC and MCr from flowing to either the wiring OL[j] or the wiring OLB[j], the circuit MP brings the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state, and brings the circuit MCr and the wiring OL[j] and the circuit MC and the wiring OLB[j] into a non-conductive state.

[0213] An example of the above operations is shown below. i (k-1) j (k) When the first data w is "1", a current may flow from the wiring OL[j] or wiring OLB[j] to the wiring VE[j] via the circuit MC, and a current does not flow from the wiring OL[j] or wiring OLB[j] to the wiring VE[j] via the circuit MCr. i (k-1) j (k) When the second data z is "-1", current may not flow from the wiring OL[j] or wiring OLB[j] to the wiring VE[j] via the circuit MC, and current may flow from the wiring OL[j] or wiring OLB[j] to the wiring VEr[j] via the circuit MCr. i (k-1) When the second data z is "1", the circuit MC and the wiring OL[j], and the circuit MCr and the wiring OLB[j] are in a conductive state. i (k-1)When the first data w is "-1", the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j] are in a conductive state. i (k-1) j (k) and the second data z i (k-1) When the product of the first data w is a positive value, a current flows from the wiring OL[j] to the wiring VE[j] via the circuit MCr, or a current flows from the wiring OL[j] to the wiring VEn[j] via the circuit MCr. i (k-1) j (k) and the second data z i (k-1) When the product of the first data w is a negative value, either a current flows from the wiring OL[j] to the wiring VEr[j] via the circuit MCr, or a current flows from the wiring OLB[j] to the wiring VE[j] via the circuit MC. i (k-1) j (k) and the second data z i (k-1) When the product is zero, no current flows from the wiring OL[j] or wiring OLB[j] to the wiring VE[j], and no current flows from the wiring OL[j] or wiring OLB[j] to the wiring VEr[j].

[0214] To take the above example as a specific example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "1", for example, a current I1[i,j] having a first current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value can be set to zero, that is, no current flows from the circuit MCr to the wiring OLB[j]. i (k-1) j (k) is "-1", and the second data z i(k-1) When the first data w is "1", for example, a current I1[i,j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a first current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value can be set to zero, for example, meaning that no current flows from the circuit MC to the wiring OL[j]. i (k-1) j (k) is "0", and the second data z i (k-1) is "1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OLB[j]. In this case, the magnitude of the second current value can be, for example, zero, that is, no current flows from the circuit MC to the wiring OL[j], and no current flows from the circuit MCr to the wiring OLB[j].

[0215] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1) When the first data w is "-1", a current I1[i,j] having a first current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value can be set to zero, for example, meaning that no current flows from the circuit MCr to the wiring OL[j]. i (k-1) j (k) is "-1", and the second data z i (k-1) When the first data w is "-1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a first current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value can be set to zero, for example, meaning that no current flows from the circuit MC to the wiring OLB[j]. i (k-1)j (k) is "0", and the second data z i (k-1) is "-1", a current I1[i,j] having a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i,j] having a second current value flows from the circuit MCr to the wiring OL[j]. In this case, the magnitude of the second current value can be, for example, zero, that is, no current flows from the circuit MC to the wiring OLB[j], and no current flows from the circuit MCr to the wiring OL[j].

[0216] Also, the second data z i (k-1) When the first data w is "0", for example, the circuit MC and the wiring OL[j] and the circuit MC and the wiring OLB[j] are in a non-conductive state. Similarly, the circuit MCr and the wiring OL[j] and the circuit MCr and the wiring OLB[j] are in a non-conductive state. Therefore, the first data w i (k-1) j (k) Whatever the value of is, no current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j].

[0217] In this way, as an example, the first data w i (k-1) j (k) and the second data z i (k-1) When the product of the first data w and the second data w is a positive value, a current flows from either the circuit MC or the circuit MCr to the wiring OL[j]. i (k-1) j (k) When is a positive value, current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) When the first data w is a negative value, a current flows from the circuit MCr to the wiring OL[j]. i (k-1) j (k) and the second data zi (k-1) When the product of w and w is a negative value, a current flows from either the circuit MC or the circuit MCr to the wiring OLB[j]. i (k-1) j (k) When is a positive value, current flows from the circuit MC to the wiring OLB[j], and the first data w i (k-1) j (k) If is a negative value, a current flows from the circuit MCr to the wiring OLB[j]. Therefore, the sum of the currents output from the multiple circuits MC or circuits MCr connected to the wiring OL[j] flows through the wiring OL[j]. In other words, a current that is the sum of positive values ​​flows through the wiring OL[j]. On the other hand, the sum of the currents output from the multiple circuits MC or circuits MCr connected to the wiring OLB[j] flows through the wiring OLB[j]. In other words, a current that is the sum of negative values ​​flows through the wiring OLB[j]. As a result of the above operation, a product-sum operation can be performed by using the total current value flowing through the wiring OL[j], i.e., the sum of positive values, and the total current value flowing through the wiring OLB[j], i.e., the sum of negative values. For example, if the total current value flowing through the wiring OL[j] is greater than the total current value flowing through the wiring OLB[j], the product-sum operation result can be determined to be a positive value. If the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j], it can be determined that the result of the sum-of-products operation is a negative value. If the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same, it can be determined that the result of the sum-of-products operation is a zero value. Note that, if it is considered to also function as an activation function, when it is determined that the result of the sum-of-products operation is a negative value, it may be output as a zero value. In other words, it may be determined that the result of the sum-of-products operation is a zero value not only when the total current value flowing through the wiring OL[j] and the total current value flowing through the wiring OLB[j] are approximately the same, but also when the total current value flowing through the wiring OL[j] is smaller than the total current value flowing through the wiring OLB[j].

[0218] In addition, the second data z i (k-1) The same operation can be performed when the first data w is any one of two values ​​of "-1", "0", and "1", for example, when the first data w is either "-1" or "1", or when the first data w is either "0" or "1". i (k-1) j (k) The same operation can be performed when the value is any two of "-1", "0", and "1", for example, when the value is "-1" or "1", or when the value is "0" or "1".

[0219] In addition, the first data i (k-1) j (k) may take an analog value or a multi-bit (multi-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may also be, for example, the first data w i (k-1) j (k) It becomes an analog value according to the absolute value of the value.

[0220] Next, an example of a modification of the circuit MP[i,j] in Fig. 13A will be described. Note that, for the modification of the circuit MP[i,j], differences from the circuit MP[i,j] in Fig. 13A will be mainly described, and descriptions of parts common to the circuit MP[i,j] in Fig. 13A may be omitted.

[0221] The circuit MP[i,j] shown in FIG. 13B has a configuration in which the wiring IL[i] and the wiring ILB[i] in the circuit MP[i,j] of FIG. 13A are combined into a wiring IL[j].

[0222] The wirings W1L[i] and W2L[i] shown in Fig. 13B correspond to the wirings WLS[i] in Fig. 12. The wirings W1L[i] are electrically connected to the holding unit HC, and the wirings W2L[i] are electrically connected to the holding unit HCr.

[0223] Moreover, the wiring IL[j] is electrically connected to the holding portion HC and the holding portion HCr.

[0224] In the circuit MP[i,j] of Fig. 13B, when different information (e.g., voltage, resistance, current, etc.) is stored in the storage unit HC and the storage unit HCr, it is preferable to store the information in the storage unit HC and the storage unit HCr sequentially rather than simultaneously. For example, when the first data w i (k-1) j (k) Consider a case where the first information can be expressed by storing the first information in the storage unit HC and the second information in the storage unit HCr. First, a predetermined potential is applied to each of the wires W1L[i] and W2L[i], thereby establishing a conductive state between the storage unit HC and the wire IL[j] and establishing a non-conductive state between the storage unit HCr and the wire IL[j]. Next, the first information can be provided to the storage unit HC by supplying a current, voltage, etc. corresponding to the first information to the wire IL[j]. After that, a predetermined potential is applied to each of the wires W1L[i] and W2L[i], thereby establishing a non-conductive state between the storage unit HC and the wire IL[j] and establishing a conductive state between the storage unit HCr and the wire IL[j]. Then, a current, voltage, etc. corresponding to the second information is supplied to the wire IL[j], thereby providing the second information to the storage unit HCr. As a result, the circuit MP[i,j] stores w as the first data. i (k-1) j (k) can be set.

[0225] In addition, when the holding unit HC and the holding unit HCr hold substantially the same information (for example, voltage, resistance value, current, etc.) (the first data w i (k-1) j (k)is set by storing approximately equal information in the holding unit HC and the holding unit HCr, respectively), a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i] so that a state of conduction is established between the holding unit HC and the wiring IL[j] and a state of conduction is established between the holding unit HCr and the wiring IL[j], and then a current, voltage, etc. according to the information is supplied from the wiring IL[j] to the holding unit HC and the holding unit HCr.

[0226] The circuit MP[i,j] in FIG. 13B stores the first data w in the holding unit HC and the holding unit HCr. i (k-1) j (k) and holds the potential according to the second data z i (k-1) 13A , a potential corresponding to the first data w is supplied to the wiring OL[j] and the wiring OLB[j]. i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0227] The circuit MP[i,j] shown in Fig. 13C is a modified example of the circuit MP[i,j] of Fig. 13A. The circuit MP[i,j] of Fig. 13C includes a circuit MC and a circuit MCr, similar to the circuit MP[i,j] of Fig. 13A. However, the circuit MP[i,j] of Fig. 13C and the circuit MP[i,j] of Fig. 13A have different wiring configurations for electrical connections.

[0228] Specifically, the circuit MP[i,j] in Fig. 13C has a configuration similar to that of the circuit MP[i,j] in Fig. 13A, except that the wiring OL[j] and the circuit MCr are not electrically connected, and the wiring OLB[j] and the circuit MC are not electrically connected. Therefore, the circuit MP[i,j] in Fig. 13C has a configuration similar to that of the circuit MP[i,j] in Fig. 13A, except that the wiring X1L[i] and the wiring X2L[i] are replaced with wiring XL[i]. The wiring XL[i] corresponds to the wiring XLS[i] in Fig. 12 and is electrically connected to the circuit MC and the circuit MCr.

[0229] In the circuit MP[i,j] of Fig. 13C, the wiring OL[j] and the circuit MCr are not electrically connected, and the wiring OLB[j] and the circuit MC are not electrically connected, so the second data (value of the neuron signal) input to the circuit MP may be different from that of the circuit MP[i,j] of Fig. 13A. For example, when a high-level potential is applied to the wiring XL, the second data (value of the neuron signal) can be set to "+1," and when a low-level potential is applied to the wiring XL, the second data (value of the neuron signal) can be set to "0."

[0230] The circuit MP[i,j] shown in FIG. 13D stores the first data w i (k-1) j (k) and the second data z i (k-1) 13D is a circuit capable of outputting a current according to the product of [i, j] and [i, j]. The circuit MP[i, j] in FIG. 13D can be applied to, for example, the arithmetic circuit 130 in FIG.

[0231] The circuit MP[i,j] in FIG. 13D includes a circuit MC, a circuit MCr, and a transistor MZ.

[0232] A first terminal of the transistor MZ is electrically connected to a first terminal of the circuit MC and a first terminal of the circuit MCr. A second terminal of the transistor MZ is electrically connected to the wiring VL. A gate of the transistor MZ is electrically connected to the wiring XL[i].

[0233] 13A to 13C, the wiring VL functions as a wiring that applies a constant voltage. The constant voltage is preferably determined by the configuration of the circuit MP[i,j], the arithmetic circuit 130, etc. The constant voltage may be, for example, a high-level potential VDD, a low-level potential VSS, a ground potential, or the like.

[0234] Moreover, the wiring WL[i] shown in Fig. 13D corresponds to the wiring WLS[i] in the arithmetic circuit 130 in Fig. 12. The wiring WL[i] is electrically connected to the holding unit HC and the holding unit HCr.

[0235] The wiring OL[j] is electrically connected to the second terminal of the circuit MC. The wiring OLB[j] is electrically connected to the second terminal of the circuit MCr.

[0236] Moreover, the wiring IL[j] is electrically connected to the holding unit HC, and the wiring ILB[j] is electrically connected to the holding unit HCr.

[0237] In the circuit MP[i,j] of Figure 13D, for the operation when a potential corresponding to the first data is held in each of the holding unit HC and the holding unit HCr, please refer to the explanation of the operation of holding a potential corresponding to the first data in the circuit MP[i,j] of Figure 13A.

[0238] In the circuit MP[i,j] of Fig. 13D, the circuit MC has a function of flowing a current corresponding to the potential held in the holding unit HC between the first and second terminals of the circuit MC when a constant voltage given by the wiring VL is supplied to the first terminal of the circuit MC. Also, the circuit MCr has a function of flowing a current corresponding to the potential held in the holding unit HCr between the first and second terminals of the circuit MCr when a constant voltage given by the wiring VL is supplied to the first terminal of the circuit MC. In other words, when the holding unit HC and the holding unit HCr of the circuit MP[i,j] are respectively supplied with the first data w i (k-1) j (k) By maintaining a potential according to the voltage VL, it is possible to determine the amount of current flowing between the first and second terminals of the circuit MC and the amount of current flowing between the first and second terminals of the circuit MCr. Note that when the constant voltage provided by the wiring VL is not supplied to the first terminal of the circuit MC (circuit MCr), the circuit MC (circuit MCr) may, for example, not allow current to flow between the first and second terminals of the circuit MC (circuit MCr).

[0239] For example, if the first data w of "1" is stored in each of the storage units HC and HCr, i (k-1) j (k) When a potential according to is held, a constant voltage is applied to the circuit MC by the wiring VL, and the circuit MC passes a predetermined current between the first and second terminals of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. Note that at this time, the circuit MCr does not pass a current between the first and second terminals of the circuit MCr. Therefore, no current flows between the circuit MCr and the wiring OLB. Also, for example, when the first data w of "-1" is stored in each of the holding units HC and HCr, i (k-1) j (k)When a potential according to is held, a constant voltage given by the wiring VL is given to the circuit MC, and the circuit MCr passes a predetermined current between the first and second terminals of the circuit MCr. Therefore, a current flows between the circuit MCr and the wiring OLB. Note that at this time, the circuit MC does not pass a current between the first and second terminals of the circuit MC. Therefore, no current flows between the circuit MC and the wiring OL. Also, for example, when the first data w of "0" is stored in each of the holding units HC and HCr, i (k-1) j (k) is held, regardless of whether the constant voltage of the wiring VL is applied to the circuits MC and MCr, the circuit MC does not pass a current between its first and second terminals, and the circuit MCr does not pass a current between its first and second terminals. In other words, no current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OLB.

[0240] In the circuit MP[i,j] of FIG. 13D, the first data w i (k-1) j (k) For a specific example of the potential corresponding to the potential, please refer to the description of the circuit MP[i,j] in Fig. 10A. In the circuit MP[i,j] in Fig. 13D, the holding units HC and HCr have the function of holding information such as a current or a resistance value instead of a potential, similar to the circuit MP[i,j] in Fig. 10A, and the circuits MC and MCr may have the function of flowing a current corresponding to the information.

[0241] The wiring XL[i] shown in FIG. 13D corresponds to the wiring XLS[i] in the arithmetic circuit 130 in FIG. 12. Note that the second data z i (k-1) For example, the potential and current of the wiring XL[i] are determined. Therefore, the gate of the transistor MZ is connected to the second data z i (k-1) A potential according to the voltage is input.

[0242] For example, the second data z i (k-1) Consider the case where the second data z takes either of the two values ​​"0" or "1". i (k-1) When the second data z is "1", a high-level potential is applied to the wiring XL[i]. At this time, the transistor MZ is turned on, so the circuit MP brings the wiring VL and the first terminal of the circuit MC into a conductive state, and brings the wiring VL and the first terminal of the circuit MCr into a conductive state. In other words, i (k-1) When the second data z i (k-1) When the second data z is "0", a low-level potential is applied to the wiring XL[i]. At this time, the circuit MP puts the circuit MC and the wiring OLB[j] in a non-conductive state, and puts the circuit MCr and the wiring OL[j] in a non-conductive state. That is, i (k-1) When is "0", the constant voltage is not applied to the circuit MC and the circuit MCr from the line VL.

[0243] Here, for example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) is "1", a current flows between the circuit MC and the wiring OL, and a current does not flow between the circuit MCr and the wiring OLB. i (k-1) j (k) is "-1", and the second data z i (k-1) is "1", no current flows between the circuit MC and the wiring OL, and a current flows between the circuit MCr and the wiring OLB. i (k-1) j (k) is "0", and the second data z i (k-1)is "1", no current flows between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB. i (k-1) is "0", the first data w i (k-1) j (k) is "-1", "0", or "1", no current flows between the circuit MC and the wiring OL, and between the circuit MCr and the wiring OLB.

[0244] That is, the circuit MP[i,j] in FIG. 13D, like the circuit MP[i,j] in FIG. 13C, uses, for example, the first data w i (k-1) j (k) takes one of the three values ​​"-1", "0", or "1", and the second data z i (k-1) 13C, the circuit MP[i,j] of FIG. 13D can perform calculations when the first data w i (k-1) j (k) It can also be operated when the first data w is any of two values ​​of "-1", "0", and "1", for example, when it is two values ​​of "-1" and "1", or when it is two values ​​of "0" and "1". i (k-1) j (k) may take an analog value or a multi-bit (multi-valued) digital value. As a specific example, a "negative analog value" may be used instead of "-1", and a "positive analog value" may be used instead of "1". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr may also be, for example, the first data w i (k-1) j (k) It becomes an analog value according to the absolute value of the value.

[0245] <<Circuit ILD>> For example, the circuit ILD transmits first data w1, which is a weighting coefficient, to each of the circuits MP[1,1] to MP[m,n] via the wirings IL[1] to IL[n] and the wirings ILB[1] to ILB[n]. (k-1) 1 (k) Or even w m (k-1) n (k) As a specific example, the circuit ILD has a function of inputting information (for example, potential, resistance value, current value, etc.) corresponding to the circuit MP[i,j]. i (k-1) j (k) information (for example, potential, resistance value, or current value) corresponding to the wiring IL[j] and wiring ILB[j] is supplied via the wiring IL[j] and wiring ILB[j].

[0246] FIG. 14A shows an example of the circuit configuration of the circuit ILD that can be applied to the arithmetic circuit 130. Note that FIG. 14A also shows wiring OL[j] and wiring OLB[j] to explain the electrical connection between the circuit ILD and the array unit ALP. The circuit ILD has a current source circuit ISC, a switch SWIA, a switch SWIAB, a switch SWLA, and a switch SWLAB. The wiring OL[j] is electrically connected to a first terminal of the switch SWIA and a first terminal of the switch SWLA. The wiring OLB[j] is electrically connected to a first terminal of the switch SWIAB and a first terminal of the switch SWLAB. The current source circuit ISC is electrically connected to a second terminal of the switch SWIA and a second terminal of the switch SWIAB. The wiring VCN is electrically connected to a second terminal of the switch SWLA and a second terminal of the switch SWLAB.

[0247] The current source circuit ISC has, for example, one or more constant current sources. In FIG. 14A, as an example, the multiple constant current sources include constant current source circuit ISC1, constant current source circuit ISC2, and constant current source circuit ISC3. Furthermore, as an example, the current source circuit ISC has multiple switches to select from the multiple constant current sources. In FIG. 14A, the multiple switches include switch SWC1, switch SWC2, and switch SWC3. Note that if the current source circuit ISC has only one constant current source, the current source circuit ISC does not need to have a switch. Alternatively, if the constant current source circuit ISC1, constant current source circuit ISC2, and constant current source circuit ISC3 each have a function to control whether or not to output a current, the switches SWC1, SWC2, and SWC3 may not be provided.

[0248] Incidentally, the currents flowing through the wiring OL[j] and the wiring OLB[j] for storing the first data (weighting coefficient) in any one of the circuits MP[1,j] to MP[m,j] are preferably generated by the same current source circuit ISC, as shown in FIG. 14A. When the currents flowing through the wiring OL[j] and the wiring OLB[j] are generated by different current source circuits, variations in the characteristics of the transistors due to factors such as the transistor manufacturing process may occur, resulting in differences in performance between different current source circuits. On the other hand, when the same current source circuit is used, it is possible to flow currents of the same magnitude through the wiring OL[j] and the wiring OLB[j], thereby improving the calculation accuracy.

[0249] As the switches SWIA, SWIAB, SWLA, SWLAB, SWC1, SWC2, and SWC3 described in FIG. 14A, for example, switches that can be applied in the same manner as the switches SWR1, SWR1B, SWR2, and SWR2B described above can be used.

[0250] Specific configuration examples of the constant current source circuits ISC1 to ISC3 are shown in Figures 14B and 14C. The constant current source circuit ISC1 (constant current source circuits ISC2 and ISC3) shown in Figure 14B has a transistor PTr, which is a p-channel transistor. A first terminal of the transistor PTr is electrically connected to the wiring VSO, a second terminal of the transistor PTr is electrically connected to the second terminal of the switch SWC1 (switches SWC2 and SWC3), and a gate of the transistor PTr is electrically connected to the wiring VB. The constant current source circuit ISC1 (constant current source circuits ISC2 and ISC3) shown in Figure 14C has a transistor NTr, which is an n-channel transistor. A first terminal of the transistor NTr is electrically connected to the wiring VSO, a second terminal of the transistor NTr is electrically connected to the second terminal of the switch SWC1 (switches SWC2 and SWC3), and a gate of the transistor NTr is electrically connected to the wiring VB. In each of the constant current source circuits ISC1 (constant current source circuits ISC2, constant current source circuits ISC3) in Figures 14B and 14C, the wiring VB functions as a wiring for inputting a bias voltage to the gate of each transistor. A pulse signal may be supplied to the wiring VB, which makes it possible to control whether or not a current is output from each constant current source circuit. In this case, the switches SWC1, SWC2, and SWC3 do not need to be provided. Alternatively, an analog voltage may be supplied to the wiring VB, which makes it possible to supply an analog current from the constant current source circuit.

[0251] The wiring VSO functions as a wiring that supplies a constant voltage to each of the constant current source circuits ISC1 to ISC3. For example, when a current flows from the circuit ILD (wiring VSO) to the wiring OL or OLB, the constant voltage is preferably a potential higher than ground potential (e.g., VDD). Furthermore, it is preferable to use the constant current source circuit ISC1 (constant current source circuits ISC2 and ISC3) shown in FIG. 14B. Furthermore, when a current flows from the wiring OL or OLB to the circuit ILD (wiring VSO), the constant voltage is preferably a potential higher than ground potential and lower than the high-level potential, such as ground potential or a negative potential. Furthermore, it is preferable to use the constant current source circuit ISC1 (constant current source circuits ISC2 and ISC3) shown in FIG. 14C. Note that in this specification and the like, the current flowing from the circuit ILD to the wiring OL or OLB may be referred to as a positive current. Therefore, the current flowing from the wiring OL or the wiring OLB to the circuit ILD may be referred to as a negative current.

[0252] By the way, the current flowing from the constant current source circuit ISC1 is I ut As an example, the current flowing through the constant current source circuit ISC2 is 2I ut It is preferable that the current flowing from the constant current source circuit ISC3 is 4I ut That is, when the current source circuit ISC has P constant current sources (P is an integer of 1 or more), the current flowing from the p-th constant current source (p is an integer of 1 or more and P or less) is preferably 2 (p-1) ×I ut That is, by switching each of the switches SWC1 to SWC3 between the on state and the off state, the magnitude of the current flowing from the current source circuit ISC can be changed.

[0253] For example, let us assume that the number of constant current sources in the current source circuit ISC is three (P=3). utIf you want to pass a current of 5I, you can turn on the switch SWIA, turn off the switch SWIAB, turn on the switch SWC1, and turn off the switches SWC2 and SWC3. ut To flow a current of 1, the switches SWC1 and SWC3 are turned on and the switch SWC2 is turned off. In other words, the amount of current output from the current source circuit ISC can be one of eight values ​​("0", "I" ut ", "2I ut ", "3I ut ", "4I ut ", "5I ut ", "6I ut ", "7I ut ) can be any one of eight values. If it is desired to output a current with more than eight values, the number of constant current sources should be four or more. Similarly, by turning the switch SWIA off and the switch SWIAB on, one of eight current values ​​can be passed through the wiring OLB[j]. If no current is to be output from the current source circuit ISC, the switches SWC1 to SWC3 of the current source circuit ISC may not be turned off, and the switches SWIA and SWIAB may be turned off. By arranging multiple constant current sources in this way, a circuit that can generate a current with multiple values ​​can be easily realized. It is also possible to arrange only one current source circuit and operate it to change the current value that is output in an analog manner.

[0254] The wiring VCN functions as a wiring that supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. For example, when a current (positive current) flows from the circuit ILD to the wiring OL or the wiring OLB, the constant voltage applied by the wiring VCN is preferably a low-level potential (e.g., VSS). Furthermore, when a current (negative current) flows from the wiring OL or the wiring OLB to the circuit ILD, the constant potential applied by the wiring VCN is preferably a high-level potential. Note that, as shown in FIGS. 20A to 20C, 21A, and 21B (described later), when the capacitor C1 is electrically connected to the source terminal of a transistor M1 or the like and the source terminal is connected to a power supply line or the like, the constant voltage applied by the wiring VCN is preferably a low-level potential (e.g., VSS) when a positive current flows from the circuit ILD to the wiring OL or the wiring OLB. In other words, when a constant voltage is supplied from the wiring VCN, it is desirable that the potential difference across the capacitor C1 be close to zero. In other words, it is desirable to supply to the wiring VCN a potential that prevents current from being output from the circuit MC, for example, a potential that is substantially equal to the potential applied by the wiring VE.

[0255] Here, the first data (weighting coefficient) input to the circuit MP will be described.

[0256] When positive first data is to be input to the circuit MP, a current corresponding to the first data is input to the wiring OL[j], and a constant potential provided by the wiring VCN is input to the wiring OLB[j]. As an example, the current source circuit ISC and the wiring OL[j] are brought into a conductive state, the current source circuit ISC and the wiring OLB[j] are brought into a non-conductive state, the wiring VCN and the wiring OL[j] are brought into a non-conductive state, and the wiring VCN and the wiring OLB[j] are brought into a conductive state. That is, the switches SWIA and SWLAB are turned on, and the switches SWIAB and SWLA are turned off. This brings the current source circuit ISC and the wiring OL[j] into a conductive state, allowing a current to flow from the current source circuit ISC to the circuit MP via the wiring OL[j]. Incidentally, when the number of constant current sources in the current source circuit ISC is P, the current is calculated as follows:P The positive weighting coefficient input to the circuit MP is determined according to the current, so the weighting coefficient is 2 P The value can be any one of the values ​​−1. Furthermore, since the wiring VCN and the wiring OLB[j] are in a conductive state, a constant voltage is input from the wiring VCN to the wiring OLB[j].

[0257] Furthermore, when negative first data is to be input to the circuit MP, a current corresponding to the first data is input to the wiring OLB[j], and a constant potential provided by the wiring VCN is input to the wiring OL[j]. As an example, the current source circuit ISC and the wiring OL[j] are brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] are brought into a conductive state, the wiring VCN and the wiring OL[j] are brought into a conductive state, and the wiring VCN and the wiring OLB[j] are brought into a non-conductive state. That is, the switches SWIAB and SWLA are turned on, and the switches SWIA and SWLAB are turned off. This brings the current source circuit ISC and the wiring OLB[j] into a conductive state, allowing a current to flow from the current source circuit ISC to the circuit MP via the wiring OLB[j]. Incidentally, when the number of constant current sources in the current source circuit ISC is P, the current is calculated as follows: P The negative weighting coefficient input to the circuit MP is determined according to the current, so the weighting coefficient is 2 P The value can be any one of the values ​​−1. Furthermore, since the wiring VCN and the wiring OL[j] are in a conductive state, a constant voltage is input from the wiring VCN to the wiring OL[j].

[0258] Furthermore, when first data 0 is to be input to the circuit MP, the constant potential provided by the wiring VCN can be input to each of the wirings OL[j] and OLB[j]. As an example, the current source circuit ISC and the wiring OL[j] can be brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] can be brought into a non-conductive state, the wiring VCN and the wiring OL[j] can be brought into a conductive state, and the wiring VCN and the wiring OLB[j] can be brought into a conductive state. That is, the switches SWLA and SWLAB can be turned on, and the switches SWIA and SWIAB can be turned off. This brings the wiring VCN and the wiring OL[j] into a conductive state, and the wiring VCN and the wiring OLB[j] into a conductive state, so that the constant voltage from the wiring VCN can be input to the wiring OL[j] and the wiring OLB[j].

[0259] In other words, by setting the number of constant current sources in the current source circuit ISC to P, the number of weighting coefficients that can be input to the circuit MP (the sum of positive weighting coefficients, negative weighting coefficients, and 0 weighting coefficients) is 2 P+1 -1 piece.

[0260] Although the above description has been given of a configuration in which the circuit ILD includes the current source circuit ISC, one embodiment of the present invention is not limited to this. For example, a voltage source circuit may be provided instead of the current source circuit ISC. For example, at least one current source circuit ISC may be provided for each of the wiring OL[j] and the wiring OLB[j], as separate circuits. For example, as shown in FIG. 14A , at least one current source circuit ISC may be provided for each pair of wirings OL[j] and OLB[j]. Note that the circuit ILD may be provided as a separate circuit from the circuit AFP, but one embodiment of the present invention is not limited to this. For example, the circuit ILD may be integrated with the circuit AFP.

[0261] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit 130 in Fig. 12 will be described. In the description of this example of the operation, the arithmetic circuit 130A shown in Fig. 15 will be used as an example.

[0262] 15 is a diagram in which the circuit ACTF[j] shown in FIG. 8 is applied to the arithmetic circuit 130 of FIG. 12, and is illustrated focusing on the circuit located in the j-th column of the arithmetic circuit 130 of FIG. 12. Therefore, the arithmetic circuit 130A of FIG. 15 is similar to the neuron N j (k) neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) (This may be referred to as first data or second data. Here, it is referred to as second data.) and a weighting coefficient w1 (k-1) j (k) Or even w m (k-1) j (k) (This may be referred to as first data or second data. Here, it will be referred to as first data.) and a circuit that performs a product-sum operation on the data and the activation function using the result of the product-sum operation.

[0263] 13A is applied to the circuit MP included in the array portion ALP of the arithmetic circuit 130A in Fig. 15, and the wirings WL[1] to WL[m] are illustrated as the wirings WLS[1] to WLS[m], and the wirings X1L[1] to X1L[m] and the wirings X2L[1] to X2L[m] are illustrated as the wirings XLS[1] to XLS[m]. Also, the circuit IVTR (circuit IVTRr) shown in Fig. 6A is applied to the circuit IVTR and the circuit IVTRr included in the circuit ACTF[j] of the arithmetic circuit 130A in Fig. 15.

[0264] First, in the arithmetic circuit 130A, the first data w1 (k-1) j (k) Or even w m (k-1) j(k) The first data w is set. i (k-1) j (k) As a method of setting the first data, a predetermined potential is input to the wirings WLS[1] to WLS[m] in order by the circuit WLD to sequentially select the circuits MP[1,j] to MP[m,j], and a potential, current, or the like according to the first data is supplied from the circuit ILD to the circuit MC and the holding unit HC and holding unit HCr of the circuit MCr included in the selected circuit MP via the wirings OL[j] and OLB[j]. After the supply of the potential, current, or the like, the circuit WLD deselects each of the circuits MP[1,j] to MP[m,j], thereby storing the first data w1 in the holding unit HC of the circuit MC and the holding unit HCr of the circuit MCr included in each of the circuits MP[1,j] to MP[m,j]. (k-1) j (k) Or even w m (k-1) j (k) As an example, the potential, current, etc. according to the first data w1 (k-1) j (k) Or even w m (k-1) j (k) If any of the first data w1 takes a positive value, a value corresponding to the positive value is input to the holding unit HC, and a value equivalent to zero is input to the holding unit HCr. (k-1) j (k) Or even w m (k-1) j (k) If any of the first data w1 takes a negative value, a value equivalent to zero is input to the holding unit HC, and a value corresponding to the absolute value of the negative value is input to the holding unit HCr. (k-1) j (k) Or even w m (k-1) j (k)If any of the above takes the value 0, a value equivalent to zero is input to the holding unit HC, and a value corresponding to the absolute value of the value of zero is input to the holding unit HCr.

[0265] Next, the circuit XLD applies second data z1 (k-1) ~z m (k-1) As a specific example, the second data z1 is supplied to the wiring X1L[i] and the wiring X2L[i]. (k-1) is supplied.

[0266] Second data z1 input to each of the circuits MP[1,j] to MP[m,j] (k-1) ~z m (k-1) The conduction state between the circuits MC and MCr included in the circuits MP[1,j] to MP[m,j] and the wirings OL[j] and OLB[j] is determined according to the second data z i (k-1) Depending on the second data z1, one of the following modes is selected: a mode in which "the circuit MC and the wiring OL[j] are in a conductive state, and the circuit MCr and the wiring OLB[j] are in a conductive state," a mode in which "the circuit MC and the wiring OLB[j] are in a conductive state, and the circuit MCr and the wiring OL[j] are in a conductive state," and a mode in which "the circuit MC and the circuit MCr are in a non-conductive state with the wiring OL[j] and the wiring OLB[j], respectively." (k-1) When the second data z1 is a positive value, a value that can bring the circuit MC and the wiring OL[j] into a conductive state and can bring the circuit MCr and the wiring OLB[j] into a conductive state is input to the wiring X1L[1]. Then, a value that can bring the circuit MC and the wiring OLB[j] into a non-conductive state and can bring the circuit MCr and the wiring OL[j] into a non-conductive state is input to the wiring X2L[1]. Then, the second data z1 (k-1)When the second data z1 is a negative value, a value that can bring the circuit MC and the wiring OLB[j] into a conductive state and can bring the circuit MCr and the wiring OL[j] into a conductive state is input to the wiring X1L[1]. Then, a value that can bring the circuit MC and the wiring OL[j] into a non-conductive state and can bring the circuit MCr and the wiring OLB[j] into a non-conductive state is input to the wiring X2L[1]. Then, the second data z1 (k-1) When the value of 0 is taken for the wiring X1L[1], a value that can bring the circuit MC and the wiring OLB[j] into a non-conductive state and can bring the circuit MCr and the wiring OL[j] into a non-conductive state is input to the wiring X1L[1]. Then, a value that can bring the circuit MC and the wiring OL[j] into a non-conductive state and can bring the circuit MCr and the wiring OLB[j] into a non-conductive state is input to the wiring X2L[1].

[0267] The second data z input to the circuit MP[i,j] i (k-1) The conduction state between the circuit MC and the wiring OL[j] and the wiring OLB[j] included in the circuit MP[i,j] is determined in accordance with the first data w set in the circuit MP[i,j], and current is input and output between the circuit MC and the wiring OL[j] and the wiring OLB[j]. i (k-1) j (k) and / or second data z i (k-1) It depends on:

[0268] For example, in the circuit MP[i,j], the current flowing from the wiring OL[j] to the circuit MC or the circuit MCr is I[i,j], and the current flowing from the wiring OLB[j] to the circuit MC or the circuit MCr is I B [i,j]. Then, the current flowing from the circuit ACTF[j] to the wiring OL[j] is I out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] is I Bout If [j], then I out [j] and I Bout [j] can be expressed by the following formula:

[0269]

number

[0270] In the circuit MP[i,j], as an example, the first data w i (k-1) j (k) When is "+1", I(+1) flows between the circuit MC and one of the wiring OL[j] and the wiring OLB[j], and I(-1) flows between the circuit MCr and the other of the wiring OL[j] and the wiring OLB[j]. i (k-1) j (k) When the first data w is "-1", I(-1) flows between the circuit MC and either the wiring OL[j] or the wiring OLB[j], and I(+1) flows between the circuit MCr and the other wiring OL[j] or the wiring OLB[j]. i (k-1) j (k) When is "0", I(-1) flows between the circuit MC and either the wiring OL[j] or the wiring OLB[j], and I(-1) flows between the circuit MCr and the other wiring OL[j] or the wiring OLB[j].

[0271] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) is "+1", the configuration is such that "the circuit MC and the wiring OL[j] are in a conductive state, the circuit MCr and the wiring OLB[j] are in a conductive state, the circuit MC and the wiring OLB[j] are in a non-conductive state, and the circuit MCr and the wiring OL[j] are in a non-conductive state", and the second data z i (k-1) is "-1", the configuration is such that "the circuit MC and the wiring OLB[j] are in a conductive state, the circuit MCr and the wiring OL[j] are in a conductive state, the circuit MC and the wiring OL[j] are in a non-conductive state, and the circuit MCr and the wiring OLB[j] are in a non-conductive state", and the second data z i (k-1)When is "0", the configuration is such that "there is a non-conductive state between the circuit MC and the wiring OL[j], and between the circuit MC and the OLB[j], and there is a non-conductive state between the circuit MCr and the wiring OL[j], and between the circuit MCr and the OLB[j]."

[0272] At this time, in the circuit MP[i,j], the current I[i,j] flows from the wiring OL[j] to the circuit MC or the circuit MCr, and the current I B [i,j] is as shown in the table below. In some cases, the circuit MP[i,j] may be configured so that the current amount of I(-1) is 0. The current I[i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i, j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OLB[j].

[0273] [Table 1]

[0274] The circuit ACTF[j] is, for example, a current I flowing through the wiring OL[j] and wiring OLB[j]. out [j] and I Bout [j], and generate a voltage according to I out Voltage and I according to [j] Bout Depending on the difference between the voltages according to [j] and j (k) is the signal z sent to the (k+1)th layer neuron. j (k) Output.

[0275] For the operation of the circuit ACTF[j], please refer to the explanation of the operation example of the arithmetic circuit 110A in FIG. 8 of the first embodiment.

[0276] <Configuration example 2 of an arithmetic circuit> The arithmetic circuit 130A shown in FIG. Bout I rather than [j]out When [j] is large (u j (k) is positive), the circuit AC will j (k) and I out I rather than [j] Bout When [j] is large (u j (k) is negative), the circuit AC outputs a digital signal z j (k) However, one embodiment of the present invention is not limited to this. For example, the arithmetic circuit 130A outputs I out I rather than [j] Bout When [j] is large (u j (k) is negative), the circuit AC generates a negative value of the output signal z j (k) The configuration may be changed to output the following.

[0277] An example of such an arithmetic circuit is shown in FIG. 16. The arithmetic circuit 140 shown in FIG. 16 has a configuration obtained by modifying the circuit ACTF[j] included in the circuit AFP of the arithmetic circuit 130A of FIG. 15. The circuit configuration of the arithmetic circuit 140 is also an example of the arithmetic circuit 120 shown in FIG. 4A. The circuit ACTF[j] includes switches SWR1M, SWR1MB, SWR1P, SWR1PB, SWR2M, SWR2MB, SWR2P, SWR2PB, capacitances CREM, CREP, a circuit ACM, a circuit ACP, a circuit IVTR, and a circuit IVTRr. The circuit ACP includes terminals mbt1p and mbt2p, and the circuit ACM includes terminals mbt1m and mbt2m.

[0278] Note that the switches SWR1P, SWR2P, SWR1PB, SWR2PB, capacitance CREP, and circuit ACP included in the circuit ACTF[j] of the arithmetic circuit 140 correspond to the switches SWR1, SWR2, SWR1B, SWR2B, capacitance CRE, and circuit AC included in the circuit ACTF[j] of Fig. 15. Also, the terminals mbt1p and mbt2p of the circuit ACP of Fig. 16 correspond to the terminals mbt1 and mbt2 of the circuit AC of Fig. 15. Therefore, the description of the circuit ACTF[j] shown in Fig. 15 should be referred to for the connection configurations, functions, and the like of the switches SWR1P, SWR2P, SWR1PB, SWR2PB, capacitance CREP, and circuit ACP.

[0279] A first terminal of the switch SWR1M is electrically connected to the circuit IVTR, the terminal T1, and the first terminal of the switch SWR1P. A second terminal of the switch SWR1M is electrically connected to the first terminal of the capacitor CREM and the first terminal of the switch SWR2MB. A second terminal of the switch SWR2MB is electrically connected to the terminal mbt1m of the circuit ACM. A first terminal of the switch SWR1MB is electrically connected to the circuit IVTRr, the terminal T2, and the first terminal of the switch SWR1PB. A second terminal of the switch SWR1MB is electrically connected to the second terminal of the capacitor CREM and the first terminal of the switch SWR2M. A second terminal of the switch SWR2M is electrically connected to the wiring VCN3.

[0280] The circuit ACM may have the same circuit configuration as the circuit ACP, that is, the circuit AC in Fig. 15. Furthermore, the circuit ACP may be configured, for example, to output a digital signal with a value of 0 from the terminal mbt2p when a potential lower than a predetermined potential (for example, the GND potential) is input to the terminal mbt1p, and similarly, the circuit ACM may be configured, for example, to output a digital signal with a value of 0 from the terminal mbt2m when a potential lower than a predetermined potential (for example, the GND potential) is input to the terminal mbt1m.

[0281] Furthermore, switches SWR1M, SWR2M, SWR1MB, and SWR2MB may each be, for example, switches that can be applied in the same manner as the above-mentioned switches SWR1, SWR1B, SWR2, and SWR2B. Here, each of switches SWR1M, SWR2M, SWR1MB, SWR2MB, SWR1P, SWR2P, SWR1PB, and SWR2PB is turned on when a high-level potential is input to its control terminal, and turned off when a low-level potential is input to its control terminal.

[0282] Furthermore, it is preferable that the control terminals of the switches SWR1M, SWR1P, SWR1MB, and SWR1PB are electrically connected to the same wiring. In other words, it is preferable that the switches SWR1M, SWR1P, SWR1MB, and SWR1PB operate so as to be simultaneously turned on or off.

[0283] Furthermore, it is preferable that the control terminals of the switches SWR2M and SWR2P are electrically connected to the same wiring. In other words, it is preferable that the switches SWR2M and SWR2P operate so as to be simultaneously turned on or off.

[0284] Furthermore, it is preferable that the control terminals of the switches SWR2MB and SWR2PB are electrically connected to the same wiring. In other words, it is preferable that the switches SWR2MB and SWR2PB operate so that they are simultaneously turned on or off.

[0285] Here, in the arithmetic circuit 140 of FIG. 16, the circuit ACTF[j] receives the I out [j], I flowing from wiring OLB[j] BoutConsider the case of reading [j]. It is assumed that the control terminals of switches SWR1M, SWR1P, SWR1MB, and SWR1PB are electrically connected to wiring SRL1, the control terminals of switches SWR2M and SWR2P are electrically connected to wiring SRL2-1, and the control terminals of switches SWR2MB and SWR2PB are electrically connected to wiring SRL2-2.

[0286] current I out [j] is I Bout If it is larger than [j], as in the example of operation described above, at time T04, the potential V of the first terminal of the capacitance CREP Iout is the potential V of the second terminal of the capacitance CREP IBout Then, from time T04 to time T05, the voltage between the first terminal and the second terminal of the capacitor CREP is maintained, and from time T06 to time T07, the capacitive coupling of the capacitor CREP causes the potential of the second terminal of the capacitor CREP to become higher than the GND potential. After time T07, this potential is input to the terminal mbt1p of the circuit ACP, and a digital signal corresponding to this potential is output from the terminal mbt2p of the circuit ACP.

[0287] On the other hand, at time T04, the potential V of the first terminal of the capacitor CREM Iout is the potential V of the second terminal of the capacitor CREM IBout Then, from time T04 to time T05, the voltage between the first terminal and the second terminal of the capacitor CREM is maintained, and from time T06 to time T07, the capacitive coupling of the capacitor CREM causes the potential of the first terminal of the capacitor CREM to be lower than the GND potential. From time T07 onwards, this potential is input to the terminal mbt1m of the circuit ACM, and a digital signal with a value of 0 is output from the terminal mbt2m of the circuit ACM.

[0288] That is, the current I out [j] is I Bout When it is greater than [j], a digital signal according to the potential of terminal mbt1p is output from terminal mbt2p of circuit ACP. Zis output, and the GND potential is output from the terminal mbt2m of the circuit ACM. Then, the pair of these two digital signals is output by the circuit ACTF[j] as a positive value output signal z j (k) It can be said that:

[0289] Also, the current I out [j] is I Bout If it is smaller than [j], as in the example of operation described above, at time T04, the potential V of the first terminal of the capacitance CREP Iout is the potential V of the second terminal of the capacitance CREP IBout Then, from time T04 to time T05, the voltage between the first terminal and the second terminal of the capacitor CREP is maintained, and from time T06 to time T07, the capacitive coupling of the capacitor CREP causes the potential of the second terminal of the capacitor CREP to become lower than the GND potential. After time T07, this potential is input to the terminal mbt1p of the circuit ACP, and a digital signal with a value of 0 is output from the terminal mbt2p of the circuit ACP.

[0290] On the other hand, at time T04, the potential V of the first terminal of the capacitor CREM Iout is the potential V of the second terminal of the capacitor CREM IBout Then, from time T04 to time T05, the voltage between the first terminal and the second terminal of the capacitor CREM is maintained, and from time T06 to time T07, the capacitive coupling of the capacitor CREM causes the potential of the first terminal of the capacitor CREM to be higher than the GND potential. From time T07 onwards, this potential is input to the terminal mbt1m of the circuit ACM, and a digital signal corresponding to this potential is output from the terminal mbt2m of the circuit ACM.

[0291] That is, the current I out [j] is I Bout When the potential of the terminal mbt1p is smaller than the potential of the terminal mbt2p of the circuit ACP, the terminal mbt2m of the circuit ACM outputs a digital signal corresponding to the potential of the terminal mbt1p. The set of these two digital signals is then expressed as a negative output signal z j(k) It can be said that:

[0292] <Configuration example 3 of an arithmetic circuit> 12, the wirings IL[j], ILB[j], OL[j], and OL[j] are electrically connected to the circuit MP[i,j]; however, one embodiment of the present invention is not limited to this. For example, the arithmetic circuit 130 can have a configuration in which the wirings IL[j] and OL[j] are collectively defined as the wiring OL[j], and the wirings ILB[j] and OLB[j] are collectively defined as the wiring OLB[j].

[0293] An example of the configuration of this arithmetic circuit is shown in Fig. 17. The arithmetic circuit 150 shown in Fig. 17 has a configuration in which, in the arithmetic circuit 130, the wirings IL[j] and OL[j] are combined into wiring OL[j], and the wirings ILB[j] and OLB[j] are combined into wiring OLB[j].

[0294] The arithmetic circuit 150 also includes switching circuits TW[1] to TW[n]. Each of the switching circuits TW[1] to TW[n] includes a terminal TSa, a terminal TSaB, a terminal TSb, a terminal TSbB, a terminal TSc, and a terminal TScB. The terminal TSa is electrically connected to a wiring OL[j], the terminal TSbB is electrically connected to a circuit ILD, and the terminal TSc is electrically connected to a circuit ACTF[i]. The terminal TSaB is electrically connected to a wiring OLB[j], the terminal TSbB is electrically connected to the circuit ILD, and the terminal TScB is electrically connected to the circuit ACTF[j].

[0295] The switching circuit TW[j] has a function of establishing a conductive state between the terminal TSa and either the terminal TSb or the terminal TSc, and a non-conductive state between the terminal TSa and the other of the terminal TSb or the terminal TSc. The switching circuit TW[j] also has a function of establishing a conductive state between the terminal TSaB and either the terminal TSbB or the terminal TScB, and a non-conductive state between the terminal TSaB and the other of the terminal TSbB or the terminal TScB.

[0296] That is, the first data w1, which is a weighting coefficient, is assigned to any one of the circuits MP[1,j] to MP[m,j]. (k-1) 1 (k) Or even w m (k-1) n (k) When it is desired to input information (for example, a potential, a resistance value, a current value, etc.) corresponding to the first data w1 from the circuit ILD to the wiring OL[j] and the wiring OLB[j], the first data w1 is transmitted from the circuit ILD to the wiring OL[j] and the wiring OLB[j] by bringing the terminals TSa and TSb into a conductive state and bringing the terminals TSaB and TSbB into a conductive state in the switching circuit TW[j]. (k-1) 1 (k) Or even w m (k-1) n (k) It is possible to provide information (for example, potential, resistance value, current value, etc.) corresponding to the above.

[0297] Furthermore, when the circuit ACTF[j] wants to obtain the result of the sum of products (equation (1.2)) of the weight coefficients and the neuron signal values ​​calculated by the circuits MP[1,j] to MP[m,j], the switching circuit TW[j] can supply information (e.g., potential, current value, etc.) corresponding to the result of the sum of products from the wiring OL[j] and wiring OLB[j] to the circuit ACTF[j] by bringing the terminals TSa and TSc into a conductive state and bringing the terminals TSaB and TScB into a conductive state. Also, in the circuit ACTF[j], the value of the activation function is calculated from the input result of the sum of products, and for example, the signal z is output as the neuron output signal. j (k) can be obtained.

[0298] Next, a description will be given of the switching circuit TW[j] and the circuit ILD included in the arithmetic circuit 150. Fig. 18A shows a configuration example of the switching circuit TW[j] and the circuit ILD that can be applied to the arithmetic circuit 150. Note that Fig. 18A also shows a wiring OL[j], a wiring OLB[j], and a circuit AFP to show the configuration of the electrical connection between the switching circuit TW[j] and the circuit ILD.

[0299] The switching circuit TW[j] includes, for example, a switch SWI, a switch SWIB, a switch SWO, a switch SWOB, a switch SWL, and a switch SWLB.

[0300] The circuit ILD includes, for example, a current source circuit ISC. The configuration of the current source circuit ISC can be the same as that of the current source circuit ISC in the circuit ILD of Fig. 14A. Therefore, for the current source circuit ISC in Fig. 18A, the description of the circuit ISC included in the circuit ILD of Fig. 14A should be taken into consideration.

[0301] As the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB described in FIG. 18A, for example, switches that can be applied in the same manner as the switches SWR1, SWR1B, SWR2, and SWR2B described above can be used.

[0302] In one example of the switching circuit TW[j], the terminal TSa is electrically connected to a first terminal of the switch SWI, a first terminal of the switch SWO, and a first terminal of the switch SWL. The terminal TSaB is electrically connected to a first terminal of the switch SWIB, a first terminal of the switch SWOB, and a first terminal of the switch SWLB. The second terminal of the switch SWI is electrically connected to a terminal TSb1. The second terminal of the switch SWIB is electrically connected to a terminal TSbB1. The second terminal of the switch SWO is electrically connected to a terminal TSc. The second terminal of the switch SWOB is electrically connected to a terminal TScB. The second terminal of the switch SWL is electrically connected to a terminal TSb2. The second terminal of the switch SWLB is electrically connected to a terminal TSbB2.

[0303] Terminals TSb1 and TSb2 shown in Fig. 18A correspond to the terminal TSb shown in Fig. 17. Terminals TSbB1 and TSbB2 shown in Fig. 18A correspond to the terminal TSbB shown in Fig. 17.

[0304] The wiring VCN functions as a wiring that supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j], similar to the wiring VCN of the circuit ILD in Fig. 14A. Therefore, for the wiring VCN in Fig. 18A, the description of the wiring VCN in Fig. 14A should be referred to.

[0305] The switching circuit TW[j] can change the circuit that is in a conductive state with the wiring OL[j] and the wiring OLB[j] by switching each of the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB to an on or off state.

[0306] For example, to input a positive weighting coefficient to the circuit MP, a current corresponding to the weighting coefficient is input to the wiring OL[j], and a constant potential provided by the wiring VCN is input to the wiring OLB[j]. As an example, the current source circuit ISC and the wiring OL[j] are brought into conduction, the current source circuit ISC and the wiring OLB[j] are brought into non-conduction, the circuit AFP and the wiring OL[j] are brought into non-conduction, the circuit AFP and the wiring OLB[j] are brought into non-conduction, the wiring VCN and the wiring OL[j] are brought into non-conduction, and the wiring VCN and the wiring OLB[j] are brought into conduction. That is, in the switching circuit TW[j], the switches SWI and SWLB are turned on, and the switches SWIB, SWO, SWOB, and SWL are turned off. This establishes a conductive state between the current source circuit ISC and the wiring OL[j], allowing current to flow from the current source circuit ISC to the circuit MP via the wiring OL[j]. Also, since a conductive state exists between the wiring VCN and the wiring OLB[j], a constant voltage is input from the wiring VCN to the wiring OLB[j].

[0307] Furthermore, for example, when a negative weighting coefficient is to be input to the circuit MP, a current corresponding to the weighting coefficient is input to the wiring OLB[j], and a constant potential provided by the wiring VCN is input to the wiring OL[j]. As an example, the current source circuit ISC and the wiring OL[j] are brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] are brought into a conductive state, the circuit AFP and the wiring OL[j] are brought into a non-conductive state, the circuit AFP and the wiring OLB[j] are brought into a non-conductive state, the wiring VCN and the wiring OL[j] are brought into a conductive state, and the wiring VCN and the wiring OLB[j] are brought into a non-conductive state. That is, in the switching circuit TW[j], the switches SWIB and SWL are turned on, and the switches SWI, SWO, SWOB, and SWLB are turned off. This establishes a conductive state between the current source circuit ISC and the wiring OLB[j], allowing current to flow from the current source circuit ISC to the circuit MP via the wiring OLB[j]. Also, since a conductive state exists between the wiring VCN and the wiring OL[j], a constant voltage is input from the wiring VCN to the wiring OL[j].

[0308] Furthermore, for example, when a weighting coefficient of 0 is to be input to the circuit MP, the constant potential provided by the wiring VCN can be input to each of the wirings OL[j] and OLB[j]. As an example, the current source circuit ISC and the wiring OL[j] can be brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] can be brought into a non-conductive state, the circuit AFP and the wiring OL[j] can be brought into a non-conductive state, the circuit AFP and the wiring OLB[j] can be brought into a non-conductive state, the wiring VCN and the wiring OL[j] can be brought into a conductive state, and the wiring VCN and the wiring OLB[j] can be brought into a conductive state. That is, in the switching circuit TW[j], the switches SWL and SWLB can be turned on, and the switches SWI, SWIB, SWO, and SWOB can be turned off. This brings about a state of conduction between wiring VCN and wiring OL[j], and between wiring VCN and wiring OLB[j], so that a constant voltage from wiring VCN is input to wiring OL[j] and wiring OLB[j].

[0309] Furthermore, for example, when information (e.g., potential, current, etc.) is supplied from the circuit MP[i,j] to the circuit AFP, for example, the current source circuit ISC and the wiring OL[j] may be brought into a non-conductive state, the current source circuit ISC and the wiring OLB[j] may be brought into a non-conductive state, the circuit AFP and the wiring OL[j] may be brought into a conductive state, the circuit AFP and the wiring OLB[j] may be brought into a conductive state, the wiring VCN and the wiring OL[j] may be brought into a non-conductive state, and the wiring VCN and the wiring OLB[j] may be brought into a non-conductive state. That is, in the switching circuit TW[j], the switches SWO and SWOB may be turned on, and the switches SWI, SWIB, SWL, and SWLB may be turned off. This brings the circuit AFP and the circuit MP[i,j] into a conductive state, so that information (e.g., potential, current, etc.) can be supplied from the circuit MP[i,j] to the circuit AFP.

[0310] Note that the switching circuit TW[j] and the circuit ILD that can be used in the arithmetic circuit 150 of one embodiment of the present invention are not limited to the circuit configuration shown in Figure 18A. The circuit configurations of the switching circuit TW[j] and the circuit ILD can be changed depending on the situation. For example, switches SWH and SWHB may be added to the switching circuit TW[j] shown in Figure 18A, and a wiring VCN2 may be provided in the circuit ILD. An example of such a configuration is shown in Figure 18B.

[0311] 18B, a first terminal of the switch SWH is electrically connected to the line OL[j], and a second terminal of the switch SWH is electrically connected to the line VCN2. Also, a first terminal of the switch SWHB is electrically connected to the line OLB[j], and a second terminal of the switch SWHB is electrically connected to the line VCN2.

[0312] The wiring VCN2 functions as a wiring that supplies a constant voltage to the wiring OL[j] and / or the wiring OLB[j]. For example, when a current (positive current) flows from the circuit ILD to the wiring OL or the wiring OLB via the switching circuit TW[j], the constant voltage provided by the wiring VCN2 is preferably a high-level potential (e.g., VDD). Furthermore, when a current (negative current) flows from the wiring OL or the wiring OLB to the circuit ILD via the switching circuit TW[j], the constant potential provided by the wiring VCN2 is preferably a ground potential or a low-level potential (e.g., VSS). In particular, the voltage provided by the wiring VCN4 is preferably the voltage of the wiring VCN4 described in FIGS. 6A and 6C.

[0313] In the circuit configuration of FIG. 18B, by turning off the switches SWI, SWIB, SWO, SWOB, SWL, and SWLB and turning on the switches SWH and SWHB, the voltage applied by the wiring VCN2 can be input to each of the wiring OL[j] and the wiring OLB[j]. Here, for example, if the voltage applied by the wiring VCN2 is the same as the voltage applied by the wiring VCN4 described in FIGS. 6A to 6C, the same voltage as that applied by the wiring VCN4 can be applied to the wiring OL[j] and the wiring OLB[j] by turning on the switches SWH and SWHB instead of turning on the switches SWR3 and SWR3B between times T01 and T02 in the operation example of the timing chart of FIG. 9. In other words, by applying the circuit configuration of FIG. 18B to the arithmetic circuit 140, the switch SWR3 (switch SWR3B) illustrated in the circuit IVTR (circuit IVTRr) of FIGS. 6A to 6C can be omitted.

[0314] Here, an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 150 will be described.

[0315] 19A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 150. Specifically, the circuit MP[i,j] in FIG. 19A is a circuit obtained by modifying the configuration of the circuit MP[i,j] in FIG. 13A, and is configured by combining the wiring IL[j] and wiring OL[j] of the circuit MP[i,j] in FIG. 13A into one wiring, and by combining the wiring ILB[j] and wiring OLB[j] into one wiring. Therefore, for the circuit MP[i,j] in FIG. 19A, the description of the circuit MP[i,j] in FIG. 13A should be referred to.

[0316] Next, an example of a modification of the circuit MP[i,j] in Fig. 19A will be described. Note that, for the modification of the circuit MP[i,j], differences from the circuit MP[i,j] in Fig. 19A will be mainly described, and descriptions of parts common to the circuit MP[i,j] in Fig. 19A may be omitted.

[0317] The circuit MP[i,j] shown in FIG. 19B has a configuration in which the wiring X1L[i] in the circuit MP[i,j] of FIG. 19A is replaced with wiring WX1L[i]. That is, in the circuit MP[i,j] of FIG. 19B, the wiring WX1L[i] and the wiring WL[i] function as wirings that supply a predetermined potential in order to switch the conductive state or non-conductive state between the wiring OL[j] and the holding unit HC, and to switch the conductive state or non-conductive state between the wiring OLB[j] and the holding unit HCr. Also, in the circuit MP[i,j] of FIG. 19B, the wiring WX1L[i] and the wiring X2L[i] are used to supply the second data z input to the circuit MP[i,j]. i (k-1) 19B. The specific circuit configuration of FIG.

[0318] Next, an example of modifying the circuit MP[i,j] in FIG. 19A, which is different from FIG. 19B, will be described. The circuit MP[i,j] shown in FIG. 19C is a modified example of the circuit MP[i,j] in FIG. 19A. The circuit MP[i,j] in FIG. 19C has a circuit MC and a circuit MCr, similar to the circuit MP[i,j] in FIG. 19A. However, the circuit MP[i,j] in FIG. 19C is different from the circuit MP[i,j] in FIG. 19A in that the holding portion HCr is not included in the circuit MCr.

[0319] In addition, since the circuit MCr does not have the holding portion HCr, the arithmetic circuit to which the circuit MP[i,j] in FIG. 19C is applied may not have a wiring for supplying the potential held in the holding portion HCr. Further, the circuit MCr may not be electrically connected to the wiring WL[i].

[0320] In the circuit MP[i,j] of FIG. 19C, the holding portion HC included in the circuit MC is electrically connected to the circuit MCr. That is, the circuit MP[i,j] of FIG. 19C is configured such that the circuit MCr and the circuit MC share the holding portion HC with each other. As an example, an inverted signal can be supplied from the holding portion HC to the circuit MCr for the signal held in the holding portion HC. Thereby, different operations can be performed by the circuit MC and the circuit MCr. Alternatively, the internal circuit configurations of the circuit MC and the circuit MCr can be made different, and as a result, the magnitudes of the currents output by the circuit MC and the circuit MCr can be made different for the same signal held in the holding portion HC. Here, the holding portion HC holds the potential corresponding to the first data w i (k-1) j (k) and supplies the potential corresponding to the second data z i (k-1) to the wirings X1L[i] and X2L[i]. Thereby, the circuit MP[i,j] supplies the first data w i (k-1) j (k) and the second data z i (k-1)It is possible to output a current corresponding to the product with. Note that the specific circuit configuration of FIG. 19C will be described in Embodiment 3.

[0321] The circuit MP[i,j] shown in FIG. 19D is a modification of the circuit MP[i,j] in FIG. 19A and is also a modification of the circuit MP[i,j] in FIG. 13C. Specifically, the circuit MP[i,j] in FIG. 19D is configured by combining the wiring IL[j] and the wiring OL[j] into one wiring OL[j] and combining the wiring ILB[j] and the wiring OLB[j] into one wiring OLB[j] in FIG. 13C. Therefore, for the circuit MP[i,j] in FIG. 19D, refer to the description of the circuit MP[i,j] in FIG. 13C.

[0322] The circuit MP[i,j] shown in FIG. 19E is a modification of the circuit MP[i,j] in FIG. 19A and is also a modification of the circuit MP[i,j] in FIG. 13D. Specifically, the circuit MP[i,j] in FIG. 19D is configured without providing the wiring IL[j] and the wiring ILB[j] in FIG. 13D. Therefore, for the circuit MP[i,j] in FIG. 19D, refer to the description of the circuit MP[i,j] in FIG. 13D.

[0323] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0324] (Embodiment 3) In this embodiment, specific configuration examples of the circuit MP described in Embodiment 1 and Embodiment 2 will be described.

[0325] In Embodiment 1 and Embodiment 2, [1,1], [i,j], [m,n], etc. indicating the positions in the array unit ALP are appended to the reference numerals of the circuit MP. However, in this embodiment, unless otherwise specified, descriptions such as [1,1], [i,j], [m,n], etc. are omitted for the reference numerals of the circuit MP.

[0326] <Configuration Example 1> First, an example of a circuit configuration applicable to the circuit MP of Fig. 13A will be described. The circuit MP shown in Fig. 20A is an example of the configuration of the circuit MP of Fig. 13A, and the circuit MC included in the circuit MP of Fig. 20A has, for example, a transistor M1, switches S2 to S5, and a capacitor C1. Note that, for example, the switch S2, the switch S5, and the capacitor C1 form a holding unit HC.

[0327] Note that the switches S2 to S5 may be electric switches or mechanical switches. The electric switches may be, for example, transistors. That is, the switches S2 to S5 may be transistors similar to the transistor M1. In particular, it is preferable to use an OS transistor with a very low off-state current as the switch S2 in order to hold a potential at the first terminal of the capacitor C1 for a long time. Note that the OS transistor will be described in detail in Embodiment 5.

[0328] 20A, the circuit MCr has a circuit configuration similar to that of the circuit MC, and therefore, the circuit elements of the circuit MCr are designated by the letter "r" to distinguish them from the circuit elements of the circuit MC.

[0329] The transistor M1 shown in FIG. 20A is, for example, an n-channel transistor with a multi-gate structure having gates above and below the channel. The transistor M1 has a first gate and a second gate. For convenience, the present specification and the like distinguishes between the first gate (sometimes referred to as a front gate) and the second gate (sometimes referred to as a back gate). However, the first gate and the second gate can be interchanged. Therefore, the term "gate" can be interchanged with the term "back gate." Similarly, the term "back gate" can be interchanged with the term "gate." Specifically, the connection configuration in which "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be replaced with the connection configuration in which "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring." For example, as shown in FIG. 20B, the back gate of the transistor M1 may be electrically connected to the first terminal of the capacitor C1 and the first terminal of the switch S2.

[0330] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the connection configuration of the back gate of the transistor. The back gate of the transistor M1 in FIG. 20A is illustrated, but the connection configuration of the back gate is not illustrated. However, the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and the back gate of the transistor M1 may be electrically connected. Furthermore, for example, in a transistor having a back gate, a wiring electrically connected to an external circuit or the like may be provided so that a potential can be applied to the back gate of the transistor from the external circuit or the like to change the threshold voltage of the transistor or reduce the off-state current of the transistor. Note that this also applies to transistors described elsewhere in the specification or illustrated in other drawings, not just FIG. 20A.

[0331] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the structure of the transistor included in the semiconductor device. For example, the transistor M1 illustrated in FIG. 20A may have a structure without a back gate, that is, a single-gate transistor, as illustrated in FIG. 20C. Alternatively, some transistors may have a back gate, and other transistors may not have a back gate. This applies not only to the circuit diagram illustrated in FIG. 20A but also to transistors described elsewhere in the specification or illustrated in other drawings.

[0332] Furthermore, in this specification and the like, transistors with various structures can be used as transistors. Therefore, the type of transistor to be used is not limited. Examples of transistors include transistors having single crystal silicon, and transistors having non-single crystal semiconductor films typified by amorphous silicon, polycrystalline silicon, and microcrystalline (also referred to as microcrystal, nanocrystal, or semi-amorphous) silicon. Alternatively, thin film transistors (TFTs) formed by thinning such semiconductors can be used. The use of TFTs offers various advantages. For example, TFTs can be manufactured at lower temperatures than single crystal silicon, thereby reducing manufacturing costs and increasing the size of the manufacturing equipment. The use of larger manufacturing equipment allows for manufacturing on a large substrate. Therefore, a large number of display devices can be manufactured simultaneously, resulting in low manufacturing costs. Alternatively, the low manufacturing temperature allows for the use of a substrate with poor heat resistance. Therefore, transistors can be manufactured on a light-transmitting substrate. Alternatively, light transmission through a display element can be controlled using a transistor on a light-transmitting substrate. Alternatively, the thin film thickness of the transistor allows light to pass through a portion of the film forming the transistor. Therefore, the aperture ratio can be improved.

[0333] Examples of transistors that can be used include transistors containing compound semiconductors (e.g., SiGe, GaAs, etc.) or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, In-Sn-O (ITO), Sn-O, Ti-O, Al-Zn-Sn-O (AZTO), In-Sn-Zn-O, etc.). Alternatively, thin-film transistors formed by thinning these compound semiconductors or these oxide semiconductors can be used. This allows the manufacturing temperature to be lowered, making it possible to manufacture transistors at room temperature, for example. As a result, transistors can be formed directly on substrates with low heat resistance, such as plastic substrates or film substrates. These compound semiconductors or oxide semiconductors can be used not only for the channel portion of transistors but also for other applications. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistors, pixel electrodes, or light-transmitting electrodes. These can be deposited or formed simultaneously with transistors, thereby reducing costs.

[0334] As an example of a transistor, a transistor formed by an inkjet method or a printing method can be used. These methods allow manufacturing at room temperature, in a low vacuum, or on a large substrate. Therefore, manufacturing can be performed without using a mask (reticle), and the layout of the transistor can be easily changed. Furthermore, manufacturing can be performed without using a resist, which reduces material costs and the number of steps. Furthermore, since a film can be applied only to a necessary portion, material is not wasted and manufacturing can be performed at a low cost compared to a manufacturing method in which a film is formed on the entire surface and then etched.

[0335] As an example of a transistor, a transistor having an organic semiconductor or a carbon nanotube can be used. This allows a transistor to be formed on a flexible substrate. A device using a transistor having an organic semiconductor or a carbon nanotube can be made resistant to impacts.

[0336] It should be noted that various other structures of transistors can be used. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as transistors. By using MOS transistors as transistors, the size of the transistors can be reduced. Therefore, a large number of transistors can be mounted. By using bipolar transistors as transistors, a large current can be passed. Therefore, the circuit can operate at high speed. It should be noted that MOS transistors and bipolar transistors can be mixed and formed on a single substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc.

[0337] As an example of a transistor, a transistor with a structure in which gate electrodes are arranged above and below the active layer can be applied. By adopting a structure in which gate electrodes are arranged above and below the active layer, a circuit configuration is created in which multiple transistors are connected in parallel. This increases the channel formation region, making it possible to increase the current value. Alternatively, by adopting a structure in which gate electrodes are arranged above and below the active layer, it becomes easier to create a depletion layer, making it possible to improve the S value.

[0338] Examples of the transistor include a transistor having a structure in which a gate electrode is disposed above an active layer, a structure in which a gate electrode is disposed below an active layer, a staggered structure, an inverted staggered structure, a structure in which a channel region is divided into multiple regions, a structure in which active layers are connected in parallel, or a structure in which active layers are connected in series. Alternatively, the transistor may have various configurations, such as a planar type, a FIN type (fin type), a TRI-GATE type, a top gate type, a bottom gate type, and a double gate type (gates are disposed above and below the channel).

[0339] As an example of a transistor, a transistor having a structure in which a source electrode or a drain electrode overlaps with an active layer (or a part thereof) can be used. By adopting a structure in which a source electrode or a drain electrode overlaps with an active layer (or a part thereof), it is possible to prevent unstable operation due to charge accumulation in a part of the active layer.

[0340] As an example of a transistor, a structure with an LDD region can be applied. By providing the LDD region, it is possible to reduce the off-state current or improve the breakdown voltage (reliability) of the transistor. Alternatively, by providing the LDD region, it is possible to obtain voltage-current characteristics in which the drain current does not change much even when the voltage between the drain and source changes when operating in the saturation region.

[0341] For example, in this specification, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. Examples of such substrates include semiconductor substrates (e.g., single-crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, and base films. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is synthetic resins such as acrylic. Examples of suitable substrates include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of suitable substrates include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, and paper. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, and SOI substrates, it is possible to manufacture transistors with small size, high current capability, and little variation in characteristics, size, and shape. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0342] Alternatively, a flexible substrate may be used as the substrate, and the transistor may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistor. The peeling layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate and transfer it to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. Note that the peeling layer may be, for example, a laminated structure of inorganic films such as a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on a substrate.

[0343] That is, a transistor may be formed on a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on the other substrate. Examples of substrates onto which transistors may be transferred include, in addition to the substrates on which the transistors can be formed described above, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester)), leather substrates, and rubber substrates. The use of these substrates allows for the formation of transistors with good characteristics, the formation of transistors with low power consumption, the manufacture of durable devices, the provision of heat resistance, and the reduction of weight and thickness.

[0344] It is possible to form all of the circuits required to achieve a given function on the same substrate (e.g., a glass substrate, a plastic substrate, a single-crystal substrate, or an SOI substrate), thereby reducing the number of components and thereby reducing costs, and improving reliability by reducing the number of connections to circuit components.

[0345] It is possible that not all of the circuits necessary to realize a predetermined function are formed on the same substrate. That is, a portion of the circuits necessary to realize a predetermined function may be formed on one substrate, and another portion of the circuits necessary to realize the predetermined function may be formed on another substrate. For example, a portion of the circuits necessary to realize a predetermined function may be formed on a glass substrate, and another portion of the circuits necessary to realize the predetermined function may be formed on a single-crystal substrate (or an SOI substrate). Then, the single-crystal substrate (also called an IC chip) on which the other portion of the circuits necessary to realize the predetermined function is formed may be connected to the glass substrate by COG (Chip-On-Glass) and the IC chip may be disposed on the glass substrate. Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip-On-Film), SMT (Surface Mount Technology), a printed circuit board, or the like. In this way, forming a portion of the circuit on the same substrate as the pixel unit may reduce the number of components, thereby reducing costs, or reduce the number of connections with circuit components, thereby improving reliability. In particular, circuits with high drive voltages or high drive frequencies often consume a lot of power. Therefore, these circuits are formed on a substrate (such as a single-crystal substrate) separate from the pixel section to form an IC chip. Using this IC chip can prevent an increase in power consumption.

[0346] In the circuit MP of FIG. 20A, a first terminal of a transistor M1 is electrically connected to a wiring VE. A second terminal of the transistor M1 is electrically connected to a first terminal of a switch S3, a first terminal of a switch S4, and a first terminal of a switch S5. A gate of the transistor M1 is electrically connected to a first terminal of a capacitor C1 and a first terminal of a switch S2. A second terminal of the capacitor C1 is electrically connected to a wiring VE. A second terminal of the switch S2 is electrically connected to a second terminal of the switch S5 and a wiring IL. A control terminal of the switch S2 is electrically connected to a wiring WL. A second terminal of the switch S3 is electrically connected to a wiring OL, and a control terminal of the switch S3 is electrically connected to a wiring X1L. A second terminal of the switch S4 is electrically connected to a wiring OLB, and a control terminal of the switch S4 is electrically connected to a wiring X2L.

[0347] A connection configuration in the circuit MCr that is different from that in the circuit MC will be described. The second terminal of the switch S3r is electrically connected to the wiring OLB instead of the wiring OL, and the second terminal of the switch S4r is electrically connected to the wiring OL instead of the wiring OLB. The first terminal of the transistor M1r and the first terminal of the capacitor C1r are electrically connected to the wiring VEr.

[0348] 20A may be changed to the configuration of the circuit MP of FIG. 21A. Specifically, the first terminal of the transistor M1 may be electrically connected to another wiring VEm instead of the wiring VE, and the first terminal of the transistor M1r may be electrically connected to another wiring VEmr instead of the wiring VEr. In addition to the circuit MP of FIG. 20A, circuit diagrams of other drawings may also be configured such that the first terminal of the transistor M1 is electrically connected to another wiring VEm instead of the wiring VE, and / or the first terminal of the transistor M1r is electrically connected to another wiring VEmr instead of the wiring VEr.

[0349] In the holding unit HC shown in FIG. 20A, the electrical connection point between the gate of the transistor M1, the first terminal of the capacitor C1, and the first terminal of the switch S2 is defined as a node n1.

[0350] As described in the first embodiment, the holding unit HC has a function of holding a potential corresponding to the first data, for example. The holding unit HC included in the circuit MC of FIG. 20A holds the potential by inputting a potential from the wiring IL and writing it to the capacitor C1 when the switches S2 and S5 are turned on, and then turning off the switch S2. This allows the potential of the node n1 to be held as a potential corresponding to the first data. At this time, a current is input from the wiring OL, and a potential corresponding to the magnitude of the current can be held in the capacitor C1. This reduces the influence of variations in the current characteristics of the transistor M1.

[0351] In addition, since the transistor M1 holds the potential of the node n1 for a long time, it is preferable to use a transistor with low off-state current. For example, an OS transistor can be used as the transistor M1. Alternatively, a transistor with a back gate may be used as the transistor M1, and a low-level potential may be applied to the back gate to shift the threshold voltage to the positive side, thereby reducing the off-state current.

[0352] In the operation example described below, in order to simply explain the current flowing in and out of the circuit MP, one end of the wiring IL shown in Figure 20A is referred to as node ina, one end of the wiring OL is referred to as node outa, one end of the wiring ILB is referred to as node inb, and one end of the wiring OLB is referred to as node outb.

[0353] For example, the wiring VE functions as a wiring that supplies a constant voltage. When the switch S3, the switch S3r, the switch S4, or the switch S4r is an n-channel transistor and / or when the potential provided by the wiring VSO in FIGS. 14A to 14C is a high-level potential, the constant voltage can be, for example, a low-level potential VSS, a ground potential, or another low-level potential. Similarly to the wiring VE, each of the wirings VEm, VEr, and VEmr functions as a voltage line that supplies a constant voltage. The constant voltage can be a low-level potential VSS, a low-level potential other than VSS, or a ground potential. The constant voltage may also be a high-level potential VDD. In this case, when any of FIGS. 6A to 6C is used as the circuit IVTR (circuit IVTRr) of the arithmetic circuit 110, the constant voltage provided by the wiring VCN4 electrically connected to the circuits ACTF[1] to ACTF[n] is preferably higher than the potential VDD provided by the wirings VE and VEr.

[0354] Furthermore, the constant voltages supplied by the wirings VE, VEm, VEAr, and VEmr may be different from one another, or some or all of them may be the same. Furthermore, if the voltages supplied by the wirings are the same, those wirings may be selected and used as the same wiring. For example, if the constant voltages supplied by the wirings VE, VEm, VEAr, and VEmr are approximately the same, the wirings VEm, VEAr, and VEmr may be used as the same wiring as the wiring VE, as shown in the circuit MP of FIG. 21B. Alternatively, if the constant voltages supplied by the wirings VE and VEAr are approximately the same, the wirings VE and VEAr may be used as a single wiring. Alternatively, in FIG. 21A, for example, the wirings VE and VEAr may be used as a single wiring, and the wirings VEm and VEmr may be used as a single wiring. Alternatively, for example, the wirings VE and VEmr may be used as a single wiring, and the wirings VEm and VEr may be used as a single wiring (not shown).

[0355] The configuration of the circuit MP in FIG. 20A can be changed depending on the situation. For example, as shown in FIG. 22A, the transistors M1 and M1r in the circuit MP in FIG. 20A may be replaced with p-channel transistors M1p and M1pr, respectively. In this case, the constant voltage applied by the wirings VE and VEr is preferably a high-level potential, VDD. In addition, when any of FIGS. 6A to 6C is used as the circuits IVTR and IVTRr included in the circuits ACTF[1] to ACTF[n] of the arithmetic circuit 110, the constant voltage applied by the wiring VCN4 is preferably a ground potential or VSS. In this way, when the potential of the wiring is changed, the direction of current flow is also changed.

[0356] 22B, for example, the switches S3, S3r, S4, and S4r in the circuit MP of FIG. 20A may be replaced with analog switches AS3, AS4, AS3r, and AS4r, respectively. Note that FIG. 22B also illustrates wires X1LB and X2LB for operating the analog switches AS3, AS4, AS3r, and AS4r. The wire X1LB is electrically connected to the analog switches AS3 and AS3r, and the wire X2LB is electrically connected to the analog switches AS4 and AS4r. An inverted signal of a signal input to the wire X1L is input to the wire X1LB, and an inverted signal of a signal input to the wire X2L is input to the wire X2LB. Alternatively, the wires X1L and X2L may be combined into a single wire, and the wires X1LB and X2LB may be combined into a single wire (not illustrated). As an example, the analog switches AS3, AS4, AS3r, and AS4r may have a CMOS configuration using n-channel transistors and p-channel transistors.

[0357] Furthermore, when transistors are applied to the switches S3, S3r, S4, and S4r shown in FIGS. 20A to 20C, 21A, 21B, and 22A, it is preferable that the sizes of the transistors, such as channel length and channel width, are equal to each other. Such a circuit configuration may enable an efficient layout. It may also enable the currents flowing through the switches S3, S3r, S4, and S4r to be uniform. Similarly, it is preferable that the sizes of the transistors M1 and M1r shown in FIGS. 20A to 20C, 21A, and 21B are equal to each other. Similarly, when transistors are applied to the switches S2 and S2r shown in FIGS. 20A to 20C, 21A, and 21B, it is preferable that the sizes of the transistors are equal to each other. <<Example 1>> Next, an operation example of the circuit MP shown in FIG. 20A will be described. FIGS. 23A to 23C, 24A to 24C, and 25A to 25C are timing charts showing an operation example of the circuit MP, each showing fluctuations in the potential of the wiring WL, the wiring X1L, the wiring X2L, the node n1, and the node n1r. Note that "high" in FIGS. 23A to 23C, 24A to 24C, and 25A to 25C indicates a high-level potential, and "low" indicates a low-level potential. In this operation example, the amount of current input from the node ina to the wiring IL (or from the wiring IL to the node ina) is I IL The amount of current input from node inb to wiring ILB (or from wiring ILB to node inb) is I ILB In addition, the amount of current output from the wiring OL to the node outa (or from the node outa to the wiring OL) is I OL The amount of current output from wiring OLB to node outb (or from node outb to wiring OLB) is I OLB In the timing charts shown in FIGS. 23A to 23C, 24A to 24C, and 25A to 25C, the amount of current I IL , I ILB , I OL , I OLB The change in the

[0358] In this operation example, the constant voltages applied by the wirings VE, VEm, VAr, and VEmr are VSS (low-level potential). In this case, in FIG. 14A, a high-level potential is applied to the wiring VSO, and a current flows from the wiring VSO to the wiring VE or VAr via the wiring OL. Similarly, a current flows from the wiring VSO to the wiring VE or VAr via the wiring OLB. In the circuit configuration shown in FIG. 14A, the potential applied by the wiring VCN is VSS. By establishing electrical continuity between the wiring VCN and the second terminal of the transistor M1, VSS is applied to the second terminal of the transistor M1. As will be described in detail later, at this time, the potential of the gate of the transistor M1 also becomes VSS, so the transistor M1 is turned off. Similarly, by establishing electrical continuity between the wiring VCN and the second terminal of the transistor M1r, the potentials of the second terminal and gate of the transistor M1r become VSS, so the transistor M1r is turned off.

[0359] In this operation example, the circuit IVTR (circuit IVTRr) included in the circuit ACTF is the circuit IVTR (circuit IVTRr) shown in Fig. 6A. In the circuit IVTR (circuit IVTRr) shown in Fig. 6A, the potential applied by the wiring VCN4 is VDD.

[0360] In the circuit MP shown in FIG. 20A, when the switches S2 and S5 are on, the transistor M1 is diode-connected. Therefore, when a current flows from the wiring OL to the circuit MC, the potentials of the second terminal of the transistor M1 and the gate of the transistor M1 are approximately equal. This potential is determined by the amount of current flowing from the wiring OL to the circuit MC and the potential of the first terminal of the transistor M1 (VSS in this case). Here, by holding the potential of the gate of the transistor M1 in the capacitor C1 and then turning off the switch S2, the transistor M1 functions as a current source that flows a current corresponding to the potential of the gate of the transistor M1. This reduces the effects of variations in the current characteristics of the transistor M1.

[0361] For example, when switches S2 and S5 are in the on state and a current I1 flows from wiring OL to wiring VE via circuit MC, the potential of the gate (node ​​n1) of transistor M1 becomes V1. Here, by turning switch S2 off, V1 is held by the holding unit HC. This allows transistor M1 to flow, between the source and drain of transistor M1, a current I1 that corresponds to the potential VSS of the first terminal of transistor M1 and the potential V1 of the gate of transistor M1. In this specification, this type of operation is referred to as "transistor M1 has the amount of current flowing between the source and drain of transistor M1 set (programmed) to I1."

[0362] In this operation example, the amount of current flowing from the wiring OL to the circuit MC is assumed to be three levels: 0, I1, and I2. Therefore, the amount of current set to the transistor M1 is three levels: 0, I1, and I2. For example, when the gate potential of the transistor M1 held in the holding unit HC is VSS, the potentials of the first and second terminals of the transistor M1 are also VSS. Therefore, if the threshold voltage of the transistor M1 is higher than 0, the transistor M1 is in the off state. Therefore, no current flows between the source and drain of the transistor M1, and the amount of current flowing between the source and drain of the transistor M1 can be said to be set to 0. Also, for example, when the gate potential of the transistor M1 held in the holding unit HC is V1, if the threshold voltage of the transistor M1 is lower than V1-VSS, the transistor M1 is in the on state. In this case, the amount of current flowing through the transistor M1 is assumed to be I1. Therefore, when the gate potential of the transistor M1 is V1, the amount of current flowing between the source and drain of the transistor M1 can be said to be set to I1. Furthermore, for example, when the gate potential of transistor M1 held in holding unit HC is V2, if the threshold voltage of transistor M1 is lower than V2-VSS, transistor M1 is turned on. At this time, the amount of current flowing through transistor M1 is set to I2. Therefore, when the gate potential of transistor M1 is V2, the amount of current flowing between the source and drain of transistor M1 can be said to be set to I2.

[0363] It is assumed that the current amount of I1 is greater than 0 and smaller than I2. The potential V1 is higher than VSS and lower than V2. The threshold voltage of the transistor M1 is higher than 0 and lower than V1-VSS. I1 is, for example, the current I generated by the constant current source circuit ISC1 in the description of FIG. 14A. ut and I2 can be replaced with, for example, 2I generated by the constant current source circuit ISC2 in the description of FIG. 14A. ut can be replaced with

[0364] Before describing the operation example, the first data (here, a weighting coefficient, for example) held by the circuit MP will be defined as follows: When VSS is held at node n1 of the holding unit HC and VSS is held at node n1r of the holding unit HCr, the circuit MP will hold "0" as the first data (weighting coefficient). When V1 is held at node n1 of the holding unit HC and VSS is held at node n1r of the holding unit HCr, the circuit MP will hold "+1" as the first data (weighting coefficient). When V2 is held at node n1 of the holding unit HC and VSS is held at node n1r of the holding unit HCr, the circuit MP will hold "+2" as the first data (weighting coefficient). When VSS is held at node n1 of the holding unit HC and V1 is held at node n1r of the holding unit HCr, the circuit MP will hold "-1" as the first data (weighting coefficient). When VSS is held at node n1 of the holding unit HC and V2 is held at node n1r of the holding unit HCr, it is assumed that the circuit MP holds "-2" as the first data (weighting coefficient).

[0365] Furthermore, the second data (here, the neuron signal value (computed value)) input to the circuit MP is defined as follows, for example: When a high-level potential is applied to the wire X1L and a low-level potential is applied to the wire X2L, "+1" is input to the circuit MP as the second data (neuron signal value). When a low-level potential is applied to the wire X1L and a high-level potential is applied to the wire X2L, "-1" is input to the circuit MP as the second data (neuron signal value). When a low-level potential is applied to the wire X1L and a low-level potential is applied to the wire X2L, "0" is input to the circuit MP as the second data (neuron signal value). Note that, as an example, the high-level potential is VDD or a potential that is 10% or more, or 20% or more higher than VDD.

[0366] Furthermore, in this specification and the like, unless otherwise specified, the transistors M1 and M1r are considered to ultimately operate in the saturation region when they are on. That is, the gate voltage, source voltage, and drain voltage of each of the above-described transistors are considered to include a case where they are appropriately biased to a voltage range in which they operate in the saturation region. However, one aspect of the present invention is not limited to this. In order to reduce the amplitude of the supplied voltage, the transistors M1 and M1r may operate in the linear region. Note that when the first data (weighting coefficient) is an analog value, the transistors M1 and M1r may operate in both the linear region and the saturation region depending on the magnitude of the first data (weighting coefficient), for example.

[0367] Furthermore, in this specification and the like, unless otherwise specified, switches S2, S2r, S3, S3r, S4, S4r, S5, and S5r are assumed to be in an on state when a high-level potential is input to their control terminals, and to be in an off state when a low-level potential is input to their control terminals.

[0368] Below, we will explain an example of the operation of circuit MP for each combination of values ​​that the first data (for example, referred to as a weighting coefficient below) and the second data (for example, referred to as the neuron signal value (calculated value) below) can take.

[0369] [Condition 1] First, as an example, consider the case where the first data (weighting coefficient) is "0" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "+1." Figure 23A is a timing chart of the circuit MP in this case.

[0370] Between time T11 and time T12, the holding units HC and HCr hold the initial potentials. In Fig. 23A, for example, it is assumed that the nodes n1 and n1r hold a potential higher than the potential VSS as the initial potential.

[0371] Furthermore, a low-level potential is applied to the wiring WL, the wiring X1L, and the wiring X2L, and as a result, a low-level potential is input to the control terminals of the switches S2, S2r, S3, S3r, S4, S4r, S5, and S5r, and therefore the switches S2, S2r, S3, S3r, S4, S4r, S5, and S5r are each turned off.

[0372] Between time T12 and time T13, a high-level potential is applied to the wiring WL, which causes the control terminals of the switches S2, S2r, S5, and S5r to receive high-level potential, turning on the switches S2, S2r, S5, and S5r.

[0373] Although not shown in FIG. 23A, the wiring IL and the wiring ILB are each supplied with an initialization potential V ini Since the switches S2, S2r, S5, and S5r are in the on state, the potentials of the node n1 of the holding unit HC and the node n1r of the holding unit HCr are V ini That is, between time T12 and time T13, the potentials of the node n1 of the holding unit HC and the node n1r of the holding unit HCr are initialized.

[0374] In addition, the initialization potential V ini For example, it is preferable to set the initial potential V ini The initial potential V may be VSS, a potential higher than the ground potential, or a potential lower than the ground potential. ini The wirings IL and ILB may be set to different potentials. iniIt is not necessary to input the initialization potential V. It is not necessary to provide a period from time T12 to time T13. It is also not necessary to perform the initialization between time T12 and time T13. It is also possible to input the initialization potential V ini Although a wiring for applying the initial potential V and a switch for connecting the wiring to the wiring IL and the wiring ILB are not shown in the figure, in this operation example, the circuit ILD shown in FIG. 14A applies the initial potential V to the wiring IL and the wiring ILB. ini It shall have the function of providing the following.

[0375] Between time T13 and time T14, the potential VSS is input from the wiring IL to the circuit MC, and the potential VSS is input from the wiring ILB to the circuit MCr. In FIG. 14A, this is achieved by turning on the switches SWLA and SWLAB and turning off the switches SWIA and SWIAB. Also, in FIG. 6A, this is achieved by turning off the switch SWR3 (switch SWR3B). As a result, the potential of the node n1 of the holding unit HC becomes VSS, and the potential of the node n1r of the holding unit HCr becomes VSS. As a result, in the circuit MC, the transistor M1 is set to pass a current of 0, so no current flows from the wiring OL to the wiring VE via the circuit MC. Also, in the circuit MCr, the transistor M1r is set to pass a current of 0, so no current flows from the wiring OLB to the wiring VE via the circuit MCr. In other words, between time T13 and time T14, the transistors M1 and M1r are in the off state, so that there is no conduction between the wiring OL and the wiring VE, and there is no conduction between the wiring OLB and the wiring VEr.

[0376] Between time T14 and time T15, a low-level potential is applied to the wiring WL and the wiring X1L. As a result, a low-level potential is input to the control terminals of the switches S2, S2r, S5, and S5r, respectively, and the switches S2, S2r, S5, and S5r are turned off. With the switches S2 and S2r turned off, the potential VSS of the node n1 of the holding unit HC is held, and the potential VSS of the node n1r of the holding unit HCr is held. Furthermore, with the switch S5 turned off, no current flows from the wiring IL to the wiring VE via the circuit MC. Similarly, with the switch S5r turned off, no current flows from the wiring ILB to the wiring VEr via the circuit MCr. Between time T14 and time T15, the switches SWR3 and SWR3B shown in FIG. 6A may be turned on to initialize the potentials of the wiring OL and the wiring OLB. By initializing the potentials of the wirings OL and OLB, the potentials of the wirings OL and OLB can be changed by the current output from the circuit MP after time T15.

[0377] Through the operation from time T11 to time T15, "0" is set as the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, the switches SWIA, SWIAB, SWLA, and SWLAB in FIG. 14A may be turned off. After the weighting coefficient is set in the circuit MP, the switches SWR3 and SWR3B shown in FIG. 6A may be turned on to initialize the potentials of the wirings OL and OLB. After the potentials of the wirings OL and OLB are initialized, the switches SWR3 and SWR3B may be turned off.

[0378] After time T15, a high-level potential is input to the wire X1L and a low-level potential is input to the wire X2L as an input of the neuron signal (computed value) "+1" to the circuit MP. At this time, a high-level potential is input to the control terminals of the switches S3 and S3r, and a low-level potential is input to the control terminals of the switches S4 and S4r. As a result, the switches S3 and S3r are turned on, and the switches S4 and S4r are turned off. In other words, this operation brings about a conductive state between the circuit MC and the wire OL, and between the circuit MCr and the wire OLB, and a non-conductive state between the circuit MC and the wire OLB, and between the circuit MCr and the wire OL. As a result, a conductive state is brought about between the circuit MC and the circuit AFP, and a conductive state is brought about between the circuit MCr and the circuit AFP.

[0379] Since the transistor M1 is in the off state (since the amount of current is set to 0), in the circuit MC, no current flows from the wiring OL and wiring OLB to the wiring VE. Similarly, since the transistor M1r is in the off state (since the amount of current is set to 0), in the circuit MCr, no current flows from the wiring OL and OLB to the wiring VE. From the above, the current I output from the node outa of the wiring OL OL , and the current I output from node outb of wiring OLB OLB does not change before and after time T15. Therefore, the current I OL does not flow, and the current I OLB does not flow.

[0380] In this condition, the first data (weighting coefficient) is set to "0" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "+1". Therefore, when using equation (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is that in the operation of the circuit MP, the current I OL and current IOLB The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" corresponds to the case where the signal z j (k) is output as

[0381] Note that once the first data (e.g., weighting coefficient) is input, multiple product-sum operations may be performed by changing only the second data (e.g., neuron signal value or calculated value) without updating the first data. In this case, updating the first data (weighting coefficient) is not necessary, which reduces power consumption. Note that in order to reduce the frequency of updating the first data (weighting coefficient), the first data (weighting coefficient) needs to be held for a long period of time. In this case, for example, by using an OS transistor, the first data (weighting coefficient) can be held for a long period of time by taking advantage of its low off-state current.

[0382] [Condition 2] Next, as an example, consider a case where the first data (weighting coefficient) is "+1" and the second data (neuron signal value (calculated value)) input to the circuit MP is "+1." Figure 23B is a timing chart of the circuit MP in this case.

[0383] The operation from time T11 to time T13 is similar to the operation from time T11 to time T13 in condition 1, so the explanation of the operation from time T11 to time T13 in condition 1 will be taken into consideration.

[0384] Between time T13 and time T14, a current of I1 is input from the wiring IL to the circuit MC, and a potential VSS is input from the wiring ILB to the circuit MCr. This is achieved by turning on the switches SWIA and SWLAB and turning off the switches SWIAB and SWLA in FIG. 14. As a result, the potential of the node n1 of the holding unit HC becomes V1, and the potential of the node n1r of the holding unit HCr becomes VSS. As a result, in the circuit MC, the transistor M1 is set to pass a current of I1, so that a current of I1 flows from the wiring IL to the wiring VE via the circuit MC. Furthermore, in the circuit MCr, the transistor M1r is set to pass a current of 0, so no current flows from the wiring ILB to the wiring VEr via the circuit MCr.

[0385] Between time T14 and time T15, a low-level potential is applied to the wiring WL. As a result, a low-level potential is input to the control terminals of the switches S2, S2r, S5, and S5r, respectively, and the switches S2, S2r, S5, and S5r are turned off. With the switches S2 and S2r turned off, the potential V1 of the node n1 of the holding unit HC is held, and the potential VSS of the node n1r of the holding unit HCr is held. With the switch S5 turned off, no current flows from the wiring OL to the wiring VE via the circuit MC. Similarly, with the switch S5r turned off, no current flows from the wiring OLB to the wiring VEr via the circuit MCr. Between time T14 and time T15, the switches SWR3 and SWR3B shown in FIG. 6A may be turned on to initialize the potentials of the wiring OL and the wiring OLB. By initializing the potentials of the wirings OL and OLB, the potentials of the wirings OL and OLB can be changed by the current output from the circuit MP after time T15.

[0386] Through the operations from time T11 to time T15, "+1" is set as the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, the switches SWIA, SWIAB, SWLA, and SWLAB in FIG. 14A may be turned off. After the first data (weighting coefficient) is set in the circuit MP, the switches SWR3 and SWR3B may be turned on to initialize the potentials of the wirings OL and OLB. After the potentials of the wirings OL and OLB are initialized, the switches SWR3 and SWR3B may be turned off.

[0387] After time T15, as the second data (neuron signal value (computed value)) "+1" is input to the circuit MP, a high-level potential is input to the wire X1L and a low-level potential is input to the wire X2L. At this time, a high-level potential is input to the control terminals of the switches S3 and S3r, and a low-level potential is input to the control terminals of the switches S4 and S4r. As a result, the switches S3 and S3r are turned on, and the switches S4 and S4r are turned off. In other words, this operation brings about a conductive state between the circuit MC and the wire OL, and between the circuit MCr and the wire OLB, and a non-conductive state between the circuit MC and the wire OLB, and between the circuit MCr and the wire OL. As a result, a conductive state is established between the circuit MC and the circuit AFP, and a conductive state is established between the circuit MCr and the circuit AFP.

[0388] In the circuit MC, the switch S3 is on and the transistor M1 is on (since the amount of current is set to I1), so a current flows from the wiring OL to the wiring VE. Also, in the circuit MC, the switch S4 is off, so no current flows from the wiring OLB to the wiring VE. On the other hand, in the circuit MCr, the switch S3r is on, but the transistor M1r is off (since the amount of current is set to 0), so no current flows from the wiring OLB to the wiring VE. Also, in the circuit MCr, the switch S4r is off, so no current flows from the wiring OL to the wiring VE. From the above, the current I output from the node outa of the wiring OL OL After time T15, I1 increases, and the current I output from node outb of wiring OLB OLB does not change before and after time T15. Therefore, a current I of a current magnitude I1 flows between the circuit AFP and the wiring OL. OL flows, and the current I flows between the circuit AFP and the wiring OLB. OLB does not flow.

[0389] In this condition, the first data (weighting coefficient) is set to "+1" and the second data (neuron signal value) input to the circuit MP is set to "+1". Therefore, using equation (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "+1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "+1" is that in the operation of the circuit MP, the current I OL I1 increases, and the current I OLB This corresponds to the case where the product of the first data (weighting coefficient) and the second data (neuron signal value) is "+1." In FIG. 15, the signal z j (k) is output as

[0390] Note that, during the period from time T13 to time T14 under this condition, for example, by setting the current flowing from the wiring OL to the circuit MC to I2 instead of I1, V2 can be held in the holding unit HC. As a result, "+2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "+2" and the neuron signal input to the circuit MP to "+1", the product of the first data (weighting coefficient) and the second data (neuron signal value) becomes "+2" according to equation (1.1). As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) becoming "+2", in the operation of the circuit MP, the current I OL increases, and the current I OLB In this way, by holding VSS in the holding unit HCr in the circuit MCr and setting a current amount other than I1 in the circuit MC, a positive value other than "+1" can be set as the first data (weighting coefficient) of the circuit MP.

[0391] [Condition 3] Next, as an example, consider a case where the first data (weighting coefficient) w is "-1" and the second data (the value (calculated value) of the neuron signal) input to the circuit MP is "+1." Figure 23C is a timing chart of the circuit MP in this case.

[0392] The operation from time T11 to time T13 is similar to the operation from time T11 to time T13 in condition 1, so the explanation of the operation from time T11 to time T13 in condition 1 will be taken into consideration.

[0393] Between time T13 and time T14, a potential VSS is input from the wiring IL to the circuit MC, and a current I1 is input from the wiring ILB to the circuit MCr. This is achieved by turning on the switches SWIAB and SWLA and turning off the switches SWIA and SWLAB in FIG. 14. As a result, the potential of the node n1 of the holding unit HC becomes VSS, and the potential of the node n1r of the holding unit HCr becomes V1. As a result, in the circuit MCr, the transistor M1 is set to have a current of 0, so no current flows from the wiring IL to the wiring VE via the circuit MC. Furthermore, in the circuit MCr, the transistor M1r is set to pass a current I1, so a current I1 flows from the wiring ILB to the wiring VEr via the circuit MCr.

[0394] Between time T14 and time T15, a low-level potential is applied to the wiring WL. As a result, a low-level potential is input to the control terminals of the switches S2, S2r, S5, and S5r, respectively, and the switches S2, S2r, S5, and S5r are turned off. With the switches S2 and S2r turned off, the potential VSS of the node n1 of the holding unit HC is maintained, and the potential V1 of the node n1r of the holding unit HCr is maintained. With the switch S5 turned off, no current flows from the wiring OL to the wiring VE via the circuit MC. Similarly, with the switch S5r turned off, no current flows from the wiring OLB to the wiring VEr via the circuit MCr. Between time T14 and time T15, the switches SWR3 and SWR3B shown in FIG. 6A may be turned on to initialize the potentials of the wiring OL and the wiring OLB. By initializing the potentials of the wirings OL and OLB, the potentials of the wirings OL and OLB can be changed by the current output from the circuit MP after time T15.

[0395] Through the operation from time T11 to time T15, "-1" is set as the first data (weighting coefficient) of the circuit MP. After the first data (weighting coefficient) is set in the circuit MP, the switches SWIA, SWIAB, SWLA, and SWLAB in FIG. 14 may be turned off. After the first data (weighting coefficient) is set in the circuit MP, the switches SWR3 and SWR3B may be turned on to initialize the potentials of the wirings OL and OLB. After the potentials of the wirings OL and OLB are initialized, the switches SWR3 and SWR3B may be turned off.

[0396] After time T15, as the second data (neuron signal (computed value)) "+1" is input to the circuit MP, a high-level potential is input to the wire X1L and a low-level potential is input to the wire X2L. At this time, a high-level potential is input to the control terminals of the switches S3 and S3r, and a low-level potential is input to the control terminals of the switches S4 and S4r. As a result, the switches S3 and S3r are turned on, and the switches S4 and S4r are turned off. In other words, this operation brings about a conductive state between the circuit MC and the wire OL, and between the circuit MCr and the wire OLB, and a non-conductive state between the circuit MC and the wire OLB, and between the circuit MCr and the wire OL. As a result, a conductive state is established between the circuit MC and the circuit AFP, and a conductive state is established between the circuit MCr and the circuit AFP.

[0397] In the circuit MC, the switch S3 is on, but the transistor M1 is off (set to pass 0 as the amount of current), so no current flows from the wiring OL to the wiring VE. In the circuit MC, the switch S4 is off, so no current flows from the wiring OLB to the wiring VE. On the other hand, in the circuit MCr, the switch S3r is on and the transistor M1r is on (set to pass I1 as the amount of current), so a current flows from the wiring OLB to the wiring VE. In the circuit MCr, the switch S4r is off, so no current flows from the wiring OL to the wiring VE. From the above, the current I output from the node outa of the wiring OL OL does not change before and after time T15, and the current I output from node outb of wiring OLB OLB After time T15, the current I1 increases. Therefore, the current I OL does not flow, and a current I of magnitude I1 flows between the circuit AFP and the wiring OLB. OLB is playing.

[0398] In this condition, the first data (weighting coefficient) is set to "-1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "+1". Therefore, when using formula (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-1" is that in the operation of the circuit MP, the current I OL does not change, and the current I OLB corresponds to the case where I1 increases. In addition, the result where the product of the first data (weighting coefficient) and the second data (value of the neuron signal) is "-1" is the result where the signal z j (k) is output as

[0399] Note that, during the period from time T13 to time T14 under this condition, for example, by setting the current flowing from the wiring OLB to the circuit MCr to I2 instead of I1, V2 can be held in the holding unit HCr. As a result, "-2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "-2" and the second data (neuron signal value) input to the circuit MP to "+1", the product of the first data (weighting coefficient) and the second data (neuron signal value) becomes "-2" according to equation (1.1). As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) becoming "-2", in the operation of the circuit MP, the current I OL does not change, and the current I OLB In this way, by holding VSS in the holding unit HC in the circuit MC and setting a current amount other than I1 in the circuit MCr, it is possible to set a positive value other than "+1" as the weighting coefficient of the circuit MP.

[0400] [Condition 4] In this condition, as an example, consider the operation of the circuit MP when the first data (weighting coefficient) is set to "0" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1." Figure 24A is a timing chart of the circuit MP in this case.

[0401] The operation from time T11 to time T15 is similar to the operation from time T11 to time T15 in condition 1, so the explanation of the operation from time T11 to time T15 in condition 1 will be taken into consideration.

[0402] After time T15, as the second data (neuron signal value (computed value)) "-1" is input to the circuit MP, a low-level potential is input to the wire X1L and a high-level potential is input to the wire X2L. At this time, a low-level potential is input to the control terminals of the switches S3 and S3r, and a high-level potential is input to the control terminals of the switches S4 and S4r. As a result, the switches S3 and S3r are turned off, and the switches S4 and S4r are turned on. In other words, this operation causes a non-conductive state between the circuit MC and the wire OL and between the circuit MCr and the wire OLB, and a conductive state between the circuit MC and the wire OLB and between the circuit MCr and the wire OL. As a result, a conductive state is established between the circuit MC and the circuit AFP, and a conductive state is established between the circuit MCr and the circuit AFP.

[0403] Since the transistor M1 is in an off state (the amount of current is set to 0), no current flows through the wiring OL and from the wiring OLB to the wiring VE in the circuit MC. In other words, the current I output from the node outa of the wiring OL OL , and the current I output from node outb of wiring OLB OLB does not change before and after time T15. Similarly, since the transistor M1r is in the off state (since the amount of current is set to 0), no current flows in the circuit MCr from the wiring OL and the wiring OLB to the wiring VEr. In other words, the current I output from the node outa of the wiring OL OL , and the current I output from node outb of wiring OLB OLB Therefore, the current I OL does not flow, and the current I OLB does not flow.

[0404] In this condition, the first data (weighting coefficient) is set to "0" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "-1". Therefore, when using equation (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0", in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) are changed, which is the same as the result of the circuit operation under condition 1. In addition, the result where the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0" is the result where the signal z j (k) is output as

[0405] [Condition 5] In this condition, as an example, consider the operation of the circuit MP when the first data (weighting coefficient) is set to "+1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1." Figure 24B is a timing chart of the circuit MP in this case.

[0406] The operation from time T11 to time T15 is similar to the operation from time T11 to time T15 in condition 2, so the explanation of the operation from time T11 to time T15 in condition 2 will be taken into consideration.

[0407] After time T15, as the second data (neuron signal value (computed value)) "-1" is input to the circuit MP, a low-level potential is input to the wire X1L and a high-level potential is input to the wire X2L. At this time, a low-level potential is input to the control terminals of the switches S3 and S3r, and a high-level potential is input to the control terminals of the switches S4 and S4r. As a result, the switches S3 and S3r are turned off, and the switches S4 and S4r are turned on. In other words, this operation causes a non-conductive state between the circuit MC and the wire OL and between the circuit MCr and the wire OLB, and a conductive state between the circuit MC and the wire OLB and between the circuit MCr and the wire OL. As a result, a conductive state is established between the circuit MC and the circuit AFP, and a conductive state is established between the circuit MCr and the circuit AFP.

[0408] In the circuit MC, the switch S3 is in the off state, so no current flows from the wiring OL to the wiring VE. Also, in the circuit MC, the switch S4 is in the on state and the transistor M1 is in the on state (since it is set to pass a current of I1), so a current flows from the wiring OLB to the wiring VE. On the other hand, in the circuit MCr, the switch S3r is in the off state, so no current flows from the wiring OLB to the wiring VE. Also, in the circuit MCr, the switch S4r is in the on state and the transistor M1 is in the off state (since it is set to pass a current of 0), so no current flows from the wiring OL to the wiring VE. From the above, the current I output from the node outa of the wiring OL OL does not change before and after time T15, and the current I output from node outb of wiring OLB OLB After time T15, the current I1 increases. Therefore, the current I OL does not flow, and a current I of magnitude I1 flows between the circuit AFP and the wiring OLB. OLB is playing.

[0409] In this condition, the first data (weighting coefficient) is set to "+1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "-1". Therefore, when using formula (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "-1". The result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-1" is that in the operation of the circuit MP, the current I OL does not change, and the current I OLB corresponds to the case where I1 increases, which coincides with the result of the circuit operation under condition 3. Note that the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "-1" is the same as under condition 3, as shown in FIG. 15, when the signal z j (k) is output as

[0410] As described in Condition 2, during the period from time T13 to time T14 under this condition, for example, the current flowing from the wiring OL to the circuit MC may be set to I2 instead of I1, and V2 may be held in the holding unit HC. As a result, "+2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "+2" and the neuron signal input to the circuit MP to "-1," the product of the first data (weighting coefficient) and the second data (neuron signal value) becomes "-2" according to equation (1.1). As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) becoming "-2," in the operation of the circuit MP, the current I OL does not change, and the current I OLB In this way, by holding VSS in the holding unit HCr in the circuit MCr and setting a current amount other than I1 in the circuit MC, it is possible to set a positive value other than "+1" as the weighting coefficient of the circuit MP.

[0411] [Condition 6] In this condition, as an example, consider the operation of the circuit MP when the first data (weighting coefficient) is set to "-1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is set to "-1." Figure 24C is a timing chart of the circuit MP in this case.

[0412] The operation from time T11 to time T15 is similar to the operation from time T11 to time T15 in condition 3, so the explanation of the operation from time T11 to time T15 in condition 3 should be taken into consideration.

[0413] After time T15, as the second data (neuron signal value (computed value)) "-1" is input to the circuit MP, a low-level potential is input to the wire X1L and a high-level potential is input to the wire X2L. At this time, a low-level potential is input to the control terminals of the switches S3 and S3r, and a high-level potential is input to the control terminals of the switches S4 and S4r. As a result, the switches S3 and S3r are turned off, and the switches S4 and S4r are turned on. In other words, this operation causes a non-conductive state between the circuit MC and the wire OL and between the circuit MCr and the wire OLB, and a conductive state between the circuit MC and the wire OLB and between the circuit MCr and the wire OL. As a result, a conductive state is established between the circuit MC and the circuit AFP, and a conductive state is established between the circuit MCr and the circuit AFP.

[0414] In the circuit MC, the switch S3 is in the off state, so no current flows from the wiring OL to the wiring VE. Also, in the circuit MC, the switch S4 is in the on state, but the transistor M1 is in the off state (since it is set to pass a current of 0), so no current flows from the wiring OLB to the wiring VE. On the other hand, in the circuit MCr, the switch S3r is in the off state, so no current flows from the wiring OLB to the wiring VE. Also, in the circuit MCr, the switch S4r is in the on state, and the transistor M1 is in the on state (since it is set to pass a current of I1), so a current flows from the wiring OL to the wiring VE. From the above, the current I output from the node outa of the wiring OL is OL After time T15, I1 increases, and the current I output from node outb of wiring OLB OLB does not change before and after time T15. Therefore, a current I of a current magnitude I1 flows between the circuit AFP and the wiring OL. OL flows, and the current I flows between the circuit AFP and the wiring OLB. OLB does not flow.

[0415] In this condition, the first data (weighting coefficient) is set to "-1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "-1". Therefore, when using formula (1.1), the product of the first data (weighting coefficient) and the second data (neuron signal value) is "+1". As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "+1", in the operation of the circuit MP, the current I OL changes, and the current I OLB This corresponds to the case where there is no change, which coincides with the result of the circuit operation under condition 2. Note that the result where the product of the first data (weight coefficient) and the first data (value of the neuron signal) is "+1" is the same as under condition 2, as shown in FIG. 15, when the signal z from the circuit AFP is j (k) is output as

[0416] As described in Condition 3, during the period from time T13 to time T14 under this condition, for example, the current flowing from the wiring OLB to the circuit MCr may be set to I2 instead of I1, and V2 may be held in the holding unit HC. As a result, "-2" is set as the first data (weighting coefficient) of the circuit MP. By setting the first data (weighting coefficient) to "-2" and the second data (neuron signal value) input to the circuit MP to "-1", the product of the first data (weighting coefficient) and the second data (neuron signal value) becomes "+2" according to equation (1.1). As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) becoming "+2", in the operation of the circuit MP, the current I OL does not change, and the current I OLB In this way, by holding VSS in the holding unit HC in the circuit MC and setting a current amount other than I1 in the circuit MCr, it is possible to set a positive value other than "+1" as the weighting coefficient of the circuit MP.

[0417] [Condition 7] In this condition, as an example, the operation of the circuit MP is considered under condition 7, where the first data (weighting coefficient) is "0" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "0." Figure 25A is a timing chart of the circuit MP in this case.

[0418] The operation from time T11 to time T15 is similar to the operation from time T11 to time T15 in condition 1, so the explanation of the operation from time T11 to time T15 in condition 1 will be taken into consideration.

[0419] After time T15, a low-level potential is input to the wire X1L and a low-level potential is input to the wire X2L as an input of second data (neuron signal value (computed value)) "0" to the circuit MP. At this time, a low-level potential is input to the control terminals of the switches S3, S3r, S4, and S4r. As a result, the switches S3, S3r, S4, and S4r are each turned off. In other words, this operation causes a non-conductive state between the circuit MC and the wire OL, between the circuit MCr and the wire OLB, between the circuit MC and the wire OLB, and between the circuit MCr and the wire OL. This causes a non-conductive state between the circuit MC and the circuit AFP, and also a non-conductive state between the circuit MCr and the circuit AFP.

[0420] Therefore, in the circuit MC, regardless of the set amount of current flowing through the transistor M1, no current flows from the wiring OL to either the wiring VE or the wiring VEl. Similarly, in the circuit MCr, regardless of the set amount of current flowing through the transistor M1r, no current flows from the wiring OLB to the other of the wiring VE or the wiring VEl. In other words, the current I output from the node outa of the wiring OL OL , and the current I output from node outb of wiring OLB OLB Each of these does not change before and after time T15. Therefore, the current I OL does not flow, and the current I OLB does not flow.

[0421] In this condition, the first data (weighting coefficient) is set to "0" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0", in the operation of the circuit MP, the current I OL and current I OLBThis corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) change, which coincides with the circuit operation results for conditions 1 and 4. Note that, as with conditions 1 and 4, the result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0" is the result of the signal z j (k) is output as

[0422] [Condition 8] In this condition, as an example, the operation of the circuit MP is considered under the condition 8 where the first data (weighting coefficient) is "+1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "0." Figure 25B is a timing chart of the circuit MP in this case.

[0423] The operation from time T11 to time T15 is similar to the operation from time T11 to time T15 in condition 2, so the explanation of the operation from time T11 to time T15 in condition 2 will be taken into consideration.

[0424] After time T15, a low-level potential is input to the line X1L and a low-level potential is input to the line X2L as the second data (neuron signal value (computed value)) "0" is input to the circuit MP. At this time, a low-level potential is input to the control terminals of the switches S3, S3r, S4, and S4r. As a result, the switches S3, S3r, S4, and S4r are each turned off. That is, as in condition 7, this operation causes a non-conduction state between the circuit MC and the line OL, between the circuit MCr and the line OLB, between the circuit MC and the line OLB, and between the circuit MCr and the line OL, regardless of the set amount of current flowing through the transistor M1 and the transistor M1r. This causes a non-conduction state between the circuit MC and the circuit AFP, and also between the circuit MCr and the circuit AFP. Therefore, no current flows from the wiring OL to either the wiring VE or the wiring VEl, and no current flows from the wiring OLB to the other of the wiring VE or the wiring VEl. Therefore, the current I output from the node outa of the wiring OL is OL, and the current I output from node outb of wiring OLB OLB Each of these does not change before and after time T15. Therefore, the current I OL does not flow, and the current I OLB does not flow.

[0425] In this condition, the first data (weighting coefficient) is set to "+1" and the second data (neuron signal (calculated value)) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0", in the operation of the circuit MP, the current I OL and current I OLB This corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) change, which coincides with the results of the circuit operation under conditions 1, 4, and 7. Note that the result where the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0" is the same as under conditions 1, 4, and 7, in FIG. 15, when the signal z j (k) is output as

[0426] [Condition 9] In this condition, as an example, the operation of the circuit MP is considered under the condition 9 where the first data (weighting coefficient) is "-1" and the second data (value of the neuron signal (calculated value)) input to the circuit MP is "0." Figure 25C is a timing chart of the circuit MP in this case.

[0427] The operation from time T11 to time T15 is similar to the operation from time T11 to time T15 in condition 3, so the explanation of the operation from time T11 to time T15 in condition 3 should be taken into consideration.

[0428] After time T15, a low-level potential is input to the line X1L and a low-level potential is input to the line X2L as the second data (neuron signal value (computed value)) "0" is input to the circuit MP. At this time, a low-level potential is input to the control terminals of the switches S3, S3r, S4, and S4r. As a result, the switches S3, S3r, S4, and S4r are each turned off. That is, as in condition 7, this operation causes a non-conduction state between the circuit MC and the line OL, between the circuit MCr and the line OLB, between the circuit MC and the line OLB, and between the circuit MCr and the line OL, regardless of the set amount of current flowing through the transistor M1 and the transistor M1r. This causes a non-conduction state between the circuit MC and the circuit AFP, and also between the circuit MCr and the circuit AFP. Therefore, no current flows from the wiring OL to either the wiring VE or the wiring VEl, and no current flows from the wiring OLB to the other of the wiring VE or the wiring VEl. Therefore, the current I output from the node outa of the wiring OL is OL , and the current I output from node outb of wiring OLB OLB Each of these does not change before and after time T15. Therefore, the current I OL does not flow, and the current I OLB does not flow.

[0429] In this condition, the first data (weighting coefficient) is set to "-1" and the second data (neuron signal value (calculated value)) input to the circuit MP is set to "0", so when formula (1.1) is used, the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0". As a result of the product of the first data (weighting coefficient) and the second data (neuron signal value) being "0", in the operation of the circuit MP, the current I OL and current I OLBThis corresponds to the case where none of the first data (weighting coefficient) and the second data (neuron signal value) change, which coincides with the results of the circuit operation under conditions 1, 4, 7, and 8. Note that the result where the product of the first data (weighting coefficient) and the second data (neuron signal value) is "0" is the same as under conditions 1, 4, 7, and 8, in FIG. 15, when the signal z j (k) is output as

[0430] The results of the operation examples under the above-mentioned conditions 1 to 9 are summarized in the table below. In the table below, high-level potential is written as "high" and low-level potential is written as "low."

[0431] [Table 2]

[0432] Here, an example is shown in which one circuit MC and one circuit MCr are connected to each of the wiring OL and wiring OLB. However, as shown in Figures 2 to 5, 8, 12, 15 to 17, if multiple circuits MC and multiple circuits MCr are connected to each of the wiring OL and wiring OLB, the currents output from each circuit MC and circuit MCr are added together based on Kirchhoff's current law. As a result, a sum operation is performed. In other words, a product operation is performed in the circuits MC and MCr, and a sum operation is performed by adding together the currents from the multiple circuits MC and MCr. As a result of the above, a product-sum operation is performed.

[0433] By the way, in the operation of circuit MP, by performing calculations with the first data (weighting coefficient) having only two values, "+1" and "-1", and the second data (neuron signal value) having only two values, "+1" and "-1", circuit MP can perform the same operation as an exclusive OR negation circuit (match circuit).

[0434] Furthermore, in the operation of circuit MP, by performing calculations in which the first data (weighting coefficient) has only two values, "+1" and "0", and the second data (neuron signal value) has only two values, "+1" and "0", circuit MP can perform the same operation as a logical product circuit.

[0435] In this operation example, the potentials held in the holding units HC and HCr of the circuits MC and MCr of the circuit MP are multi-valued, such as VSS, V1, and V2, but the holding units HC and HCr may hold potentials that indicate two values ​​or analog values. For example, when the first data (weighting coefficient) is a "positive analog value," a high-level analog potential is held at the node n1 of the holding unit HC, and a low-level potential is held at the node n1r of the holding unit HCr. When the first data (weighting coefficient) is a "negative analog value," for example, a low-level potential is held at the node n1 of the holding unit HC, and a high-level analog potential is held at the node n1r of the holding unit HCr. Then, the current I OL and current I OLB The magnitude of the current in the holding unit HC corresponds to the analog potential. Furthermore, the holding unit HC and the holding unit HCr hold the potential indicating the analog value not only in the operation example of the circuit MP shown in FIG. 19A but also in other circuits MP shown in this specification.

[0436] <<Example 2>> Furthermore, if the circuit IVTR (circuit IVTRr) of FIG. 6A is used as the circuit IVTR and circuit IVTRr in the circuit ACTF[j] included in the circuit AFC, or if the circuit ACTF[j] of FIG. 10 is used as the circuit ACTF[j] included in the circuit AFC, with the loads LE and LEB replaced by capacitances CRT and CRTB, respectively, the amount of current input from the wiring OL to either circuit MC or circuit MCr, and the amount of current input from the wiring OLB to the other circuit MC or circuit MCr, are determined depending on the input time of the second data (neuron signal value) to the circuit MP. Therefore, the potentials input to the first terminals of the switches SWR1 and SWR1B are also determined depending on the amount of current. Here, by defining the second data (neuron signal value) depending on the input time, the second data (neuron signal value) can be input to the circuit MP as multi-valued or analog value information. This allows for a multiply-and-accumulate operation of the first data and the second data (multi-valued or analog value).

[0437] 26A to 26C show examples of operation after time T15 in the timing chart of FIG. 23B (condition 2). Note that the timing charts of FIG. 26A to 26C do not show the potentials of the nodes n1 and n1r, but instead show the amount of charge Q accumulated in the first terminal of the capacitor CRT. OL and the amount of charge Q stored in the first terminal of the capacitor CRTB OLB and,

[0438] FIG. 26A shows the input time of the second data (the value of the neuron signal) to the circuit MP as t ut 26A shows an example of the operation of the arithmetic circuit 110 when the input time is from time T15 to time T16. ut During the period from time T15 to time T16, the second data (value of the neuron signal) is input, so that the current I1 flows through the wiring OL to the circuit MC. Also, during this period, the first terminal of the capacitor CRT is supplied with a current I1×t ut In the timing chart of FIG. 26A, the charge amount of I1×tut is listed as Q1.

[0439] Also, FIG. 26B shows the input time of the second data (value of the neuron signal) to the circuit MP as 2t ut 26B shows an example of the operation of the arithmetic circuit 110 when the input time is from time T15 to time T16. ut Considering the same as the timing chart of FIG. 26A, in the operation example shown in FIG. 26B, during the period from time T15 to time T16, the first terminal of the capacitor CRT is charged with I1×2t ut =2Q1 charge is accumulated.

[0440] As shown in Fig...

Claims

1. a cell and a first circuit, the first circuit includes a first switch, a second switch, a third switch, a fourth switch, a first capacitance, a first current-voltage conversion circuit, a second current-voltage conversion circuit, and a second circuit; The cell is electrically connected to one terminal of the first switch via a first wiring, The cell is electrically connected to one terminal of the second switch via a second wiring, the other terminal of the first switch is electrically connected to one terminal of the third switch; the other terminal of the first switch is electrically connected to one terminal of the first capacitance, the other terminal of the first switch is electrically connected to the first current-voltage conversion circuit; the other terminal of the second switch is electrically connected to one terminal of the fourth switch, the other terminal of the second switch is electrically connected to the other terminal of the first capacitor, the other terminal of the second switch is electrically connected to the second circuit; The other terminal of the third switch is electrically connected to a third wiring to which a reference potential is supplied, the other terminal of the fourth switch is electrically connected to the second current-voltage conversion circuit, the cell has a function of holding first data and a function of causing a first current corresponding to the first data and the second data to flow between the cell and the first wiring and a second current corresponding to the first data and the second data to flow between the cell and the second wiring when second data is input to the cell; the first current-voltage conversion circuit has a function of outputting a first potential in response to the first current input to the first current-voltage conversion circuit; the second current-voltage conversion circuit has a function of outputting a second potential in response to the second current input to the second current-voltage conversion circuit; the first capacitance has a function of holding a differential voltage between the first potential and the second potential, The second circuit is a semiconductor device having a function of outputting a signal corresponding to the differential voltage.

2. In claim 1, the first current-voltage conversion circuit includes a fifth switch; the second current-voltage conversion circuit includes a sixth switch; one terminal of the fifth switch is electrically connected to the other terminal of the first switch, The other terminal of the fifth switch is electrically connected to a fourth wiring to which a constant voltage is supplied, one terminal of the sixth switch is electrically connected to the other terminal of the fourth switch, The other terminal of the sixth switch is electrically connected to the fourth wiring.

3. A semiconductor device according to claim 1 or 2, and a housing, An electronic device that performs neural network calculations using the semiconductor device.

Images