Fault detection method and plasma processing apparatus

Abstract

To detect a failure of an impedance adjustment unit.SOLUTION: In a plasma processing apparatus that has a processing container partitioned into an antenna room and a processing room, and comprises: a metal window having a plurality of partial windows; an antenna generating inductive coupling plasma; an electrostatic chuck holding a substrate; and a bottom electrode supporting the electrostatic chuck, a failure detection method of an impedance adjustment unit between a plurality of partial windows including a plurality of capacitive elements existing between the plurality of partial windows and earth, and earth comprises the steps of: applying direct-current voltage to an attraction electrode of the electrostatic chuck; starting supply of source high-frequency power and / or bias high-frequency power; constantly supplying source high-frequency power and bias high-frequency power; measuring capacitive element voltage that is applied to each of the plurality of capacitive elements during performing processing of the substrate; and determining failures of a plurality of impedance adjustment units on the basis of a comparison result between the capacitive element voltage of the plurality of capacitive elements and the predetermined threshold value.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a fault detection method and a plasma processing apparatus. [Background technology]

[0002] For example, Patent Document 1 discloses an inductively coupled plasma processing apparatus having a processing chamber for accommodating a substrate to be processed and performing plasma processing therein, and a high-frequency antenna for forming an inductive electric field within the processing chamber. In the inductively coupled plasma processing apparatus, a non-magnetic metal window is formed between the high-frequency antenna and the processing chamber, and is insulated from a main body container constituting the processing chamber. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-29584 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a technique capable of detecting a failure in a part that adjusts the impedance of a plasma processing apparatus. [Means for solving the problem]

[0005] According to one aspect of the present disclosure, there is provided a plasma processing apparatus having a processing vessel, a metal window dividing the processing vessel into an antenna chamber and a processing chamber and having a plurality of partial windows, an inductively coupled antenna generating inductively coupled plasma by a source radio frequency power supplied to the antenna chamber, an electrostatic chuck electrostatically attracting a substrate to be processed within the processing chamber, and a lower electrode supporting the electrostatic chuck and receiving a bias voltage radio frequency power, the plasma processing apparatus having a plurality of impedance adjustment units including a plurality of capacitive elements provided between the plurality of partial windows and ground and adjusting impedance at the plurality of partial windows, the plurality of impedance adjustment units comprising the plurality of capacitive elements, the plurality of impedance adjustment units being connected to a ground and configured to supply a DC voltage to the electrostatic chuck, Effect of the Invention

[0006] According to one aspect, a failure in a part that adjusts the impedance of a plasma processing apparatus can be detected. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view showing an example of a plasma processing apparatus according to an embodiment; [Diagram 2] FIG. 2 is a diagram showing an example of an impedance adjustment circuit according to the embodiment. [Diagram 3] 4A and 4B are diagrams showing an example of the arrangement of a plurality of partial windows and impedance adjustment circuits according to the embodiment; [Figure 4] FIG. 2 is a diagram showing a hardware configuration of a control unit according to the embodiment. [Diagram 5] FIG. 2 is a diagram showing the functional configuration of a control unit according to the embodiment. [Figure 6]4 is a flowchart showing a failure detection method according to the embodiment. [Figure 7] FIG. 4 is a diagram showing an example of a measurement result of a capacitance element voltage according to the embodiment. [Figure 8] 13 is an example of a table storing the maximum capacitance element voltage value and the determination result. [Figure 9] 3 is a flowchart showing an abnormality determination method according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and duplicated descriptions may be omitted.

[0009] [Plasma processing equipment] A plasma processing apparatus according to an embodiment will be described with reference to Figs. 1 to 3. Fig. 1 is a schematic cross-sectional view showing an example of a plasma processing apparatus 100 according to an embodiment. Fig. 2 is a diagram showing an example of an impedance adjustment circuit 18 according to an embodiment. Fig. 3 is a diagram showing an example of an arrangement of a plurality of partial windows and the impedance adjustment circuit 18 according to an embodiment.

[0010] The plasma processing apparatus 100 according to the embodiment is used for etching metal films, ITO films, oxide films, etc., and ashing resist films when forming thin film transistors on a glass substrate for a flat panel display (FPD). Examples of FPD include liquid crystal displays (LCDs), electroluminescence (EL) displays, and plasma display panels (PDPs).

[0011] The plasma processing apparatus 100 has an airtight processing vessel 1 in a rectangular cylindrical shape made of a conductive material such as aluminum whose inner wall surface has been anodized (alumite-treated). The processing vessel 1 is grounded by a ground wire 1a. The processing vessel 1 is divided into an upper antenna chamber 3 and a lower processing chamber 4 by a metal window 2 formed insulated from the processing vessel 1. In this example, the metal window 2 constitutes the ceiling wall of the processing chamber 4. The metal window 2 is made of, for example, a non-magnetic conductive metal. An example of the metal in the present disclosure is aluminum or an alloy containing aluminum. The metal window 2 may be supported on a side wall of the processing vessel 1, or may be suspended from the ceiling of the antenna chamber 3.

[0012] A gas supply pipe 20a that penetrates the antenna chamber 3 in the vertical direction is provided. A gas flow path 12 in the gas supply pipe 20a branches into multiple branch pipes (not shown) and is connected to partial windows 22a, 22b, and 22c of the metal window 2 that is divided into multiple parts by an insulator 6 to supply gas to each partial window. The partial windows 22a, 22b, and 22c are part of the partial windows of the metal window 2 and are collectively referred to as partial windows 22.

[0013] Each partial window 22 has a gas space therein (not shown) and has a plurality of gas discharge ports on the surface facing the processing chamber 4, and gas is supplied into the processing chamber 4 from the plurality of gas discharge holes. The gas supply pipe 20a penetrates from the ceiling of the processing vessel 1 to the outside, and is connected to the processing gas supply unit 20. With this configuration, when a substrate G to be processed (hereinafter also referred to as a substrate G) is subjected to plasma processing, the processing gas supplied from the processing gas supply unit 20 is discharged into the processing chamber 4 through the gas supply pipe 20a.

[0014] A radio frequency (RF) antenna 13 is disposed on the metal window 2 in the antenna chamber 3 so as to face the metal window 2. The radio frequency antenna 13 is separated from the metal window 2 by a spacer 17 made of an insulating material. The radio frequency antenna 13 forms a spiral antenna. The metal window 2 is divided into, for example, 24 partial windows 22 at the bottom of the spiral antenna (see FIG. 3). However, the number of partial windows 22 is not limited to this and may be one or more, such as 40. The radio frequency antenna 13 is an example of an inductively coupled antenna that generates inductively coupled plasma by source radio frequency power supplied to the antenna chamber 3.

[0015] During plasma processing, the first high frequency power supply 15 supplies source high frequency power (hereinafter also referred to as source RF power) for forming an induction electric field, for example, having a frequency of 13.56 MHz, to the high frequency antenna 13 via the matching box 14 and the power supply member 16. The high frequency antenna 13 in this example is composed of an outer annular antenna, an intermediate annular antenna, and an inner annular antenna, which are concentrically arranged, and each has power supply parts 41, 42, and 43 connected to the power supply member 16. Antenna wires extend from each of these power supply parts 41, 42, and 43 in the circumferential direction to form the three-ring high frequency antenna 13. A capacitor (not shown) is connected to the end of each antenna wire, and each antenna wire is grounded via the capacitor. Each of the power supply parts 41, 42, and 43 may be one or more. The high frequency antenna 13 to which the source RF power is supplied in this manner forms an induction electric field in the processing chamber 4 via the metal window 2, and the induction electric field generates plasma of the processing gas supplied into the processing chamber 4. Therefore, after the source RF power is supplied to the high frequency antenna 13, the substrate G is subjected to plasma processing by the generated plasma of the processing gas.

[0016] A stage ST is provided at the bottom of the processing chamber 4, facing the high frequency antenna 13 with the metal window 2 interposed therebetween. The stage ST has a lower electrode 23 and an insulator frame 24. The lower electrode 23 is made of a conductive material, for example, aluminum whose surface is anodized. The substrate G is placed on an electrostatic chuck 48 disposed on the upper surface of the lower electrode 23. An adsorption electrode 49 is provided inside the electrostatic chuck 48. The adsorption electrode 49 is connected to a DC power supply 47 via a power supply line 46. By applying a DC voltage from the DC power supply 47 to the adsorption electrode 49, the substrate G is held by the electrostatic chuck 48 by electrostatic adsorption.

[0017] The lower electrode 23 is housed in an insulator frame 24, and is supported on the bottom surface of the processing chamber 4. A side wall 4a of the processing chamber 4 is provided with a loading / unloading port 27a for loading and unloading the substrate G, and a gate valve 27 for opening and closing the loading / unloading port 27a.

[0018] The lower electrode 23 is connected to a second high frequency power supply 29 via a matching unit 28 by a power supply line 25a provided in a hollow support 25. During plasma processing, the second high frequency power supply 29 applies high frequency power for bias voltage (hereinafter also referred to as bias RF power) having a frequency of, for example, 3.2 MHz to the lower electrode 23. Ions in the plasma generated in the processing chamber 4 are effectively attracted to the substrate G by the bias RF power.

[0019] Furthermore, in order to control the temperature of the substrate G, a temperature control mechanism including a heating means such as a ceramic heater and a coolant flow path, and a temperature sensor (none of which are shown) are provided within the lower electrode 23. Pipes and wiring for these mechanisms and members are all led out to the outside of the processing chamber 1 through hollow support 25.

[0020] Between the stage ST and the side wall 4a of the processing chamber 4, a baffle plate 32 formed in an annular shape by a plurality of members is provided to surround the stage ST, and a gas is passed through a plurality of through holes provided in at least a part of the baffle plate 32 to an exhaust space. An exhaust pipe 31 is provided at the bottom of the processing chamber 4, and an exhaust device 30 including a vacuum pump and the like is connected via the exhaust pipe 31. The exhaust device 30 exhausts gas from within the processing chamber 4, and the inside of the processing chamber 4 is controlled to a predetermined vacuum atmosphere (e.g., 1.33 Pa). A He gas flow path (not shown) is provided in the lower electrode 23, and He gas is supplied to the back surface of the substrate G placed on the lower electrode 23 via the He gas flow path.

[0021] Each component of the plasma processing apparatus 100 is connected to and controlled by a control unit 50, which is a computer. Under the control of the control unit 50, the plasma processing apparatus 100 performs a desired process.

[0022] [Impedance adjustment circuit] Impedance adjustment circuits 18a, 18b, 18c are connected to the metal window 2 on the antenna chamber 3 side. Potential detectors C1, C2, C3 are provided at the connections that connect the impedance adjustment circuits 18a, 18b, 18c to the partial windows 22a, 22b, 22c. As a result, the potential detectors C1, C2, C3... are arranged in a one-to-one relationship near each impedance adjustment circuit 18. The potential detectors C1, C2, C3... are also collectively referred to as potential detector VC.

[0023] The impedance adjustment circuits 18a, 18b, and 18c are an example of an impedance adjustment unit that adjusts the impedance between the plurality of partial windows of the metal window 2 and the ground, and are collectively referred to as the impedance adjustment circuits 18.

[0024] The impedance adjustment circuit 18 will be described with reference to Fig. 2 and Fig. 3. Fig. 2 shows a cross section of one partial window 22 among a plurality of partial windows included in the metal window 2, and the impedance adjustment circuit 18 connected to the partial window 22.

[0025] As shown in FIG. 3 as an example, the metal window 2 is divided into 24 partial windows 22. These partial windows 22 are parts of the divided metal window 2, and are arranged adjacent to each other with an insulator 6 interposed therebetween to form the metal window 2. Each partial window may be fixed, for example, by hanging it from the ceiling of the antenna chamber 3 by a support member (not shown). In this example, the overall shape of the ceiling, which is the wall surface of the processing chamber 4 facing the lower electrode 23, i.e., the metal window 2, is rectangular, and is divided into an inner peripheral area at the center of the rectangle, an annular intermediate area, and an annular outer peripheral area. The inner peripheral area has four partial windows 22 obtained by dividing the rectangular inner peripheral area approximately diagonally. The four partial windows 22 in the inner peripheral area are composed of two triangles facing each other with the short side as the base, and two trapezoids facing each other with the long side as the base. The intermediate area has a total of eight partial windows 22 obtained by dividing the annular intermediate area by each side, and further dividing each side into two equal parts in the radial direction. The outer peripheral area has a total of 12 partial windows 22, which are obtained by radially dividing the annular outer peripheral area into three equal parts for each side. In this embodiment, although not shown, the inner annular antenna corresponds to the inner peripheral area, the intermediate annular antenna corresponds to the intermediate area, and the outer annular antenna corresponds to the outer peripheral area.

[0026] Since each partial window 22 is disposed via an insulator 6, the partial windows 22 are insulated from the processing vessel 1 and are also insulated from each other. Examples of materials for the insulator 6 include ceramics and polytetrafluoroethylene (PTFE).

[0027] 2 and 3, one impedance adjustment circuit 18 is provided for each of the partial windows 22a, 22b, 22c, etc. In other words, in this example, 24 impedance adjustment circuits 18 are connected one-to-one to the 24 partial windows 22. However, this is not limited to the above, and one impedance adjustment circuit 18 may be provided for each of the partial windows 22. In other words, the partial windows 22 may be divided into one or more areas, and each of the one or more areas may be connected to an impedance adjustment circuit. For example, the 24 partial windows 22 may have one impedance adjustment circuit connected to each of the three areas, the inner peripheral area, the intermediate area, and the outer peripheral area.

[0028] 2, the impedance adjustment circuit 18 includes a capacitive element 60 and adjusts the impedance between the partial window 22 and the ground. The impedance adjustment circuit 18 is an R+C parallel circuit having a capacitive element 60 and a resistive element 61. In this example, one capacitive element 60 is connected to each partial window 22, and one resistive element 61 is connected in parallel to the capacitive element 60. The capacitive element 60 is connected to the partial window 22 at one end and to the ground at the other end. The resistive element 61 is connected to the partial window 22 at one end in parallel to the capacitive element 60, and to the ground at the other end.

[0029] The capacitance element 60 may be a variable capacitance element or a fixed capacitance element. However, by using the capacitance element 60 as a variable capacitance element, the impedance between the metal window 2 functioning as an anode electrode when bias RF power is applied to the lower electrode 23 and the ground (hereinafter also referred to as anode impedance) can be variably adjusted, and the impedance can be adjusted more accurately.

[0030] When the impedance adjustment circuit 18 is provided for each of the multiple areas, the capacitive element 60 and the resistive element 61 may be connected to multiple partial windows 22 for each area. Note that the capacitance component C0 shown in Fig. 2 indicates stray capacitance other than the capacitance component C due to the capacitive element 60, and is mainly the sum of capacitance components caused by the space between the metal window and other conductive members directly or indirectly connected to ground.

[0031] An insulating temperature control medium is passed through a flow path formed in the metal window 2, thereby controlling the temperature of the metal window 2. When the insulating temperature control medium flows, frictional electrification occurs, and charges are accumulated in the metal window 2, causing the metal window 2 to be charged up. Some of the electrons in the plasma may accumulate in the metal window 2, causing the metal window 2 to be charged up. If the metal window 2 is charged up, the plasma becomes unstable, affecting the processing of the substrate G, so it is important not to allow uncontrollable charges to accumulate in the metal window 2. Therefore, the impedance adjustment circuit 18 connects a resistance element 61 to the metal window 2 in parallel with the capacitance element 60. As a result, charges accumulated in the metal window 2 are released to the ground through the resistance element 61, eliminating the charge-up of the metal window 2 due to uncontrollable charges and ensuring the stability of the plasma.

[0032] Each of the potential detectors VC (C1, C2, C3,...) is installed near the impedance adjustment circuits 18a, 18b, 18c,... and detects the potential applied to the capacitive element 60 (hereinafter also referred to as the capacitive element voltage). In the example of Fig. 1, the potential detectors C1, C2, C3 are installed near the impedance adjustment circuits 18a, 18b, 18c. The potential detectors C1, C2, C3 measure, as the capacitive element voltage, a potential difference generated by the transfer of charge occurring in each of the capacitive elements 60 of the impedance adjustment circuits 18a, 18b, 18c during the processing of the substrate G.

[0033] With this configuration, high frequency power for bias voltage is supplied to the lower electrode 23, the lower electrode 23 is a cathode electrode, the metal window 2 is an anode electrode that is an opposing electrode facing the lower electrode 23, and the impedance adjustment circuit 18 adjusts the anode impedance. This allows a desired potential difference to be generated between the metal window 2 and the plasma by the capacitance of the capacitance element 60, making it possible to perform cleaning by removing deposits of by-products that have adhered to the metal window 2 due to plasma sputtering. Furthermore, when high frequency power for bias voltage is supplied to the lower electrode 23, although other parts in the processing vessel 1 can also function as anodes, the metal window 2 is made to function more actively as an anode to strengthen coupling with the cathode electrode, i.e., the lower electrode 23. This makes it possible to suppress wear of other parts in the processing vessel 1 due to plasma sputtering.

[0034] If the potential difference at the metal window 2 is too large, not only will the by-products adhering to the metal window 2 not be removed but the metal window 2 will also be worn, whereas if the potential difference is too small, the by-products adhering to the metal window 2 will not be sufficiently removed. Therefore, it is important to adjust the capacitance of the capacitance element 60 to a range that can prevent excessive wear of the metal window 2 and other parts in the processing vessel 1 during cleaning while removing the by-products adhering to the metal window 2. This makes it possible to extend the life of each part and extend the maintenance cycle while suppressing particles.

[0035] [Control Unit Configuration] Next, the hardware configuration and functional configuration of the control unit 50 that controls a fault detection method for the impedance adjustment circuit 18, which will be described later, will be described with reference to Fig. 4 and Fig. 5. Fig. 4 is a diagram showing the hardware configuration of the control unit 50 according to the embodiment. Fig. 5 is a diagram showing the functional configuration of the control unit 50 according to the embodiment.

[0036] The control unit 50 includes a central processing unit (CPU) 101, a read only memory (ROM) 102, a random access memory (RAM) 103, an I / O port 104, an operation panel 105, and a hard disk drive (HDD) 106. Each unit is connected to the other units via a bus B.

[0037] The CPU 101 controls various operations and processes of the plasma processing apparatus 100 based on various programs loaded into the RAM 103 and recipes that define processing procedures for the substrate G, such as etching, film formation, and cleaning. The processing of the substrate G (substrate processing) includes not only plasma processing of the substrate G, but also electrostatic adsorption processing in which a DC voltage is applied to the adsorption electrode 49 before the plasma processing is performed. The programs include a program for executing a failure detection method. The CPU 101 executes the failure detection method based on these programs loaded into the RAM 103.

[0038] The ROM 102 is configured by an EEPROM (Electrically Erasable Programmable ROM), a flash memory, a hard disk, etc., and is a storage medium that stores programs, recipes, etc. of the CPU 101. The RAM 103 functions as a work area for the CPU 101, etc.

[0039] The I / O port 104 acquires values ​​of various sensors that detect a capacitance element voltage, temperature, pressure, gas flow rate, etc. from various sensors attached to the plasma processing apparatus 100 and transmits them to the CPU 101. The I / O port 104 also outputs control signals output by the CPU 101 to each part of the plasma processing apparatus 100. An operation panel 105 through which an operator (user) operates the plasma processing apparatus 100 is also connected to the I / O port 104.

[0040] The HDD 106 is an auxiliary storage device and may store process recipes, programs, etc. The HDD 106 may also store log information of measurement values ​​measured by various sensors.

[0041] The functional configuration of the control unit 50 shown in Fig. 5 will be described. The control unit 50 is connected to the potential detector VC, i.e., the 24 potential detectors C1 to C24, by wires. The control unit 50 has an acquisition unit 51, an A / D conversion unit 52, an abnormality detection and determination unit 53, an abnormality identification unit 54, a display unit 55, a process execution unit 56, and a storage unit 57. The potential detector VC measures the capacitive element voltage while the substrate G is being processed. The potential detector VC may measure the capacitive element voltage across each of the multiple capacitive elements 60 while the substrate G is being processed through a process consisting of multiple processing steps. The potential detector VC may measure the capacitive element voltage across one or more of the multiple processing steps in which the substrate G is processed.

[0042] The storage unit 57 stores a recipe in which a processing procedure is set for performing processing on the substrate G. The storage unit 57 stores a table 57a (see FIG. 8) used in a failure detection method described later.

[0043] The process execution unit 56 processes the substrate G based on the recipe. The processes include electrostatic adsorption processing, plasma processing, etc. While processing the substrate G, the process execution unit 56 applies a DC voltage to the adsorption electrode 49 of the electrostatic chuck 48 to perform electrostatic adsorption processing for adsorbing the substrate G to the electrostatic chuck 48, and supplies source RF power and bias RF power to perform plasma processing on the substrate G.

[0044] The acquiring unit 51 acquires the measured capacitive element voltage from the potential detector VC while processing the substrate G. For example, the acquiring unit 51 acquires the measured capacitive element voltage and the number (No.) of the impedance adjustment circuit 18 including the corresponding capacitive element 60. The acquiring unit 51 may acquire the measured capacitive element voltage, the number (No.) of the impedance adjustment circuit 18 including the corresponding capacitive element 60, and the processing step number (No.) of the processing step when the capacitive element voltage was measured.

[0045] The A / D conversion unit 52 converts the analog signal of the capacitive element voltage acquired by the acquisition unit 51 into a digital signal. The abnormality detection determination unit 53 determines whether or not there is a failure in each of the multiple impedance adjustment circuits 18 based on a result of comparing the digitally converted capacitive element voltage of each of the multiple capacitive elements 60 with a predetermined threshold value.

[0046] Each of the multiple capacitance elements 60 is short-circuited when a failure occurs. At this time, the partial window 22, which serves as the counter electrode of the lower electrode 23 to which the bias RF power is supplied, is substantially at ground potential as viewed from the lower electrode due to the short-circuited capacitance element 60. Therefore, when a DC voltage is applied to the electrostatic chuck 48 or when the supply of at least one of the source RF power and the bias RF power is started, the potential of the partial window 22 does not fluctuate, and substantially no potential difference occurs between both ends of the capacitance element 60. Therefore, when the measured capacitance element voltage falls below the threshold value, it can be determined that the corresponding capacitance element 60 is short-circuited (failed).

[0047] The abnormality detection and determination unit 53 may determine a fault in each of the multiple impedance adjustment circuits 18 based on the capacitive element voltage measured at least at any one or more of the timings of the start of application of the DC voltage, the start of supply of source RF power, during steady supply of source RF power, the start of supply of bias RF power, during steady supply of bias RF power, and the stop of application of the DC voltage.

[0048] For example, the abnormality detection and judgment unit 53 may compare the capacitive element voltage with a threshold value for each capacitive element 60 connected to each of the multiple partial windows 22, and judge a fault for each impedance adjustment circuit 18 including each capacitive element 60 based on the comparison result for each capacitive element 60.

[0049] When the capacitance element voltage measured over one or more of a plurality of processing steps does not exceed the threshold value, the abnormality detection and determination unit 53 may determine that the impedance adjustment circuit 18 including the corresponding capacitance element is faulty.

[0050] The anomaly identifying unit 54 may identify, from among the multiple partial windows 22, an impedance adjustment circuit 18 including a capacitive element 60 whose capacitive element voltage did not exceed the threshold value, or a partial window 22 connected to the impedance adjustment circuit 18. This makes it possible not only to detect a failure of the impedance adjustment circuit 18, but also to identify the failed part.

[0051] When the processing of the substrate G is completed, the display unit 55 issues an alarm on a screen monitored by the operator, to notify the operator that an abnormality has occurred during the processing of the substrate G. In the case of an unmanned system not monitored by an operator, the determination flag of the faulty impedance adjustment circuit 18 in the table 57a may be rewritten to abnormal and stored in the memory unit 57.

[0052] The control unit 50 may notify the host computer 59 of the failure of the impedance control circuit 18 and information identifying the impedance control circuit 18 or the partial window 22 that has been determined to be in failure.

[0053] The acquisition unit 51 can be realized by the I / O port 104. The A / D conversion unit 52, the abnormality detection determination unit 53, the abnormality identification unit 54, and the process execution unit 56 can be realized by an A / D conversion circuit incorporated in the CPU 101 or the CP 101. The display unit 55 can be realized by the operation panel 105. The storage unit 57 can be realized by the ROM 102, the RAM 103, and the HDD 106.

[0054] [Fault detection method] Next, a fault detection method according to the embodiment will be described with reference to Figs. 6 to 8. Fig. 6 is a flowchart showing the fault detection method according to the embodiment. Fig. 7 is a diagram showing an example of a measurement result of a capacitive element voltage according to the embodiment. Fig. 8 is an example of a table 57a storing a capacitive element voltage (MAX value) and a determination result used in the fault detection method of Fig. 6.

[0055] 6 is executed by the respective units of the control unit 50. The failure detection method is started in parallel with the process execution unit 56 starting processing of the substrate G. When processing of the substrate G is started according to the recipe, in step S1, the process execution unit 56 places the substrate G on the lower electrode 23 in the processing vessel 1 to prepare it. When processing of the substrate G is started, each of the potential detectors VC (potential detectors C1, C2, C3,...) measures the capacitance element voltage near each of the impedance adjustment circuits 18 (impedance adjustment circuits 18a, 18b, 18c,...).

[0056] Next, in step S3, the process execution unit 56 applies a DC voltage to the attraction electrode 49 of the electrostatic chuck 48. As a result, the substrate G is held on the electrostatic chuck 48 by electrostatic attraction.

[0057] Next, in step S5, the process execution unit 56 starts supplying at least one of source RF power and bias RF power. The supply of source RF power and bias RF power may be started simultaneously or one may be started first depending on the processing of the substrate G. Next, in step S7, the process execution unit 56 converts the gas supplied from the processing gas supply unit 20 into plasma by the source RF power supplied to the antenna chamber 3, generates inductively coupled plasma, and performs plasma processing of the substrate G.

[0058] Next, in step S9, the acquiring unit 51 acquires the capacitance element voltages, which are potential detection values ​​measured by the potential detectors VC. The acquiring unit 51 acquires the 24 capacitance element voltages measured by the 24 potential detectors VC. Note that, for convenience of illustration in FIG. 6, step S9 is depicted as being executed simultaneously with or immediately after step S7, but in reality, acquisition of the capacitance element voltages begins at least simultaneously with step S3 or before that. The acquiring unit 51 continues to acquire the capacitance element voltages of the potential detectors VC provided near the impedance adjustment circuits 18, i.e., the capacitance element voltages of the 24, periodically or irregularly.

[0059] Next, in step S11, the A / D conversion unit 52 converts the analog signal of the capacitance element voltage acquired by the acquisition unit 51 into a digital signal.

[0060] Next, in step S13, the abnormality detection determination unit 53 determines whether the capacitive element voltage after digital conversion is greater than the capacitive element voltage MAX value. The initial value of the capacitive element voltage MAX value (hereinafter also simply referred to as the MAX value) is set to 0 for each potential detector VC. If the abnormality detection determination unit 53 determines that the capacitive element voltage is equal to or less than the MAX value, it skips step S15 and proceeds to step S17. If the abnormality detection determination unit 53 determines that the capacitive element voltage is greater than the MAX value, it updates the MAX value to the value of the capacitive element voltage. As a result, the maximum value of the capacitive element voltage measured by the potential detector VC during substrate processing is stored in the memory unit 57 as the capacitive element voltage MAX value (see FIG. 8).

[0061] Next, in step S17, the abnormality detection determination unit 53 determines whether the processing step has been completed. If the abnormality detection determination unit 53 determines that the processing step has not been completed, the process returns to step S9 and repeats the processing of steps S9 to S15. As a result, the MAX value stores the largest value at that time among the capacitance element voltages measured by the potential detector VC during the substrate processing for each processing step.

[0062] If the abnormality detection determination unit 53 determines that the processing step has been completed, the process proceeds to step S19, where it determines whether the processing of the substrate G has been completed. If the abnormality detection determination unit 53 determines that the processing of the substrate G has not been completed, the process returns to step S9, and the processes of steps S9 to S15 are repeated for the next processing step. As a result, the maximum value of the capacitance element voltage measured by the potential detector VC during the substrate processing in the next processing step is stored as the capacitance element voltage MAX value for the next processing step.

[0063] When the abnormality detection and determination unit 53 determines that the processing of the substrate G has been completed, the process proceeds to step S21, where the abnormality determination process shown in FIG. 9 is executed, and the process ends.

[0064] For example, in the example shown in Fig. 7, the processing of substrate G is composed of processing steps 1 and 2. Processing step 1 involves processing including plasma processing, and processing step 2 involves processing including a charge removal process for removing charge from substrate G and the like. The horizontal axis of Fig. 7 indicates time from the start of substrate processing at 0 seconds, and the vertical axis (left) indicates each of the RF powers (W) of the source RF power and the bias RF power, and the DC voltage (V). The vertical axis (right) of Fig. 7 indicates the capacitance element voltage (V) measured at each time shown on the horizontal axis.

[0065] In processing step 1, at the start of substrate processing (0 seconds), when a DC voltage is supplied to the electrostatic chuck 48 as shown by line d, the capacitance element voltage fluctuates as shown by line e. This is because the capacitance element 60 is not short-circuited and is normal, so the potential detector VC detects the movement of electric charge charged in the capacitance element 60 due to the fluctuation in the DC voltage at the time of application of the DC voltage, and measures this value as the capacitance element voltage.

[0066] At time t1, the supply of source RF power indicated by line a begins, and continues until time t4. At time t2, the supply of bias RF power indicated by line b begins, and continues until time t4. The potential detector VC detects fluctuations in these RF powers at the time when the source RF power and the bias RF power are supplied, and from time t1 to time t2 in between, and measures the capacitance element voltage indicated by line e.

[0067] The period from time t3 to time t4 corresponds to the steady supply of source RF power shown by line a and the steady supply of bias RF power shown by line b. The potential detector VC measures the capacitance element voltage shown by line e from time t3 to time t4.

[0068] The potential detector VC outputs information including the processing step number (No.), the impedance adjustment circuit number (No.), and the measured capacitance element voltage, and the acquisition unit 51 acquires this information. As shown in Fig. 8, the storage unit 57 stores, in correspondence with the processing step number (No.), the impedance adjustment circuit number (No.) for identifying each of the 24 impedance adjustment circuits 18, and the capacitance element voltage MAX value obtained by the processing of Fig. 6.

[0069] In processing step 1 of FIG. 7, the capacitive element voltage MAX value is stored as the capacitive element voltage MAX value, which is the capacitive element voltage (about 80 V) indicated by line e immediately after the start of substrate processing.

[0070] 6 is executed, the MAX value of the capacitance element voltage measured in process step 2 is also stored in storage unit 57. In process step 2, potential detector VC measures the capacitance element voltage indicated by line e at time t5 when application of the DC voltage supplied to electrostatic chuck 48 is stopped, at time t6 when supply of source RF power is started, and during steady supply of source RF power.

[0071] In process step 2 of FIG. 7, the capacitive element voltage indicated by line e at time t5 when the application of the DC voltage is stopped is stored as the capacitive element voltage MAX value. The capacitive element voltage measured by the potential detector VC may have a negative value. Therefore, the capacitive element voltage used in the process of FIG. 6 means the absolute value of the capacitive element voltage. In other words, in process step 2 of FIG. 7, the absolute value of the capacitive element voltage at time t5 when the supply is stopped (about 40V) is stored as the capacitive element voltage MAX value.

[0072] It is not necessary to calculate the capacitive element voltage MAX value separately for processing steps 1 and 2. One capacitive element voltage MAX value may be calculated for each impedance adjustment circuit 18 and stored in the storage unit 57 when the substrate processing is completed.

[0073] In this manner, the potential detector VC outputs, as a capacitive element voltage, a potential difference generated by the movement of charge charged in the capacitive element 60 in response to a transient phenomenon caused by the supply of the DC voltage, the source RF power, and the bias RF power supplied to the electrostatic chuck 48.

[0074] Therefore, when the capacitance element voltage MAX value is greater than the predetermined threshold value, it can be determined that the capacitance element 60 is not short-circuited and is normal. On the other hand, when the capacitance element voltage MAX value is less than the predetermined threshold value, it can be determined that the capacitance element 60 is short-circuited and is abnormal. For example, although the threshold value is not shown in FIG. 7, the threshold value may be a value greater than 0 volts and less than or equal to several volts, taking into consideration noise and the like. Line f indicates that the capacitance element voltage is 0 in process step 1 and process step 2. In this case, it is determined that the capacitance element 60 of the impedance adjustment circuit 18 corresponding to the measured potential detector VC (near the potential detector VC) is short-circuited and is abnormal.

[0075] In the abnormality determination method described below, the normality or abnormality of the capacitive element 60 (impedance adjustment circuit 18) is determined based on the presence or absence of a change in the capacitive element voltage in response to the transient phenomenon. Note that the abnormality determination method is preferably performed after the substrate processing as shown in FIG. 6, but may be performed each time each processing step is completed.

[0076] [Abnormality determination method] Fig. 9 is a flowchart showing an abnormality determination method according to the embodiment. The abnormality determination method in Fig. 9 is started when called by step S21 in Fig. 6. That is, when it is determined that the processing of the substrate G has been completed, the execution of the abnormality determination method in Fig. 9 is started.

[0077] In step S23, the abnormality detection determination unit 53 determines whether the determination has been completed for all impedance adjustment circuits 18. Since the determination is "No" when step S23 is executed for the first time, the process proceeds to step S25, where the abnormality detection determination unit 53 determines whether the capacitive element voltage MAX value of the undetermined impedance adjustment circuit 18 is equal to or greater than a predetermined threshold value. The capacitive element voltage MAX value here is the absolute value of the capacitive element voltage MAX value.

[0078] If the abnormality detection determination unit 53 determines in step S25 that the capacitive element voltage MAX value is equal to or greater than the predetermined threshold value, the process proceeds to step S27, where it determines that the impedance adjustment circuit 18 is normal. The storage unit 57 stores "0", indicating normal, in the determination flag in the table 57a corresponding to the impedance adjustment circuit 18, and returns to step S23.

[0079] If the abnormality detection and determination unit 53 determines in step S25 that the capacitive element voltage MAX value is below the predetermined threshold value, the process proceeds to step S29, where it determines that the impedance adjustment circuit 18 is abnormal. The storage unit 57 stores "1", which indicates an abnormality, in the determination flags in the table 57a corresponding to the impedance adjustment circuit 18, and returns to step S23.

[0080] In step S23, the abnormality detection determination unit 53 repeats the processes of steps S25 to S29 until it determines that it has completed the determination of the capacitive element voltage MAX values ​​corresponding to all the impedance adjustment circuits 18. If the abnormality detection determination unit 53 determines in step S23 that it has completed the determination of all the impedance adjustment circuits 18, it proceeds to step S31 and extracts the determination flags of all the processing steps for each impedance adjustment circuit 18.

[0081] Next, in step S33, the abnormality detection / determination unit 53 determines whether the values ​​of the determination flags of all the processing steps are all 1 for each impedance adjustment circuit 18. The abnormality detection / determination unit 53 may refer to the table 57a in the storage unit 57 to determine whether all the determination flags are 1 for each impedance adjustment circuit 18. When the abnormality detection / determination unit 53 determines that all the determination flags are 1, the process proceeds to step S37, where it determines that the impedance adjustment circuit 18 is abnormal, and identifies the portion where the abnormality was found. As the portion where the abnormality was found, the number of the impedance adjustment circuit 18 whose determination flag is "1" may be identified, or the partial window 22 to which the impedance adjustment circuit 18 whose determination flag is "1" is attached may be identified. The processing step number may be identified together with these pieces of information.

[0082] Next, in step S39, the anomaly detection / determination unit 53 notifies the host computer 59 of the anomaly in the impedance adjustment circuit 18 and information on the partial window 22 in which the anomaly was found, in one example of notifying the anomaly. In another example of notifying the anomaly, the display unit 55 issues an alarm on a screen monitored by an operator to notify the operator. In the case of an unmanned system not monitored by an operator, the anomaly detection / determination unit 53 may transmit the table 57a to the host computer 59 or another device to notify the operator of the failure.

[0083] In step S33, if the abnormality detection judgment unit 53 judges that at least one of the judgment flags of all processing steps for each impedance adjustment circuit 18 is 0, the abnormality detection judgment unit 53 proceeds to step S35, judges that the impedance adjustment circuit 18 is normal, and terminates this process.

[0084] In the abnormality determination method described above, the corresponding impedance adjustment circuit 18 is determined to be abnormal only when the determination flag indicates an abnormality in all processing steps, but this is not limited to the above. An impedance adjustment unit 18 including a capacitive element whose capacitive element voltage measured over one or more processing steps of a plurality of processing steps does not exceed a threshold may be determined to be faulty. For example, in a substrate processing consisting of a plurality of processing steps, the corresponding impedance adjustment circuit 18 may be determined to be abnormal when the determination flag indicates an abnormality in one processing step.

[0085] As described above, according to the failure detection method and plasma processing apparatus of the present embodiment, it is possible to detect a failure in the impedance adjustment circuit 18 of the plasma processing apparatus 100. In addition, it is possible to identify the failed impedance adjustment circuit 18 or the partial window 22 in which the failed impedance adjustment circuit 18 is provided.

[0086] For example, if the potential difference generated in the capacitive element 60 in response to one of three transient phenomena, namely, start of application of a DC voltage, start of supply of source RF power, and start of supply of bias RF power, two RF steady supplies, namely, steady supply of source RF power and steady supply of bias RF power, and stop of application of a DC voltage, is detected by the potential detector VC, and the capacitive element voltage is measured, there is a possibility of erroneous determination in determining whether the capacitive element 60 is normal or abnormal. However, in the above-described failure detection method, in the example of processing step 1 of FIG. 7, the potential difference generated in the capacitive element 60 in response to three transient phenomena, namely, start of application of a DC voltage supplied to the electrostatic chuck, start of supply of source RF power, and start of supply of bias RF power, and two RF steady supplies, namely, steady supply of source RF power and steady supply of bias RF power, is detected by the potential detector VC, and the capacitive element voltage is measured. In the example of processing step 2 of FIG. 7, the potential difference generated in the capacitive element 60 in response to two transient phenomena, namely, stop of application of a DC voltage supplied to the electrostatic chuck, and start of supply of source RF power, is detected by the potential detector VC, and the capacitive element voltage is measured. Therefore, according to the fault detection method and the abnormality determination method of the present embodiment, two or more transient phenomena of at least one of the DC voltage and the multiple RF powers are detected by the potential detector VC, and the capacitance element voltage is measured, thereby making it possible to accurately detect a fault in the impedance adjustment circuit 18.

[0087] The fault detection method and plasma processing apparatus according to the disclosed embodiments should be considered as illustrative and not restrictive in all respects. The embodiments can be modified and improved in various ways without departing from the scope and spirit of the appended claims. The matters described in the above embodiments can be configured in other ways without any contradiction, and can be combined without any contradiction.

[0088] The objects to be plasma processed by the plasma processing apparatus 100 of the present disclosure include, for example, a 1.5 m x 1.85 m processed substrate G of G6 and rectangular processed substrates G of other dimensions, but are not limited to these, and various members such as disk-shaped wafers may be processed. [Explanation of symbols]

[0089] 1 Processing vessel 2 Metal Windows 3 Antenna Room 4 Processing Room 6. Insulation 13 High Frequency Antenna 15 First high frequency power source 16 Power supply components 18 Impedance adjustment circuit 20 Processing gas supply section 22 Partial Window 23 Lower electrode 29 Second high frequency power source 30 Exhaust system 32 Baffle plate 60 Capacitive element 61 Resistance element G. Substrate to be processed C1, C2, C3 potential detector ST Stage

Claims

1. a metal window dividing the inside of the processing vessel into an antenna chamber and a processing chamber and having a plurality of partial windows; an inductively coupled antenna generating inductively coupled plasma by a source high frequency power supplied to the antenna chamber; an electrostatic chuck electrostatically attracting a substrate to be processed within the processing chamber; and a lower electrode supporting the electrostatic chuck and receiving a bias voltage high frequency power, a plurality of impedance adjustment units including a plurality of capacitance elements provided between the plurality of partial windows and a ground, the impedance adjustment units adjusting impedance between the plurality of partial windows and a ground; A method for detecting a failure of the plurality of impedance adjustment units, comprising: applying a DC voltage to the electrostatic chuck; starting the supply of at least one of the source high frequency power and the bias voltage high frequency power; a step of steadily supplying the source high frequency power and the bias voltage high frequency power; measuring a capacitance element voltage applied to each of the plurality of capacitance elements while processing the substrate; determining whether or not the plurality of impedance adjustment units have a failure based on a comparison result between each of the plurality of capacitance elements and a predetermined threshold value; A fault detection method comprising:

2. Each of the plurality of capacitance elements is short-circuited in the event of a failure, the step of determining a fault includes determining that an impedance adjustment unit including a capacitive element whose capacitive element voltage does not exceed the threshold value is faulty; The fault detection method according to claim 1 .

3. The step of measuring the capacitance element voltage includes measuring a capacitance element voltage applied to each of the plurality of capacitance elements while the substrate is subjected to a process including a plurality of process steps; the step of determining a failure includes determining, as a failure, an impedance adjustment unit including a capacitive element whose capacitive element voltage measured over one or more of the plurality of processing steps does not exceed the threshold; The fault detection method according to claim 2 .

4. The step of determining a failure includes determining a failure of the plurality of impedance adjustment units based on the capacitance element voltage measured at least at any one or more of a time point at which the application of the DC voltage starts, a time point at which the supply of the high frequency power for the source starts, a time point at which the high frequency power for the source is steadily supplied, a time point at which the supply of the high frequency power for the bias voltage starts, a time point at which the high frequency power for the bias voltage is steadily supplied, and a time point at which the application of the DC voltage stops. The fault detection method according to any one of claims 1 to 3.

5. the step of determining a fault includes comparing the capacitance element voltage with the threshold value for each of the capacitance elements connected to each of the plurality of partial windows, and determining a fault for each of the impedance adjustment units including the capacitance element based on a comparison result for each of the capacitance elements. The fault detection method according to any one of claims 1 to 4.

6. identifying a partial window connected to the capacitive element in which the capacitive element voltage does not exceed the threshold value among the plurality of partial windows; The fault detection method according to any one of claims 1 to 5.

7. a processing vessel; a metal window dividing the inside of the processing vessel into an antenna chamber and a processing chamber and having a plurality of partial windows; an inductively coupled antenna for generating inductively coupled plasma by a source high frequency power supplied to the antenna chamber; an electrostatic chuck for electrostatically attracting a substrate to be processed within the processing chamber; a lower electrode for supporting the electrostatic chuck and receiving a bias voltage high frequency power; a plurality of impedance adjustment units including a plurality of capacitance elements provided between the plurality of partial windows and ground and for adjusting an impedance between the plurality of partial windows and ground; and a control unit; The control unit is applying a DC voltage to the electrostatic chuck; starting the supply of at least one of the source high frequency power and the bias voltage high frequency power; a step of steadily supplying the source high frequency power and the bias voltage high frequency power; measuring a capacitance element voltage applied to each of the plurality of capacitance elements while processing the substrate; determining whether or not the plurality of impedance adjustment units have a failure based on a comparison result between each of the plurality of capacitance elements and a predetermined threshold value; A plasma processing apparatus that controls the plasma processing apparatus.

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