Pixel driving circuit and driving method thereof, and display panel

Abstract

This application discloses a pixel driving circuit, a driving method thereof, and a display panel. Here, the pixel driving circuit includes a light emitting element, a power line connected to the light emitting element, a pulse amplitude modulation unit, and a pulse amplitude modulation unit. The pulse amplitude modulation unit includes a first driving transistor connected to the light emitting element and the power line, and supplies driving currents of different amplitudes to the light emitting element according to a voltage applied to a gate electrode of the first driving transistor. The pulse amplitude modulation unit includes a second driving transistor connected to the light emitting element and the amplitude modulation unit, and controls the duration of the driving current of the light emitting element according to a voltage applied to a gate electrode of the second driving transistor. With the above configuration, the light emitting element is always operated in a high efficiency range.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority from Chinese patent application no. 202211401508.3, filed on November 09, 2022, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of display panels, and in particular to a pixel driving circuit and a driving method thereof, and a display panel. [Background technology]

[0003] Inorganic micro light emitting diode (Micro LED) display is one of the hotspots in the current display research field.

[0004] Compared with OLED displays, Micro LEDs have the advantages of high reliability, low power consumption, high brightness, and fast response speed, etc. Here, the driving circuit for controlling LED light emission is the core technology content of Micro LED displays and has important research significance.

[0005] However, the luminous efficiency of LEDs varies greatly with different driving currents, so in order to reduce the power consumption of Micro LED displays, the LEDs need to be operated at relatively high currents to keep them operating in their high-efficiency range at all times. Summary of the Invention

[0006] The main technical problem to be solved by the present application is to provide a pixel driving circuit, a driving method thereof, and a display panel, which enable a light emitting element to always operate within a high efficiency range.

[0007] In order to solve the above technical problems, the first technical solution adopted by this application is as follows: An image driving circuit is provided, the image driving circuit includes a light emitting element, a power line, a pulse amplitude modulation unit, and a pulse width modulation unit, the power line is connected to the light emitting element, the pulse amplitude modulation unit includes a first driving transistor connecting the light emitting element and the power line, and supplies driving currents of different amplitudes to the light emitting element according to a voltage applied to a gate of the first driving transistor, the pulse amplitude modulation unit includes a second driving transistor connecting the light emitting element and the amplitude modulation unit, and the duration of the driving current of the light emitting element is controlled according to a voltage applied to a gate of the second driving transistor.

[0008] Here, the source electrode of the first driving transistor is connected to the power line, the drain electrode is connected to the source electrode of the second driving transistor, and the drain electrode of the second driving transistor is connected to the light emitting element.

[0009] Here, the pixel driving circuit further includes a driving current detection unit, which is connected to the drain electrode of the first driving transistor and is used to detect the driving current of the first driving transistor, and the driving current detection unit includes a first switching transistor, a source electrode of the first switching transistor is connected to the drain electrode of the first driving transistor, a drain electrode is connected to a measurement wiring, and a gate electrode is connected to a scanning control line.

[0010] Here, the pulse width modulation unit further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor, a first plate of the first capacitor is connected to the gate electrode of the second driving transistor, a second plate of the first capacitor is connected to a power supply line, a source electrode of the first transistor is connected to a first signal line, a drain electrode of the first transistor is connected to the gate electrode of the second driving transistor, a gate electrode of the first transistor is connected to a first scanning control line, a source electrode of the second transistor is connected to a second signal line, a drain electrode of the second driving transistor is connected to a gate electrode of the second driving transistor, a gate electrode of the second transistor is connected to a drain electrode of the third transistor and a first plate of the second capacitor, a source electrode of the third transistor is connected to a third signal line, a drain electrode of the second transistor is connected to a gate electrode of the second transistor and a first plate of the second capacitor, a gate electrode of the fourth transistor is connected to a control signal line, a drain electrode of the second capacitor is connected to a second plate of the second capacitor, and a gate electrode of the fourth transistor is connected to a third scanning control line.

[0011] Here, the pulse width modulation unit further includes a fifth transistor, which is connected in parallel with the first transistor to control the gate voltage of the second driving transistor, and a source electrode of the fifth transistor is connected to the first signal line, a drain electrode of the fifth transistor is connected to the gate electrode of the second driving transistor, and a gate electrode of the fifth transistor is connected to the second scanning control line to maintain an initial voltage of the gate of the second driving transistor.

[0012] Here, the pixel driving circuit further includes a control unit, which is connected to the light-emitting element and the power line, and is used to control the on / off of the light-emitting element, and the control unit includes a second switching transistor, a source electrode of the second switching transistor is connected to the drain electrode of the second driving transistor, a drain electrode of the second switching transistor is connected to the light-emitting element, and a gate electrode of the second switching transistor is connected to a fourth scanning control line.

[0013] Here, the pulse amplitude modulation unit further includes a sixth transistor and a third capacitor, the source electrode of the sixth transistor is connected to the data line, the drain electrode of the sixth transistor is connected to the gate electrode of the first driving transistor, and the first plate of the third capacitor is connected to the gate electrode of the sixth transistor is connected to the first scanning control line, and the second plate of the third capacitor is connected to the power supply line.

[0014] Here, the first driving transistor and the second driving transistor are N-type transistors and / or P-type transistors.

[0015] In order to solve the above technical problem, the second technical solution adopted by the present application is as follows: A driving method for a pixel driving circuit is provided, in which a pulse amplitude modulation unit of the pixel driving circuit further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor, a first electrode plate of the first capacitor is connected to the gate electrode of the second driving transistor, a second electrode plate is connected to a power supply line, a source electrode of the first transistor is connected to a first signal line, a drain electrode is connected to the gate electrode of the second driving transistor, a gate electrode is connected to a first scanning control line, a source electrode of the second transistor is connected to a second signal line, a drain electrode is connected to the gate electrode of the second driving transistor, a gate electrode is connected to the drain electrode of the third transistor and the first electrode plate of the second capacitor, a source electrode of the third transistor is connected to a third signal line, a drain electrode is connected to the gate electrode of the second transistor and the first electrode plate of the second capacitor, a gate electrode is connected to a second scanning control line, a source electrode of the fourth transistor is connected to a control signal line, a drain electrode is connected to the drain electrode of the second capacitor. a gate electrode of the second transistor connected to a third scanning control line, and a first scanning control line of the Nth row controls a first transistor to be turned on, and a first voltage of the first signal line is transmitted to the first plate of the first capacitor and the gate electrode of the second driving transistor through the first transistor, and is maintained through the first capacitor to turn off the second driving transistor; a second scanning control line of the Nth row controls a third transistor to be turned on, and a third voltage of the third signal line is transmitted to the gate electrode of the second transistor and the first plate of the second capacitor through the third transistor, to turn off the second transistor; and a second scanning control line of the Nth row controls a fourth transistor to be turned on, and a first level voltage of the control signal line is written to the second plate of the second capacitor through the fourth transistor, and is transmitted to the gate electrode of the second transistor through a coupling effect of the second capacitor;a third step in which the second level voltage of the control signal line is written to the second plate of the second capacitor through the fourth transistor, and is transferred to the gate electrode of the second transistor through the coupling effect of the second capacitor to turn off the second transistor; and a fourth step in which the third scanning control line of all rows controls the fourth transistor to be on, and the swing voltage of the control signal line is transferred to the gate electrode of the second transistor through the fourth transistor to turn on the second transistor, at which time the second voltage of the second signal line is transferred to the gate electrode of the second driving transistor through the second transistor to turn on the second driving transistor.

[0016] Here, the driving method of the pixel driving circuit includes controlling a conduction time of the second transistor via the swing voltage, and further controlling the conduction time of the second driving transistor, thereby controlling a light-emitting time of the light-emitting element.

[0017] Here, the second transistor is a P-type transistor, and the swing voltage is a uniformly dropping voltage.

[0018] Here, the second transistor is an N-type transistor, and the swing voltage is a uniformly rising voltage.

[0019] The light emitting time of the light emitting element is related to the slope of the swing voltage.

[0020] Here, the pulse amplitude modulation unit of the pixel driving circuit further includes a sixth transistor and a third capacitor, a source electrode of the sixth transistor is connected to the data line, a drain electrode of the sixth transistor is connected to the gate electrode of the first driving transistor, and is also connected to the first plate of the third capacitor, a gate electrode of the sixth transistor is connected to the first scanning control line, and the second plate of the third capacitor is connected to the power supply line, in a first stage, the first scanning control line of the Nth row further controls the sixth transistor to be turned on, and the data voltage of the data line is transmitted to the first plate of the third capacitor and the gate electrode of the first driving transistor through the sixth transistor, and the data voltage is maintained through the third capacitor, thereby realizing the amplitude setting of the driving current of the first driving transistor.

[0021] Here, the pixel driving circuit further includes a driving current detection unit, the driving current detection unit includes a first switching transistor, a source electrode of the first switching transistor is connected to the drain electrode of the first driving transistor, a drain electrode of the first switching transistor is connected to the measurement wiring, and a gate electrode of the first switching transistor is connected to the scanning control line, and in the second or third stage, the scanning control line of the Nth row further controls the first switching transistor to be turned on, so as to form a path between the drain electrode of the first driving transistor and the measurement wiring, and detects the driving current of the first driving transistor.

[0022] Here, the scanning control line is the second scanning control line or the third scanning control line.

[0023] Here, the pulse width modulation unit further includes a fifth transistor, a source electrode of the fifth transistor is connected to the first signal line, a drain electrode of the fifth transistor is connected to the gate electrode of the second driving transistor, and a gate electrode of the fifth transistor is connected to the second scanning control line, and in a second stage, the second scanning control line of the Nth row further controls the fifth transistor to be turned on, and the first voltage of the first signal line is transmitted to the first plate of the first capacitor and the gate electrode of the second driving transistor, and the voltage of the gate electrode of the second driving transistor remains unchanged.

[0024] Here, the pixel driving circuit further includes a control unit for the light emitting element and the power supply line, and in a fourth stage, the control unit controls the light emitting element and the power supply line to form a path.

[0025] Here, the control unit further includes a second switching transistor, the source electrode of the second switching transistor is connected to the drain electrode of the second driving transistor, the drain electrode is connected to the light-emitting element, and the gate electrode is connected to a fourth scanning control line, and in a fourth stage, the fourth scanning control line controls the second switching transistor to be turned on, thereby forming a path between the power line and the light-emitting element, and realizing the light-emitting element to emit light.

[0026] In order to solve the above technical problems, the third technical solution adopted by the present application is as follows: A display panel is provided, the display panel includes a plurality of pixel units arranged in an array, and each of the pixel units is provided with a pixel driving circuit as described in any of the embodiments of the first technical solution.

[0027] The beneficial effect of the present application is different from the prior art, the present application provides a pixel driving circuit, its driving method and display panel. Through the transistor and the control line, the driving current of the light-emitting element is modulated by controlling the gate voltage of the first driving transistor of the pulse amplitude modulation unit, and the light-emitting time of the light-emitting element is modulated by controlling the gate voltage of the second driving transistor of the pulse width modulation unit. The present application realizes PWM modulation and PAM modulation by controlling the gate voltages of the two TFTs respectively, so that the light-emitting element can always operate in the high efficiency range and easily realize the cutting of the grayscale. [Brief description of the drawings]

[0028] In order to more clearly describe the technical solutions in the embodiments of the present application, the following briefly describes the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. Those skilled in the art can obtain other drawings from these drawings without creative efforts. [Figure 1] FIG. 2 is a framework structure schematic diagram of an embodiment of an image driving circuit of the present application; [Diagram 2] FIG. 2 is a structural schematic diagram of an image pixel circuit according to a first specific embodiment of the present application; [Diagram 3] FIG. 2 is a driving signal timing diagram of a first embodiment of the driving method of the pixel driving circuit of the present application; [Figure 4] FIG. 2 is an equivalent circuit diagram of a first step of the driving method of the first pixel driving circuit of the present application. [Diagram 5] FIG. 2 is an equivalent circuit diagram of a second stage of the driving method of the first pixel driving circuit of the present application. [Figure 6] FIG. 2 is an equivalent circuit diagram of a third step of the driving method of the first pixel driving circuit of the present application. [Figure 7] FIG. 11 is an equivalent circuit diagram of a fourth step of the driving method of the first pixel driving circuit of the present application. [Figure 8] FIG. 2 is a schematic structural diagram of a second specific embodiment of a pixel driving circuit of the present application; [Figure 9] FIG. 11 is an equivalent circuit diagram of a second step of the driving method of the second pixel driving circuit of the present application. [Figure 10] FIG. 2 is a schematic structural diagram of an embodiment of a display panel of the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, the technical solutions of the embodiments of the present application will be described clearly and completely with reference to the drawings of the embodiments of the present application. It is understood that the described embodiments are only some of the embodiments of the present application, but not all of them. Based on the embodiments of the present application, all other embodiments that a person skilled in the art can obtain without inventive work are all within the scope of protection of the present application.

[0030] The terms used in the embodiments of this application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a," "the," and "the" used in the embodiments and claims of this application are also intended to include the plural forms unless otherwise clearly indicated. "Plural types" usually includes at least two types, but does not exclude the case where it includes at least one type.

[0031] The term "and / or" used in this specification is merely for describing the association of related objects, and three relationships can exist. For example, A and / or B means that A exists alone, A and B exist simultaneously, and B exists alone. Also, the character " / " in this specification generally means that the related objects before and after are in an "or" relationship. The terms "first", "second", etc. in the specification and claims of this application, as well as the above drawings, are used to distinguish similar objects and are not necessarily used to describe a specific order or order before and after.

[0032] As used herein, the terms "comprise," "have," and any variations thereof are intended to cover a non-exclusive inclusion, whereby a process, method, product, or apparatus of a set of elements not only includes those elements, but also includes other elements not expressly listed or that are inherent to such process, method, article, or apparatus. Without further limitation, an element qualified by the term "comprises" does not exclude the presence of the same element in a process, method, article, or apparatus that includes the recited element.

[0033] The term "embodiment" as referred to in this specification means that a particular feature, structure, or characteristic described with reference to the embodiment may be included in at least one embodiment of the present application. The appearance of the combination in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. As will be understood by those skilled in the art, both explicitly and implicitly, the embodiment described in this specification can be combined with other embodiments.

[0034] This application provides a pixel driving circuit, specifically referring to Figure 1, which is a framework structure schematic diagram of an embodiment of the pixel driving circuit of this application. As shown in Figure 1, the pixel driving circuit includes a light emitting element, a power line, a pulse amplitude modulation unit (PAM) and a pulse width modulation unit (PWM).

[0035] Here, the power supply line includes a high potential power supply line VDD and a low potential power supply line VSS. Power flows through the light emitting element via the high potential power supply line VDD and flows to the low potential power supply line VSS. Here, the low potential power supply line VSS may be grounded and is not limited here. In this embodiment, the power supply line refers to the high potential power supply line VDD.

[0036] In this embodiment, the power line and the light-emitting element are connected by a pulse amplitude modulation unit and a pulse width modulation unit, the pulse amplitude modulation unit adjusts the driving current of the light-emitting element, and the pulse width modulation unit adjusts the light-emitting time of the light-emitting element.

[0037] Specifically, the pulse amplitude modulation unit includes a first driving transistor, the source electrode of the first driving transistor is connected to a high potential power line, and the drain electrode is connected to the light emitting element, and the driving current of different amplitudes is supplied to the light emitting element according to the voltage applied to the gate of the first driving transistor, that is, the magnitude of the current flowing through the source current / drain of the first driving transistor is controlled by controlling the gate voltage of the first driving transistor. Here, the driving current is expressed by the following formula (1), V GSis the gate source voltage of the first driving transistor, and V th is the threshold voltage at which the first drive transistor turns on. Here, the drive current is the drive current flowing through the light emitting element, and is related to the light emission luminance of the light emitting element.

[0038] JPEG0007636642000001.jpg11170

[0039] The pulse width modulation unit includes a second driving transistor, and the source electrode of the second driving transistor is connected to the drain electrode of the first driving transistor, and the drain electrode is connected to the light-emitting element, so as to connect the pulse amplitude modulation unit and the light-emitting element. The pulse width modulation unit controls the conduction time of the second driving transistor by adjusting the voltage applied to the gate of the second driving transistor, thereby controlling the duration of the driving current flowing to the light-emitting element, i.e., the light-emitting time of the light-emitting element. In this embodiment, the pulse width modulation unit and the pulse amplitude modulation unit are connected in series.

[0040] In other embodiments, the pulse amplitude modulation unit and the pulse width modulation unit can further be reversed in order, which is not limited here.

[0041] The beneficial effects of this embodiment are as follows: the driving current and light emitting time of the light emitting element are respectively controlled by the first driving transistor and the second driving transistor, and the driving current and light emitting time of the light emitting element can be controlled by controlling the gate voltages of the first transistor and the second transistor respectively, which is convenient to control and adjust; the driving current and light emitting time of the light emitting element can be controlled by controlling the gate voltages of the first transistor and the second transistor respectively, which is convenient to control and adjust.

[0042] The present application further provides a specific circuit configuration of the first pixel driving circuit, specifically referring to Figure 2. Figure 2 is a structural schematic diagram of a first specific embodiment of the pixel driving circuit of the present application. As shown in Figure 2, specifically, the pulse width modulation unit (PWM) further includes a first transistor T8, a second transistor T7, a third transistor T6, a fourth transistor T5, and a first capacitor C2 and a second capacitor C3.

[0043] Here, the first plate of the first capacitor C2 is connected to the gate electrode of the second driving transistor T4, and the second plate of the first capacitor C2 is connected to the high potential power line VDD.

[0044] The source electrode of the first transistor T8 is connected to the first signal line gh1, the drain electrode of the first transistor T8 is connected to the gate electrode of the second driving transistor T4 and the first plate of the first capacitor C2, and the gate electrode of the first transistor T8 is connected to the first scanning control line scan1. The first transistor T8 charges the gate electrode of the second driving transistor T4 with a first voltage gh1, and the first voltage gh1 is maintained through the first plate of the first capacitor C2. Here, the first voltage gh1 makes the second driving transistor T4 non-conductive.

[0045] A source electrode of the second transistor T7 is connected to the second signal line gl, a drain electrode of the second transistor T7 is connected to the gate electrode of the second driving transistor T4, and a gate of the second transistor T7 is connected to the drain electrode of the third transistor T6 and the first plate of the second capacitor C3.

[0046] A source electrode of the third transistor T6 is connected to the third signal line gh2, a drain electrode of the third transistor T6 is connected to the gate electrode of the second transistor T7, and a gate electrode of the third transistor T6 is connected to the second scanning control line scan2 and the first plate of the second capacitor C3.

[0047] The source electrode of the fourth transistor T5 is connected to the control signal line a, the drain electrode of the fourth transistor T5 is connected to the second plate of the second capacitor C3, and the gate electrode of the fourth transistor T5 is connected to the third scan control line scan3. The third transistor T6 and the fourth transistor T5 jointly adjust the gate voltage of the second transistor T7.

[0048] In this embodiment, an initial voltage is applied to the gate electrode of the second driving transistor T4 via the first transistor T8, thereby ensuring that the second driving transistor T4 is not conductive, and the conduction of the second transistor T7 is controlled by controlling the gate voltage of the second transistor T7, so that a conductive voltage is applied to the gate electrode of the second driving transistor T4 via the second transistor T7, making the second driving transistor T4 conductive, and controlling the conductive time of the second driving transistor T4 can control the light-emitting time of the light-emitting element LED.

[0049] In one specific embodiment, to prevent the gate voltage of the second driving transistor T4 from changing due to the second transistor T7 being erroneously turned on when the gate voltage of the second transistor T7 is modulated, the gate electrode of the second transistor T4 is connected in series with one fifth transistor T9, which is connected in parallel with the first transistor T8 to control the gate voltage of the second driving transistor during charging.

[0050] In another embodiment, the voltage changes of the third transistor T6 and the fourth transistor T5 may not necessarily turn on the second transistor T7, but there may be a certain probability that the fifth transistor T9 may not be installed.

[0051] Furthermore, in this specific embodiment, in order to prevent the second driving transistor T4 from being turned on to cause the light-emitting element LED to emit light during the charging process, a control unit is provided between the light-emitting element and the power line, which is used to control the on or off between the light-emitting element and the power line. Here, the control unit can be connected at any position between the power line and the light-emitting element. In this embodiment, the control unit is connected between the pulse width modulation unit and the light-emitting element LED. In other embodiments, the control unit can also be connected between the pulse amplitude modulation unit and the pulse width modulation unit, but is not limited thereto.

[0052] In this specific embodiment, the control unit includes one second switching transistor T10, the source electrode of the second switching transistor T10 is connected to the drain electrode of the second driving transistor T4, the drain electrode of the second switching transistor T10 is connected to the light-emitting element LED, and the gate electrode of the second switching transistor T10 is connected to the fourth scanning control line EM. In this embodiment, the path of the light-emitting element is controlled by the second switching transistor T10, so that the light-emitting element does not emit light even if the second driving transistor T4 is turned on in the non-emitting stage. In this embodiment, the fifth transistor T9 can be omitted, and as shown in FIG. 2, the fifth transistor T9 is indicated by a dotted line. In this specific embodiment, the control unit not only prevents the light-emitting element LED from being turned on unexpectedly, but also controls the light-emitting element LED to be turned off.

[0053] In this embodiment, the pulse amplitude modulation unit includes a first driving transistor T2, a sixth transistor T1 and a third capacitor C1. Specifically, the source electrode of the sixth transistor T1 is connected to the data line data, the drain electrode of the sixth transistor T1 is connected to the gate electrode of the first driving transistor T2 and is connected to the first plate of the third capacitor C1, and the gate electrode of the sixth transistor T1 is connected to the first scanning control line scan1. The sixth transistor T1 applies a data voltage to the first driving transistor T2 to turn on the first driving transistor T2, and maintains the data voltage through the third capacitor C1 to make the first driving transistor T2 always on. The gate voltage of the first driving transistor T2 is controlled by controlling the magnitude of the data voltage, thereby controlling the driving current.

[0054] In this embodiment, the pulse amplitude modulation unit directly compensates the gate voltage of the first driving transistor T2 through the data line data. In other embodiments, the pulse amplitude modulation unit can also be compensated by other internal compensation structures, which are not described here in detail.

[0055] In this embodiment, the pixel driving circuit further includes a driving current detection unit, the driving current detection unit is disposed between the pulse amplitude modulation unit and the pulse width modulation unit, and detects the driving current of the pulse amplitude modulation unit when the second driving transistor of the pulse width modulation unit is not conductive. Specifically, one end of the driving current detection unit is connected to the drain electrode of the first driving transistor of the pulse amplitude modulation unit, and the other end of the driving current detection unit is connected to the data line data by a measurement line, thereby detecting the driving current of the first driving transistor, and then compensating the data line data, thereby realizing the amplitude control of the driving current.

[0056] Specifically, the driving current detection unit includes a first switching transistor T3, the source electrode of the first switching transistor T3 is connected to the drain electrode of the first driving transistor T2, the drain electrode of the first switching transistor T3 is connected to the measurement wiring detect, and the gate electrode of the first switching transistor T3 is connected to the scanning control line, which controls the conduction of the first switching transistor T3. In this embodiment, the scanning control line is the second scanning control line scan2, which controls the first switching transistor T3 to be turned on in the second stage, thereby realizing the measurement of the driving current. Here, the measurement wiring detect is connected to the timing controller, which facilitates compensating the data line data in the subsequent stage. The first switching transistor T3 and the third transistor T6 share one second scanning control line scan2, so that the detection of the driving current can be realized, as well as the increase of wiring can be avoided. In other embodiments, the scanning control line is the third scanning control line scan3, which is not limited here.

[0057] In this embodiment, T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10 in the pixel driving circuit are all low-potential conductive P-type transistors. In other embodiments, T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10 may all be high-potential conductive N-type transistors, or may be a hybrid driving circuit in which some of the transistors are P-type transistors and some of the transistors are N-type transistors, and is not limited here.

[0058] In the following, the driving method will be described taking as an example a P-type transistor in which T1, T2, T3, T4, T5, T6, T7, T8, T9, and T10 are all low potential conductive transistors.

[0059] This application provides a first driving method based on the structure of the pixel driving transistor of the first embodiment, specifically referring to FIG. 3, which is a driving signal timing diagram of the first embodiment of the driving method of the pixel driving circuit of this application. As shown in FIG. 3, the driving method of the pixel driving circuit includes a first stage, a second stage, a third stage and a fourth stage. Here, the first stage, the second stage and the third stage are data writing stages, and writing is performed row by row, while in other embodiments, writing is performed column by column, but not limited here. The fourth stage is an emission stage of all rows, and the fourth stage is entered after the data writing of the pixels of all rows is completed.

[0060] In the first stage, the first scanning control line of the Nth row controls the sixth transistor T1 and the first transistor T8 to be turned on, and the data voltage Vdata of the data line data is transmitted to the first plate of the third capacitor C1 and the gate electrode of the first driving transistor T2 through the sixth transistor T1, and the data voltage Vdata is maintained by the third capacitor C1, so as to realize the amplitude setting of the driving current of the first driving transistor T2. At the same time, the first voltage Vgh1 of the first signal line ghl is transmitted to the gate electrode of the second driving transistor T4 and the first plate of the first capacitor C2 through the first transistor T8, and the first voltage Vgh1 is maintained by the first capacitor C2, so as to maintain the second driving transistor T4 in an off state. Here, the first voltage Vgh1 should be a positive voltage, so that the second driving transistor T4, which is turned on at a low level, is not turned on. Obviously, when the second driving transistor T4 is a negative voltage, the first voltage Vgh1 should be a negative voltage, and is not limited here. The first voltage Vgh1 is a voltage that does not cause the second drive transistor T4 to be conductive.

[0061] Specifically, further refer to FIG. 4, which is an equivalent circuit diagram of the first driving method of the pixel driving circuit of the present application in the first stage. As shown in FIG. 4, in the first stage, the sixth transistor T1 is turned on, the first transistor T8 is turned on, the voltage at point A is Vdata and is maintained by the third capacitor C1. The voltage at point C is Vgh1 and is maintained by the first capacitor C2. At this time, the light-emitting element LED does not emit light.

[0062] In the second stage, the second scanning control line scan2 of the Nth row controls the third transistor T6 to be turned on, and the third voltage Vgh2 of the third signal line gh2 is transmitted to the gate electrode of the second transistor T7 and the first plate of the second capacitor C3 through the third transistor T6, and the second transistor T7 is kept turned off by the second capacitor C3. At the same time, the third scanning control line scan3 controls the fourth transistor T5 to be turned on, and the first level voltage Va of the control signal line a is written to the second plate of the second capacitor C3 through the fourth transistor, and is transmitted to the gate electrode of the second transistor T7 due to the coupling effect of the second capacitor C3. Here, the first level voltage Va is a negative voltage, i.e. -Va.

[0063] Specifically, as shown in FIG. 5, FIG. 5 is an equivalent circuit diagram of the second stage of the first driving method of the pixel driving circuit of the present application. As shown in FIG. 5, a low level voltage is applied to the second scanning control line scan2 and the third scanning control line scan3, respectively, and the third transistor T6 and the fourth transistor T5 are controlled to be conductive. The third voltage Vgh2 of the third signal line gh2 is transmitted to the gate electrode of the second transistor T7 through the third transistor T6, and at this time, the voltage at point E is Vgh2. At the same time, the fourth transistor T5 is turned on, and at the moment when the fourth transistor T5 is turned on, the voltage at point E is coupled to Vgh2-Va through the second capacitor C3. When the third transistor T6 is turned on, the voltage at point E quickly returns to Vgh2. Here, Vgh2 is the voltage that puts the second transistor T6 into an off state. In this embodiment, the third voltage Vgh2 is a positive voltage, and the first level voltage Va is a negative voltage.

[0064] Since Vgh2-Va may be less than 0, the P-type second transistor T7 may unexpectedly turn on, which may turn on the second driving transistor T4 and cause the light-emitting element LED to emit light. In this embodiment, a second switching transistor T10 is provided between the second driving transistor T4 and the light-emitting element LED to control that the power line VDD and the light-emitting element LED are not electrically connected. In another embodiment, a fifth compensation transistor T9 is provided on the gate electrode of the second driving transistor T4 to maintain the gate voltage of the second driving transistor T4 at a non-conducting voltage, thereby preventing the second driving transistor T4 from being electrically connected.

[0065] In other embodiments, the first level voltage Va can also be controlled so that Vgh2-Va is greater than or equal to 0, thereby controlling the second transistor T7 to be turned off and the second driving transistor T4 to be turned off, but this is not limited thereto.

[0066] In this embodiment, even if the second driving transistor T4 is turned on, the second switching transistor T10 is in an off state, so the light-emitting element LED does not emit light. If the second transistor T7 is not turned on as expected (turns on unexpectedly), the voltage at point C changes, that is, the initial voltage at point C before starting the light-emitting phase does not change from Vgh1 to Vgl, but from an unknown voltage to Vgl. However, in this embodiment, as shown in FIG. 3, the second transistor T7 is not conductive at the voltage Vgh2-Va, so the initial voltage at point C does not change before emitting light.

[0067] In this embodiment, the driving current can be measured by controlling the first switching transistor T3 to be on in the second stage. In other embodiments, the driving current can be measured by controlling the conduction of the first switching transistor T3 in the third stage, and is not limited thereto. Specifically, the scanning control line is the second scanning control line scan2 or the third scanning control line scan3, and in other embodiments, the scanning control line can be a separate control signal line. In the second stage, the scanning control line of the Nth row controls the first switching transistor T3 to be on, and the drain electrode of the first driving transistor T2 and the measurement wiring detect form a path, so that the driving current of the first driving transistor T2 is measured by the measurement wiring detect.

[0068] In the third stage, the third scanning control line scan3 of the Nth row controls the conduction of the fourth transistor T5, and the second level voltage Va0=0V of the control signal line a is written to the second plate of the second capacitor C3 through the fourth transistor, and is transmitted to the gate electrode of the second transistor T7 due to the coupling effect of the second capacitor C3, thereby turning off the second transistor T7.

[0069] Specifically, as shown in FIG. 6, FIG. 6 is an equivalent circuit diagram of the third stage of the first driving method of the pixel driving circuit of the present application. As shown in FIG. 6, the fourth transistor T5 is turned on, and the other transistors are turned off, that is, the third transistor T6 is turned off, and at this time, the voltage at point E is maintained at Vgh2. Near the end of the third stage, the control signal line a inputs the second level voltage, where the second level potential is the initial potential Va0, and in this embodiment, the second level potential is 0 potential. At this time, the voltage of the control signal line a changes from -Va to 0, and the voltage at point E changes to Vgh2+Va due to the capacitive coupling effect, and then turns off the fourth transistor T5. In other embodiments, the second level potential Va0 does not need to be 0 potential, but it is necessary to ensure that the difference between the first level voltage Va and the second level voltage Va0 is Va, so as to change the gate voltage (point E voltage) of the second transistor T7 to Vgh2+Va.

[0070] Here, in the third stage, as shown in Fig. 3, the signal change width of the control signal line a is smaller than the width of the third scanning control line scan3. That is, the moment when the voltage of the control signal line a changes from low potential to high potential is earlier than the moment when the third scanning control line scan3 changes from low potential to high potential, so that the potential of point E changes from Vgh to Vgh+Va. Furthermore, in the second stage, the moment when the voltage of the control signal line a changes from high potential to low potential is later than the moment when the third scanning control line scan3 changes from high potential to low potential, so that the potential of E changes from Vgh2 to Vgh2-Va and then to Vgh2. In the second stage, the control signal line a and the third scanning control line scan3 can also change simultaneously, and are not limited here.

[0071] In the fourth stage, the third scanning control lines scan3 of all rows control the fourth transistor T5 to be turned on, and the swing voltage Vsweep of the control signal line a is transmitted to the gate electrode of the second transistor T7 through the fourth transistor T5, thereby controlling the conduction of the second transistor T7; at this time, the second voltage of the second signal line Vgl is transmitted to the gate electrode of the second driving transistor T4 through the second transistor T7, thereby controlling the conduction of the second driving transistor T4.

[0072] In this embodiment, in the fourth stage, the fourth scanning control line EM controls the second switching transistor T10 to be on, so that a path is formed between the light emitting element LED and the power supply line VDD.

[0073] Specifically, refer to FIG. 7, which is an equivalent circuit diagram of the fourth stage of the first driving method of the pixel driving circuit of the present application. As shown in FIG. 7, the third scanning control line scan3 controls the fourth transistor T5 to be on, the swing voltage Vsweep of the control signal line a controls the second transistor T7 to be on, and the second voltage Vgl of the second signal line gl controls the second driving transistor T4 to be on. The first driving transistor T2 is always in an on state due to the action of the third capacitor C1. The fourth scanning control line EM controls the second switching transistor T10 to be on. The first driving transistor T2, the second driving transistor T4 and the second switching transistor T10 are turned on, so that the high potential power line VDD flows to the low potential power line VSS and flows to the light emitting element LED to make the light emitting element LED emit light.

[0074] Here, the swing voltage Vsweep is a uniform rising voltage or a uniform falling voltage, and when the swing voltage Vsweep rises or falls to a certain value, it reaches the on-voltage (Vth) of the second transistor T7 and is maintained by the second capacitor C3, so that the second transistor T7 is always on, and the second driving transistor T4 is controlled to be on, causing the light-emitting element LED to emit light. When the swing voltage Vsweep returns to the potential -Va, the potential at point E returns to Vgh2, and the second transistor T7 is turned off. At this time, the second driving transistor T4 is turned on at the second voltage Vgl, so that in order to control the light-emitting element LED not to emit light, it is necessary to control the second switching transistor T10 to be turned off. In this embodiment, after the light emission is finished, the voltage at point C is always maintained at Vgl until the next first transistor T8 is turned on, and then becomes Vgh1. Here, Vgh1 may be 0 or a positive value.

[0075] In the fourth stage, the third scan control line scan3 is at a low potential voltage, and the fourth transistor T5 is always on, so that the swing voltage Vsweep is input to the gate electrode of the second transistor T7.

[0076] In this embodiment, without the second switching transistor T10, the second driving transistor T4 is always on at the second voltage Vgl, and the light-emitting element LED can always be in a light-emitting state, so that the purpose of width modulation cannot be achieved. In other embodiments, the second switching transistor T10 may also be disposed between the gate electrode of the second driving transistor T4 and the drain electrode of the second transistor T7.

[0077] In this embodiment, the second transistor T7 is a P-type transistor, and the swing voltage Vsweep is a uniformly dropping voltage. The swing voltage Vsweep is coupled to point E through a capacitor, and the voltage at point E is uniformly dropped. When the collimation at point E reaches the on-voltage (i.e., the threshold voltage Vth) of the second transistor T7, the second voltage Vgl of the second signal line is written to point C, which turns on the second driving transistor T4, and at this time, the circuit from VDD to VSS is turned on, and the LED emits light. Assuming that the slope of the uniform drop of Vsweep is K and the total time of the light-emitting stage is T0, the light-emitting time is T0-(Vgh2+Va-Vth) / K. Here, the light-emitting time is not only related to K, but also to the Va voltage.

[0078] In one specific embodiment, the Va voltage can also be compensated through the control signal line a. Because the first driving transistor T2 and the second transistor T7 are located in the same pixel, it is believed that the threshold voltages Vth of the first driving transistor T2 and the second transistor T7 drift to the same extent. In the second stage, when the driving current detection unit compensates the data line data, the Va voltage can also be compensated, thereby realizing pulse width modulation.

[0079] In another embodiment, when the second transistor T7 is a P-type transistor, the swing voltage Vsweep is a uniformly rising voltage, and the light emitting time of the light emitting element LED is similarly related to the slope of the swing voltage Vsweep, and the analysis process may refer to the above embodiment, and detailed description will be omitted here.

[0080] The beneficial effects of the first embodiment are as follows: the driving current and light-emitting time of the light-emitting element LED in the pixel are respectively adjusted by controlling the gate voltages of the first driving transistor and the second driving transistor; the driving current of the LED is measured through the driving current detection unit, which facilitates the compensation and adjustment of the driving current thereafter; and the pulse width modulation of the driving current I is realized by the slope of the swing voltage.

[0081] In this embodiment, the control signals of the first scanning control line scan1, the second scanning control line scan2, the third scanning control line scan3, the control signal line a and the fourth scanning control line EM are low-level voltages. In other embodiments, the control signals of the first scanning control line scan1, the second scanning control line scan2, the third scanning control line scan3, the control signal line a and the fourth scanning control line EM can be high-level voltages, or some of them can be high-level voltages and some of them can be low-level voltages, which can be specifically set according to the P / N type of the transistor, and are not limited here.

[0082] The present application further provides a second kind of pixel driving circuit, specifically shown in Figure 8, which is a structural schematic diagram of a second specific embodiment of the pixel driving circuit of the present application. As shown in Figure 8, the pixel driving circuit includes a pulse width modulation unit PWM, which includes a second driving transistor T4, a first transistor T8, a second transistor T7, a third transistor T6, a fourth transistor T5, a first capacitor C2, a second capacitor C3 and a fifth transistor T9.

[0083] Specifically, the first plate of the first capacitor C2 is connected to the gate electrode of the second drive transistor T4, and the second plate of the first capacitor C2 is connected to the high potential power line VDD.

[0084] The source electrode of the first transistor T8 is connected to the first signal line gh1, the drain electrode of the first transistor T8 is connected to the gate electrode of the second driving transistor T4 and the first plate of the first capacitor C2, and the gate electrode of the first transistor T8 is connected to the first scan control line scan1. The first transistor T8 applies a first voltage gh1 to the gate electrode of the second driving transistor T4, which is maintained through the first plate of the first capacitor C2. Here, the first voltage gh1 turns off the second driving transistor T4.

[0085] A source electrode of the second transistor T7 is connected to the second signal line gl, a drain electrode of the second transistor T7 is connected to the gate electrode of the second driving transistor T4, and a gate electrode of the second transistor T7 is connected to the drain electrode of the third transistor T6 and the first plate of the second capacitor C3.

[0086] A source electrode of the third transistor T6 is connected to the third signal line gh2, a drain electrode of the third transistor T6 is connected to the gate electrode of the second transistor T7, and a gate electrode of the third transistor T6 is connected to the second scanning control line scan2 and the first plate of the second capacitor C3.

[0087] The source electrode of the fourth transistor T5 is connected to the control signal line a, the drain electrode of the fourth transistor T5 is connected to the second plate of the second capacitor C3, and the gate electrode of the fourth transistor T5 is connected to the third scan control line scan3. The third transistor T6 and the fourth transistor T5 jointly adjust the gate electrode voltage of the second transistor T7.

[0088] The source electrode of the fifth transistor T9 is connected to the first signal line gh1, the drain electrode of the fifth transistor T9 is connected to the gate electrode of the second driving transistor T4 and the first plate of the first capacitor C2, and the gate electrode of the fifth transistor T9 is connected to the second scanning control line scan2.

[0089] In this embodiment, by turning on the fifth transistor T9 in the second stage, the fifth transistor T9 and the third transistor T6 are turned on simultaneously, so that even if the second transistor T7 is turned on, when the Vgl voltage is applied to the second driving transistor T4, the gate electrode of the second driving transistor T4 can be charged via the fifth transistor T9, the voltage of the second driving transistor T4 is offset, and the voltage of the second driving transistor T4 can be maintained unchanged.

[0090] In this embodiment, the resistance of the fifth transistor T9 is much smaller than the resistance of the second transistor T7, so that the voltage input by the second transistor T7 to the second driving transistor T4 flows out through the fifth transistor T9 and does not change the gate voltage of the second driving transistor T4.

[0091] In this embodiment, the timing chart of the driving signals of each transistor is similar to that of the first embodiment, and for details, refer to FIG. 3, and the description thereof will be omitted here.

[0092] In this embodiment, the differences are as follows: In the second stage, the fifth transistor T9 is turned on. Specifically referring to FIG. 9, FIG. 9 is an equivalent circuit diagram of the second stage of the driving method of the second pixel driving circuit of the present application.

[0093] In the second stage, the fifth transistor T9 is controlled to be turned on, and even if the second transistor T7 is turned on at a certain moment, the fifth transistor T9 is turned on, so that the potential at point C does not change significantly, thereby ensuring the off state of the second driving transistor T4. Specifically, the gate electrode of the fifth transistor T9 is controlled by the second scanning control line scan2, so that it is turned on in the second stage, and transmits the first voltage Vgh1 of the first signal line gh1 to the first plate of the first capacitor C2 and the gate electrode of the second driving transistor T4, so that the voltage of the gate electrode of the second driving transistor T4 does not change suddenly, and the second driving transistor T4 does not conduct. The conduction status of each of the other transistors remains unchanged, and the specific description will be given with reference to the first specific embodiment.

[0094] In the first, third and fourth stages, the conductive state of each transistor remains unchanged, for specific details please refer to the first specific embodiment.

[0095] In this embodiment, the third scanning control line scan3 controls the fourth transistor T5 to be on, the swing voltage Vsweep of the control signal line a controls the second transistor T7 to be on, and the second voltage Vgl of the second signal line gl controls the second driving transistor T4 to be on. The first driving transistor T2 always maintains an on state under the action of the third capacitor C1 until the next data write stage is started. When the next data write stage is started, the first scanning control line scan1 controls the first transistor T8 to be on, writes an initial voltage to the second driving transistor T4, turns off the second driving transistor T4, and causes the light-emitting element LED to emit light. In this embodiment, the second driving transistor T4 belongs to the uncontrollable stage from the emission end stage to the next write stage, and this embodiment is less preferable than the first embodiment.

[0096] The beneficial effects of this embodiment are as follows: The internal compensation of the PWM makes the PWM ON during the light-emitting phase and OFF during the non-light-emitting phase.

[0097] The present application further provides a display panel, which includes a plurality of pixel units arranged in an array, and each pixel unit is provided with a pixel driving circuit according to any of the above embodiments. Specifically, as shown in Fig. 10, Fig. 10 is a structural schematic diagram of an embodiment of the display panel of the present application. As shown in Fig. 10, the display panel includes a plurality of pixel units 100, and each pixel unit 100 is provided with a pixel driving circuit.

[0098] The beneficial effects of the present application are as follows: PAM and PWM modulation of light-emitting elements in a display panel is realized by 9 / 10 TFTs, three capacitors C and multiple control lines.

[0099] The above is an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by utilizing the contents of the specification and drawings of the present application, or directly or indirectly applicable to other related technical fields, is similarly included in the patent protection scope of the present application.

Claims

1. A pixel driving circuit including a light emitting element, a power line, a pulse amplitude modulation unit, and a pulse width modulation unit, The power supply lines include a high potential power supply line and a low potential power supply line, and are connected to the light emitting element; The pulse amplitude modulation unit includes a first driving transistor connecting the light emitting device and the high potential power line, and a driving current having a different amplitude is supplied to the light emitting device according to a voltage applied to a gate electrode of the first driving transistor; The pulse width modulation unit includes a second driving transistor connecting the light emitting element and the pulse amplitude modulation unit, and a duration of a driving current of the light emitting element is controlled according to a voltage applied to a gate electrode of the second driving transistor, where the pulse width modulation unit further includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor, a first electrode of the first capacitor is connected to a gate electrode of the second driving transistor, a second electrode of the first capacitor is connected to the high potential power line, a source electrode of the first transistor is connected to a first signal line, a drain electrode of the first transistor is connected to a gate electrode of the second driving transistor, and a gate electrode of the first transistor is connected to a first scanning control line. a source electrode of the second transistor is connected to a second signal line, a drain electrode of the second transistor is connected to a gate electrode of a second driving transistor, a gate electrode of the second transistor is connected to a drain electrode of the third transistor and a first plate of the second capacitor, a source electrode of the third transistor is connected to a third signal line, a drain electrode of the third transistor is connected to a gate electrode of the second transistor and a first plate of the second capacitor, a gate electrode of the third transistor is connected to a second scanning control line, a source electrode of the fourth transistor is connected to a control signal line, a drain electrode of the fourth transistor is connected to the second plate of the second capacitor, and a gate electrode of the fourth transistor is connected to a third scanning control line.

2. 2. The pixel driving circuit of claim 1, wherein a source electrode of the first driving transistor is connected to the high potential power line, a drain electrode of the first driving transistor is connected to a source electrode of the second driving transistor, and a drain electrode of the second driving transistor is connected to the light emitting element.

3. The pixel driving circuit further includes a driving current detection unit, the driving current detection unit is connected to the drain electrode of the first driving transistor, and is used to detect the driving current of the first driving transistor; 2. The pixel driving circuit of claim 1, wherein the driving current detection unit includes a first switching transistor, a source electrode of the first switching transistor is connected to a drain electrode of the first driving transistor, a drain electrode of the first switching transistor is connected to a measurement wiring, and a gate electrode of the first switching transistor is connected to a scanning control line.

4. The pulse width modulation unit further includes a fifth transistor, the fifth transistor being connected in parallel with the first transistor to control a gate voltage of the second driving transistor; 2. The pixel driving circuit of claim 1, wherein a source electrode of the fifth transistor is connected to the first signal line, a drain electrode of the fifth transistor is connected to a gate electrode of the second driving transistor, and a gate electrode of the fifth transistor is connected to the second scanning control line, thereby maintaining an initial voltage of the gate electrode of the second driving transistor.

5. The pixel driving circuit further includes a control unit, the control unit being connected to the light emitting element and the high potential power line, and used for controlling the light emitting element to be turned on / off; 2. The pixel driving circuit of claim 1, wherein the control unit includes a second switching transistor, a source electrode of the second switching transistor is connected to a drain electrode of the second driving transistor, a drain electrode of the second switching transistor is connected to the light-emitting element, and a gate electrode of the second switching transistor is connected to a fourth scanning control line.

6. the pulse amplitude modulation unit further includes a sixth transistor and a third capacitor; 2. The pixel driving circuit of claim 1, wherein a source electrode of the sixth transistor is connected to a data line, a drain electrode of the sixth transistor is connected to a gate electrode of the first driving transistor and a first plate of the third capacitor, a gate electrode of the sixth transistor is connected to a first scanning control line, and a second plate of the third capacitor is connected to the high potential power line.

7. 2. The pixel driving circuit of claim 1, wherein the first driving transistor, the second driving transistor, the first transistor, the second transistor, the third transistor and the fourth transistor are N-type transistors and / or P-type transistors.

8. 2. A method for driving the pixel driving circuit according to claim 1, comprising the steps of: The pulse amplitude modulation unit of the pixel driving circuit further includes a sixth transistor and a third capacitor, a source electrode of the sixth transistor is connected to a data line, a drain electrode of the sixth transistor is connected to a gate electrode of the first driving transistor, and a first plate of the third capacitor is connected, a gate electrode of the sixth transistor is connected to a first scanning control line, and a second plate of the third capacitor is connected to the high potential power line; The driving method of the pixel driving circuit includes: a first step in which the first scanning control line of the Nth row controls the sixth transistor and the first transistor to be turned on, a data voltage of the data line is transmitted to the first plate of the third capacitor and the gate electrode of the first driving transistor through the sixth transistor and the data voltage is maintained through the third capacitor, thereby realizing the amplitude setting of the driving current of the first driving transistor; a first voltage of the first signal line is transmitted to the first plate of the first capacitor and the gate electrode of the second driving transistor through the first transistor and the data voltage is maintained by the first capacitor, thereby making the second driving transistor turn off; a second step in which the second scanning control line of the Nth row controls the third transistor to be turned on, and a third voltage of the third signal line is transmitted to the gate electrode of the second transistor and the first plate of the second capacitor through the third transistor, so as to keep the second transistor off; and at the same time, the third scanning control line controls the fourth transistor to be turned on, and a first level voltage of the control signal line is written to the second plate of the second capacitor through the fourth transistor, and transmitted to the gate electrode of the second transistor by a coupling effect of the second capacitor; a third step in which the third scanning control line of the Nth row controls the fourth transistor to be turned on, and a second level voltage of the control signal line is written to the second plate of the second capacitor through the fourth transistor, and is transmitted to the gate electrode of the second transistor by a coupling effect of the second capacitor, thereby turning off the second transistor; a fourth step in which the third scanning control line of all rows controls the fourth transistor to be turned on, and a swing voltage of the control signal line is transmitted to a gate electrode of the second transistor through the fourth transistor, thereby controlling the second transistor to be turned on, in which the second voltage of the second signal line is transmitted to a gate electrode of a second driving transistor through the second transistor, thereby controlling the second driving transistor to be turned on; Including, The method for driving a pixel driving circuit further comprises controlling a conduction time of the second transistor by the swing voltage, and further controlling a conduction time of the second driving transistor, thereby controlling a light emission time of the light emitting element.

9. 9. The driving method of the pixel driving circuit of claim 8, wherein the second transistor is a P-type transistor, the swing voltage is a uniformly dropping voltage, and the light emitting time of the light emitting element is related to the slope of the swing voltage.

10. 9. The driving method of the pixel driving circuit of claim 8, wherein the second transistor is an N-type transistor, and the swing voltage is a uniformly rising voltage.

11. 9. The driving method for a pixel driving circuit according to claim 8, wherein in the second step or the third step, the second scanning control line or the third scanning control line of the Nth row further controls a first switching transistor to be on, so as to form a path between the drain electrode of the first driving transistor and a measurement wiring, and detects the driving current of the first driving transistor.

12. The pulse width modulation unit further includes a fifth transistor, a source electrode of the fifth transistor is connected to the first signal line, a drain electrode of the fifth transistor is connected to the gate electrode of the second driving transistor, and a gate electrode of the fifth transistor is connected to the second scanning control line; 9. The driving method of the pixel driving circuit of claim 8, wherein in the second step, the second scanning control line of the Nth row further controls the fifth transistor to be turned on, and the first voltage of the first signal line is transmitted to the first plate of the first capacitor and the gate electrode of the second driving transistor, so as to keep the gate voltage of the second driving transistor unchanged.

13. The pixel driving circuit further includes a control unit, the control unit includes a second switching transistor, a source electrode of the second switching transistor is connected to a drain electrode of the second driving transistor, a drain electrode of the second switching transistor is connected to the light emitting element, and a gate electrode of the second switching transistor is connected to a fourth scanning control line; 9. The driving method for a pixel driving circuit according to claim 8, wherein in the fourth step, the fourth scanning control line controls the second switching transistor to be on, thereby forming a path between the high potential power line and the light emitting element, thereby realizing light emission of the light emitting element.

14. A display panel including a plurality of pixel units arranged in an array, wherein a pixel driving circuit described in any one of claims 1 to 7 is installed in each of the pixel units.

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