Photoresist development with halogenated chemicals

Abstract

To provide development of resists useful in forming a patterning mask in the context of high-resolution patterning.SOLUTION: The development can be accomplished using a halide-containing chemical such as a hydrogen halide. A metal-containing resist film may be deposited on a semiconductor substrate using a dry or wet deposition technique. The resist film may be an EUV-sensitive organo-metal oxide thin film resist or organo-metal-containing thin film resist. After exposure, the photopatterned metal-containing resist is developed using wet or dry development.SELECTED DRAWING: Figure 4B

Description

[Background technology]

[0001] [Incorporated by reference] A PCT application is being filed contemporaneously herewith as a part of this application. Each of the applications to which this application claims the benefit of priority, as identified in the contemporaneously filed PCT application, is hereby incorporated by reference in its entirety for all purposes.

[0002] The manufacture of semiconductor devices, such as integrated circuits, is a multi-step process that involves photolithography. In general, the process involves depositing material on a wafer and patterning the material by lithographic techniques to form the structural features (e.g., transistors and circuits) of the semiconductor device. The steps of a typical photolithography process known in the art include: preparing a substrate; applying a photoresist, such as by spin-coating; exposing the photoresist to a desired pattern to make the exposed areas of the photoresist somewhat soluble in a developer; developing by applying a developer to remove either the exposed or unexposed areas of the photoresist; and then processing, for example by etching or material deposition, to form features in the areas of the substrate from which the photoresist was removed.

[0003] Evolution in semiconductor design has created the need for, and been driven by, the ability to create ever-smaller features on semiconductor substrate materials. This advancement in technology is characterized in "Moore's Law," which states that transistor density in high-density integrated circuits doubles every two years. Indeed, advances in chip design and manufacturing have resulted in modern microprocessors that may contain billions of transistors and other circuit functions on a single chip. Individual features on such chips may be on the order of 22 nanometers (nm) or smaller, and in some cases, less than 10 nm.

[0004] One of the challenges in manufacturing devices with such small features is the ability to reliably and reproducibly create photolithography masks with sufficient resolution. Current photolithography processes typically use 193 nm ultraviolet (UV) light to expose photoresist. The fact that the light has a wavelength that is significantly larger than the desired size of the features to be created on the semiconductor substrate creates inherent problems. Achieving feature sizes smaller than the wavelength of the light requires the use of complex resolution enhancement techniques such as multi-patterning. Thus, there has been significant interest and research effort in developing photolithography techniques that use shorter wavelength light, such as extreme ultraviolet (EUV), which has a wavelength of 10 nm to 15 nm, e.g., 13.5 nm.

[0005] However, EUV photolithography processes can present challenges including low light output and loss of light during patterning. Conventional organic chemically amplified resists (CARs), similar to those used in 193 nm UV lithography, have potential drawbacks when used in EUV lithography. In particular, they have low absorption coefficients in the EUV region, and diffusion of photoactivated chemical species can cause blurring or line edge roughness. Furthermore, to provide the etch resistance necessary for patterning into the underlying device layers, fine features patterned in conventional CAR materials can result in high aspect ratios with the risk of pattern collapse. Thus, there remains a need for improved EUV photoresist materials with properties such as reduced thickness, greater absorbance, and greater etch resistance.

[0006] The "Background" description provided herein is intended to provide a general context for the present technology. To the extent described in the "Background" section of the present specification, the work of the inventors named herein, as well as aspects of the present specification that may not be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art to the present technology. Summary of the Invention

[0007] Developing a photoresist can be useful, for example, to form a patterning mask in the context of high resolution patterning. Development can selectively remove either exposed or unexposed portions of the resist using specific development chemistries. The development chemistries include halides, such as hydrogen halides or mixtures of hydrogen and halide gases. In some embodiments, the development is a dry development. In some embodiments, the resist is a photopatterned metal-containing EUV resist. In some embodiments, the dry development process is a thermal process without plasma.

[0008] Disclosed herein are methods and systems for processing a semiconductor substrate that include providing a photopatterned metal-containing resist on a substrate layer of a semiconductor substrate in a process chamber and developing the photopatterned metal-containing resist by selectively removing portions of the resist by exposure to a halide-containing developer chemistry to form a resist mask.

[0009] In some implementations, the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist. In some implementations, developing the photo-patterned metal-containing EUV resist includes selectively removing the EUV unexposed portions of the EUV resist with a developing chemical relative to the EUV exposed portions to form a resist mask. In some implementations, the developing chemical includes hydrogen halide, hydrogen gas and a halide gas, an organic halide, an acyl halide, a carbonyl halide, a thionyl halide, or a mixture thereof. In some implementations, the developing chemical includes hydrogen fluoride, hydrogen chloride, hydrogen bromide, or hydrogen iodide. In some implementations, developing the photo-patterned metal-containing resist by exposure to a developing chemical includes dry developing the photo-patterned metal-containing resist by exposure to a dry developing chemical. In some implementations, dry developing the photo-patterned metal-containing resist includes applying a remote plasma including halide radicals to the resist. In some implementations, dry developing the photopatterned metal-containing resist is performed at a temperature between −60° C. and 120° C., at a chamber pressure between 0.1 mTorr and 500 mTorr or between about 0.5 Torr and about 760 Torr, and with a gas flow rate of halide between 100 sccm and 2000 sccm, and the resist mask etch selectivity is tunable based at least in part on the temperature, the chamber pressure, the gas flow rate, or a combination thereof. In some implementations, the temperature is between −20° C. and 20° C. In some implementations, the photopatterned metal-containing resist comprises an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. In some implementations, the method further includes exposing the photopatterned metal-containing resist to an inert gas plasma after developing the photopatterned metal-containing resist.In some implementations, the method further includes depositing a metal-containing EUV resist film on the semiconductor substrate and non-selectively removing the metal-containing EUV resist film from the semiconductor substrate without removing a substrate layer prior to providing the photopatterned metal-containing resist.

[0010] Disclosed herein is an apparatus for resist development, the apparatus including a process chamber having a substrate support, a vacuum line coupled to the process chamber, and a developer chemical line coupled to the process chamber, the apparatus further including a controller configured with instructions for processing a semiconductor substrate, the instructions including code for providing a photopatterned metal-containing resist on a substrate layer of the semiconductor substrate in the process chamber, and code for developing the photopatterned metal-containing resist by selectively removing portions of the resist by exposure to a developer chemical that includes a halide to form a resist mask.

[0011] In some implementations, the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist, and the controller is configured with instructions, the instructions including code for developing the photo-patterned metal-containing EUV resist and for selectively removing the EUV non-exposed portions of the EUV resist relative to the EUV exposed portions with a developing chemistry to form a resist mask. In some implementations, the apparatus further includes one or more heaters coupled to the substrate support, the one or more heaters including a plurality of independently controllable temperature control zones. In some implementations, the interior of the process chamber is coated with a corrosion inhibitor. In some implementations, the apparatus further includes a cold trap coupled to the process chamber, the cold trap configured to remove water from the process chamber. In some implementations, the apparatus further includes a UV or IR lamp coupled to the process chamber, the UV or IR lamp configured to cure the photo-patterned metal-containing resist or remove excess halide from the process chamber.

[0012] Disclosed herein is a method of processing a semiconductor substrate, the method including providing a dry deposited photo-patterned metal oxide EUV resist on a substrate layer of a semiconductor substrate in a process chamber, and dry developing the photo-patterned metal oxide EUV resist by selectively removing non-EUV exposed portions of the EUV resist by exposure to a dry developing chemistry that includes a hydrogen halide to form a resist hard mask from the EUV exposed portions.

[0013] In some implementations, the dry development is a plasma-free thermal process, and the exposure to the dry development chemistry is at a temperature between about −20° C. and about 20° C. In some implementations, the photopatterned metal oxide EUV resist comprises an organotin oxide.

[0014] These and other features of the disclosed embodiments are described in detail below with reference to the associated drawings. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 illustrates a flow diagram of an exemplary method for depositing and developing photoresist, according to some embodiments.

[0016] [Figure 2A] FIG. 2A shows schematic cross-sectional views of various processing stages of dry development according to some embodiments. [Figure 2B] FIG. 2B shows schematic cross-sectional views of various processing stages of dry development according to some embodiments. [Figure 2C] FIG. 2C shows schematic cross-sectional views of various processing stages of dry development according to some embodiments.

[0017] [Diagram 3] FIG. 3 illustrates an exemplary dry development mechanism of a chemical reaction between hydrogen bromide (HBr) and exposed and unexposed portions of an EUV photoresist, according to some embodiments.

[0018] [Figure 4A] FIG. 4A shows a schematic cross-sectional view of dry development without application of an inert gas plasma according to some embodiments.

[0019] [Figure 4B] FIG. 4B shows a schematic cross-sectional view of a dry development cyclic inert gas plasma for descum treatment, according to some embodiments.

[0020] [Diagram 5] FIG. 5 shows a graph comparing the etch rate of exposed and unexposed EUV photoresist using helium plasma during dry development.

[0021] [Figure 6A]FIG. 6A shows scanning electron microscope (SEM) images comparing wet and dry development with respect to line collapse. [Figure 6B] FIG. 6B shows scanning electron microscope (SEM) images comparing wet and dry development with respect to line collapse.

[0022] [Figure 7A] FIG. 7A shows SEM images comparing wet and dry development with respect to roughness and critical dimension (CD) control. [Figure 7B] FIG. 7B shows SEM images comparing wet and dry development with respect to roughness and critical dimension (CD) control.

[0023] [Figure 8] FIG. 8 shows SEM images comparing wet and dry development with respect to scum after opening the hard mask.

[0024] [Figure 9A] FIG. 9A shows a graph illustrating the effect of a second post-exposure bake operation on dry development selectivity for various pressures and temperatures. [Figure 9B] FIG. 9B shows a graph illustrating the effect of a second post-exposure bake operation on dry development selectivity for various pressures and temperatures.

[0025] [Figure 10] FIG. 10 shows SEM images showing the effect of pressure on the EUV resist profile.

[0026] [Figure 11A] FIG. 11A shows SEM images of EUV resist at different line / space pitches and different thicknesses. [Figure 11B] FIG. 11B shows SEM images of EUV resist at different line / space pitches and different thicknesses.

[0027] [Figure 12]FIG. 12 illustrates a schematic diagram of an exemplary process station for maintaining a low pressure environment suitable for performing development, cleaning, rework, descum, and smoothing operations, according to some embodiments.

[0028] [Figure 13] FIG. 13 shows a schematic diagram of an exemplary multi-station processing tool suitable for performing the various developing, cleaning, rework, descumming, and smoothing operations described herein.

[0029] [Figure 14] FIG. 14 illustrates a cross-sectional schematic diagram of an example inductively coupled plasma apparatus for carrying out certain embodiments and operations described herein.

[0030] [Figure 15] FIG. 15 illustrates a semiconductor process cluster tool architecture having a vacuum integrated deposition and patterning module interfaced with a vacuum transfer module suitable for implementing the processes described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The present disclosure relates generally to the field of semiconductor processing. In certain aspects, the present disclosure is directed to processes and apparatus for developing photoresists (e.g., EUV-sensitive metal-containing photoresists and / or metal oxide-containing photoresists) using halogenated chemistries, for example to form patterning masks in the context of EUV patterning.

[0032] Reference will now be made in detail to specific embodiments of the present disclosure. Examples of specific embodiments are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the present disclosure to such specific embodiments. Rather, the present disclosure is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0033] introduction Patterning of thin films in semiconductor processing is often a key step in semiconductor manufacturing. Patterning involves lithography. In traditional photolithography, such as 193 nm photolithography, a pattern is formed by firing photons from a photon source onto a mask and printing the pattern onto a light-sensitive photoresist, causing a chemical reaction in the photoresist, which, after development, removes certain portions of the photoresist to form the pattern.

[0034] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include the 22 nm, 16 nm, and beyond. For example, at the 16 nm node, the width of a typical via or line in a damascene structure is typically about 30 nm or less. The scaling of features on advanced semiconductor integrated circuits (ICs) and other devices is driving improvements in lithographic resolution.

[0035] Extreme ultraviolet (EUV) lithography can extend lithography techniques by moving to shorter imaging light source wavelengths than are feasible with traditional photolithography methods. EUV sources with wavelengths of about 10-20 nm, or 11-14 nm, for example 13.5 nm, can be used in state-of-the-art lithography tools, also called scanners. EUV radiation works in a vacuum because it is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor.

[0036] EUV lithography utilizes EUV resists that are patterned to form a mask used to etch the underlying layers. The EUV resists can be polymer-based chemically amplified resists (CARs) fabricated by liquid-based spin-on techniques. An alternative to CARs are directly photopatternable metal oxide-containing films, available, for example, from Inpria (Corvallis, OR) and described, for example, in U.S. Patent Publication Nos. 2017 / 0102612, 2016 / 021660, and 2016 / 0116839, which are incorporated by reference herein at least for their disclosure of photopatternable metal oxide-containing films. Such films can be fabricated by spin-on techniques or dry vapor deposition. Metal oxide-containing films can be directly patterned (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum environment, as described, for example, in U.S. Patent No. 9,996,004, issued June 12, 2018, entitled "PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS," and / or International Application No. PCT / US19 / 31618, filed May 9, 2019, entitled "METHODS FOR MAKING EUV PATTERNABLE HARD MASKS," providing patterning resolutions of less than 30 nm, the disclosures of which at least those portions pertaining to the composition, deposition, and patterning of directly photopatternable metal oxide films are incorporated herein by reference. Generally, patterning involves exposing an EUV resist to EUV radiation to form a photopattern in the resist, followed by development to remove portions of the resist according to the photopattern to form a mask.

[0037] It should also be understood that the present disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, but is also applicable to other next generation lithographic techniques. In addition to EUV, which includes the standard 13.5 nm EUV wavelength currently in use and under development, the most relevant radiation sources for such lithography are DUV (deep-UV), which generally refers to the use of 248 nm or 193 nm excimer laser sources, X-ray, which formally includes EUV in the lower energy range of the X-ray range, and electron beam, which can cover a wide energy range. Specific methods may depend on the specific materials and applications used in the semiconductor substrate and final semiconductor device. Thus, the methods described in this application are merely exemplary of methods and materials that may be used in the present technology.

[0038] Directly photopatternable EUV resists may consist of or include metals and / or metal oxides mixed in an organic component. Metals / metal oxides hold great promise in terms of enhanced EUV photon adsorption, secondary electron generation, and / or increased etch selectivity to the underlying layer stack and device layers. So far, these resists have been developed using wet (solvent) techniques, which require moving the wafer on a track where it is exposed to a developing solvent, dried, and baked. Wet development not only limits productivity, but can also result in line collapse due to surface tension and / or delamination.

[0039] Dry development techniques have been proposed to overcome these problems by eliminating substrate delamination and interface failure. Dry development can improve performance (e.g., prevent line collapse due to surface tension and delamination in wet development) and increase throughput (e.g., by avoiding wet development tracks). Other advantages may include eliminating the use of organic solvent developers, reducing sensitivity to adhesion issues, increasing EUV absorption for improved dose efficiency, and no limitations based on solubility. Dry development can also provide greater tunability, additional critical dimension (CD) control, and scum removal.

[0040] Dry development has its own challenges including etch selectivity between unexposed and EUV exposed resist materials, which can result in larger dose to size requirements for effective resist exposure when compared to wet development. If the selectivity is not optimal, corner rounding of the PR corners can occur due to longer exposure under etching gases, which can increase line CD variation in the subsequent transfer etch step.

[0041] EUV resist development According to various aspects of the present disclosure, the photopatterned metal-containing photoresist is developed by exposure to a halide-containing chemical. An EUV-sensitive metal or metal oxide-containing film, such as organotin oxide, is disposed on a semiconductor substrate. The EUV-sensitive metal or metal oxide-containing film is directly patterned by EUV exposure in a vacuum environment. The pattern is then developed using a development chemical to form a resist mask. In some embodiments, the development chemical is a dry development chemical. In some embodiments, the dry development chemical includes hydrogen and a halide. Such dry development techniques may be performed using either a mild plasma (high pressure, low power) or thermal process while flowing a hydrogen and halide dry development chemical. The present disclosure provides processes and apparatus configured to develop the metal-containing resist as part of a resist mask formation process. Various embodiments include a combination of all dry operations by vapor deposition, EUV lithography patterning, and dry development. Various other embodiments include a combination of wet and dry processing operations, for example, a spin-on EUV photoresist (wet process) may be combined with a dry development or other wet or dry process as described herein. Also described are various post-deposition (or post-application) processes such as bevel and backside cleaning, chamber cleaning, descumming, smoothing, curing to modify and enhance film properties, and photoresist work processes.

[0042] FIG. 1 illustrates a flow diagram of an exemplary method of depositing and developing photoresist, according to some embodiments. The operations of process 100 may be performed in a different order and / or with different, fewer, or additional operations. Aspects of process 100 may be described with reference to FIGS. 2A-2C, 3, and 4A-4B. One or more operations of process 100 may be performed using an apparatus as described in any one of FIGS. 12-15. In some embodiments, the operations of process 100 may be implemented, at least in part, in accordance with software stored on one or more non-transitory computer-readable media.

[0043] In block 102 of process 100, a layer of photoresist is deposited. This can be either a dry deposition process, such as a vapor deposition process, or a wet process, such as a spin-on deposition process.

[0044] The photoresist may be a metal-containing EUV resist. The EUV-sensitive metal or metal oxide-containing film may be deposited on the semiconductor substrate by any suitable technique, including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, the described process is demonstrated for organotin oxide-based EUV photoresist compositions and is applicable to both commercially spin-coatable formulations (such as those available from Inpria Corp (Corvallis, OR)) and formulations applied using dry vacuum deposition techniques as further described below.

[0045] The semiconductor substrate may include any material structure suitable for photolithographic processing, particularly for the manufacture of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer on which features with irregular surface topography have been fabricated ("underlying features"). As referred to herein, "surface" is the surface on which the film of the present disclosure will be deposited or the surface that will be exposed to EUV during processing. The underlying features may include areas where material has been removed (e.g., by etching) or where material has been added (e.g., by deposition) during processing prior to performing the method of the present disclosure. Such pre-processing may include the method of the present disclosure or other processing methods in an iterative process in which two or more layers of features are formed on the substrate.

[0046] EUV-sensitive thin films may be deposited on semiconductor substrates, and such films may be used as resists for subsequent EUV lithography and processing. Such EUV-sensitive thin films include materials that undergo changes upon exposure to EUV, such as loss of bulky pendant substituents bonded to metal atoms in low-density M-OH-rich materials, allowing crosslinking to higher-density MOM-bonded metal oxide materials. EUV patterning creates regions of the film with altered physical or chemical properties compared to unexposed regions. These properties may be exploited in subsequent processing, for example, to dissolve either unexposed or exposed regions, or to selectively deposit material in either exposed or unexposed regions. In some embodiments, under conditions under which such subsequent processing is performed, the unexposed film has a more hydrophobic surface than the exposed film. For example, material removal may be achieved by exploiting differences in chemical composition, density, and crosslinking of the film. Removal may be achieved by wet or dry processing, as further described below.

[0047] In various embodiments, the thin film is an organometallic material, such as an organotin material that includes tin oxide or other metal oxide materials / moieties. The organometallic compound may be formed in a gas phase reaction of an organometallic precursor with a counter-reactant. In various embodiments, the organometallic compound is formed by mixing a specific combination of an organometallic precursor having a bulky alkyl or fluoroalkyl group with a counter-reactant and polymerizing the mixture in the gas phase to produce a low density EUV sensitive material that is deposited on the semiconductor substrate.

[0048] In various embodiments, the organometallic precursors contain at least one alkyl group for each metal atom capable of undergoing gas phase reaction, while the ligands or ions coordinated to the metal atoms can be replaced with counter-reactants. M a R b L c (Formula 1) where M is an element having a high patterning radiation absorption cross section; R is alkyl, e.g., C n H 2n+1 where preferably n≧2; L is a ligand, ion, or other moiety that reacts with the counterreactant, and a≧1, b≧1, and c≧1.

[0049] In various embodiments, M is 1x10 7 cm 2 / mol or more. M may be, for example, selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, M is tin. R may be fluorinated, for example, represented by the formula C n F x H (2n+1)In various embodiments, R has at least one beta hydrogen or beta fluorine. For example, R may be selected from the group consisting of ethyl, i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec-butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L may be any moiety that is readily displaced by a counter reactant to generate the M-OH moiety, such as a moiety selected from the group consisting of an amine (dialkylamino, monoalkylamino, etc.), an alkoxy, a carboxylic acid, a halogen, and mixtures thereof.

[0050] The organometallic precursor may be any of a wide variety of possible metal organic precursors. For example, when M is tin, such precursors include t-butyltris(dimethylamino)tin, i-butyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, i-propyl(tris)dimethylaminotin, n-propyltris(dimethylamino)tin, ethyltris(dimethylamino)tin, and similar alkyl(tris)(t-butoxy)tin compounds such as t-butyltris(t-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0051] Counter-reactants have the ability to replace reactive moieties, ligands, or ions (e.g., L in formula 1 above) to link at least two metal atoms by a chemical bond. Counter-reactants may include water, peroxides (e.g., hydrogen peroxide), di- or polyhydroxy alcohols, fluorinated di- or polyhydroxy alcohols, fluorinated glycols, and other sources of hydroxyl moieties. In various embodiments, the counter-reactant reacts with the organometallic precursor by forming oxygen bridges between adjacent metal atoms. Other potential counter-reactants include hydrogen sulfide and hydrogen disulfide, which may bridge metal atoms by sulfur bridges.

[0052] The thin film may include optional materials in addition to the organometallic precursor and counter-reactant to modify the chemical or physical properties of the film, for example, to modify the film's sensitivity to EUV or to increase the etch resistance. Such optional materials may be introduced by doping during vapor formation, for example, before deposition on the semiconductor substrate, after deposition of the thin film, or both. In some embodiments, a mild remote H2 plasma may be introduced to replace some Sn-L bonds with Sn-H, which may increase the reactivity of the resist under EUV.

[0053] In various embodiments, the EUV patternable film is prepared and deposited on the semiconductor substrate using vapor deposition equipment and processes known in the art. In such processes, a polymerized organometallic material is formed in the vapor phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with CVD components, e.g., discontinuous ALD-like processes in which the metal precursor and counter-reactant are separated in either time or space.

[0054] In general, the method includes mixing a vapor flow of an organometallic precursor with a vapor flow of a counter-reactant to form a polymerized organometallic material, and depositing the organometallic material on a surface of a semiconductor substrate. In some embodiments, more than one organometallic precursor is included in the vapor flow. In some embodiments, more than one counter-reactant is included in the vapor flow. As will be appreciated by one of skill in the art, the mixing and deposition aspects of the process may be simultaneous in a substantially continuous process.

[0055] In an exemplary continuous CVD process, two or more gas streams of organometallic precursor and counter-reactant sources are introduced into the deposition chamber of a CVD apparatus through separate inlet paths, where they mix and react in the gas phase to form an agglomerated polymeric material (e.g., metal-oxygen-metal bond formation). These flows may be introduced, for example, using separate inlets or a dual plenum showerhead. The apparatus is configured such that the organometallic precursor and counter-reactant flows are mixed in the chamber, and the organometallic precursor and counter-reactant react to form a polymerized organometallic material. Without limiting the mechanism, function, or utility of the present technology, it is believed that the products from such gas phase reactions are heavier in molecular weight because the metal atoms are cross-linked by the counter-reactant, and then condense or deposit on the semiconductor substrate. In various embodiments, the steric hindrance of the bulky alkyl groups prevents the formation of a tightly packed network, forming a smooth, porous, low-density film.

[0056] CVD processes are typically carried out under reduced pressure, such as between 10 mTorr and 10 Torr. In some embodiments, the processes are carried out at 0.5 to 2 Torr. In some embodiments, the temperature of the semiconductor substrate is equal to or lower than the temperature of the reactant streams. For example, the substrate temperature can be between 0° C. and 250° C., or between ambient temperature (e.g., 23° C.) and 150° C. In various processes, deposition of the polymerized organometallic material onto the substrate occurs at a rate that is inversely proportional to the surface temperature.

[0057] In some embodiments, the EUV patternable film is fabricated and deposited on the semiconductor substrate using wet deposition equipment and processes known in the art, for example, an organometallic material is formed by spin coating onto the surface of the semiconductor substrate.

[0058] The thickness of the EUV patternable film formed on the surface of the semiconductor substrate may vary depending on the surface characteristics, the materials used, and the processing conditions. In various embodiments, the thickness of the film may range from 0.5 nm to 100 nm and may be thick enough to absorb a majority of the EUV light under the conditions of EUV patterning. The EUV patternable film may be capable of accommodating 30% or more absorption, which results in significantly fewer available EUV photons toward the bottom of the EUV patternable film. Higher EUV absorption leads to more crosslinking and densification near the top of the EUV exposed film compared to the bottom of the EUV exposed film. Insufficient crosslinking may cause the resist to lift or collapse in wet development, but with dry development, there is no such risk. An all-dry lithography approach may facilitate more efficient utilization of EUV photons with a more opaque resist film. It will be appreciated that efficient utilization of EUV photons may occur with EUV patternable films with higher overall absorption, but in some cases, the EUV patternable film may be less than about 30%. For comparison, most other resist films have a maximum overall absorption of less than 30% (e.g., 10% or less, or 5% or less), so that the resist material at the bottom of the resist film is fully exposed. In some embodiments, the thickness of the film is 10 nm to 40 nm, or 10 nm to 20 nm. Without limiting the mechanism, function, or utility of the present disclosure, it is believed that unlike wet spin-coating processes in the art, the process of the present disclosure has fewer limitations on the surface adhesion properties of the substrate and therefore may be applied to a wide variety of substrates. In addition, as discussed above, the deposited film may closely conform to surface features, providing the advantage that a mask may be formed on a substrate, such as a substrate having underlying features, without "filling" or planarizing such features.

[0059] At block 104, an optional cleaning process is performed to clean the backside and / or bevel edge of the semiconductor substrate. Backside and / or bevel edge cleaning may non-selectively etch the EUV resist film to evenly remove films with different levels of oxidation or crosslinking at the backside and bevel edge of the substrate. During application of the EUV patternable film by either wet or dry deposition processes, unintended deposition of resist material may occur at the bevel edge and / or backside of the substrate. Unintended deposition may cause unwanted particles to migrate to the top side of the semiconductor substrate later and become particle defects. Moreover, this bevel edge and backside deposition may cause downstream processing issues, including contamination of patterning (scanner) and development tools. Traditionally, this removal of bevel edge and backside deposits is performed by wet cleaning techniques. For spin-coated photoresist materials, this process is called edge bead removal (EBR) and is performed by directing a flow of solvent from above and below the bevel edge while the substrate is rotating. The same process can be applied to soluble organotin oxide based resists deposited by vapor deposition techniques.

[0060] Cleaning the bevel edge and / or backside of the substrate may also be a dry cleaning process. In some embodiments, the dry cleaning process involves vapor and / or plasma with one or more of the following gases: HBr, HCl, BCl3, SOCl2, Cl2, BBr3, H2, O2, PCl3, CH4, methanol, ammonia, formic acid, NF3, HF. In some embodiments, the dry cleaning process may use the same chemistry as the dry developing process described herein. For example, cleaning the bevel edge and backside may use a hydrogen halide developing chemistry. In the backside and bevel edge cleaning process, the vapor and / or plasma must be limited to certain areas of the substrate to ensure that only the backside and bevel are removed without any degradation of the film on the front side of the substrate.

[0061] Process conditions may be optimized for bevel edge and backside cleaning. In some embodiments, higher temperatures, higher pressures, and / or higher flow rates of reactants may lead to increased etch rates. Suitable process conditions for dry bevel edge and backside cleaning may be reactant flow rates of 100-10,000 sccm (e.g., 500 sccm HCl, HBr, HI, or H2 with Cl2 or Br2, BCl3, or H2), temperature of 20-140° C. (e.g., 80° C.), pressure of 20-1000 mTorr (e.g., 100 mTorr), plasma power of 0-500 W at radio frequency (e.g., 13.56 MHz), and time of about 10-20 seconds, depending on the photoresist film and composition and properties. These conditions are suitable for some process reactors, e.g., Kiyo etch tools available from Lam Research Corporation (Fremont, Calif.), but it should be understood that a wider range of process conditions may be used depending on the capabilities of the process reactor.

[0062] Alternatively, the dry cleaning operation may be extended to a full photoresist removal or photoresist "rework" where the applied EUV photoresist is removed, and to a semiconductor substrate prepared for photoresist reapplication, such as when the original photoresist is damaged or defective. Photoresist rework must be performed without damaging the underlying semiconductor substrate, so oxygen-based etches should be avoided. Alternately, variations of the halide-containing chemistries described herein may be used. It will be understood that the photoresist rework operation may be applied at any stage during the process 100. Thus, the photoresist rework operation may be applied after photoresist deposition, after bevel edge and backside cleaning, after PAB processing, after EUV exposure, after PEB processing, or after development. In some embodiments, the photoresist rework may be performed for removal that is non-selective to exposed and unexposed areas of the photoresist, but selective to the underlying layers.

[0063] In some embodiments, the photoresist rework process involves steam and / or plasma having one or more of the following gases: HBr, HCl, HI, BCl3, Cl2, BBr3, H2, PCl3, CH4, methanol, ammonia, formic acid, NF3, HF. In some embodiments, the photoresist rework process may use the same chemistries as the dry development processes described herein. For example, photoresist rework may use hydrogen halide development chemistries.

[0064] Process conditions may be optimized for photoresist rework. In some embodiments, higher temperatures, higher pressures, and / or higher flow rates of reactants may lead to increased etch rates. Suitable process conditions for photoresist rework include reactant flow rates of 100-500 sccm (e.g., 500 sccm HCl, HBr, HI, BCl3, or H2 with Cl2 or Br2), temperatures of 20-140° C. (e.g., 80° C.), pressures of 20-1000 mTorr (e.g., 300 mTorr), plasma power of 300-800 W (e.g., 500 W) at high frequency (e.g., 13.56 MHz), and wafer bias of 0-200 V, sufficient to completely remove EUV photoresist, depending on the photoresist film and composition and properties. b (Higher bias may be used for harder underlying substrate materials), and time may be about 20 seconds to 3 minutes. These conditions are suitable for some processing reactors, e.g., Kiyo etch tools available from Lam Research Corporation (Fremont, Calif.), but it should be understood that a wider range of process conditions may be used depending on the capabilities of the processing reactor.

[0065] In block 106 of process 100, an optional post-application bake (PAB) is performed after deposition of the EUV patternable film and before EUV exposure. The PAB process may involve a combination of thermal treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV patternable film, thereby reducing the EUV dose to develop a pattern in the EUV patternable film. The PAB process temperature may be adjusted and optimized to increase the sensitivity of the EUV patternable film. For example, the process temperature may be about 90° C. to about 200° C., or about 150° C. to about 190° C. In some embodiments, the PAB process may be performed at a pressure between atmospheric pressure and vacuum, and a process duration of about 1 to 15 minutes, such as about 2 minutes. In some embodiments, the PAB process is performed at a temperature of about 100° C. to 200° C. for about 1 to 2 minutes.

[0066] In block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally speaking, EUV exposure causes changes in chemical composition and crosslinking in the metal-containing EUV resist film, creating a contrast in etch selectivity that can be exploited for subsequent development.

[0067] The metal-containing EUV resist film may then be patterned by exposing areas of the film to EUV light, typically under a relatively high vacuum. EUV devices and imaging methods useful herein include methods known in the art. Specifically, as described above, EUV patterning results in exposed areas of the film having altered physical or chemical properties compared to unexposed areas. For example, metal-carbon bond cleavage may occur in the exposed areas, such as through beta hydride elimination, leaving reactive and accessible metal hydride functional groups that can be converted to hydroxides and bridging metal oxide moieties through metal-oxygen bridges during a subsequent post-exposure bake (PEB) step. This process can be used to create chemical contrast for development as a negative resist. In general, the higher the number of beta Hs in the alkyl group, the higher the sensitivity of the film. This can also be explained as weaker Sn-C bonds with more branching. Following exposure, the metal-containing EUV resist film may be baked to create additional crosslinks in the metal oxide film. Subsequent processing may exploit the difference in properties between the exposed and unexposed regions, such as dissolving the unexposed regions or depositing material in the exposed regions, For example, the pattern can be developed using dry methods to form a metal oxide-containing mask.

[0068] Specifically, in various embodiments, hydrocarbyl-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed regions of the imaging layer, especially when the exposure is performed in a vacuum using EUV. However, by removing the exposed imaging layer from the vacuum into air or by the controlled introduction of oxygen, ozone, H2O2, or water, the surface Sn-H can be oxidized to Sn-OH. For example, the irradiated regions, the non-irradiated regions, or both, may be reacted with one or more reagents to selectively add or remove material from the imaging layer, thereby exploiting the property differences between the exposed and non-exposed regions in subsequent processing.

[0069] Without limiting the mechanism, function, or utility of the present technology, for example, 10 mJ / cm 2 ~100mJ / cm 2 EUV exposure at doses of 1000 nm leads to the cleavage of Sn-C bonds, resulting in the disappearance of alkyl substituents, relieving steric hindrance and allowing the collapse of low density films. In addition, reactive metal-H bonds generated in the beta hydride elimination reaction can react with adjacent active groups such as hydroxyls in the film, resulting in further cross-linking and densification, creating chemical contrast between exposed and unexposed regions.

[0070] Exposing the metal-containing EUV resist film to EUV light results in a photopatterned metal-containing EUV resist, which includes EUV exposed and unexposed areas.

[0071] In block 110 of process 100, an optional post-exposure bake (PEB) is performed to further increase the etch selectivity contrast of the photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist can be thermally treated in the presence of various chemical species to promote crosslinking of the EUV exposed regions or can simply be baked on a hotplate in ambient air at, for example, 150° C.-250° C. for 1-5 minutes (e.g., 190° C. for 2 minutes).

[0072] In various embodiments, the bake strategy includes careful control of the bake environment, introduction of reactive gases, and / or careful control of the bake temperature ramp rate. Examples of useful reactive gases include, for example, air, HO, HO2 vapor, CO2, CO, O2, O3, CH4, CH3OH, N2, H2, NH3, NO, alcohol, acetylacetone, formic acid, Ar, He, or mixtures thereof. The PEB process is designed to (1) promote complete evaporation of organic fragments generated during EUV exposure, (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated in the metal hydroxide by EUV exposure, and (3) promote cross-linking between adjacent Sn-OH groups to form a more densely cross-linked SnO2-like network. The bake temperature is carefully selected to achieve optimal EUV lithography performance. Too low a PEB temperature results in insufficient cross-linking, which results in a reduced chemical contrast for development at a given dose. Too high a PEB temperature can suffer from adverse effects including severe oxidation and film shrinkage in unexposed areas (in this example, areas that are removed by development of the patterned film to form the mask) and undesirable interdiffusion at the interface between the photopatterned metal-containing EUV resist and the underlayer, both of which can cause loss of chemical contrast and increased defect density due to insoluble scum. The PEB treatment temperature can be from about 100°C to about 300°C, from about 170°C to about 290°C, or from about 200°C to about 240°C. In some embodiments, the PEB treatment can be performed at a pressure between atmospheric pressure and vacuum, and for a treatment duration of about 1 to 15 minutes, for example about 2 minutes. In some embodiments, the PEB thermal treatment can be repeated to further increase the etch selectivity.

[0073] In block 112 of process 100, the photopatterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, either the exposed areas are removed (positive tone) or the unexposed areas are removed (negative tone). In some embodiments, the development may include selective deposition of the photopatterned metal-containing EUV resist either on the exposed areas or on the unexposed areas, followed by an etching operation. In various embodiments, these processes may be dry or wet processes. In some embodiments, the development may be performed without generating a plasma. Alternatively, the development may be performed with a flow of hydrogen and halides (e.g., H2, and Cl2, and / or Br2) activated in a remote plasma source or activated by exposure to remote UV radiation. The photoresist for development may include an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The element may have a large patterning radiation absorption cross-section. In some embodiments, the element may have a large EUV absorption cross-section. In some embodiments, the metal-containing EUV resist may have an overall absorptivity of greater than 30%. In an all-dry lithography process, this results in more efficient utilization of EUV photons, allowing for the development of thicker, more opaque resists.

[0074] An example process for development involves subjecting an organotin oxide-containing EUV-sensitive photoresist film (e.g., 10-30 nm thick, e.g., 20 nm thick) to an EUV exposure dose and a post-exposure bake, followed by development. The photoresist film may be deposited based on the gas-phase reaction of an organotin precursor, such as isopropyl(tris)(dimethylamino)tin with water vapor, or may be a spin-on film containing tin clusters in an organic matrix.

[0075] The photopatterned metal-containing EUV resist is developed by exposure to a development chemical, the development chemical being a halide-containing chemical. In some embodiments, the development chemical comprises hydrogen and a halide, such as a hydrogen halide (e.g., HBr or HCl), or hydrogen and a halogen gas (e.g., H2 and Cl2). In some embodiments, the development chemical comprises a hydrogen halide, hydrogen and a halogen gas, boron trichloride, or a combination thereof. The development of the EUV resist can be performed by wet development using a halide-containing chemical, or dry development using a hydrogen halide-containing chemical. In embodiments where the EUV resist is developed using wet development, the wet development may be combined with other wet processing operations, such as wet deposition (e.g., spin-on deposition) of a metal-containing EUV resist film. Alternatively, the wet development may be combined with other dry processing operations, such as vapor deposition (e.g., CVD) of a metal-containing EUV resist film. In embodiments where the EUV resist is developed using dry development, the dry development may be combined with other dry processing operations, such as dry deposition (e.g., CVD) of a metal-containing EUV resist film. In alternative embodiments where the EUV resist is developed using dry development, the dry development may be combined with other wet processing operations, such as wet deposition (eg, spin-on deposition) of a metal-containing EUV resist film.

[0076] In some embodiments, the processing of the semiconductor substrate may combine all dry steps including film formation by vapor deposition, EUV lithography patterning, and dry development. In fact, each of the operations 102-112 of the process 100 may be a dry processing operation. Such processing operations may avoid material and productivity costs associated with wet processing operations such as wet development. Dry processing may provide greater tunability and add additional critical dimension (CD) control and scum removal. Wet processing generally involves moisture and / or oxygen, which more easily leads to the formation of scum. Wet development is limited by solubility and cluster size, whereas dry development is not. Wet development is prone to pattern collapse and delamination issues, whereas dry development avoids these issues. Furthermore, the use of all dry processing operations may facilitate integration in interconnected vacuum processing chambers without exposure to and contamination by ambient air or trace contaminants contained therein. For example, the PEB heat treatment, in which the exposed areas undergo further cross-linking, may occur in the same chamber as development, although it will be understood that the PEB heat treatment may be performed in a separate chamber.

[0077] The development process can be performed by delivering the development chemicals in liquid or gas phase. In some embodiments, the dry development process can be performed by using either a gentle plasma (high pressure, low power) or thermal process while flowing a hydrogen halide-containing dry development chemical such as HF, HCl, HBr, or HI. For example, dry development can be performed with a thermal process using a dry development chemical such as HCl or HBr. In some embodiments, the hydrogen halide-containing chemical can rapidly remove the unexposed material, leaving behind a pattern of the exposed film that can be transferred to the underlying layer by a plasma-based etching process, such as a conventional etching process.

[0078] In a thermal development process, the substrate is exposed to a development chemical (e.g., Lewis acid) in a process chamber (e.g., oven). In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a development chemical line may be coupled to the process chamber for delivering the development chemical to the process chamber. The process chamber may include one or more heaters for temperature control, such as a heater coupled to a substrate support in the process chamber for substrate temperature control. In some embodiments, the chamber interior may be coated with a corrosion resistant film, such as an organic polymer or inorganic coating. One such coating is polytetrafluoroethylene (PTFE), e.g., Teflon 1M. Such materials may be used in the thermal processes of the present disclosure without the risk of removal by plasma exposure.

[0079] In a thermal development process, the photopatterned metal-containing EUV resist is exposed to a development chemistry at a temperature optimized for etch selectivity between exposed and unexposed regions. Lower temperatures may increase the etch selectivity contrast, while higher temperatures may decrease the etch selectivity contrast. In some embodiments, the temperature may be about -60°C to about 120°C, about -20°C to about 60°C, or about -20°C to about 20°C, for example, about -10°C. The chamber pressure may be adjusted, and the chamber pressure may affect the etch selectivity between exposed and unexposed regions during development. In some embodiments, the chamber pressure may be relatively low and without dilution, and the chamber pressure may be about 0.1 mTorr to about 300 mTorr, about 0.2 mTorr to about 100 mTorr, or about 0.5 mTorr to about 50 mTorr. In some embodiments, the chamber pressure may be about 20 mTorr to about 800 mTorr, or about 20 mTorr to about 500 mTorr, for example, about 300 mTorr. In some embodiments, the chamber pressure may be relatively high, with high flow rates and no dilution, and the chamber pressure may be about 100 Torr to about 760 Torr, or about 200 Torr to about 760 Torr. The flow rate of the reactants may be adjusted, and the flow of the reactants may affect the etch selectivity between the exposed and unexposed regions during development. In some embodiments, the flow rate of the reactants may be about 50 sccm to about 2000 sccm, about 100 sccm to about 2000 sccm, or about 100 sccm to about 1000 sccm, for example, about 500 sccm. At high flow rates, the flow rate of the reactants may be about 1 L to about 10 L. The duration of exposure may be adjusted in the thermal development process. The duration of exposure may depend on how much resist one desires to remove, the developer chemistry, the amount of crosslinking in the resist, and the composition and properties of the resist, among other factors, In some embodiments, the duration of exposure may be from about 5 seconds to about 5 minutes, from about 10 seconds to about 3 minutes, or from about 10 seconds to about 1 minute.

[0080] The thermal development process may expose the photopatterned metal-containing EUV resist to certain halide-containing chemicals in the gas or liquid phase. In some embodiments, the development chemicals include hydrogen halides, hydrogen and halogen gases, boron trichloride, organic halides, acyl halides, carbonyl halides, thionyl halides, or mixtures thereof. Hydrogen halides may include, but are not limited to, HF, HCl, HBr, and HI. For example, the hydrogen halides may be HCl or HBr. Hydrogen and halogen gases may include, but are not limited to, F2, Cl2, Br2, or I2 mixed with hydrogen gas (H2). Boron trichloride (BCl3) may be used in combination with any of the aforementioned hydrogen halides or hydrogen and halogen gases. Organic halides include C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z where x, y, and z are values ​​equal to or greater than 0. Acyl halides can include, but are not limited to, CH3COF, CH3COCl, CH3COBr, CH3COI. Carbonyl halides can include, but are not limited to, COF2, COCl2, COBr2, COI2. Thionyl halides can include, but are not limited to, SOF2, SOCl2, SoBr2, and SOI2. In some embodiments, the halide-containing chemicals can be flowed with or without an inert / carrier gas, such as He, Ne, Ar, Xe, and N2.

[0081] The thermal development process may be performed without plasma. By applying a non-plasma thermal approach, multiple wafers can be batch developed simultaneously in a low-cost thermal vacuum chamber / oven, greatly increasing productivity. However, in some embodiments, the thermal development process may be followed by exposure to plasma. Subsequent exposure to plasma may occur for desorption, descumming, smoothing, or other processing operations.

[0082] In a plasma development process, the photo-patterned metal-containing EUV resist is exposed to a development chemical that includes radicals / ions of one or more gases. The process chamber that processes the semiconductor substrate may be a plasma generation chamber or may be coupled to a plasma generation chamber that is remote from the process chamber. In some embodiments, the dry development may be performed by a remote plasma. The plasma generation chamber may be an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, or a capacitively coupled plasma (CCP) reactor using equipment and techniques known in the art. An electromagnetic field acts on one or more gases to generate a plasma in the plasma generation chamber. The ions and / or radicals from the remote plasma may interact with the photo-patterned metal-containing EUV resist. In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a development chemical line may be coupled to the plasma generation chamber to deliver one or more gases to the plasma generation chamber. The process chamber may include one or more heaters for temperature control, such as a heater coupled to a substrate support in the process chamber for substrate temperature control. In some embodiments, the process chamber interior may be coated with a corrosion resistant film, such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene (PTFE), e.g., Teflon 1M. Such materials may be used in the thermal processes of the present disclosure without risk of removal by plasma exposure.

[0083] In the plasma development process, the photopatterned metal-containing EUV resist is exposed to a remote plasma under conditions optimized for etch selectivity between exposed and unexposed regions. The conditions may be optimized to generate a mild plasma, which may be characterized by high pressure and low power. The chamber pressure may be adjusted, and the chamber pressure may affect the etch selectivity between exposed and unexposed regions during development. In some embodiments, the chamber pressure may be about 5 mTorr or more, or about 15 mTorr or more. In some embodiments, the chamber pressure may be relatively high with high flow rates and no dilution, and the chamber pressure may be about 100 Torr to about 760 Torr, or about 200 Torr to about 760 Torr. The RF power level may be adjusted, and the RF power may affect etch selectivity, roughness, descum processing, and other development characteristics. In some embodiments, the RF power may be about 1000 W or less, about 800 W or less, or about 500 W or less. The temperature may be adjusted, and may affect various aspects of the development, such as etch selectivity. In some embodiments, the temperature may be about -60°C to about 300°C, about 0°C to about 300°C, or about 30°C to about 120°C. The gas flow rate may be adjusted, and the gas flow may affect the etch selectivity between exposed and unexposed areas during development. In some embodiments, the gas flow rate may be about 50 sccm to about 2000 sccm, about 100 sccm to about 2000 sccm, or about 200 sccm to about 1000 sccm, for example, about 500 sccm. The duration of the exposure may be adjusted in the plasma development process. The duration of the exposure may depend on how much resist one wishes to remove, the development chemistry, the amount of crosslinking in the resist, and the composition and properties of the resist, among other factors. In some embodiments, the duration of the exposure may be about 1 second to about 50 minutes, about 3 seconds to about 20 minutes, or about 10 seconds to about 6 minutes.

[0084] The plasma development process may expose the photo-patterned metal-containing EUV resist to radicals of a particular halide-containing gas. In some embodiments, the radicals are generated from a remote plasma source. For example, the plasma development may expose the photo-patterned metal-containing EUV resist to radicals of hydrogen and halide gases generated from a remote plasma source. In some embodiments, the halide-containing gas includes hydrogen halide, hydrogen and halogen gas, boron trichloride, organic halide, acyl halide, carbonyl halide, thionyl halide, or mixtures thereof. The hydrogen halide may include, but is not limited to, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For example, the hydrogen halide may be HCl or HBr. The hydrogen and halogen gas may include, but is not limited to, fluorine gas (F2), chlorine gas (Cl2), bromine gas (Br2), or iodine gas (I2) mixed with hydrogen gas (H2). Organic halides are C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z where x, y, and z are values ​​equal to or greater than 0. Acyl halides can include, but are not limited to, CH3COF, CH3COCl, CH3COBr, and CH3COI. Carbonyl halides can include, but are not limited to, COF2, COCl2, COBr2, and COI2. Thionyl halides can include, but are not limited to, SOF2, SOCl2, SoBr2, and SOI2. In some embodiments, the halide-containing gas may be flowed with or without an inert / carrier gas, such as He, Ne, Ar, Xe, and N2.

[0085] In addition to or instead of plasma activation, activation of one or more gases in the dry development process may occur by photoactivation. In some embodiments, photoactivation may be achieved by exposure to ultraviolet (UV) radiation. For example, the process chamber may include a lamp, such as a UV lamp, configured to generate UV radiation. Exposing one or more gases to UV radiation may generate radicals of one or more gases, which can be used in dry development of the photopatterned metal-containing EUV resist. The one or more gases may be exposed to UV radiation in a manner that does not expose the photopatterned resist to UV radiation. In other words, the photopatterned resist is not visible to the UV lamp. Thus, the UV lamp may be remote from the process chamber or positioned to avoid exposing the photopatterned resist to UV radiation.

[0086] It will be understood that the aforementioned methods of thermal development, plasma development, and light-activated development may be combined together. Such development methods may be applied simultaneously or sequentially. The development method may be applied with a flow of dry development chemicals in liquid or gas phase, the dry development chemicals being of the formula R x Z y where R=B, Al, Si, C, S, SO, and x>0; Z=Cl, H, Br, F, CH4, and y>0. Development can result in positive or negative tone, and R x Z y The chemical species selectively removes either the unexposed or exposed material, leaving the corresponding exposed or unexposed portions as a mask.

[0087] As described above, the etch selectivity during dry development is adjustable by controlling process conditions such as temperature, pressure, gas flow, gas composition, and plasma power, among other adjustable process conditions. By adjusting the etch selectivity in a single step or multiple steps, desired patterned characteristics can be realized. In some embodiments, the etch selectivity during dry development is adjusted over one or more steps that affect the EUV resist profile. More specifically, the amount of taper or re-entrant angle of the EUV resist profile can be controlled by applying development chemistries with different etch selectivities over one or more steps. Descumming, photoresist rework, hardening, smoothing, and cleaning operations can also be adjusted according to the adjustable etch selectivity.

[0088] 2A-2C show schematic cross-sectional views of various processing stages of dry development, according to some embodiments. The examples shown in FIGS. 2A-2C show negative tone dry development. As shown in FIG. 2A, wafer 200 includes substrate 202 and substrate layer 204 to be etched. In some embodiments, substrate layer 204 includes an ashable hard mask, such as spin-on carbon (SoC), or other materials, such as silicon, silicon oxide, silicon nitride, silicon carbide. In some embodiments, substrate layer 204 may be a layer stack disposed on substrate 202. Wafer 200 further includes photo-patterned metal-containing EUV resist film 206. For example, photo-patterned metal-containing EUV resist film 206 may be an organometallic-containing layer disposed on substrate layer 204 to be etched. Photo-patterned metal-containing EUV resist film 206 may have a thickness of about 5 nm to about 50 nm, or about 10 nm to about 30 nm. The photo-patterned metal-containing EUV resist film 206 may be provided in a process chamber after photo-patterning in an EUV scanner and / or after PEB processing, as described above. The photo-patterned metal-containing EUV resist film 206 includes non-EUV exposed regions 206a and EUV exposed regions 206b. As shown in FIG. 2B, the non-EUV exposed regions 206a of the photo-patterned metal-containing EUV resist film 206 may be removed in a dry development process by exposing it to a flow of dry development chemicals without generating a plasma. The dry development chemicals may include halide-containing chemicals, such as hydrogen halide or hydrogen and halogen gases. Removal of the non-EUV exposed regions 206a forms a resist mask 208 after development. The substrate layer 204 to be etched may then be etched using the resist mask 208 to result in the structure shown in FIG. 2C.

[0089] FIG. 3 illustrates an exemplary dry development mechanism of the chemical reaction of HBr with exposed and unexposed portions of an EUV photoresist according to some embodiments. While FIG. 3 illustrates a possible dry development mechanism, it will be understood that the present disclosure is not limited by any particular mechanism, function, theory, or utility. The organometallic oxide film may have a tetrahedrally coordinated structure. The exposed regions have a higher level of Sn-O-Sn crosslinking, resulting in higher density and lower / slower reactivity with HBr or HCl. The unexposed regions are less dense due to the presence of bulky alkyl substituents that prevent the Sn-OH moieties from approaching and condensing. In the unexposed regions, the hydrogen halide more readily protonates the more "basic" and accessible oxygen lone pairs characteristic of the more tetrahedrally coordinated organotin oxide hydroxides. Volatile by-products of RSnX3 (X=Cl or Br) are rapidly generated and removed from the unexposed regions. In Figure 3, HBr selectively protonates the oxygen lone pair to form the volatile by-product R-Sn-Br. Water is also a by-product. Removal of water can increase the reaction rate. When the alkyl group is isopropyl, a typical EUV patterning dose will remove at least two out of every three isopropyl substituents, resulting in the exposed regions condensing after the PEB step to form a denser SnO2-like material that is less reactive with hydrogen halides due to the tin structure more nearly in hexagonal coordination, which makes oxygen atoms less accessible, resulting in a much slower reaction with hydrogen halides. In Figure 3, the exposed regions experience a significant decrease in dry etch rate associated with the loss of isopropyl substituents, allowing condensation into a material with more / most oxygen atoms bonded to three (instead of two) tin atoms, which significantly reduces the reaction rate with HBr or HCl.

[0090] In some cases, residue or scum may remain after development. Residue may result from slower etching components in less homogeneous EUV resist formulations, including those applied by spin-coating techniques. Such scum may contain high concentrations of metals, which may be problematic during subsequent pattern transfer.

[0091] Additionally or alternatively, after development, roughness may form on the sidewalls of etched features in the developed pattern, some of which may be due to stochastic or non-optimal Gaussian distribution of light, which may result in partially or fully exposed material in areas where the resist should remain unexposed.

[0092] In some embodiments, the dry develop may be accompanied by a descum / smoothing operation. In some embodiments, the descumming and smoothing operation may be an inert gas plasma desorption operation. For example, the inert gas plasma desorption operation may be a helium plasma desorption operation. The inert gas plasma desorption operation may be performed after the dry develop or may be repeated in conjunction with the dry develop.

[0093] FIG. 4A shows a schematic cross-sectional view of dry development without application of inert gas plasma, according to some embodiments. The photopatterned metal-containing EUV resist film includes exposed and unexposed regions. As shown in FIG. 4A, metal oxide (e.g., SnO x ) particles or clusters may occupy the unexposed areas. As dry development proceeds, the metal oxide clusters become more concentrated. Metal oxide clusters are generally difficult to remove. Development may be selective to the removal of organic materials. After removal of the unexposed areas, the metal oxide clusters may remain on the substrate surface as scum. Metal oxide clusters remaining on the sidewalls of the exposed areas may lead to roughness.

[0094] FIG. 4B shows a schematic cross-sectional view of a dry development repeated inert gas plasma for descum processing according to some embodiments. The first stage involves dry development to remove a substantial portion of the unexposed regions of the photopatterned metal-containing EUV resist film. The dry development chemistry may include, for example, HBr. The substantial portion may represent at least more than 70% by volume of the unexposed regions, more than 80% by volume of the unexposed regions, or more than 90% by volume of the unexposed regions. Metal oxide clusters concentrate on the surface of the remaining unexposed regions of the EUV resist film. The second stage involves applying an inert gas plasma, such as a helium plasma, at low power and high ion energy for a short period of time. The helium plasma removes the metal oxide clusters. In addition, the helium plasma removes the clusters from the sidewalls and smoothes the sidewalls. The helium plasma treatment may also serve to harden or cure the patterned EUV resist film to form a denser metal oxide such as a hard mask. After the helium plasma treatment, a less selective dry etch step can be used to remove any residue remaining in the unexposed areas of the EUV resist film.

[0095] In some embodiments, dry development may be repeated in conjunction with helium plasma treatment for one or more cycles until the unexposed areas of the EUV resist film are removed. To improve results, helium plasma descumming / smoothing may be repeated in conjunction with dry development, as described above. In this way, for example, most of the organic components in the unexposed areas of the pattern are removed by dry development, and then a short helium plasma operation removes some of the metal concentrated at the surface, providing access to the remaining underlying organic material, which can then be removed in a subsequent dry development operation / cycle. Another cycle of helium plasma may be used to remove any remaining metal, leaving a clean, smooth feature surface. The cycles may continue until all or substantially all of the scum and roughness residues are removed, leaving a clean, smooth feature surface.

[0096] The process conditions for the descumming and smoothing operations may be controlled during or after development. In some embodiments, the reactant flow may be about 50 sccm to about 1000 sccm, about 100 sccm to about 500 sccm, for example, about 500 sccm He. In some embodiments, the temperature may be about -60°C to about 120°C, about -20°C to about 60°C, or about 20°C to about 40°C, for example, about 20°C. In some embodiments, the chamber pressure may be about 1 mTorr to about 300 mTorr, about 5 mTorr to about 100 mTorr, about 5 mTorr to about 20 mTorr, for example, about 10 mTorr. The plasma power may be relatively low with high ion energy. In some embodiments, the plasma power may be about 50W to about 1000W, about 100W to about 500W, or about 100W to about 300W, for example, about 300W. In some embodiments, the wafer bias is about 10V to about 500V, about 50V to about 300V, for example, about 200V. The plasma may be generated using a high RF frequency. In some embodiments, the RF frequency is 13.56 MHz. To avoid excessive exposure to UV radiation during plasma exposure, the duration of exposure to the inert gas plasma may be relatively short. In some embodiments, the duration of exposure is about 0.5 seconds to about 5 seconds, about 1 second to about 3 seconds, for example, about 2 seconds.

[0097] The inert gas plasma treatment for descumming and cleaning of unexposed resist residue may have the side benefit of curing and hardening the exposed resist, thereby enhancing its hardmask function in the subsequent operation of etching the underlying substrate. This resist hardening is achieved by exposing the EUV-exposed resist to UV radiation generated by the inert gas plasma, which may be continued with the bias turned off after descumming / smoothing is completed. If descumming / smoothing is not required or performed, an inert gas plasma cure may be performed instead.

[0098] In some embodiments, inert gas plasma desorption descumming and smoothing may be used in conjunction with the wet development process. Wet development has been shown to have very high selectivity and a well-defined on / off behavior, resulting in the wet development process being unable to remove areas exposed by "stray" EUV photons. After the wet development process, residual residues remain, resulting in scum and increased line edge and width roughness. Interestingly, due to the tunability of the dry development process, where the etch rate and selectivity can be adjusted based on multiple knobs (e.g., time, temperature, pressure, gas / flow), an inert gas plasma and / or dry development can be further applied to descum and smooth the metal-containing resist lines by removing these partially exposed residues.

[0099] FIG. 5 shows a graph comparing the etch rate of exposed and unexposed portions of an EUV photoresist using helium plasma during dry development. The EUV photoresist may be an organotin oxide EUV photoresist. The unexposed portions are etched at a faster rate than the exposed portions. However, as the dry development using HBr progresses, the etch rate decreases. Without being limited by any theory, it is believed that the presence of tin oxide particles / clusters slows the etch rate. By applying helium desorption, more of the unexposed portions of the EUV photoresist may be etched.

[0100] 6A and 6B show SEM images comparing wet and dry development with respect to line collapse. In FIG. 6A, photopatterned metal-containing EUV resist is exposed to wet development chemistry such as organic solvent. After a liquid drying step, some pattern line collapse is observed. This may be due in part to the action of surface tension due to capillary forces. In FIG. 6B, photopatterned metal-containing EUV resist is exposed to dry development chemistry such as hydrogen halide gas. Dry development by gas phase reaction without a liquid drying step prevents pattern line collapse or delamination.

[0101] 7A and 7B show SEM images comparing wet development with dry development in terms of roughness and critical dimension (CD) control. In 7A and 7B, an organotin oxide film is deposited on an ashable hard mask. The organotin oxide film was exposed to EUV at various doses and various focal depths. The organotin oxide film was wet developed in 7A and dry developed in 7B. The organotin oxide resist mask had a square profile after wet development, while the organotin oxide resist mask had a tapered profile after dry development. Line bridging was observed after pattern transfer in wet development, but not in dry development. Line collapse and wiggling were observed at smaller line widths or lower doses due to surface tension during solvent drying after wet development. No line collapse or wiggling occurred at narrower line widths or lower doses after dry development. A larger process window is available in dry development, over a wider dose and focus range.

[0102] FIG. 8 shows SEM images comparing wet development and dry development with respect to scum after opening the hard mask. As shown in FIG. 8, more scum is observed after wet development compared to dry development. Without being limited by any theory, dry development prevents the formation of scum by using gas chemistries that do not contain oxygen or moisture oxidation sources, which prevent metal oxide bridging of unexposed EUV resist. The scum resembles exposed EUV resist with metal oxide bridging. In FIG. 8, descumming and smoothing operations can be performed after wet or dry development.

[0103] 9A and 9B show graphs illustrating the effect of a second post-exposure bake operation on the selectivity of dry development for various pressures and temperatures. As shown in FIG. 9A, the second post-exposure bake shows improved etch selectivity. As shown in FIG. 9B, during dry development, the etch selectivity improves with lower temperatures. In addition, during dry development, the etch selectivity improves with lower pressures.

[0104] Figure 10 shows SEM images depicting the effect of pressure on the EUV resist profile. In the case of dry development, pressure changes affect the EUV resist profile. In general, higher pressure allows for a higher etch rate. However, lower pressure demonstrated an improvement in the EUV resist profile. Lowering the pressure in Figure 10 resulted in a straighter EUV resist profile.

[0105] 11A and 11B show SEM images of EUV resist at different line / space pitches and different thicknesses. EUV resist masks with 32 nm pitch and 26 nm pitch were developed. The film thickness before development was 15 nm to 40 nm. For the 32 nm pitch, the EUV resist mask thickness ranged from 7.8 nm to 22.5 nm after development. No wiggling was observed. For the 26 nm pitch, the EUV resist mask thickness after development ranged from 7.9 nm to 22.2 nm. Due to undercutting of the bottom of the resist, some wiggling was observed when the film thickness was 30 nm or more.

[0106] Device The apparatus of the present disclosure is configured to develop EUV resist. The apparatus may be configured to perform other processing operations such as deposition, bevel and backside cleaning, post-apply bake, EUV scan, post-exposure bake, photoresist rework, descum, smoothing, curing, and other operations. In some embodiments, the apparatus is configured to perform all dry operations. In some embodiments, the apparatus is configured to perform all wet operations. In some embodiments, the apparatus is configured to perform a combination of wet and dry operations. The apparatus may include a single wafer chamber or may include multiple stations in the same process chamber. When there are multiple stations in the same process chamber, various processing operations as described in this disclosure may be performed at different stations in the same process chamber. For example, a PEB thermal treatment may be performed in one station and development may be performed in another station.

[0107] An apparatus configured for developing an EUV resist includes a process chamber having a substrate support. The apparatus may include a vacuum line coupled to the process chamber for pressure control and a developer chemical line coupled to the process chamber for delivering a developer chemical. In some embodiments, the developer chemical comprises a halide-containing gas or a radical of a halide-containing gas. In some embodiments, the process chamber is a plasma generation chamber or is coupled to a plasma generation chamber that functions as a remote plasma source. The plasma generation chamber may be an ICP, TCP, or CCP reactor. The apparatus may include one or more heaters for temperature control. Such heaters may be provided in the process chamber and / or in the substrate support.

[0108] In some embodiments, the process chamber interior is coated with a corrosion resistant film, such as a polymer or inorganic coating. In one example, the process chamber interior is coated with anodized alumina. In another example, the process chamber interior is coated with yttrium oxide (Y2O3).

[0109] In some embodiments, the process chamber is made of an inexpensive material such as plastic. The process chamber does not necessarily need to be made of metal or ceramic. The plastic material may be sufficient to withstand the halide-containing chemicals during development. Vacuum lines and / or development chemical lines may be coupled to the plastic chamber.

[0110] In some embodiments, the substrate support may be used to process a substrate using a temperature distribution having radial and azimuthal components. The substrate support may include multiple independently controllable temperature control zones arranged in close proximity to the substrate position above the temperature control zones. This allows one or more heaters in the substrate support to more precisely and locally control the temperature. The temperature control zones may be arranged in a predetermined pattern, such as a rectangular grid, a hexagonal grid, or other suitable pattern to generate a desired temperature profile. In some embodiments, the temperature control zones may be spatially arranged in the electrostatic chuck to correct for azimuthal or local CD non-uniformity.

[0111] In some embodiments, the apparatus may further include a showerhead for delivering one or more gases into the process chamber. In some embodiments, the showerhead may provide multiple separate gases to the reaction region while keeping the gases largely separate within the showerhead. The showerhead may include multiple plenum volumes, which allows for separation of precursor gases, carrier gases, developer gases, and cleaning gases, among other chemistries.

[0112] Removing water and moisture from the process chamber may speed up the reaction of the photopatterned metal-containing EUV resist with the developing chemicals. In some embodiments, a cold trap may be coupled to the process chamber to remove by-product water vapor. The cold trap may condense the by-product water vapor into a liquid or solid form.

[0113] In some embodiments, the apparatus may further include a UV source, such as a UV lamp, and / or an IR source, such as an IR lamp, for resist hardening and dehalogenation. The UV source and / or the IR source may provide exposure to radiation to cure the EUV resist. Additionally or alternatively, the UV source may assist in photoactivation of the development chemicals. Additionally or alternatively, the UV source may assist in halogen removal. Halogen residues may form on the semiconductor substrate or on the chamber surfaces, which may be removed by UV exposure.

[0114] FIG. 12 shows a schematic diagram of an embodiment of a process station 1200 having a process chamber body 1202 for maintaining a low pressure environment suitable for the described dry development, cleaning, rework, descum, and smoothing embodiments. Multiple process stations 1200 may be included in a common low pressure process tool environment. For example, FIG. 13 shows an embodiment of a multi-station processing tool 1300, such as a VECTOR® processing tool available from Lam Research Corporation (Fremont, Calif.). In some embodiments, one or more hardware parameters of the process station 1200, including parameters discussed in detail below, may be programmatically adjusted by one or more computer controllers 1250.

[0115] The process stations may be configured as modules within a cluster tool. Figure 15 illustrates a semiconductor processing cluster tool architecture having a vacuum integrated deposition and patterning module suitable for implementing the embodiments described herein. Such a cluster processing tool architecture may include a resist deposition module, a resist exposure (EUV scanner) module, a resist development module, and an etch module, as described above and further below with reference to Figures 14 and 15.

[0116] In some embodiments, certain processing functions, such as dry development and etching, may be performed sequentially in the same module, and embodiments of the present disclosure are directed to methods and apparatus for, following photopatterning in an EUV scanner, placing a wafer including a photopatterned EUV resist thin film layer disposed on a layer or layer stack to be etched in a dry development / etch chamber, dry developing the photopatterned EUV resist thin film layer, and then etching the underlying film using the patterned EUV resist as a mask as described herein.

[0117] Returning to Figure 12, the process station 1200 is in fluid communication with a reactant delivery system 1201a for delivering process gases to a distribution showerhead 1206. The reactant delivery system 1201a optionally includes a mixing vessel 1204 for mixing and / or conditioning process gases for delivery to the showerhead 1206. One or more mixing vessel inlet valves 1220 may control the introduction of process gases to the mixing vessel 1204. If plasma exposure is used, the plasma may also be delivered to the showerhead 1206 or may be generated in the process station 1200. As discussed above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0118] 12 includes an optional vaporization point 1203 for vaporizing a liquid reactant provided to the mixing vessel 1204. In some embodiments, a liquid flow controller (LFC) may be provided upstream of the vaporization point 1203 to control the mass flow rate of the liquid for vaporization and delivery to the process station 1200. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. A plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM.

[0119] The showerhead 1206 distributes process gases toward the substrate 1212. In the embodiment depicted in Figure 12, the substrate 1212 is shown positioned below the showerhead 1206 and resting on a pedestal 1208. The showerhead 1206 may have any suitable shape and may have any suitable number and configuration of ports for distributing process gases to the substrate 1212.

[0120] In some embodiments, the pedestal 1208 may be raised or lowered to expose the substrate 1212 to the volume between the substrate 1212 and the showerhead 1206. It will be appreciated that in some embodiments, the height of the pedestal may be programmatically adjusted by a suitable computer controller 1250. In some embodiments, the showerhead 1206 may have multiple plenum volumes with multiple temperature controls.

[0121] In some embodiments, the pedestal 1208 may be temperature controlled via a heater 1210. In some embodiments, the pedestal 1208 may be heated to a temperature greater than 0° C. up to or greater than 300° C., e.g., between 50° C. and 120° C., e.g., between about 65° C. and 80° C., during non-plasma thermal exposure of the photopatterned resist to a hydrogen halide dry developing chemistry, such as HBr or HCl, as described in the disclosed embodiments. In some embodiments, the heater 1210 of the pedestal 1208 may include multiple independently controllable temperature control zones.

[0122] Additionally, in some embodiments, pressure control for the process station 1200 may be provided by a butterfly valve 1218. As shown in the embodiment of FIG. 12, the butterfly valve 1218 throttles the vacuum supplied by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the process station 1200 may also be adjusted by varying the flow rate of one or more gases introduced to the process station 1200.

[0123] In some embodiments, the position of the showerhead 1206 relative to the pedestal 1208 may be adjusted to change the volume between the substrate 1212 and the showerhead 1206. Further, it will be understood that the vertical position of the pedestal 1208 and / or the showerhead 1206 may be altered by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 1208 may include a rotation axis to rotate the orientation of the substrate 1212. It will be understood that in some embodiments, one or more of these exemplary adjustments may be implemented programmatically by one or more suitable computer controllers 1250.

[0124] When a plasma is used, for example in a mild plasma-based dry development embodiment and / or an etching operation performed in the same chamber, the showerhead 1206 and pedestal 1208 are in electrical communication with a radio frequency (RF) power source 1214 and matching network 1216 to power the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 1214 and matching network 1216 may be operated at any suitable power to form a plasma having a desired composition of radical species. An example of a suitable power is up to about 500 W.

[0125] In some embodiments, instructions for the controller 1250 may be provided via input / output control (IOC) sequence instructions. In one example, instructions for setting conditions for a process phase may be included in a corresponding recipe phase of a process recipe. In some cases, recipe steps may be arranged in sequence such that all instructions for a process step are executed simultaneously with that process step. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe step. For example, a recipe step may include instructions for setting a flow rate of a dry developing chemical reactant gas, such as HBr or HCl, and a time delay instruction for the recipe step. In some embodiments, the controller 1250 may include any of the features described below with respect to the system controller 1350 of FIG. 13.

[0126] As mentioned above, one or more process stations may be included in a multi-station processing tool. FIG. 13 shows a schematic diagram of an embodiment of a multi-station processing tool 1300 with an inbound load lock 1302 and an outbound load lock 1304, either or both of which may include a remote plasma source. A robot 1306 at atmospheric pressure is configured to move a wafer from a cassette loaded through a pod 1308 into the inbound load lock 1302 through an atmospheric port 1310. The wafer is placed by the robot 1306 on a pedestal 1312 in the inbound load lock 1302, the atmospheric port 1310 is closed, and the load lock is pumped down. If the inbound load lock 1302 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment to treat the silicon nitride surface in the load lock before being introduced into the processing chamber 1314. Additionally, the wafer may also be heated in the inbound load lock 1302, for example, to remove moisture and adsorbed gases. The chamber transfer port 1316 to the processing chamber 1314 is then opened and another robot (not shown) places the wafer into the reactor on the pedestal of the first station shown in the reactor for processing. Although the embodiment shown in Figure 13 includes a load lock, it will be understood that in some embodiments direct entry of the wafer into the process stations may be provided.

[0127] The illustrated processing chamber 1314 includes four process stations, numbered 1 through 4 in the embodiment shown in FIG. 13. Each station has a heated pedestal (labeled 1318 for station 1) and a gas line inlet. It will be understood that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, the process stations may be switchable between a dry development mode and an etch process mode. Additionally or alternatively, in some embodiments, the processing chamber 1314 may include one or more matched pairs of dry development and etch process stations. Although the illustrated processing chamber 1314 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0128] FIG. 13 illustrates an embodiment of a wafer handling system 1390 for transferring wafers within the processing chamber 1314. In some embodiments, the wafer processing system 1390 may transfer wafers between various process stations and / or between process stations and load locks. It will be understood that any suitable wafer handling system may be employed. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 13 also illustrates an embodiment of a system controller 1350 used to control process conditions and hardware states of the process tool 1300. The system controller 1350 may include one or more memory devices 1356, one or more mass storage devices 1354, and one or more processors 1352. The processor 1352 may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0129] In some embodiments, the system controller 1350 controls all of the operations of the process tool 1300. The system controller 1350 executes system control software 1358, which is stored on the mass storage device 1354, loaded into the memory device 1356, and executed by the processor 1352. Alternatively, the control logic may be hard-coded into the controller 1350. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), and the like may be used for these purposes. In the following description, wherever "software" or "code" is used, functionally equivalent hard-coded logic may be used instead. The system control software 1358 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process being performed by the process tool 1300. The system control software 1358 may be configured in any suitable manner. For example, subroutines or control objects for the various process tool components may be written to control the operation of the process tool components used to implement the various process tool processes. The system control software 1358 may be coded in any suitable computer readable programming language.

[0130] In some embodiments, the system control software 1358 may include input / output control (IOC) sequence instructions for controlling the various parameters mentioned above. In some embodiments, other computer software and / or programs stored on the mass storage device 1354 and / or memory device 1356 associated with the system controller 1350 may be used. Examples of programs or portions of programs for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0131] A substrate alignment program may include program code for the process tool components used to load the substrate onto the pedestal 1318 and control the spacing between the substrate and other parts of the process tool 1300 .

[0132] The process gas control program may include code for controlling the composition and flow rate of a halide-containing gas (e.g., HBr or HCl gas as described herein), and optionally, code for flowing gas into one or more process stations prior to deposition to stabilize the pressure in the process station. The pressure control program may include code for controlling the pressure in the process station, for example, by adjusting a throttle valve in the exhaust system of the process station, the flow of gas into the process station.

[0133] The heater control program may include code for controlling the current to a heating unit used to heat the substrate, or alternatively, the heater control program may control the supply of a heat transfer gas (e.g., helium) to the substrate.

[0134] A plasma control program may include code for setting RF power levels applied to process electrodes in one or more process stations according to embodiments herein.

[0135] The pressure control program may include code for maintaining pressure in the reaction chamber according to embodiments herein.

[0136] In some embodiments, there may be a user interface associated with the system controller 1350. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and a user input device, e.g., a pointing device, a keyboard, a touch screen, a microphone.

[0137] In some embodiments, the parameters adjusted by the system controller 1350 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (e.g., RF bias power levels), etc. These parameters may be provided to a user in the form of a recipe, which may be entered using a user interface.

[0138] Signals for monitoring the process may be provided from various process tool sensors by analog and / or digital input connections of the system controller 1350. Signals for controlling the process may be output to analog and digital output connections of the process tool 1300. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0139] The system controller 1350 may provide program instructions for carrying out the deposition process described above. The program instructions may control various process parameters such as DC power levels, RF bias power levels, pressure, temperature, etc. The instructions may control parameters operating the development and / or etching processes according to various embodiments described herein.

[0140] The system controller 1350 will typically include one or more memory devices and one or more processors configured to execute instructions such that the apparatus performs methods according to the disclosed embodiments. Machine-readable media containing instructions for controlling process operations according to the disclosed embodiments may be coupled to the system controller 1350.

[0141] In some embodiments, the system controller 1350 is part of a system, which may be part of the examples above. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics to control pre-, during, and post-processing operations of the semiconductor wafer or substrate. The electronics may be referred to as a "controller" that may control various components or subparts of the system(s). The system controller 1350 may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operation settings, wafer transfer to and from tools and other transfer tools and / or load locks connected or interfaced with the particular system, depending on the processing conditions and / or type of system.

[0142] Broadly speaking, the system controller 1350 may be defined as electronics having various integrated circuits, logic, memory, and / or software to receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions communicated to the system controller 1350 in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, the operational parameters may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0143] In some embodiments, the system controller 1350 may be part of or coupled to a computer that is embedded in or coupled to the system, or networked to the system, or a combination thereof. For example, the system controller 1350 may be in the "cloud" or all or part of a fab host computer system, thereby enabling remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance indicators from multiple manufacturing operations, modify parameters of a current process, set up processing steps following a current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the system controller 1350 receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that the system controller 1350 is configured to interface with or control. Thus, as described above, the system controller 1350 may be distributed, for example, by including one or more individual controllers that are networked together and directed to a common purpose, such as the process or control described herein. An example of a distributed controller for such a purpose may be one or more integrated circuits on the chamber in communication with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control the process at the chamber.

[0144] Without being limited thereto, exemplary systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a development chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0145] As described above, depending on the process steps being performed by the tool, the system controller 1350 may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from tool locations and / or load ports in the semiconductor manufacturing factory to transport wafer containers in and out of the tool locations.

[0146] In certain embodiments, an inductively coupled plasma (ICP) reactor is described herein, which may be suitable for etching operations suitable for implementing some embodiments. Although an ICP reactor is described herein, it should be understood that in some embodiments, a capacitively coupled plasma reactor may also be used.

[0147] 14 shows a schematic cross-sectional view of an inductively coupled plasma apparatus 1400 suitable for implementing certain embodiments or aspects of embodiments, such as dry developing and / or etching, an example of which is the Kiyo® Reactor manufactured by Lam Research Corp. (Fremont, Calif.) In other embodiments, other tools or tool types capable of performing the dry developing and / or etching processes described herein may be used for implementation.

[0148] The inductively coupled plasma apparatus 1400 includes an overall process chamber 1424 structurally defined by a chamber wall 1401 and a window 1411. The chamber wall 1401 may be fabricated from stainless steel, aluminum, or plastic. The window 1411 may be fabricated from quartz or other dielectric material. An optional internal plasma grid 1450 divides the overall process chamber into an upper sub-chamber 1402 and a lower sub-chamber 1403. In most embodiments, the plasma grid 1450 may be removed to utilize the chamber space created by the sub-chambers 1402 and 1403. A chuck 1417 is located within the lower sub-chamber 1403 near a bottom inner surface. The chuck 1417 is configured to receive and hold a semiconductor wafer 1419 on which etching and deposition processes are performed. The chuck 1417 may be an electrostatic chuck for supporting the wafer 1419 when present. In some embodiments, an edge ring (not shown) surrounds the chuck 1417 and has a top surface that is approximately flush with the top surface of the wafer 1419 when the wafer 1419 is on the chuck 1417. The chuck 1417 also includes an electrostatic electrode for chucking and dechucking the wafer 1419. For this purpose, a filter and DC clamp power supply (not shown) may be provided. Other control systems may also be provided for lifting the wafer 1419 from the chuck 1417. The chuck 1417 may be charged using an RF power supply 1423. The RF power supply 1423 is connected to a matching circuit 1421 via a connection 1427. The matching circuit 1421 is connected to the chuck 1417 via a connection 1425. In this manner, the RF power supply 1423 is connected to the chuck 1417. In various embodiments, the bias power of the electrostatic chuck may be set to about 50V or may be set to a different bias power depending on the process being performed according to the disclosed embodiments. For example, the bias power may be from about 20Vb to about 100V, or from about 30V to about 150V.

[0149] The elements for plasma generation include a coil 1433 located over the window 1411. In some embodiments, no coil is used in the disclosed embodiments. The coil 1433 is fabricated from a conductive material and includes at least one complete turn. The example coil 1433 shown in FIG. 14 includes three turns. A cross section of the coil 1433 is symbolically shown, with the coil having an "X" rotating and extending into the page and the coil having a "·" rotating and extending out of the page. The elements for plasma generation also include an RF power source 541 configured to provide RF power to the coil 1433. Generally, the RF power source 1441 is connected to a matching circuit 1439 via a connection 1445. The matching circuit 1439 is connected to the coil 1433 via a connection 1443. In this manner, the RF power source 1441 is connected to the coil 1433. An optional Faraday shield 1449a is located between the coil 1433 and the window 1411. The Faraday shield 1449a may be maintained in a spaced relationship relative to the coil 1433. In some embodiments, the Faraday shield 1449a is disposed directly above the window 1411. In some embodiments, the Faraday shield 1449b is between the window 1411 and the chuck 1417. In some embodiments, the Faraday shield 1449b is not maintained in a spaced relationship relative to the coil 1433. For example, the Faraday shield 1449b may be directly below the window 1411 with no gap. The coil 1433, the Faraday shield 1449a, and the window 1411 are each configured substantially parallel to one another. The Faraday shield 1449a may prevent metals or other chemical species from depositing on the window 1411 of the process chamber 1424.

[0150] Process gases may flow into the process chamber through one or more main gas inlets 1460 and / or through one or more side gas inlets 1470 located in the upper subchamber 1402. Similarly, similar gas inlets, not explicitly shown, may be used to supply process gases to the capacitively coupled plasma processing chamber. A vacuum pump, e.g., a one or two stage mechanical dry pump and / or turbomolecular pump 1440, may be used to draw process gases from the process chamber 1424 and maintain pressure therein. For example, the vacuum pump may be used to evacuate the lower subchamber 1403 during an ALD purge operation. A valve controlled conduit may be used to fluidly connect the vacuum pump to the process chamber 1424 to selectively control application of the vacuum environment provided by the vacuum pump. This may be done using a closed loop controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown), during plasma processing operations. Similarly, a vacuum pump and a valve controlled fluid connection to the capacitively coupled plasma processing chamber may also be used.

[0151] During operation of the apparatus 1400, one or more process gases may be supplied through the gas inlets 1460 and / or 1470. In certain embodiments, process gases may be supplied only through the main gas inlet 1460 or only through the side gas inlet 1470. In some cases, the gas inlets shown in the figure may be replaced with more complex gas inlets, such as one or more showerheads. The Faraday shield 1449a and / or the optional grid 1450 may include internal channels and holes that allow process gases to be supplied to the process chamber 1424. Either or both of the Faraday shield 1449a and the optional grid 1450 may function as a showerhead to supply process gases. In some embodiments, a liquid vaporization and delivery system may be located upstream of the process chamber 1424, such that once a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process chamber 1424 via the gas inlets 1460 and / or 1470.

[0152] Radio frequency power is supplied from an RF power supply 1441 to the coil 1433, causing an RF current to flow through the coil 1433. The RF current flowing through the coil 1433 creates an electromagnetic field around the coil 1433. The electromagnetic field creates an induced current inside the upper subchamber 1402. Physical and chemical interactions of the various ions and radicals created with the wafer 1419 etch features in the wafer 1419 and selectively deposit layers on the wafer 1419.

[0153] When a plasma grid 1450 is used such that both an upper subchamber 1402 and a lower subchamber 1403 are present, induced currents act on the gas present in the upper subchamber 1402 to generate an electron-ion plasma in the upper subchamber 1402. The optional internal plasma grid 1450 limits the amount of hot electrons in the lower subchamber 1403. In some embodiments, the apparatus 1400 is designed and operated such that the plasma present in the lower subchamber 1403 is an ion-ion plasma.

[0154] Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, but the ion-ion plasma will have a greater ratio of negative ions to positive ions. Volatile etch and / or deposition by-products may be removed from the lower sub-chamber 1403 via port 1422. The chuck 1417 disclosed herein may operate at elevated temperatures ranging from about 10° C. to about 250° C. The temperature will depend on the process operation and the specific recipe.

[0155] If the tool 1400 is installed in a clean room or manufacturing facility, the tool 1400 may be coupled to the facility (not shown). The facility includes plumbing to provide process gases, vacuum, temperature control, and environmental particle control. If the tool 1400 is installed in a target manufacturing facility, these facilities are coupled to the tool 1400. Additionally, the tool 1400 may be coupled to a transfer chamber to allow robotics to move semiconductor wafers in and out of the tool 1400 using typical automation equipment.

[0156] In some embodiments, a system controller 1430 (which may include one or more physical or logical controllers) controls some or all of the operation of the process chamber 1424. The system controller 1430 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 1400 includes a switching system for controlling flow rates and durations when the disclosed embodiments are implemented. In some embodiments, the apparatus 1400 may have a switching time of up to about 500 milliseconds, or up to about 750 milliseconds. The switching time may depend on the flow chemistry, the selected recipe, the reactor architecture, and other factors.

[0157] In some embodiments, the system controller 1430 is part of a system, which may be part of the examples above. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling pre-, during, and post-processing operations of semiconductor wafers or substrates. The electronics may be integrated with a system controller 1430, which may control various components or subparts of the system. The system controller may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, position and operation settings, wafer transfer to and from tools and other transfer tools and / or load locks connected or interfaced with the particular system, depending on the processing parameters and / or type of system.

[0158] Broadly speaking, the system controller 1430 may be defined as electronics having various integrated circuits, logic, memory, and / or software to receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, the operational parameters may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0159] In some embodiments, the system controller 1430 may be part of or coupled to a computer that is embedded in or coupled to the system, or networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or all or part of a fab host computer system, which may enable remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance indicators from multiple manufacturing operations, modify parameters of a current process, set up processing steps following a current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the system controller 1430 receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the system controller 1430 may be distributed, for example, by including one or more individual controllers that are networked together and directed to a common purpose, such as the process or control described herein. An example of a distributed controller for such a purpose may be one or more integrated circuits on the chamber in communication with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control the process at the chamber.

[0160] Without being limited thereto, exemplary systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a dry development chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0161] As described above, depending on the process steps being performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from tool locations and / or load ports in a semiconductor manufacturing factory to transport wafer containers in and out of the tool locations.

[0162] EUVL patterning may be performed using any suitable tool, often referred to as a scanner, such as the TWINSCAN NXE:3300B™ platform provided by ASML (Veldhoven, NL). The EUVL patterning tool may be a standalone device from which substrates enter and exit for deposition and etching, as described herein. Or, as described below, the EUVL patterning tool may be a module of a larger multi-component tool. FIG. 15 shows a semiconductor process cluster tool architecture with vacuum integrated deposition, EUV patterning, and dry develop / etch modules interfaced with a vacuum transfer module, suitable for implementing the processes described herein. The processes may be performed without such vacuum integration equipment, although such equipment may be advantageous in some embodiments.

[0163] FIG. 15 illustrates a semiconductor process cluster tool architecture with vacuum integrated deposition and patterning modules interfaced with a vacuum transfer module suitable for implementing the processes described herein. The configuration of transfer modules for "transferring" wafers between multiple containment facilities and processing modules may be referred to as a "cluster tool architecture" system. The deposition and patterning modules are vacuum integrated according to the requirements of the particular process. Other modules, such as for etching, may also be included in the cluster.

[0164] A vacuum transport module (VTM) 1538 interfaces with four processing modules 1520a-1520d, which may be individually optimized to perform various manufacturing processes. By way of example, the processing modules 1520a-1520d may be implemented to perform deposition, evaporation, ELD, dry develop, etch, strip, and / or other semiconductor processes. For example, module 1520a may be an ALD reactor, which may be operated to perform the thermal atomic layer deposition described herein non-plasma, such as a Vector tool available from Lam Research Corporation (Fremont, Calif.), and module 1520b may be a PECVD tool, such as a Lam Vector®. It should be understood that the drawings are not necessarily drawn to scale.

[0165] Airlocks 1542 and 1546, also called loadlocks or transfer modules, interface with the VTM 1538 and the patterning module 1540. For example, as mentioned above, a suitable patterning module may be a TWINSCAN NXE:3300B™ platform supplied by ASML (Veldhoven, NL). This tool architecture allows workpieces such as semiconductor substrates or wafers to be transferred under vacuum so that they do not react prior to exposure. The fact that EUVL also requires significantly lower pressures, given the strong optical absorption of incident photons by ambient gases such as H2O, O2, etc., facilitates the integration of the deposition module with the lithography tool.

[0166] As mentioned above, this integrated architecture is only one anticipated embodiment of a tool for implementing the described process. This process may also be implemented using a conventional standalone EUVL scanner and a deposition reactor such as a Lam Vector tool, either standalone, or integrated as a module into other tools such as etch, strip, etc. (e.g., Lam Kiyo or Gamma tools) in a cluster architecture, such as described with reference to FIG. 15, but without an integrated patterning module.

[0167] Airlock 1542 may be an "outward" load lock, referring to the transfer of substrates from the VTM 1538 serving deposition module 1520a to the patterning module 1540, and airlock 1546 may be an "inward" load lock, referring to the transfer of substrates from the patterning module 1540 back to the VTM 1538. The inward load lock 1546 may also provide an interface to the outside of the tool for the transfer of substrates. Each process module has a facet that interfaces the module to the VTM 1538. For example, deposition process module 1520a has facet 1536. Inside each facet, sensors are used to detect the passage of wafer 1526 as it moves between the respective stations, e.g., sensors 1-18 as shown. Patterning module 1540, as well as airlocks 1542 and 1546, may similarly include additional facets and sensors (not shown).

[0168] A main VTM robot 1522 transfers wafers 1526 between modules including airlocks 1542 and 1546. In one embodiment, the robot 1522 has one arm, and in another embodiment, the robot 1522 has two arms, each arm having an end effector 1524 to lift wafers such as wafer 1526 for transfer. A front-end robot 1544 is used to transfer wafers 1526 from the outward airlock 1542 to the patterning module 1540 and from the patterning module 1540 to the inward airlock 1546. The front-end robot 1544 may also transfer wafers 1526 between the inward loadlock and the exterior of the tool for substrate transfer. The inward airlock module 1546 has the ability to match environments between atmosphere and vacuum so that wafers 1526 can be moved between the two pressure environments without damage.

[0169] It should be noted that EUVL tools typically operate at a higher vacuum than deposition tools. In this case, it may be desirable to increase the vacuum of the substrate environment during transfer between the deposition tool and the EUVL tool so that the substrate can be degassed before entering the patterning tool. The outward airlock 1542 may provide this function by holding the transferred wafer at a lower pressure, i.e., below the pressure in the patterning module 1540, for a period of time and evacuating any exhaust gases so that the optics of the patterning tool 1540 are not contaminated by exhaust gases from the substrate. The preferred pressure of the outward airlock for exhaust gases is 1E-8 Torr or less.

[0170] In some embodiments, a system controller 1550 (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and / or its separate modules. It should be noted that the controller may be local to the cluster architecture, or may be located outside the cluster architecture on the manufacturing floor, or may be located remotely and connected to the cluster architecture via a network. The system controller 1550 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other similar components. Instructions that implement the appropriate control operations are executed by the processor. These instructions may be stored in a memory device associated with the controller, or the instructions may be provided over a network. In certain embodiments, the system controller executes system control software.

[0171] The system control software may include instructions that control the timing and / or magnitude of application of any aspect of a tool or module operation. The system control software may be configured in any suitable manner. For example, subroutines or control objects for various process tool components may be written to control the operations of the process tool components necessary to perform the various process tool processes. The system control software may be coded in any suitable computer readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequence instructions that control the various parameters described above. For example, each step of a semiconductor manufacturing process may include one or more instructions that are executed by the system controller. Instructions that set process conditions for condensation, deposition, evaporation, patterning, and / or etching steps may be included in the corresponding recipe steps, for example.

[0172] In various embodiments, an apparatus for forming a negative tone mask is provided. The apparatus may include a process chamber for patterning, deposition, and etching, and a controller including instructions for forming a negative tone mask. The instructions may include code for patterning features in a chemically amplified (CAR) resist on a semiconductor substrate in the process chamber with EUV exposure to expose a surface of the substrate, developing the photopatterned resist, and etching an underlying layer or stack of layers using the patterned resist as a mask. The development may be performed using a halide-containing chemistry.

[0173] It should be noted that the computer controlling the movement of the wafers can be local to the cluster architecture, or can be located outside the cluster architecture on the manufacturing floor, or can be located remotely and connected to the cluster architecture via a network. A controller such as that described above with respect to any of Figures 12, 13, or 14 may be implemented using the tool of Figure 15.

[0174] conclusion For example, a process and apparatus are disclosed for dry development of metal and / or metal oxide photoresists to form patterning masks in connection with EUV patterning.

[0175] It is understood that the examples and embodiments described herein are for illustrative purposes only, and in light thereof, various modifications or changes will be suggested to those skilled in the art. Various details have been omitted for clarity, but various design alternatives may be realized. Therefore, the present examples should be considered as illustrative and not restrictive, and the present disclosure is not limited to the details described herein, and may be modified within the scope of the present disclosure. The present disclosure includes the following application examples: [Application example 1] 1. A method for processing a semiconductor substrate, comprising: providing a photopatterned metal-containing resist on a substrate layer of a semiconductor substrate in a process chamber; and developing the photopatterned metal-containing resist by selectively removing portions of the resist by exposure to a halide-containing developer chemistry to form a resist mask. [Application example 2] The method according to application example 1, wherein the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist. [Application example 3] The method according to Application Example 2, wherein developing the photopatterned metal-containing EUV resist includes selectively removing non-EUV exposed portions of the EUV resist relative to EUV exposed portions with the developing chemical to form the resist mask. [Application example 4] The method according to Application Example 3, The method further comprises non-selectively removing the EUV unexposed and the EUV exposed portions of the photopatterned metal-containing resist without removing the substrate layer. [Application example 5] The method according to application example 1, wherein the developing chemicals include hydrogen halide, hydrogen gas and halogen gas, organic halide, acyl halide, carbonyl halide, thionyl halide, or mixtures thereof. [Application Example 6] The method according to application example 5, wherein the developing chemicals include hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), or hydrogen iodide (HI). [Application Example 7] The method according to application example 5, wherein the developing chemical is hydrogen gas (H 2 ) and fluorine gas (F 2 ), chlorine gas (Cl 2 ), bromine gas (Br 2 ), or iodine gas (I 2 ). [Application Example 8] The method according to application example 1, wherein the halide is flowed into the process chamber with a carrier gas, and the carrier gas is selected from the group consisting of helium (He), neon (Ne), argon (Ar), xenon (Xe), and nitrogen (N 2 ). [Application Example 9] The method of application example 1, wherein developing the photo-patterned metal-containing resist by exposure to a developing chemical comprises dry developing the photo-patterned metal-containing resist by exposure to a dry developing chemical. [Example 10] The method according to application example 9, wherein dry developing the photopatterned metal-containing resist comprises applying a remote plasma containing the halide radicals to the resist. [Application Example 11] The method according to application example 9, wherein dry developing the photopatterned metal-containing resist comprises exposing the photopatterned metal-containing resist to at least the halide in a thermal process without using plasma. [Application Example 12] 10. The method of claim 9, wherein dry developing the photopatterned metal-containing resist is performed at a temperature of about -60°C to about 120°C, a chamber pressure of 0.1 mTorr to about 760 Torr, and a gas flow rate of the halide of 100 sccm to 2000 sccm, and an etch selectivity of the resist mask is adjustable based at least in part on the temperature, the chamber pressure, the gas flow rate, or a combination thereof. [Application Example 13] The method according to Application Example 12, wherein the temperature is about -20°C to about 20°C. [Example 14] 13. The method of claim 12, wherein a profile of the resist mask is controllable based at least in part on the temperature, the chamber pressure, the gas flow rate, or a combination thereof. [Example 15] The method according to any one of Application Examples 1 to 14, wherein the photopatterned metal-containing resist is an organometallic oxide thin film or an organometallic-containing thin film. [Example 16] The method of claim 15, wherein the photopatterned metal-containing resist comprises an organotin oxide. [Application Example 17] 15. The method according to any one of Application Examples 1 to 14, wherein the photopatterned metal-containing resist comprises an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. [Example 18] The method according to any one of Application Examples 1 to 14, wherein providing the photopatterned metal-containing resist comprises vapor-depositing a metal-containing resist film on the substrate layer. [Example 19] The method according to any one of Application Examples 1 to 14, wherein providing the photopatterned metal-containing resist comprises spin-coating a metal-containing resist film onto the substrate layer. [Example 20] The method according to any one of Application Examples 1 to 14, wherein the photopatterned metal-containing resist has a thickness of about 10 nm to about 50 nm. [Example 21] The method according to any one of Application Examples 1 to 14, The method further comprising exposing the photopatterned metal-containing resist to an inert gas plasma after developing the photopatterned metal-containing resist. [Example 22] The method according to Application Example 21, The method further comprising repeating the operations of developing the photopatterned metal-containing resist and exposing the photopatterned metal-containing resist to the inert gas plasma. [Example 23] The method according to any one of Application Examples 1 to 14, The method further comprising baking the photopatterned metal-containing resist at an elevated temperature prior to developing the photopatterned metal-containing resist. [Example 24] In the method according to any one of Application Examples 1 to 14, providing the photopatterned metal-containing resist comprises: depositing a metal-containing EUV resist film on the semiconductor substrate; non-selectively removing a portion of the metal-containing EUV resist film on a backside and a bevel edge of the semiconductor substrate; exposing the metal-containing EUV resist film to EUV light to form the photopatterned metal-containing resist. [Example 25] The method according to any one of Application Examples 1 to 14, depositing a metal-containing EUV resist film on the semiconductor substrate; The method further comprising non-selectively removing the metal-containing EUV resist film from the semiconductor substrate without removing the substrate layer prior to providing the photopatterned metal-containing resist. [Example 26] An apparatus for developing a resist, the apparatus comprising: a process chamber having a substrate support; a vacuum line coupled to the process chamber; a developer chemistry line coupled to the process chamber; and a controller configured with instructions for processing a semiconductor substrate, the instructions comprising: providing a photopatterned metal-containing resist on a substrate layer of the semiconductor substrate in the process chamber; and code for developing the photopatterned metal-containing resist to form a resist mask by selectively removing portions of the resist by exposure to a developer chemistry that includes a halide. [Example 27] 27. The apparatus of claim 26, wherein the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist, and the controller is configured to have instructions including code for developing the photo-patterned metal-containing EUV resist and code for selectively removing EUV non-exposed portions of the EUV resist relative to EUV exposed portions with the developing chemical to form the resist mask. [Example 28] The device according to application example 26, The apparatus further comprising one or more heaters coupled to the substrate support, the one or more heaters comprising a plurality of independently controllable temperature control zones. [Example 29] 27. The apparatus of claim 26, wherein the interior of the process chamber is coated with a corrosion inhibitor. [Example 30] The device according to application example 26, The apparatus further comprising a cold trap coupled to the process chamber, the cold trap configured to remove water from the process chamber. [Example 31] The apparatus according to any one of Application Examples 26 to 30, wherein the process chamber comprises a plastic material. [Example 32] The apparatus according to any one of Application Examples 26 to 30, further comprising a UV lamp or an IR lamp coupled to the process chamber, the UV lamp or the IR lamp configured to cure the photopatterned metal-containing resist or remove excess halide from the process chamber. [Example 33] 1. A method for processing a semiconductor substrate, the method comprising: providing a dry deposited photopatterned metal oxide EUV resist on a substrate layer of a semiconductor substrate in a process chamber; and dry developing the photopatterned metal oxide EUV resist by selectively removing non-EUV exposed portions of the EUV resist by exposure to a dry development chemistry comprising HCl and / or HBr to form a resist hard mask from the EUV exposed portions. [Example 34] The method according to Application Example 33, wherein the dry development is performed by a thermal process without using plasma, and the exposure to the dry development chemicals is performed at a temperature of about -20°C to about 20°C. [Example 35] The method of claim 33, wherein the photopatterned metal oxide EUV resist comprises an organotin oxide.

Claims

1. 1. A method for dry developing a photopatterned EUV resist on a semiconductor substrate, comprising: and dry developing the photopatterned EUV resist, comprising unexposed organotin oxide-containing portions and EUV-exposed organotin oxide-containing portions, with a dry development chemistry comprising a halide etchant to form a resist mask, wherein the halide etchant selectively removes the unexposed organotin oxide-containing portions relative to the EUV-exposed organotin oxide-containing portions to form the resist mask.

2. 2. The method of claim 1 , The method wherein the dry developing chemistry comprises a hydrogen halide.

3. 3. The method of claim 2, The method of claim 1, wherein the hydrogen halide comprises hydrogen bromide (HBr).

4. 3. The method of claim 2, The method of claim 1, wherein the hydrogen halide comprises hydrogen chloride (HCl).

5. 2. The method of claim 1 , The method wherein the dry developing chemistry comprises a mixture of HBr and HCl.

6. 2. The method of claim 1 , The method, wherein the dry development chemistry comprises a mixture of hydrogen iodide (HI) and HBr or HCl.

7. 2. The method of claim 1 , The dry development chemistry is a mixture of hydrogen halides and boron trichloride (BCl 3 ).

8. 2. The method of claim 1 , The method wherein dry developing the photopatterned EUV resist is performed with HBr at a temperature between -60°C and 60°C.

9. 2. The method of claim 1 , The method, wherein dry developing the photopatterned EUV resist is performed with HCl at a temperature between -20°C and 120°C.

10. 2. The method of claim 1 , Dry developing the photopatterned EUV resist comprises using hydrogen halides and BCl 3 The process is carried out at a temperature of from -20°C to 120°C with a mixture of

11. 2. The method of claim 1 , The method, wherein dry developing the photopatterned EUV resist is carried out with a mixture of HBr and HCl at a temperature between -60°C and 120°C.

12. 2. The method of claim 1 , The method wherein dry developing the photopatterned EUV resist is performed at a chamber pressure of 5 mTorr or greater.

13. 2. The method of claim 1 , wherein the halide etchant selectively severs tin-oxide bonds in the organotin oxide network of the unexposed organotin oxide-containing portions to form one or more volatile by-products while leaving intact tin-oxide bonds in the organotin oxide network of the EUV-exposed organotin oxide-containing portions to form the resist mask.

14. 14. The method of claim 13, the halide etchant favors breaking oxygen-tin bonds in the organotin oxide network that is less dense in the unexposed organotin oxide-containing portion, having a lower coordination geometry, relative to oxygen-tin bonds in the organotin oxide network of the EUV-exposed organotin oxide-containing portion, having a higher coordination geometry.

15. 14. The method of claim 13, the halide etchant favors protonating more basic oxides in the organotin oxide network of the unexposed organotin oxide-containing portion relative to less basic oxides in the organotin oxide network of the EUV-exposed organotin oxide-containing portion, thereby severing the tin-oxide bonds.

16. 2. The method of claim 1 , The method, wherein dry developing the photopatterned EUV resist produces one or more volatile by-products including organotin halides and water.

17. 2. The method of claim 1 , the unexposed organotin oxide-containing portion comprises an organic ligand and the EUV-exposed organotin oxide-containing portion is free of organic ligands, and the halide etchant selectively removes the unexposed organotin oxide-containing portion that contains organic ligands to form volatile by-products while leaving the EUV-exposed organotin oxide-containing portion free of organic ligands to form the resist mask.

18. 2. The method of claim 1 , The method wherein said dry development comprises a combination of plasmaless thermal development and plasma development.

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