Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device in which the adhesion of foreign substances to a field plate and deformation can be suppressed, and a manufacturing method for the same.SOLUTION: A semiconductor device includes a semiconductor layer, a source electrode and a drain electrode provided on an upper surface of the semiconductor layer, a gate electrode provided on the upper surface of the semiconductor layer and existing between the source electrode and the drain electrode, a first insulating film provided on the gate electrode, and a field plate provided on the first insulating film and at least partially overlapping on the gate electrode. The field plate includes a first metal layer, and a second metal layer provided on an upper surface of the first metal layer. The first metal layer contains gold and the second metal layer contains at least one of tantalum, tungsten, molybdenum, niobium, and titanium.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] In a high electron mobility transistor (HEMT), a field plate is sometimes provided above the gate electrode (see, for example, Patent Document 1). The field plate can reduce electric field concentration and increase the breakdown voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-199241 A Summary of the Invention [Problem to be solved by the invention]

[0004] Field plates are sometimes made of gold (Au). Because Au is softer than other metals, there is a risk that foreign matter such as metal may adhere to the field plate and cause deformation. Therefore, the present invention aims to provide a semiconductor device and a manufacturing method thereof that can suppress the adhesion of foreign matter to and deformation of the field plate. [Means for solving the problem]

[0005] The semiconductor device according to the present disclosure comprises a semiconductor layer, a source electrode and a drain electrode provided on an upper surface of the semiconductor layer, a gate electrode provided on the upper surface of the semiconductor layer and located between the source electrode and the drain electrode, a first insulating film provided on the gate electrode, and a field plate provided on the first insulating film, at least a portion of which overlaps with the gate electrode, the field plate having a first metal layer and a second metal layer provided on the upper surface of the first metal layer, the first metal layer including gold, and the second metal layer including at least one of tantalum, tungsten, molybdenum, niobium, and titanium.

[0006] The semiconductor device according to the present disclosure comprises a semiconductor layer, a source electrode and a drain electrode provided on an upper surface of the semiconductor layer, a gate electrode provided on the upper surface of the semiconductor layer and located between the source electrode and the drain electrode, a first insulating film provided on the gate electrode, and a field plate provided on the first insulating film and at least a portion of which overlaps the gate electrode, the field plate having a first metal layer and a second metal layer provided on the upper surface of the first metal layer, and the Mohs hardness of the second metal layer is higher than the Mohs hardness of the first metal layer.

[0007] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of forming a gate electrode, the source electrode, and the drain electrode on an upper surface of a semiconductor layer such that the gate electrode is located between the source electrode and the drain electrode, forming a first insulating film on the gate electrode, and forming a field plate on the first insulating film, at least a portion of which overlaps with the gate electrode, the field plate having a first metal layer and a second metal layer provided on an upper surface of the first metal layer, the first metal layer including gold, and the second metal layer including at least one of tantalum, tungsten, molybdenum, niobium, and titanium. Effect of the Invention

[0008] According to the present disclosure, it is possible to suppress adhesion of foreign matter to and deformation of a field plate. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1A is a top view illustrating a semiconductor device according to an embodiment. [Figure 1B] FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A. [Figure 2A] FIG. 2A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 2B] FIG. 2B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 2C] FIG. 2C is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 3A] FIG. 3A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 3B] FIG. 3B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 3C] FIG. 3C is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 4A] FIG. 4A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 4B] FIG. 4B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 4C] FIG. 4C is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 5A] FIG. 5A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 5B] FIG. 5B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. [Figure 6] FIG. 6 is a cross-sectional view illustrating a semiconductor device according to the first modification. [Figure 7] FIG. 7 is a cross-sectional view illustrating a semiconductor device according to the second modification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0011] One embodiment of the present disclosure is a semiconductor device comprising: (1) a semiconductor layer, a source electrode and a drain electrode provided on an upper surface of the semiconductor layer, a gate electrode provided on the upper surface of the semiconductor layer and located between the source electrode and the drain electrode, a first insulating film provided on the gate electrode, and a field plate provided on the first insulating film and at least a portion of which overlaps the gate electrode, the field plate having a first metal layer and a second metal layer provided on the upper surface of the first metal layer, the first metal layer containing gold, and the second metal layer containing at least one of tantalum, tungsten, molybdenum, niobium, and titanium. The second metal layer is harder than the first metal layer, and therefore adhesion of foreign matter to and deformation of the field plate can be suppressed. (2) A semiconductor device comprising: a semiconductor layer, a source electrode and a drain electrode provided on an upper surface of the semiconductor layer, a gate electrode provided on the upper surface of the semiconductor layer and located between the source electrode and the drain electrode, a first insulating film provided on the gate electrode, and a field plate provided on the first insulating film and at least a portion of which overlaps the gate electrode, the field plate having a first metal layer and a second metal layer provided on the upper surface of the first metal layer, the Mohs hardness of the second metal layer being higher than that of the first metal layer. Since the second metal layer is harder than the first metal layer, adhesion of foreign matter to and deformation of the field plate can be suppressed. (3) An end of the field plate may be located between the gate electrode and the drain electrode. By providing the field plate near the drain electrode to which a high voltage is applied, electric field concentration can be effectively alleviated. (4) The second metal layer may include an oxide, which can effectively prevent metal pieces from adhering to the field plate. (5) The second metal layer may have an oxide film at least on a surface thereof, which can effectively prevent metal pieces from being pressed against the field plate. (6) The thickness of the second metal layer may be 5 nm or more and 30 nm or less. By having a thickness of 5 nm or more, defects are less likely to occur in the second metal layer. By having a thickness of 30 nm or less, a temperature rise during the manufacturing process is suppressed. (7) The semiconductor device may include a second insulating film provided on the first insulating film and the field plate, having a first opening at a position overlapping the field plate and a second opening at a position overlapping the source electrode, a first via wiring provided in the first opening and in contact with a first metal layer of the field plate, a second via wiring provided in the second opening and electrically connected to the source electrode, and a wiring electrically connected to the first via wiring and the second via wiring. Since the first via wiring contacts the first metal layer, the reliability of the connection between the first via wiring and the field plate is improved. The wiring, the first via wiring, and the second via wiring connect the source electrode and the field plate to be at the same potential. The field plate at the same potential as the source electrode can effectively reduce the electric field. (8) A method for manufacturing a semiconductor device, comprising the steps of: forming a gate electrode, the source electrode, and the drain electrode on an upper surface of a semiconductor layer such that the gate electrode is located between the source electrode and the drain electrode, forming a first insulating film on the gate electrode, and forming a field plate on the first insulating film, at least a portion of which overlaps with the gate electrode, the field plate having a first metal layer and a second metal layer provided on an upper surface of the first metal layer, the first metal layer containing gold, and the second metal layer containing at least one of tantalum, tungsten, molybdenum, niobium, and titanium. Since the second metal layer is harder than the first metal layer, adhesion of foreign matter to and deformation of the field plate can be suppressed. (9) The step of forming the field plate may include the steps of forming a resist mask on the first insulating film so that a portion of the first insulating film overlapping the gate electrode is exposed, forming the first metal layer and the second metal layer on an upper surface of the resist mask and the upper surface of the exposed first insulating film, and removing the resist mask and the first metal layer and the second metal layer provided on the upper surface of the resist mask by lift-off. Metal pieces may fly off during lift-off. The second metal layer can suppress the adhesion of the metal pieces to the field plate and also suppress deformation due to collision of the metal pieces. (10) The step of forming the field plate may include a step of continuously forming the first metal layer and the second metal layer by a vacuum deposition method. When the second metal layer formed by the vacuum deposition method is exposed to the atmosphere, it is oxidized. By forming an oxide film on the second metal layer, pressure bonding of metal pieces and the like is effectively suppressed. (11) The method may include the steps of forming a second insulating film on the first insulating film and the field plate, forming a first opening in the second insulating film at a position overlapping the field plate by etching, and forming a second opening in the first insulating film and the second insulating film at a position overlapping the source electrode by etching, removing a portion of the second metal layer exposed from the first opening, forming a first via wiring in the first opening that contacts the first metal layer of the field plate, forming a second via wiring in the second opening that is electrically connected to the source electrode, and forming wiring that is electrically connected to the first via wiring and the second via wiring. Since the first via wiring contacts the first metal layer, the reliability of the connection between the first via wiring and the field plate is improved. The wiring, the first via wiring, and the second via wiring connect the source electrode and the field plate to the same potential. The field plate at the same potential as the source electrode can effectively reduce the electric field.

[0012] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0013] (Semiconductor Device) Fig. 1A is a top view illustrating a semiconductor device 100 according to an embodiment. Fig. 1B is a cross-sectional view taken along line AA in Fig. 1A. The semiconductor device 100 shown in Fig. 1A and Fig. 1B is a HEMT.

[0014] As shown in FIG. 1B, the semiconductor device 100 includes a substrate 10, a barrier layer 12, a channel layer 14, an electron supply layer 16, a cap layer 18, a source electrode 20, a drain electrode 22, a gate electrode 24, and a field plate 30.

[0015] A barrier layer 12, a channel layer 14, an electron supply layer 16, and a cap layer 18 are laminated in this order on a substrate 10. The substrate 10 is made of, for example, silicon carbide (SiC). The barrier layer 12 is made of, for example, aluminum nitride (AlN). The channel layer 14 and the cap layer 18 are made of, for example, gallium nitride (GaN). The electron supply layer 16 is made of, for example, aluminum gallium nitride (AlGaN) and has a larger band gap than the channel layer 14. These semiconductor layers may be made of gallium arsenide (GaAs)-based semiconductors other than GaN-based semiconductors.

[0016] A source electrode 20, a drain electrode 22, and a gate electrode 24 are provided on the upper surface of the cap layer 18. The gate electrode 24 is provided between the source electrode 20 and the drain electrode 22. These three electrodes are spaced apart from each other. The source electrode 20 and the drain electrode 22 are ohmic electrodes made of metals, such as, for example, a titanium / aluminum laminate (Ti / Al) or a tantalum / aluminum laminate (Ta / Al) from the bottom up. The gate electrode 24 is made of metals, such as, for example, a Ti / gold laminate (Ti / Au) from the bottom up.

[0017] The insulating film 40 (first insulating film) is provided on the upper surface of the cap layer 18, and covers the side and upper surfaces of the source electrode 20, the drain electrode 22, and the gate electrode 24. The insulating film 42 (second insulating film) is provided on the upper surface of the insulating film 40, and covers the source electrode 20, the drain electrode 22, and the gate electrode 24. The insulating film 40 is an interlayer insulating film made of, for example, silicon nitride (SiN). The insulating film 42 is an interlayer insulating film made of, for example, silicon oxide (SiO2). The insulating film 40 may be a SiO2 film, and the insulating film 42 may be a SiN film. The insulating films 40 and 42 each have a thickness of, for example, 100 nm or more and 500 nm or less.

[0018] The field plate 30 is provided on the upper surface of the insulating film 40, and is located between the insulating film 40 and the insulating film 42. The field plate 30 is spaced apart from the source electrode 20, the drain electrode 22, and the gate electrode 24, and extends from directly above the gate electrode 24 to the outside of the gate electrode 24. One end of the field plate 30 is located between the gate electrode 24 and the drain electrode 22, and the other end is located on the gate electrode 24.

[0019] The field plate 30 has a metal layer 32 (first metal layer) and a metal layer 34 (second metal layer) laminated in this order from the insulating film 40 side. The metal layer 32 has, for example, a Ti layer and an Au layer laminated in this order from the insulating film 40 side. The Ti layer has a thickness of, for example, 2 nm to 10 nm and functions as an adhesive layer. The Au layer has a thickness of, for example, 100 nm to 500 nm. The main component of the metal layer 32 is Au. The term "main component" means that the atomic percent concentration is 50% or more.

[0020] The metal layer 34 is formed of, for example, tantalum (Ta), is in contact with the upper surface of the Au layer of the metal layer 32, and has a Mohs hardness higher than that of the metal layer 32. For example, the Mohs hardness of Au is 2.5, and the Mohs hardness of Ta is 6.5. The metal layer 34 has an oxide film 36 on its surface. The oxide film 36 is an oxide of the metal forming the metal layer 34, such as a film of tantalum oxide. The thickness of the metal layer 34 including the oxide film 36 is smaller than the thickness of the metal layer 32, and is, for example, 5 nm to 30 nm. The metal layer 34 may be formed of tungsten (W), molybdenum (Mo), niobium (Nb), or titanium (Ti) other than Ta, and contains at least one of these metals. The main component of the metal layer 34 is at least one of Ta, W, Mo, Nb, and Ti. For example, the Mohs hardness of Mo is 5.5, the Mohs hardness of Nb is 6.0, and the Mohs hardness of Ti is 6.0. In addition, the oxide film 36 is a layer formed by oxidizing the metal layer 34, and is formed of an oxide of the above metals, i.e., tantalum oxide (TaO), etc.

[0021] Two openings 44 and 45 are provided in the insulating films 40 and 42. An opening 46 (first opening) is provided in the insulating film 42. The opening 44 (second opening) is located above the source electrode 20. The opening 45 is located above the drain electrode 22. The opening 46 is located above the field plate 30. Each of the three openings extends in the stacking direction of the layers.

[0022] The via wiring 50 is provided in the opening 44 and is electrically connected to the source electrode 20. The wiring 55 is provided on the upper surface of the insulating film 42 and is connected to the source electrode 20 through the via wiring 50, and functions as a source wiring.

[0023] The via wiring 52 is provided in the opening 45, and is electrically connected to the drain electrode 22. The wiring 54 is provided on the upper surface of the insulating film 42, and is connected to the drain electrode 22 through the via wiring 52, and functions as a drain wiring.

[0024] Via wiring 53 is provided in opening 46, contacts the upper surface of metal layer 32 of field plate 30, and is electrically connected to field plate 30. Wiring 56 is provided on the upper surface of insulating film 42, extends between openings 44 and 46, and is electrically connected to wiring 55 and via wiring 53. The source electrode 20 and field plate 30 are electrically connected by via wirings 50 and 53, and wirings 55 and 56. The three via wirings and wirings 54 to 56 are formed of a metal such as Au, and include a seed metal layer (not shown).

[0025] (Manufacturing method) A method for manufacturing the semiconductor device 100 will now be described. Figures 2A to 5B are cross-sectional views illustrating an example of the method for manufacturing the semiconductor device 100. As shown in Figure 2A, a barrier layer 12, a channel layer 14, an electron supply layer 16, and a cap layer 18 are epitaxially grown in this order on a substrate 10 by, for example, metal organic chemical vapor deposition (MOCVD).

[0026] 2B, a source electrode 20 and a drain electrode 22 are provided on the top surface of the cap layer 18 by, for example, vacuum deposition, and ohmic contacts are formed between the electrodes and the semiconductor layer by heat treatment. A gate electrode 24 is then provided by vacuum deposition.

[0027] 2C, an insulating film 40 made of SiN is formed on the cap layer 18. The insulating film 40 covers the source electrode 20, the drain electrode 22, and the gate electrode 24. The insulating film 40 is formed by, for example, a plasma CVD method (Chemical Vapor Deposition), an atmospheric pressure CVD method, an ALD method (Atomic Layer Deposition), or the like.

[0028] 3A, photoresist 60 having a thickness of, for example, 0.5 μm to 2 μm is applied to the upper surface of insulating film 40, and patterning is performed by photolithography. An opening 60a is formed in photoresist 60 at a position overlapping with a part of gate electrode 24. A part of the upper surface of insulating film 40 is exposed from opening 60a.

[0029] 3B, a metal layer 32 of Au and a metal layer 34 of Ta or the like are formed in this order, for example, by vacuum deposition. By successively forming metal layer 32 and metal layer 34, metal layer 34 is provided on the surface of metal layer 32. A field plate 30 is formed on the upper surface of insulating film 40, and metal layers 32 and 34 are also provided on the upper surface of photoresist 60. Substrate 10 is removed from the deposition apparatus and exposed to the atmosphere, whereby metal layer 34 is oxidized.

[0030] 3C, the photoresist 60 and the metal layers 32 and 34 on the photoresist 60 are removed by lift-off. Specifically, a chemical solution containing an organic solvent such as N-methylpyrrolidone (NMP) is sprayed from a nozzle 62 toward the photoresist 60, and the photoresist 60 is removed from the cap layer 18.

[0031] In the lift-off process, the metal layers 32 and 34 on the photoresist 60 become metal pieces 64, for example, 1 μm or less in length, and scatter around. For example, if the field plate does not have the metal layer 34, the metal layer 32 is exposed. The metal layer 32 is a layer of Au, which is soft and does not easily oxidize on the surface. The metal pieces 64 may be pressed against the metal layer 32, and the metal layer 32 may be deformed by the collision of the metal pieces 64. If the metal pieces 64 are pressed against and deformed on the field plate 30, deformation and cracks may occur in the insulating film 42. There is a risk that a short circuit may occur between the field plate 30 and other electrodes, reducing the withstand voltage.

[0032] 3C, the field plate 30 of this embodiment has a metal layer 34 on its surface. The metal layer 34 is made of Ta or the like and has a higher Mohs hardness than the Au metal layer 32. The metal layer 34 is also easily oxidized and has an oxide film 36 on its surface. The metal piece 64 is difficult to press against the hard, oxidized surface of the metal layer 34, and deformation of the metal piece 64 due to collision is also suppressed.

[0033] As shown in FIG. 4A, the photoresist 60 is removed by lift-off, leaving the field plate 30 without the metal strips 64 attached.

[0034] As shown in FIG. 4B, an insulating film 42 is formed on the upper surface of the insulating film 40 by, for example, a plasma CVD method.

[0035] 4C, photoresist 65 having a thickness of 0.5 μm to 2 μm is applied to the upper surface of insulating film 42, and patterning is performed. Three openings are formed in photoresist 65 by patterning. After resist patterning, dry etching is performed using a fluorine-based gas such as sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), and trifluoromethane (CHF3), or a chlorine-based gas such as chlorine (Cl2), silicon tetrachloride (SiCl4), and boron trichloride (BCl3).

[0036] The insulating films 40 and 42 are dry etched to form openings 44 and 45. The source electrode 20 is exposed from the opening 44. The drain electrode 22 is exposed from the opening 45. The insulating film 42 is dry etched to form an opening 46. When forming the opening 46, the portion of the metal layer 34 that overlaps the opening 46 is also etched. The metal layer 32 of the field plate 30 is exposed in the opening 46. After etching, the photoresist 65 is removed.

[0037] 5A, a seed metal 66 is formed on the surface of the insulating film 42. The seed metal 66 covers the upper surface of the insulating film 42 and the inner walls and bottom surfaces of the openings 44 to 46. The seed metal 66 includes a Ti layer and an Au layer stacked in this order. The Ti layer functions as an adhesive layer.

[0038] 5B, an electric current is passed through the seed metal 66 to perform an electrolytic plating process, thereby forming the via wirings 50, 52, and 53, and the wirings 54 to 56. After the plating process, unnecessary seed metal 66 is removed. Part of the seed metal 66 remains under the via wirings 50, 52, and 53, and the wirings 54 and 56. Through the above steps, the semiconductor device 100 is manufactured.

[0039] According to this embodiment, the field plate 30 is provided on the upper surface of the insulating film 40 at a position overlapping the gate electrode 24. The field plate 30 has metal layers 32 and 34. The metal layer 34 is, for example, a Ta layer, which is harder than the Au metal layer 32. More specifically, the Mohs hardness of the metal layer 34 is higher than that of the metal layer 32. By having the metal layer 34, it is possible to suppress adhesion of foreign matter to the field plate 30 and to suppress deformation of the field plate 30 due to collision of the foreign matter. Deformation and cracks of the insulating film 42 are suppressed, and short circuits between the field plate 30 and other electrodes are less likely to occur. As a result, the withstand voltage of the semiconductor device 100 is improved.

[0040] Specifically, in the lift-off process shown in FIG. 3C, the metal layers 32 and 34 on the photoresist 60 fly off as metal pieces 64. If the Au metal layer 32 is exposed, there is a risk that the metal pieces 64 will be pressed against the metal layer 32. In addition to the lift-off process, there is a risk that metal or non-metallic foreign matter will adhere to the metal layer 32 during cleaning steps, transportation, and the like. According to this embodiment, the metal layer 34 covers the metal layer 32, so adhesion of foreign matter such as the metal pieces 64 can be suppressed, and deformation of the field plate 30 due to collisions with the metal pieces 64 can also be suppressed.

[0041] The metal layer 34 includes at least one of Ta, W, Mo, Nb, and Ti. The metal layer 34 including these metals has a higher Mohs hardness than the metal layer 32 of Au, and therefore can effectively suppress the adhesion of foreign matter. When a fluorine-based gas is used in the dry etching shown in FIG. 4C, a fluoride of the metal layer 34 is formed. The boiling point of the fluoride of the above metal is 300° C. or less, and it vaporizes. When a chlorine-based gas is used in the dry etching, the chloride of the metal layer 34 vaporizes. Therefore, the metal layer 34 can be easily removed by dry etching.

[0042] 1B, one end of the field plate 30 is located between the gate electrode 24 and the drain electrode 22. The field plate 30, which has a metal layer 34 and suppresses compression of the metal piece 64, is disposed near the drain electrode 22 to which a high voltage is applied. This can effectively reduce electric field concentration.

[0043] It is preferable that the metal layer 34 has an oxide film 36 at least on its surface. Metal pieces 64 and the like are less likely to be pressed onto the oxide film 36 than onto a surface that is not oxidized. The material of the metal layer 34, such as Ta, is easily oxidized. By successively forming the metal layers 32 and 34 by a vacuum deposition method, the metal layer 34 covers the surface of the metal layer 32. By exposing the metal layer 34 that is exposed on the surface to the atmosphere, the oxide film 36 is formed.

[0044] FIG. 6 is a cross-sectional view illustrating a semiconductor device 110 according to the first modification. Not only the surface but the entire metal layer 34 is oxidized. That is, the metal layer 34 is an oxide film 36 formed of an oxide of Ta or the like. The other configurations are the same as the example of FIG. 1B. As shown in FIG. 1B and FIG. 6, it is sufficient that at least the surface of the metal layer 34 is oxidized. It is possible to effectively suppress the pressure bonding of the metal piece 64 to the field plate 30. As described above, the metal layer 34 may be entirely or partially oxidized. For example, half or more of the metal layer 34 may be an oxide, or 90% or more of the metal layer 34 may be an oxide. As shown in FIG. 1A, it is preferable that the metal layer 34 has an oxide film 36 at least on its surface.

[0045] If the metal layer 34 is thin, the metal layer 34 may become a defective, discontinuous layer, exposing the metal layer 32. On the other hand, if the metal layer 34 is thick, the temperature of the field plate 30 may rise during the vacuum deposition process, and the photoresist 60 may be deformed. In order to cover the metal layer 32 and suppress the temperature rise, the thickness of the metal layer 34 is preferably 5 nm or more and 30 nm or less. The lower limit of the thickness may be, for example, 10 nm or more or 15 nm or more. The upper limit of the thickness may be, for example, 40 nm or less or 50 nm or less. The thickness of the metal layer 34 includes the thickness of the oxide film 36.

[0046] FIG. 7 is a cross-sectional view illustrating a semiconductor device 120 according to the second modification. The metal layer 34 does not have an oxide film 36. The other configurations are the same as those in the example of FIG. 1B. As shown in FIG. 7, the surface of the metal layer 34 is not oxidized. After the metal layer 34 is formed, the insulating film 42 is formed without exposing it to the air. For example, after the metal layer 34 is formed, the insulating film 42 can be provided while suppressing oxidation by storing it in a nitrogen atmosphere. Alternatively, the insulating film 42 may be formed continuously from the process of forming the metal layer 34 without exposing the metal layer 34 to the air. The metal layer 34 can be formed without forming the oxide film 36 on the surface of the metal layer 34, and the metal layer 34 can be further covered with the insulating film 42. After the insulating film 42 is formed, the same process as in the embodiment can be performed to form the semiconductor device 120. According to the second modification, pressure bonding of the metal piece 64 to the field plate 30 can be effectively suppressed.

[0047] By the etching of FIG. 4C, a part of the metal layer 34 of the field plate 30 is removed, and the oxide film 36 is removed together with the metal layer 34, exposing the metal layer 32. As shown in FIG. 1B, the via wiring 53 contacts the metal layer 32, improving the strength of the connection with the field plate 30. The metal layer 34 may remain, for example, several nm, in the etched portion of the field plate 30, and the via wiring 53 may be connected to the metal layer 34. For a stable connection with the via wiring 53, it is preferable to remove at least the oxide film 36 by etching. The source electrode 20 and the field plate 30 are electrically connected through the via wirings 50 and 53 and the wiring 56. The field plate 30 and the source electrode 20 can be at the same potential. The field plate 30 at the same potential as the source electrode 20 can effectively relax the electric field.

[0048] The via wirings 50, 52, and 53, and the wiring 56 are, for example, Au plated layers. The three via wirings and the wiring 56 can be formed by a single plating process, which simplifies the process. The via wirings 50 and 53 and the wiring 56 are the same Au layer, which increases the reliability of the connection.

[0049] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure described in the claims. [Explanation of symbols]

[0050] 10 Substrate 12 Barrier layer 14 Channel Layer 16 Electron supply layer 18 Cap Layer 20 Source electrode 22 Drain electrode 24 Gate electrode 30 Field Plate 32, 34 metal layer 36 Oxide Film 40, 42 Insulating film 44, 45, 46, 60a opening 50, 52, 53 Via wiring 54, 55, 56 Wiring 60, 65 Photoresist 62 Nozzle 64 Metal piece 66 Seed Metal 100, 110, 120 Semiconductor device

Claims

1. A semiconductor layer; a source electrode and a drain electrode provided on an upper surface of the semiconductor layer; a gate electrode provided on an upper surface of the semiconductor layer and positioned between the source electrode and the drain electrode; a first insulating film provided on the gate electrode; a field plate provided on the first insulating film, at least a portion of which overlaps the gate electrode; the field plate includes a first metal layer and a second metal layer provided on an upper surface of the first metal layer; the first metal layer comprises gold; The second metal layer includes at least one of tantalum, tungsten, molybdenum, niobium, and titanium, and includes an oxide.

2. A semiconductor layer; a source electrode and a drain electrode provided on an upper surface of the semiconductor layer; a gate electrode provided on an upper surface of the semiconductor layer and positioned between the source electrode and the drain electrode; a first insulating film provided on the gate electrode; a field plate provided on the first insulating film, at least a portion of which overlaps the gate electrode; the field plate includes a first metal layer and a second metal layer provided on an upper surface of the first metal layer; the second metal layer has a Mohs hardness greater than the Mohs hardness of the first metal layer; The second metal layer comprises an oxide.

3. 3. The semiconductor device according to claim 1, wherein an end of the field plate is located between the gate electrode and the drain electrode.

4. The semiconductor device according to claim 1 , wherein the second metal layer has an oxide film at least on a surface thereof.

5. 5. The semiconductor device according to claim 1, wherein the second metal layer has a thickness of 5 nm or more and 30 nm or less.

6. a second insulating film provided on the first insulating film and the field plate, the second insulating film having a first opening at a position overlapping the field plate and a second opening at a position overlapping the source electrode; a first via wiring provided in the first opening and in contact with a first metal layer of the field plate; a second via wiring provided in the second opening and electrically connected to the source electrode; The semiconductor device according to claim 1 , further comprising: a wiring electrically connected to the first via wiring and the second via wiring.

7. forming a gate electrode, a source electrode, and a drain electrode on an upper surface of the semiconductor layer such that the gate electrode is located between the source electrode and the drain electrode; forming a first insulating film on the gate electrode; forming a field plate on the first insulating film, the field plate having at least a portion overlapping the gate electrode; the field plate includes a first metal layer and a second metal layer provided on an upper surface of the first metal layer; the first metal layer comprises gold; the second metal layer comprises at least one of tantalum, tungsten, molybdenum, niobium, and titanium; The method for manufacturing a semiconductor device, wherein the step of forming the field plate includes the step of forming the first metal layer and the second metal layer successively by a vacuum deposition method.

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the step of forming the field plate includes the steps of: forming a resist mask on the first insulating film so as to expose a portion of the first insulating film overlapping the gate electrode; forming the first metal layer and the second metal layer on an upper surface of the resist mask and on the exposed upper surface of the first insulating film; and removing the resist mask and the first metal layer and the second metal layer provided on the upper surface of the resist mask by lift-off.

9. forming a second insulating film on the first insulating film and the field plate; forming a first opening at a position of the second insulating film overlapping the field plate by etching, and forming a second opening at a position of the first insulating film and the second insulating film overlapping the source electrode by etching; removing a portion of the second metal layer exposed through the first opening by etching; forming a first via wiring in the first opening so as to contact a first metal layer of the field plate; forming a second via wiring in the second opening, the second via wiring being electrically connected to the source electrode; 9. The method for manufacturing a semiconductor device according to claim 7, further comprising the step of forming wiring electrically connected to the first via wiring and the second via wiring.

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