Stacked Vertical Transistor Memory Cell

Abstract

The semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a lower tier including a plurality of lower transistors, including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal electrically isolated from the other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes an upper tier including at least one upper transistor, and a cross-coupling including an epitaxial region connection between the upper tier and the lower tier and a gate-to-epitaxial region connection.

Description

[Technical field]

[0001] The present invention relates to semiconductor devices, and more particularly to stacked vertical transistor memory cells and methods for fabricating the same. [Background technology]

[0002] Vertical transistors, such as vertical field effect transistors (FETs), were conceived as a way to reduce the contact poly pitch (CPP), decrease the unit cell size, and increase efficiency by orienting the current flow vertically. Furthermore, because the ohmic contacts and the channel are aligned vertically, the contact density per unit surface area of ​​a vertical transistor is higher compared to a lateral transistor. Summary of the Invention

[0003] According to one embodiment of the present invention, a semiconductor device is provided. The device includes a stacked transistor memory cell. The stacked transistor memory cell includes a lower tier including a plurality of lower transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal electrically isolated from other transistors of the stacked transistor memory cell. The stacked transistor memory cell includes an upper tier including at least one upper transistor, and a cross coupling including an epitaxial region connection between the upper tier and the lower tier and a gate-to-epitaxial region connection.

[0004] According to another embodiment of the present invention, a semiconductor device is provided. The device includes a stacked vertical transistor memory cell. The stacked vertical transistor memory cell includes a bottom tier including a plurality of bottom vertical transistors including N-type field effect transistors (nFETs) having a merged top source / drain epitaxial region (epi) and gate structure. The plurality of bottom vertical transistors includes first and second non-floating transistors and first and second floating transistors. The first and second floating transistors have at least one terminal electrically isolated from other transistors of the stacked vertical transistor memory cell. The stacked vertical transistor memory cell further includes a top tier including a plurality of top vertical transistors including P-type field effect transistors (pFETs) having a merged bottom source / drain epi and gate structure. The plurality of top vertical transistors includes first, second, third and fourth top vertical transistors. The stacked vertical transistor memory cell further includes cross couplings contacting the gate structures of the lower and upper structures, the cross couplings including merged upper source / drain epi connections between the first non-floating and floating transistors and between the second non-floating and floating transistors, merged lower source / drain epi connections between the first and third upper vertical transistors and between the second and fourth upper vertical transistors, metal gate-to-epi connections between the first non-floating transistor and the second floating transistor and between the second non-floating transistor and the first floating transistor, and metal gate-to-epi connections between the first and second upper vertical transistors and between the third and fourth upper vertical transistors.

[0005] According to yet another embodiment of the present invention, there is provided a method for fabricating a semiconductor device. The method includes forming a stacked transistor memory cell, the stacked transistor memory cell including a lower tier including a plurality of lower transistors including at least one non-floating transistor and at least one floating transistor, and an upper tier including at least one upper transistor. The at least one floating transistor has at least one terminal electrically isolated from other transistors of the stacked transistor memory cell. Forming the stacked transistor memory cell includes forming cross couplings including epitaxial region connections between the upper tier and the lower tier and a gate to epitaxial region connection.

[0006] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be taken in conjunction with the accompanying drawings.

[0007] The following description will provide details of preferred embodiments with reference to the following drawings: [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a memory cell according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a top-down view of a stacked vertical transistor memory cell according to one embodiment of the present invention. [Diagram 3] 3 is a cross-sectional view of the memory cell of FIG. 2, according to one embodiment of the present invention. [Figure 4] 3 is another cross-sectional view of the memory cell of FIG. 2, in accordance with one embodiment of the present invention. [Diagram 5] 2 is a top-down view of a sacrificial layer being etched during manufacturing of a semiconductor device according to one embodiment of the present invention. [Figure 6] 6 is a cross-sectional view of the semiconductor device shown in FIG. 5 according to one embodiment of the present invention. [Figure 7]6 is another cross-sectional view of the semiconductor device shown in FIG. 5 according to one embodiment of the present invention. [Figure 8] 2A-2C are cross-sectional views illustrating the formation of lower source / drain regions in an upper tier of a semiconductor device during fabrication of the semiconductor device in accordance with one embodiment of the present invention. [Figure 9] 4 is another cross-sectional view illustrating the formation of lower source / drain regions of an upper level of a semiconductor device during fabrication of the semiconductor device in accordance with one embodiment of the present invention. [Figure 10] 5A-5C are cross-sectional views illustrating the formation of an upper transistor and an inter-level dielectric (ILD) layer during the manufacture of a semiconductor device according to another embodiment of the present invention. [Figure 11] 4 is another cross-sectional view illustrating the formation of an upper transistor and an inter-level dielectric (ILD) layer during the fabrication of a semiconductor device according to another embodiment of the present invention. [Figure 12] 5A-5C are cross-sectional views illustrating etching performed to expose a sacrificial layer during fabrication of a semiconductor device according to another embodiment of the present invention. [Figure 13] 4 is another cross-sectional view illustrating an etch performed to expose a sacrificial layer during fabrication of a semiconductor device according to another embodiment of the present invention. [Figure 14] 11A-11C are cross-sectional views illustrating the removal of a sacrificial layer to form a cross-coupling opening during fabrication of a semiconductor device according to another embodiment of the present invention. [Figure 15] FIG. 11 is another cross-sectional view illustrating the removal of a sacrificial layer to form a cross-coupling opening during fabrication of a semiconductor device according to another embodiment of the present invention. [Figure 16] 11A-11C are cross-sectional views illustrating the formation of conductive material in cross-coupling openings to form cross-couplings during fabrication of a semiconductor device according to another embodiment of the present invention. [Figure 17] FIG. 11 is another cross-sectional view illustrating the formation of a conductive material in the cross-coupling openings to form a cross-coupling during the manufacture of a semiconductor device according to one embodiment of the present invention. [Figure 18]FIG. 2 is a block / flow diagram illustrating a system / method for manufacturing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The embodiments described herein provide a stacked transistor memory cell in a stacked three-dimensional (3D) transistor architecture. The stacked transistor memory cell may include floating transistors and non-floating transistors. As used herein, a floating transistor of a memory cell is a transistor having at least one terminal (e.g., at least one of source / drain, drain / source, and gate) that is electrically separated or isolated from other transistors of the memory cell, where none of the terminals represents an interface to the outside of the memory cell (e.g., a word line (WL), a bit line (BL), a supply voltage (VDD), and a ground (GND)). A non-floating transistor of a memory cell is a transistor that is not a floating transistor. That is, each terminal of a non-floating transistor either connects with other transistors in the memory cell or represents an interface to the outside of the memory cell.

[0010] A stacked transistor memory cell formed according to the embodiments described herein includes a top tier and a bottom tier having respective transistors. The top tier illustratively may include P-type transistors (e.g., pFETs) and the bottom tier may include N-type transistors (e.g., nFETs). For example, the top tier transistors (e.g., pFETs) may be used as pass gates.

[0011] In one embodiment, the stacked transistor memory cell is a stacked vertical transistor memory cell. More specifically, the stacked vertical transistor memory cell may include a Vertical Transport FET (VTFET). The merged lower epitaxial region ("epi") of the upper tier may be used to connect the pass gate to the drain of the first inverter (e.g., pFET). The transistor (e.g., nFET) directly below the pass gate may have an upper epi including a floating gate and a lower source / drain that is merged to the top of the epi (drain) of the second inverter (e.g., nFET). A cross-coupled contact connects the gate of the inverter, which directly contacts the pass gate lower epi and the upper epi of the floating transistor.

[0012] In accordance with aspects of the present invention, the integration of stacked transistor memory cells within a 3D monolithic scheme can provide various benefits for logic, such as one or more of: (1) tighter packaging of circuitry to reduce back end of line (BEOL) line length for power and performance benefits, and (2) higher drive strength benefits in a given area footprint.

[0013] Exemplary applications / uses to which the present invention may be applied include, but are not limited to, fabricating memory devices. For example, embodiments of the present invention may be applied to fabricating static random access memory (SRAM) devices from SRAM cells. As known in the art, SRAM cells are comprised of transistors, which may include metal oxide semiconductor FETs (MOSFETs). For example, in a six transistor SRAM cell (i.e., a 6T SRAM cell), each bit is stored in four transistors that form a cross-coupled inverter, and the other two transistors are access transistors that control access to the storage cell during read and write operations. In the embodiments of the 6T SRAM cell discussed herein, the upper tier may include four P-type transistors and the lower tier may include two N-type transistors. For example, the upper tier may include two pass gates. It should be noted that such embodiments are not limiting. For example, in alternative embodiments, the upper tier may include N-type transistors and the lower tier may include N-type transistors.

[0014] Aspects of the invention are described in conjunction with given example architectures; however, it should be understood that other architectures, structures, substrate materials and processing features and steps may vary within the scope of the aspects of the invention.

[0015] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0016] The present embodiments may include designs for integrated circuit chips that may be created in a graphical computer programming language and stored on a computer storage medium (disk, tape, physical or virtual hard drive, such as in a storage access network). If the designer does not fabricate the chip or the photolithographic masks used to fabricate the chip, the designer may transmit the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a format (e.g., GDSII) suitable for fabrication of a photolithographic mask, which may include multiple copies of the subject chip design to be formed on a wafer. The photolithographic mask is utilized to define areas of the wafer (or layers thereon) to be etched or otherwise processed.

[0017] The methods described herein may be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be distributed by manufacturers in raw wafer form (i.e., as a single wafer having multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as a plastic carrier with leads affixed to a motherboard or other higher level carrier) or in multi-chip packages (such as a ceramic carrier with either surface interconnects or embedded interconnects or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and a central processor.

[0018] It should also be understood that the source compounds are described in terms of the listed elements, e.g., SiGe. These compounds contain elements in various proportions within the compound, e.g., SiGe includes SiGe1-x, where x is 1 or less. Additionally, other elements may be included in the compound and still function according to the present principles. Compounds with additional elements will be referred to herein as alloys.

[0019] References herein to "one embodiment" or "an embodiment" of the present invention, and variations thereof, mean that the particular feature, structure, characteristic, etc. described in connection with that embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" and any other variations appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

[0020] It is to be understood that the use of any of the following " / ", "and / or", and "at least one of" are intended to include selection of only the first listed alternative (A), or selection of only the second listed alternative (B), or selection of both alternatives (A and B), e.g., "A / B", "A and / or B", and "at least one of A and B". As a further example, in the case of "A, B and / or C" and "at least one of A, B and C," such phrases are intended to include the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first and second listed alternatives (A and B), or the selection of only the first and third listed alternatives (A and C), or the selection of only the second and third listed alternatives (B and C), or the selection of all three alternatives (A, B, and C). This may extend to the number of items listed, as would be readily apparent to one of ordinary skill in the art and the relevant technical field.

[0021] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the exemplary embodiments. As used herein, the singular forms "a", "an" and "the" are intended to encompass the plural, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" or "including" or combinations thereof, when used herein, specify the presence of stated features, integers, steps, operations, elements or components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof or combinations thereof.

[0022] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings for ease of description. It will be understood that the spatially relative terms are intended to encompass various orientations of the device during use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as being "below" or "beneath" the other element or feature would thus be oriented "above" the other element or feature. Thus, the term "below" can include both an upward and downward orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may be interpreted accordingly. Additionally, when a layer is referred to as being "between" two layers, it should be understood that that layer may be the only layer between the two layers, or there may be one or more intervening layers.

[0023] Terms such as first, second, etc. may be used in this specification to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another element. Thus, a first element discussed below may be named a second element without departing from the scope of the present concept.

[0024] Referring now to the drawings, where like numbers represent the same or similar elements, and initially to FIG. 1, a schematic diagram of a memory cell 100 is provided.

[0025] The memory cell 100 comprises a stacked transistor memory cell having multiple transistors. In an exemplary embodiment, the memory cell 100 comprises a stacked vertical transistor memory cell having multiple vertical transistors.

[0026] The memory cell 100 may include floating and non-floating transistors. A floating transistor may have at least one terminal (e.g., at least one of source / drain, drain / source, and gate) that is electrically isolated from the rest of the transistor. For example, as shown, the memory cell 100 includes eight transistors, including a set of transistors 102-1 through 102-4 and a set of transistors 104-1 through 104-4. In this exemplary embodiment, the plurality of transistors may include field effect transistors (FETs). In one embodiment, the set of transistors 102-1 through 102-4 includes P-type FETs (pFETs) and the set of transistors 104-1 through 104-4 includes N-type FETs (nFETs). However, such an embodiment should not be considered limiting. Transistors 104-2 and 104-3, shown in dashed lines, correspond to floating transistors (e.g., floating nFETs).

[0027] As further shown, multiple connections between each of the multiple transistors are shown. More specifically, the cross-coupling is achieved by epitaxial region ("epi") connections and gate-to-epi connections.

[0028] More specifically, dashed-dotted line 110-1 corresponds to a merged bottom epi connection between the source / drain of transistor 102-2 and the source / drain of transistor 102-4, and dashed-dotted line 110-2 corresponds to a merged bottom epi connection between the source / drain of transistor 102-1 and the source / drain of transistor 102-3 (e.g., a merged pFET bottom epi connection).

[0029] Dotted line 120-1 corresponds to a merged top epi connection between the drain / source of transistor 104-2 and the drain / source of transistor 104-4, and dotted line 120-2 corresponds to a merged top epi connection between the drain / source of transistor 104-1 and the drain / source of transistor 104-3 (e.g., a merged nFET top epi connection).

[0030] Solid line 130-1 corresponds to a metal gate-to-epi connection between the source / drain of transistor 102-2 and the gates of transistors 102-1 and 104-1, solid line 130-2 corresponds to a metal gate-to-epi connection between the drain / source of transistor 104-2 and the gates of transistors 102-1 and 104-1, solid line 140-1 corresponds to a metal gate-to-epi connection between the source / drain of transistor 102-3 and the gates of transistors 102-4 and 104-4, and solid line 140-2 corresponds to a metal gate-to-epi connection between the drain / source of transistor 104-3.

[0031] As shown, memory cell 100 includes a plurality of lines. More specifically, a ground (GND) line 150-1 is coupled to the source / drain of transistor 104-1, and a GND line 150-2 is coupled to the source / drain of transistor 104-4. A power supply voltage (VDD) line 160-1 is coupled to the drain / source of transistor 102-1, and a VDD line 160-2 is coupled to the drain / source of transistor 102-4. A word line (WL) line 170-1 is coupled to the gate of transistor 102-2, and a WL line 170-2 is coupled to the gate of transistor 102-3. A bit line (BL) line 180-1 is coupled to the drain / source of transistor 102-3, and a complementary bit line (~BL) line 180-2 is coupled to the drain / source of transistor 102-2.

[0032] Referring to FIG. 2, a top-down view of a stacked transistor memory cell 200 having an upper level 202 and a lower level 204 is provided. In this illustrative example, the memory cell 200 is a stacked vertical transistor memory cell including eight transistors (e.g., FETs), although the number of transistors should not be considered limiting. The memory cell 200 may represent the memory cell 100 of FIG. 1. For simplicity, some components of the memory cell 200 (e.g., gate material, top and bottom epitaxial regions ("epi"), sacrificial layers for forming contacts) are not shown in FIG. 2.

[0033] Memory cell 200 may include floating and non-floating transistors. A floating transistor may have at least one terminal (e.g., at least one of source / drain, drain / source, and gate) that is electrically isolated from the rest of the transistor.

[0034] For example, as shown, memory cell 200 may include multiple fins corresponding to multiple transistors, including fins 206-2 through 206-8. The multiple fins may include any suitable material according to embodiments described herein.

[0035] As further shown, memory cell 200 may include multiple contacts including GND contacts 210-1 and 210-2, VDD contacts 212-1 and 212-2, WL contacts 214-1 and 214-2, BL contacts 216-1 and BL contacts 216-2. Additionally, memory cell 200 may include cross-coupled connections 218-1 and 218-2. As discussed with reference to FIG. 1, cross-coupled connections may provide epi connections between multiple transistors and metal gate to epi connections. Cross-sectional views of memory cell 200 taken along lines A-A' and B-B' are described below with reference to FIGS. 3 and 4, respectively.

[0036] 3 and 4, cross-sectional views of the memory cell 200 of FIG 2 are provided. More specifically, FIG 3 illustrates a cross-sectional view through line A-A' of FIG 2, and FIG 4 illustrates a cross-sectional view through line B-B' of FIG 2.

[0037] As shown, the memory cell 200 includes a substrate 220 having multiple layers formed thereon. The substrate 220 may include any suitable substrate structure, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. In one example, the substrate 220 may include a silicon-containing material. Illustrative examples of Si-containing materials suitable for the substrate 220 may include, but are not limited to, Si, SiGe, SiGeC, SiC, and multiple layers thereof. Although silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be employed as additional layers, such as germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, etc.

[0038] Memory cell 200 further includes fins 206-1 through 206-3, 206-5 through 206-7, VDD line 212-1, and BL line 216-1, as described with reference to FIG. 2. Fins 206-5 through 206-7 correspond to lower FETs, and fins 206-1 through 206-3 correspond to upper FETs. Each of the FETs may further include a gate dielectric 208 and a gate conductor 209. Gate dielectric 208 and gate conductor 209 may include any suitable material according to embodiments described herein.

[0039] For example, the gate dielectric 208 may include a high-k dielectric material. As used herein, "high-k" is a dielectric material characterized by having a dielectric constant (k) greater than that of SiO2 at room temperature (20° C.-25° C.) and atmospheric pressure (1 atm). In one embodiment, the gate dielectric 208 may include a high-k oxide, such as, for example, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3, and mixtures thereof. Other examples of high-k dielectric materials for the gate dielectric 208 include hafnium silicate, hafnium silicon oxynitride, or combinations thereof.

[0040] Examples of suitable conductive materials for the gate conductor 209 include, but are not limited to, metals, metal alloys, metal nitrides, and metal silicides, as well as stacks and composites thereof. In one embodiment, the gate conductor 209 can comprise any conductive metal, including, but not limited to, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re, as well as alloys comprising at least one of the above conductive elemental metals. The gate conductor 209 can be a doped polysilicon or polysilicon-germanium alloy material (i.e., 1×10 per cubic centimeter or more). 18 1×10 from dopant atoms 22The gate conductor 209 may include, for example, a work-function metal (WFM) and a polycide material (a doped polysilicon / metal silicide stack material).

[0041] In one embodiment, the gate dielectric 208 or the gate conductor 209, or both, may be deposited by chemical vapor deposition (CVD). Variations of CVD processes suitable for depositing at least one gate dielectric layer include, but are not limited to, APCVD, LPCVD, PECVD, MOCVD, ALD, and combinations thereof.

[0042] Memory cell 200 further includes lower epitaxial ("epi") regions 222-1 through 222-5 corresponding to lower source / drain regions. More specifically, memory cell 200 includes merged lower epi region 222-1 of FETs corresponding to fins 206-1, 206-2, and lower epi regions 222-2 through 222-5 of FETs corresponding to fins 206-5, 206-6, 206-3, and 206-7, respectively.

[0043] Memory cell 200 further includes upper epi regions 224-1 through 224-6 corresponding to upper source / drain regions. More specifically, memory cell 200 includes merged upper epi region 224-1 of FETs corresponding to fins 206-5 and 206-6, and upper epi regions 224-2 through 224-6 of FETs corresponding to fins 206-1, 206-2, 206-5, 206-3, and 206-7, respectively.

[0044] Epi regions 222-1 through 222-5 and 224-1 through 224-6 may include any suitable material according to embodiments described herein.

[0045] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material) where the grown semiconductor material (crystalline film layer) has substantially the same crystalline properties as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set such that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around the surface such that the depositing atoms orient themselves in the crystalline arrangement of the atoms of the deposition surface. Thus, epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, epitaxially grown semiconductor material deposited on a {100} oriented crystal plane will acquire a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective to forming on the semiconductor surfaces and generally does not deposit materials such as silicon dioxide or silicon nitride on exposed surfaces.

[0046] Source / drain epitaxy may be performed by UltraHigh Vacuum Chemical Vapor Deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), MetalOrganic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Limited Reaction Processing CVD, or Molecular Beam Epitaxy (MBE). Epitaxial material may be grown from gas or liquid precursors. Epitaxial material may be grown using Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), or other suitable processes. Depending on the type of transistor, epitaxial silicon, silicon germanium (SiGe) or carbon doped silicon (Si:C) or combinations thereof may be doped during deposition (in situ doped) by adding dopants such as N-type dopants (e.g. phosphorus or arsenic) or P-type dopants (e.g. boron or gallium). The dopant concentration in the source / drain is approximately 1×10 19 cm -3 From about 2 × 10 21 cm -3 up to about 2×10 20 cm -3 and about 1×10 21 cm -3 When Si:C is grown epitaxially, the Si:C layer may contain carbon in the range of 0.2% to 3.0%. When SiGe is grown epitaxially, the SiGe may have a germanium content of 5% to 80%, preferably between 20% and 60%.

[0047] The memory cell 200 further includes a dielectric layer 226 that insulates the upper and lower FET sets. The dielectric layer 226 may include any suitable material (e.g., SiO2) in accordance with embodiments described herein.

[0048] The memory cell 200 further includes a number of spacer layers 228. The number of spacer layers 228 may include any suitable spacer material according to embodiments described herein.

[0049] Memory cell 200 further includes a shallow trench isolation (STI) region 230 and an interlayer dielectric (ILD) layer 240. STI region 230 and ILD layer 240 may include any suitable dielectric material according to embodiments described herein.

[0050] The memory cell 200 further includes an insulator layer 234 that provides NP isolation. The insulator layer 234 can include any suitable material according to embodiments described herein. For example, the insulator layer 234 can include, for example, a nitride material.

[0051] The memory cell 200 further includes a GND contact 210-2, a VDD contact 212-1, a WL contact 214-2, a BL contact 216-12, and a cross-coupled connection 218-2.

[0052] The FET corresponding to fin 206-1 may correspond to a passgate FET, the FETs corresponding to fins 206-2 and 206-6 may correspond to an inverter, and the FET corresponding to fin 206-5 may correspond to an unconnected floating FET. Thus, merged bottom epi region 222-1 may be used to contact the passgate FET to the inverter FET, merged top epi region 224-3 may assist in cross-coupling, and isolated bottom epi region 222-3 may correspond to the inverter ground.

[0053] Figures 5-17 illustrate a portion of a process flow for fabricating a semiconductor device 300 that includes a three-dimensional stacked vertical FET architecture, such as device 200 described above with reference to Figures 2-4. In one embodiment, the bottom FET includes an nFET and the top FET includes a pFET.

[0054] Referring to Figures 5-7, Figure 5 provides a top-down view of device 300, Figure 6 provides a cross-sectional view of device 300 shown in Figure 5 along line C-C', and Figure 7 provides a cross-sectional view of device 300 shown in Figure 5 along line D-D'.

[0055] As shown, the device 300 includes a substrate 302. The substrate 302 may include any suitable substrate structure, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. In one example, the substrate 302 may include a silicon-containing material. Illustrative examples of Si-containing materials include, but are not limited to, Si, SiGe, SiGeC, SiC, and multiple layers thereof. Although silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials, such as germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, and the like, may be employed as additional layers.

[0056] The device 300 includes a plurality of upper level fin structures including an upper level fin 310, a cap layer 312, and a liner 314 formed on sidewalls of the upper level fin 310 and the cap layer 312. The liner 314 may include any suitable material for protecting the upper level fin 310 during downstream processing. The device 300 further includes a plurality of lower level fins 316 separated from the upper level fin 310 by an insulator layer 318. The fins 310, 316 and the insulator layer 318 may be formed from the substrate 302 using any suitable process according to the embodiments described herein. For example, the fins 310, 316 and the insulator layer 318 may be formed by etching through an SOI substrate, where the upper level fin 310 is formed from a semiconductor layer, the lower level fin 316 is formed from a base substrate layer, and the insulator layer 318 is formed from an insulator layer disposed between the base substrate layer and the semiconductor layer. In one embodiment, the lower tier fins 316 may correspond to nFETs and the upper tier fins 310 may correspond to pFETs, however, such an embodiment should not be considered limiting.

[0057] As further shown, lower level fin 316 is formed on lower level source / drain epi region 320, and STI region 322 is disposed on substrate 302 between lower level source / drain epi region 320. Lower level source / drain epi region 320 and STI region 322 may be formed from substrate 302 using any suitable process according to embodiments described herein.

[0058] The device 300 further includes a lower tier gate stack 324, a lower tier lower spacer layer 326-1, and an ILD layer 308 formed around each one of the lower fins 316, in one embodiment, similar to the spacer layer 228 and ILD layer 240 described above with reference to Figures 2-4. In one embodiment, the lower tier gate stack 324 corresponds to an nFET gate. The lower tier gate stack 324 may be formed using any suitable process according to the embodiments described herein. For example, the lower tier gate stack 324 may be formed by depositing gate stack materials including a gate dielectric and a gate conductor (e.g., high-k dielectric material and WFM), forming an ILD layer 322, and etching the exposed gate stack material. After forming the lower tier gate stack 324, a lower tier upper spacer layer 326-2 may then be formed.

[0059] The device 300 further includes a lower tier upper source / drain epi region 328 formed around each of the lower fins 316. A drive-in anneal process may be performed to form the junctions.

[0060] Device 300 further includes sacrificial layers 330-1 and 330-2 for source / drain contacts. Sacrificial layers 330-1 and 330-2 may be formed by forming a sacrificial fill, forming respective mask layers, and etching exposed portions of sacrificial layers 330-1 and 330-2. Sacrificial layers 330-1 and 330-2 may include any suitable material in accordance with embodiments described herein. For example, sacrificial layers 330-1 and 330-2 may include, for example, an oxide material.

[0061] 8 and 9, an insulator layer 332 is formed to provide NP isolation. The insulator layer 332 may include any suitable material (e.g., a nitride material) according to embodiments described herein. As further shown, the liner 314 is removed, a second liner 334 is formed, and an upper tier lower source / drain epi region 336 is formed around each of the upper fins 310. The upper tier lower source / drain epi region 336 may be formed using any suitable process according to embodiments described herein. For example, the upper tier lower source / drain epi region 336 may be formed by removing the liner 314 (shown in FIGS. 6 and 7), forming a sacrificial dielectric layer (not shown) on the insulator layer 332, forming the second liner 334 on the dielectric layer, removing the sacrificial dielectric layer, and forming the upper tier lower source / drain epi region 336 on the insulator layer 332 below the second liner 334 adjacent to the upper fin 310. The liner 338 may then be formed.

[0062] 10 and 11, a portion of the liner 338 is removed to form an upper level lower spacer 340-1, an ILD layer 342, an upper level gate stack 344, an upper level upper spacer 340-2, an upper level upper source / drain region 346, and an ILD layer 348.

[0063] 12 and 13, openings 350-1 and 350-2 are formed in liners 330-1 and 330-2, respectively. According to embodiments described herein, openings 350-1 and 350-2 may be formed using any suitable etching process, such as reactive ion etching (RIE).

[0064] 14 and 15, the liners 330-1, 330-2, and 338 are removed to form voids 352-1, 352-2. Any suitable process may be used to remove the liners 330-1, 330-2, 338 in accordance with embodiments described herein.

[0065] 16 and 17, the voids 352-1 and 352-2 are filled with a conductive material to form contacts 354-1 and 354-2, respectively. Examples of suitable conductive materials that can be used to form the contacts 354-1 and 354-2 include, but are not limited to, Cu, W, Ru, Co, Al, etc. The contacts 354-1 and 354-2 correspond to cross couplings.

[0066] Referring to FIG. 18, a block / flow diagram illustrating a system / method 400 for fabricating a semiconductor device including stacked vertical transistor memory cells, according to an embodiment, is shown.

[0067] At block 410, a lower level of stacked transistor memory cells is provided. The lower level may include a plurality of lower vertical transistors having merged upper source / drains. The plurality of lower vertical transistors may include a first non-floating transistor, a second non-floating transistor, a first floating transistor, and a second floating transistor. The floating transistor may have at least one terminal electrically isolated from other transistors of the stacked vertical transistor memory cell.

[0068] At block 420, cross couplings between the lower and upper tiers of stacked vertical transistor memory cells are formed. The upper tier may include a plurality of upper vertical transistors having merged lower source / drain epitaxial regions ("epi"). The plurality of upper vertical transistors may include a first upper vertical transistor, a second upper vertical transistor, a third upper vertical transistor, and a fourth upper vertical transistor.

[0069] The plurality of lower vertical transistors further include respective lower source / drain epitaxial layers, and the plurality of upper vertical transistors further include respective upper source / drain epitaxial layers. The lower source / drain epitaxial layers and the upper source / drain epitaxial layers may be separated by a dielectric layer. The lower and upper levels may be insulated by an insulator layer.

[0070] The plurality of lower vertical transistors may include N-type field effect transistors (nFETs) and the plurality of upper vertical transistors include P-type field effect transistors (pFETs).

[0071] The step of forming cross-couplings between the lower and upper tiers may include forming merged upper source / drain epi connections between the first non-floating and floating transistors and between the second non-floating and floating transistors, forming merged lower source / drain epi connections between the first and third upper vertical transistors and between the second and fourth upper vertical transistors, forming metal gate-to-epi connections between the first non-floating transistor and the second floating transistor and between the second non-floating transistor and the first floating transistor, and forming metal gate-to-epi connections between the first and second upper vertical transistors and between the third and fourth upper vertical transistors.

[0072] The lower and upper levels may further include respective gate structures. Forming the cross-coupling may further include contacting the gate structures of the lower and upper levels.

[0073] Further details regarding blocks 410 and 420 are provided above with reference to FIGS.

[0074] While preferred embodiments of a semiconductor device and method for its manufacture have been described, which are intended to be illustrative and not limiting, it should be noted that modifications and variations may be made by those skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Thus, while aspects of the invention have been described with the detail and particularity required by the patent laws, what is desired to be claimed and protected by Letters Patent is set forth in the appended claims.

[0075] In a preferred embodiment of the invention described herein, a stacked vertical transistor memory cell includes a lower tier including a plurality of lower vertical transistors including N-type field effect transistors (nFETs) having merged upper source / drain epitaxial regions (epi) and gate structures, the plurality of lower vertical transistors including first and second non-floating transistors and first and second floating transistors, the first and second floating transistors having at least one terminal electrically isolated from other transistors of the stacked vertical transistor memory cell; and an upper tier including a plurality of upper vertical transistors including P-type field effect transistors (pFETs) having merged lower source / drain epi and gate structures, the plurality of upper vertical transistors including first, second, third and fourth non-floating transistors and first and second floating transistors having at least one terminal electrically isolated from other transistors of the stacked vertical transistor memory cell. and a fourth upper vertical transistor, and cross couplings contacting gate structures of the upper and lower tiers, the cross couplings including merged upper source / drain epi connections between the first non-floating and floating transistors and between the second non-floating and floating transistors, merged lower source / drain epi connections between the first and third upper vertical transistors and between the second and fourth upper vertical transistors, metal gate-to-epi connections between the first non-floating transistor and the second floating transistor and between the second non-floating transistor and the first floating transistor, and metal gate-to-epi connections between the first and second upper vertical transistors and between the third and fourth upper vertical transistors. The plurality of lower vertical transistors may further include respective lower source / drain epi, and the plurality of upper vertical transistors further include respective upper source / drain epi. The device further includes a dielectric layer separating the lower source / drain epi and the upper source / drain epi, and an insulator layer separating the lower and upper levels. The device further includes wordline contacts, bitline contacts, voltage contacts, and ground contacts.

Claims

1. 1. A stacked vertical transistor memory cell, comprising: a lower tier including a plurality of lower transistors including at least one non-floating transistor and at least one floating transistor having merged upper source / drain epitaxial regions, the at least one floating transistor having at least one terminal electrically isolated from other transistors of the stacked vertical transistor memory cell; an upper tier including at least two upper transistors having merged lower source / drain epitaxial regions; cross coupling including an epitaxial region connection between the upper layer and the lower layer and a gate to epitaxial region connection; The stacked vertical transistor memory cell includes 13. A semiconductor device comprising:

2. the plurality of lower transistors includes a plurality of lower vertical transistors having the upper source / drain epitaxial regions merged, the plurality of lower vertical transistors including a first non-floating and floating transistor and a second non-floating and floating transistor; the at least two upper transistors include first, second, third and fourth upper vertical transistors having the lower source / drain epitaxial regions merged together; The device of claim 1 .

3. The cross coupling is epitaxial region connections between the first non-floating and floating transistors and between the second non-floating and floating transistors through the merged upper source / drain epitaxial region; epitaxial region connections between the first and third upper vertical transistors and between the second and fourth upper vertical transistors through the merged lower source / drain epitaxial region; metal gate to epitaxial region connections between the first non-floating transistor and the second floating transistor and between the second non-floating transistor and the first floating transistor; metal gate to epitaxial region connections between the first and second upper vertical transistors and between the third and fourth upper vertical transistors; The device of claim 2 , comprising:

4. The device of claim 2 , wherein the plurality of lower vertical transistors comprise n-type field effect transistors (nFETs) and the at least two upper transistors comprise p-type field effect transistors (pFETs).

5. 3. The device of claim 2, wherein said plurality of lower vertical transistors further comprises respective lower source / drain epitaxial regions, and said at least two upper transistors further comprise respective upper source / drain epitaxial regions.

6. 6. The device of claim 5 further comprising a dielectric layer separating said lower source / drain epitaxial region and said upper source / drain epitaxial region, and an insulator layer separating said lower level and said upper level.

7. 10. The device of claim 1 further comprising a wordline contact, a bitline contact, a supply voltage contact and a ground contact.

8. The device of claim 1 , wherein the cross coupling contacts gate structures of the lower and upper levels.

9. 1. A method for manufacturing a semiconductor device, comprising: forming a stacked vertical transistor memory cell, the stacked vertical transistor memory cell including a lower tier including a plurality of lower transistors including at least one non-floating transistor and at least one floating transistor having merged upper source / drain epitaxial regions, and an upper tier including at least two upper transistors having merged lower source / drain epitaxial regions, the at least one floating transistor having at least one terminal electrically isolated from other transistors of the stacked vertical transistor memory cell; forming the stacked vertical transistor memory cell comprises: forming cross-couplings including epitaxial region connections between the upper and lower tiers and gate to epitaxial region connections; A manufacturing method comprising:

10. the plurality of lower transistors includes a plurality of lower vertical transistors having the upper source / drain epitaxial regions merged, the plurality of lower vertical transistors including a first non-floating and floating transistor and a second non-floating and floating transistor; the at least two upper transistors include first, second, third and fourth upper vertical transistors having the lower source / drain epitaxial regions merged together; 10. The method of claim 9.

11. The step of forming a cross-coupling includes: forming epitaxial region connections through the merged upper source / drain epitaxial region between the first non-floating and floating transistors and between the second non-floating and floating transistors; forming epitaxial region connections between the first and third upper vertical transistors and between the second and fourth upper vertical transistors through the merged lower source / drain epitaxial region; forming metal gate-to-epitaxial region connections between the first non-floating and second floating transistors and between the second non-floating and first floating transistors; forming metal gate-to-epitaxial region connections between the first and second upper vertical transistors and between the third and fourth upper vertical transistors; The method of claim 10, comprising:

12. 11. The method of claim 10, wherein the plurality of lower vertical transistors comprise n-type field effect transistors (nFETs) and the at least two upper transistors comprise p-type field effect transistors (pFETs).

13. 11. The method of claim 10, wherein the plurality of lower vertical transistors further include respective lower source / drain epitaxial regions, and the at least two upper transistors further include respective upper source / drain epitaxial regions.

14. 14. The method of claim 13, wherein the lower source / drain epitaxial region and the upper source / drain epitaxial region are separated by a dielectric layer, and the lower level and the upper level are separated by an insulator layer.

15. 10. The method of claim 9, further comprising wordline contacts, bitline contacts, supply voltage contacts and ground contacts.

16. 10. The method of claim 9, wherein forming the cross-coupling comprises contacting gate structures of the lower level and the upper level.

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