Capacitorless DRAM Cell

Abstract

The present invention relates to a capacitorless DRAM cell comprising a heterostructure, a gate structure adjacent to the heterostructure in a first direction, a drain structure adjacent to the heterostructure in a second direction perpendicular to the first direction, and a source structure adjacent to the heterostructure in a direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and barrier layers being alternately stacked in the first direction.

Description

[Technical field]

[0001] The present invention relates to integrated semiconductor memory devices, and more particularly to capacitorless dynamic random access memory (DRAM) cells. [Background technology]

[0002] DRAM stores data as a positive or negative charge in a capacitive structure. The structures that provide the capacitance, and the transistors that control access to it, are collectively called DRAM cells. They are the basic building blocks within a DRAM array. Although multiple DRAM memory cell variants exist, the variant most commonly used in modern DRAMs is the one transistor, one capacitor (1T1C) cell. A transistor is used to drive current into the capacitor during a write operation and to discharge the capacitor during a read operation. Summary of the Invention

[0003] In one aspect, the invention relates to a capacitorless DRAM cell comprising a heterostructure, a gate structure adjacent the heterostructure in a first direction, a drain structure adjacent the heterostructure in a second direction perpendicular to the first direction, and a source structure adjacent the heterostructure in a direction opposite the second direction. The heterostructure comprises one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and barrier layers being alternately stacked in the first direction.

[0004] An embodiment of a capacitor-less DRAM cell ("cell" for short) may have advantages resulting from a heterostructure replacing a traditional MOSFET-type channel. Each channel layer may further be considered as a volume of material that can store or allow transport of charge carriers (electrons or holes or both) in a positive or negative second direction depending on the settings of voltages applied to the adjacent source, gate and drain structures, while each barrier layer is electrically insulating and therefore can prevent the transport of charge carriers across the barrier layer, i.e., in a positive or negative first direction. As a result, each barrier layer can contribute to increasing the retention time of electrons and / or holes by suppressing or preventing loss effects (e.g., due to recombination or tunneling out of the heterostructure) that accompany the movement of charge carriers in a positive or negative first direction.

[0005] In one embodiment, the heterostructure comprises a single barrier layer and two channel layers. In combination with alternative configurations of channel layers and barrier layers in the heterostructure, this means that the barrier layer separates the two channel layers into one channel layer facing the gate structure and one channel layer facing away from the gate structure. For example, if a negative voltage is applied to the gate structure, the gate structure will attract holes and repel electrons, and therefore the channel layer facing the gate structure can be called the "hole channel" and the channel layer facing away from the gate structure can be called the "electron channel". Alternatively, if a positive voltage is applied to the gate structure, the gate structure will attract electrons and repel holes, and therefore in this case the channel layer facing the gate structure can be called the "electron channel" and the channel layer facing away from the gate structure can be called the "hole channel".

[0006] In a further aspect, the present invention relates to a method for manufacturing a capacitor-less DRAM cell, the method comprising the steps of: forming a heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternately stacked in a first direction; forming a gate structure adjacent to the heterostructure in a first direction; forming a drain structure adjacent to the heterostructure in a second direction orthogonal to the first direction; forming a source structure adjacent to the heterostructure in a direction opposite the second direction.

[0007] In the following, embodiments of the invention are described in more detail, by way of example only, with reference to the drawings, in which: [Brief description of the drawings]

[0008] [Figure 1A] 1 is a schematic cross-sectional view of a capacitor-less DRAM cell storing a logic state "0." [Figure 1B] 1 is a schematic cross-sectional view of a capacitor-less DRAM cell storing a logic state "1." [Figure 1C] FIG. 1 is a diagram of two IV curves of a capacitor-less DRAM cell. [Figure 1D] 1 is a schematic cross-sectional view of a capacitor-less DRAM cell during a write operation for a logic state "0." [Figure 1E] 1 is a schematic cross-sectional view of a capacitor-less DRAM cell during a write operation for a logic state "1." [Diagram 2] 1 is a schematic cross-sectional view of an exemplary capacitor-less DRAM cell featuring a barrier layer connecting a gate structure and a channel layer. [Diagram 3] 1 is a schematic cross-sectional view of an exemplary capacitor-less DRAM cell featuring a barrier layer connecting two channel layers. [Figure 4] 1 is a schematic cross-sectional view of an exemplary capacitor-less DRAM cell featuring a barrier layer connecting a substrate and a channel layer. [Diagram 5]1 is a schematic cross-sectional view of an exemplary capacitor-less DRAM cell featuring two barrier layers and a channel layer. [Figure 6] 1 is a schematic cross-sectional view of an exemplary capacitor-less DRAM cell featuring three barrier layers and two channel layers. [Figure 7A] FIG. 1 is a diagram of two input signals for testing a capacitor-less DRAM cell. [Figure 7B] 1 is a diagram of an output signal of a capacitor-less DRAM cell in response to receiving two input signals for testing. [Figure 7C] 1 is a diagram of an output signal of a capacitor-less DRAM cell in response to receiving two input signals for testing. [Figure 7D] 1 is a diagram of an output signal of a capacitor-less DRAM cell in response to receiving two input signals for testing. [Figure 8] FIG. 13 illustrates the drain current response of a capacitor-less DRAM cell tested using two input signals. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The last few decades have triggered considerable research efforts to reduce the memory cell size of volatile memories such as DRAM. As of today, DRAM cells are limited in size by their external capacitors. One promising approach to enable further miniaturization is to eliminate the capacitor and instead use the blind capacitance of a transistor to store the charge carriers that represent the information. Typically, the transistor structure used in DRAM cells is a derivative of the metal-oxide-semiconductor field-effect transistor (MOSFET) that implements a sequentially arranged source, channel, and drain structure, as well as a gate structure adjacent to the channel structure.

[0010] Several candidates for such a capacitor-less one-transistor ("1T") DRAM cell have been proposed, such as ARAM and MSDRAM. These devices use the so-called floating body effect to inject holes and electrons into the channel by band-to-band tunneling when the gate and drain or gate and source are subjected to bias voltages of opposite sign. During the subsequent retention time, a sufficient fraction of the injected charge carriers remain in the channel and the cell state can be read out using a memory effect on the drain-source current flowing through the transistor. This promising concept has already been used to demonstrate a functional 1T DRAM cell and is considered just one of several ways to advance towards DRAM scaling.

[0011] Key challenges for this technology include increasing the hole retention time and increasing the drain-source current (or alternatively, reducing the required driving bias voltage). Another challenge is scalability; the total channel thickness typically cannot be scaled significantly since the recombination rate increases with charge carrier density.

[0012] Several designs of capacitorless DRAM cells have been demonstrated. As of today, increases in charge carrier retention time and drain-source current are desirable to reach full market viability.

[0013] For purposes of clarity, several terms used or conditions implied throughout this disclosure are defined below.

[0014] The materials used in the heterostructure of the capacitorless DRAM cell also include semiconductors and insulators. Each semiconductor channel layer can be a pure (undoped) semiconductor, an intrinsic semiconductor (doped or undoped i-type with equal numbers of excited electrons n and holes p), or a doped (10 18 cm -3Each insulating (non-conducting) barrier layer can be made of a material whose electrical conductivity can be increased using techniques such as doping or gating.

[0015] The capacitor-less DRAM cell is characterized by a heterostructure comprising channel and barrier layers that are alternately superimposed in a first direction. The terms "superimpose," "superimposed," and the like do not necessarily imply that the first direction coincides with vertical. In fact, it may be possible to stack layers of the heterostructure on top of each other in any first direction, including horizontally.

[0016] The memory cell may be, but is not necessarily, formed on a substrate such as a semiconductor wafer. In particular, the memory cell may be a semiconductor-on-insulator (SOI) device. When formed on a substrate, the substrate may be provided with a bias voltage, i.e., the substrate may be used as a second gate or back gate. Similarly, the source structure, gate structure, drain structure, and, if applicable, the substrate may be realized with electrical contacts to allow for the provision of a (bias) voltage and / or the establishment of a current, and may comprise any suitable known or future structure of materials such as n-type doped semiconductors, p-type doped semiconductors, intrinsic semiconductors, or i-type semiconductors, metals, high-k or low-k dielectrics, or insulators, or combinations thereof, adapted to realize the source, gate, drain, and optionally the back gate of a field effect transistor, respectively.

[0017] A capacitor-less DRAM cell can be operated as follows: Charge carriers present in the channel layer of the heterostructure can encode at least two states of a bit of information, "1" and "0". In a non-limiting, purely illustrative example, a write "1" operation can include applying a negative voltage to the gate structure and a positive voltage to the drain structure, whereby holes are injected by band-to-band tunneling into the channel layer or region facing towards the gate structure and electrons are injected by band-to-band tunneling into the channel layer or region facing away from the gate structure. The number of injected electrons is electrostatically coupled to the number of injected holes. The charge carriers stay in the heterostructure for some time due to the floating substrate effect. In an example, a write "0" operation includes emptying the heterostructure of charge carriers by a nearly flat band bias condition (i.e., setting the gate structure to a slightly positive voltage and the source and drain structures to zero voltage).

[0018] During a read operation, a small drain bias is applied and the drain current is measured. An excess of charge carriers inside the heterostructure in the "1" state results in an increase in the drain current compared to the current in the "0" state. In the example, state "0" or "1" is further preserved by applying a negative bias voltage to the gate structure. If the cell is implemented on the back gate, it is set for a positive back gate bias voltage throughout the example.

[0019] According to one embodiment, the heterostructure comprises a single barrier layer and a single channel layer. In combination with alternative configurations of the channel layer and the barrier layer in the heterostructure, this means that the barrier layer insulates the channel layer from the gate structure or any structure adjacent to the heterostructure on the side facing away from the gate structure. This can bring the benefit of increasing the charge carrier retention time by suppressing the spontaneous migration and / or tunneling of charge carriers out of the heterostructure and / or by suppressing their spontaneous recombination with further charge carriers from any structure adjacent to the heterostructure in the positive or negative first direction.

[0020] According to one embodiment, the heterostructure comprises two barrier layers and two channel layers. In combination with alternative configurations of the channel layers and barrier layers in the heterostructure, this means that one of the barrier layers separates the two channel layers from each other and the other of the barrier layers insulates the barrier layer facing the gate structure from the gate structure or the barrier layer facing away from the gate structure from further structures adjacent to the heterostructure. This can have the advantage of increasing the charge carrier retention time and / or improving the ability to miniaturize due to the barrier layers separating the two channel layers by suppressing the spontaneous migration and / or tunneling of charge carriers out of the heterostructure and / or by suppressing their spontaneous recombination with further charge carriers from any structures adjacent to the heterostructure in a positive or negative first direction. The configuration in which one of the barrier layers is located in said position facing away from the gate structure can be useful when the gate structure includes an oxide layer or other insulating layer adjacent to the heterostructure that already provides a substantial suppression of charge carrier migration out of the heterostructure.

[0021] According to one embodiment, the heterostructure comprises at least two barrier layers made of different barrier layer materials. The choice of different barrier layer materials may include, but is not limited to, the materials mentioned herein as suitable for making a barrier layer. The realization of barrier layers made of different barrier layer materials may bring the benefit of an improved ability to restrict the movement of charge carriers in the heterostructure in a first direction, positive or negative. More precisely, some or all of the barrier layers may be made of barrier layer materials that suppress the movement of one type of charge carriers (i.e. electrons or holes) more effectively than the other.

[0022] This may be useful when, during operation of the cell, some type of charge carriers that are typically selectively restricted by a given barrier layer can be expected to be localized at the location of the barrier layer. For example, if a cell is designed to maintain the cell in its programmed state, i.e., to maintain a set of injected charge carriers representing a "0" or "1" state inside the heterostructure, by applying a negative voltage to the gate structure, any injected holes can be expected to migrate near the gate structure, i.e., near the channel layer facing the gate structure, while the corresponding injected electrons can be expected to migrate to the side of the heterostructure opposite the gate structure, i.e., to the channel layer facing away from the gate structure. In this example, it may be possible to keep the holes confined to their hole channel layer by providing a barrier layer between the gate structure and the hole channel layer that is selectively opaque to holes, or to keep the electrons confined to their electron channel layer by providing a barrier layer that is selectively opaque to electrons between any structure adjacent to the heterostructure on the other side of the gate structure and the electron channel layer, or both. The particular choice of selectively impermeable barrier layer material may depend on the material making up the respective channel layer being insulated or any other structures adjacent to a given barrier layer.

[0023] According to one embodiment, the heterostructure comprises at least two channel layers made of different channel layer materials. The selection of different channel layer materials may include, but is not limited to, the materials mentioned herein as suitable for making channel layers. The realization of channel layers made of different channel layer materials can provide the possibility of designing part or all of the channel layers with specific properties that are customized for one type of charge carrier (i.e., electrons or holes).

[0024] For example, it may be possible to optimize a heterostructure that features two channel layers in the direction of increasing charge carrier mobility in each channel layer, i.e., choosing a channel layer material with high electron mobility for one of the channel layers and a channel layer material with fast apparent hole migration for the other channel layer. This can increase the conductivity of the heterostructure in the second direction, positive or negative, and thus increase the drain-source current of the cell. However, other criteria that may be specific or non-specific for some types of charge carriers, such as spin properties that affect the charge carriers or crystal lattice properties that help their compatibility with neighboring structures, may be taken into account to select the appropriate different channel layer materials.

[0025] Achieving different channel layers with charge carrier-specific properties can be useful when some types of charge carriers that are typically selectively stored in a given channel layer during operation of the cell can be expected to be localized at the location of the channel layer. For example, if a cell is designed to maintain the cell in its programmed state, i.e., to maintain a set of injected charge carriers representing a "0" or "1" state inside the heterostructure, by applying a negative voltage to the gate structure, any injected holes can be expected to migrate near the gate structure, i.e., near the channel layer facing the gate structure, while the corresponding injected electrons can be expected to migrate to the side of the heterostructure opposite the gate structure, i.e., to the channel layer facing away from the gate structure. In this example, it can be possible to select a material with the desired properties for holes as the channel layer material for the channel layer facing the gate structure, or a material with the desired properties for electrons as the channel layer material for the channel layer facing away from the gate structure, or both. The particular choice of selectively optimized channel layer material may be dependent on the material making up the adjacent barrier layer that insulates a given channel layer, or any other structure adjacent to a given channel layer.

[0026] According to one embodiment, the different channel layer materials differ in band gap energy by at least 0.5 electron volts. This may allow for optimizing some or all of the channel layers by band gap engineering. For example, a channel layer material with a lower band gap energy (or more generally, a similarly lower band gap energy, or in other words, a similarly narrow band gap) may be used to realize a channel layer that is dedicated to hole transport, since a narrower band gap can increase the apparent hole transport rate by tunneling. This allows for shorter times to inject and clear holes from the dedicated hole channel layer, thus increasing the read / write cycle time of the cell.

[0027] According to one embodiment, the different channel layer materials differ in electron mobility by at least a factor of 10. This may make it possible to dedicate one or more of the channel layers (i.e., those with higher electron mobility) to realize a channel layer that is dedicated to electron transport. This may make it possible to increase the drain-source current of the cell, for example, when it can be used during reading.

[0028] According to one embodiment, the gate structure is adjacent to one of the barrier layers. In this way, the channel layer of the heterostructure can be insulated from the gate structure so that the accumulation of gate current can be prevented. It is noted that in this case where the barrier layer is adjacent to the gate structure, it may be unnecessary to provide the gate structure with a gate insulator layer (e.g., an oxide layer), as is typically done today throughout FET manufacturing. This can result in a simplification of the manufacturing process of the capacitor-less DRAM cell. Furthermore, this can prevent or hinder the spontaneous migration of charge carriers into the gate structure or tunneling out of the heterostructure, or prevent or hinder the spontaneous recombination with charge carriers from the gate structure, or both.

[0029] According to one embodiment, the gate structure comprises a gate insulator layer adjacent to the barrier layer. The gate insulator layer may be made of an electrical insulator, such as an oxide, and may prevent exchange of charge carriers between the heterostructure and the gate structure in order to allow control of charge carriers in the heterostructure by field effect when the gate structure is biased. As mentioned above, if the heterostructure is adjacent to the gate structure with a barrier layer, it may not be necessary to provide the gate structure with a gate insulator layer, but it may still be useful to realize the gate structure with an additional gate insulator layer, since it may increase the total insulator thickness between the channel layer facing the gate structure and the conductive material realized in the gate structure in order to allow the gate structure to be set to a desired voltage. A higher total insulator thickness may reduce the probability of leakage current between the gate and the heterostructure, or may allow a higher voltage to be supplied to the gate structure, or both.

[0030] According to one embodiment, the cell is disposed on a substrate and the heterostructure is adjacent to the substrate, which increases the mechanical stability of the cell and provides the possibility to apply a back-gate voltage to the heterostructure, making the capacitor-less DRAM cell a double-gate device.

[0031] According to one embodiment, one of the barrier layers is adjacent to the substrate. In this way, the channel layer of the heterostructure can be insulated from the substrate so that the accumulation of back-gate current can be prevented. It is noted that in this case where the barrier layer is adjacent to the substrate, it may be unnecessary to provide the substrate with a substrate insulator layer (e.g., a buried oxide layer), as is often done today in the manufacture of semiconductor-on-insulator (SOI) devices. This can result in a simplification of the manufacturing process of the capacitor-less DRAM cell. Furthermore, this can prevent or hinder the spontaneous migration of charge carriers into the heterostructure or tunneling out to the substrate, or prevent or hinder spontaneous recombination with charge carriers from the substrate, or both.

[0032] According to one embodiment, the substrate comprises a substrate insulator layer and a heterostructure adjacent to the substrate insulator layer. The substrate insulator layer can be made of an electrical insulator, such as, but not limited to, an oxide, including a buried oxide layer, and can prevent exchange of charge carriers between the heterostructure and the substrate. This can be beneficial to realize the substrate as a back-gate structure, to allow control of charge carriers in the heterostructure by field effect when the back-gate structure is biased. As mentioned above, if the heterostructure is adjacent to the substrate using a barrier layer, it may not be necessary to provide the substrate with a substrate insulator layer, but if the substrate realizes a back-gate structure, it may still be useful to realize the back-gate structure with an additional gate insulator layer, since this can increase the total insulator thickness between the channel layer facing the back-gate structure and the conductive material realized in the back-gate structure, to allow the back-gate structure to be set to a desired voltage. A higher total insulator thickness can reduce the probability of leakage current between the back-gate and the heterostructure, or can allow a higher voltage to be supplied to the back-gate structure, or both.

[0033] According to one embodiment, the gate structure is adjacent to the heterostructure only in a first direction. This may allow a more uniformly directed electric field to be exerted on the heterostructure when a voltage bias is applied to the gate structure. This may therefore reduce the possibility of leakage current due to charge carriers bypassing the barrier layer due to field asymmetry.

[0034] According to one embodiment, the gate structure fills the heterostructure, which prevents the gate structure from undercutting the heterostructure and therefore increases the efficiency of charge carrier injection, retention and drainage. In other words, the number and velocity of charge carriers can be increased during injection, the retention time of charge carriers in the heterostructure can be increased, and drainage of charge carriers from the heterostructure can be accelerated compared to cells with gate structures that undercut the heterostructure.

[0035] According to one embodiment, the gate structure is aligned with the heterostructure in a second direction and in a direction opposite to the second direction. This prevents the gate structure from both undercutting the heterostructure and overlapping the source and / or drain structures. Avoiding undercut gate structures can increase the efficiency of charge carrier injection, retention, and ejection as described above, while avoiding overlapping gate structures can reduce the probability of influencing charge carriers in the source and / or drain regions by field effects, thus increasing the drain-source current.

[0036] According to one embodiment, each channel layer and each barrier layer is adjacent to both the source and drain structures, which can reduce the probability of leakage current caused by charge carriers in the heterostructure bypassing the barrier layers.

[0037] According to one embodiment, each barrier layer is made of a barrier layer material selected from the group consisting of silicon, silicon oxide, indium oxide, and indium phosphide for each barrier layer. According to one embodiment, each channel layer is made of a channel layer material selected from the group consisting of indium arsenide, gallium arsenide, indium gallium arsenide, indium tin oxide, germanium, and silicon germanium for each channel layer.

[0038] These materials can enable efficient storage and transport of charge carriers in the heterostructure. It can be useful to adjoin chemically or crystallographically or both similar materials in the heterostructure to reduce the probability of defects in the crystal structure. In an illustrative example, the heterostructure comprises a channel layer made of indium gallium arsenide, adjacent by a barrier layer made of indium oxide, adjacent by a channel layer made of indium arsenide. It is emphasized that the capacitor-less DRAM cells disclosed herein are generally material-agnostic, primarily with respect to the structure of the cell.

[0039] According to one embodiment, the heterostructure has a total length measured in the second direction of 1 nanometer to 75 nanometers. This dimension range can enable the cell to operate with higher read / write cycle speeds and / or lower voltages applied to the source, gate, or drain structures or a combination thereof, and can reduce the probability of electrostatic induction between the source and drain.

[0040] According to one embodiment, the thickness of each channel layer measured in the first direction is 1.5 to 5 times the thickness of each barrier layer measured in the first direction. This dimension range can result in the channel layer having additional volume to store charge carriers, thus increasing the capacitance of the heterostructure. This can also result in an increase in the difference and / or ratio of the read drain currents representing the "1" and "0" states of the cell.

[0041] Turning now to the drawings, FIG. 1 illustrates the general principle of operation of a capacitorless DRAM cell. FIGS. 1A, 1B, 1D, and 1E each show a schematic cross-sectional view of a capacitorless DRAM cell 100. The cell 100 is formed on a substrate 102 and includes a source structure 104, a channel structure 110, a drain structure 108, and gate structures 106, 107. The source structure 104 and the drain structure 108 are adjacent to the channel structure 110. The source structure 104, the channel structure 110, and the drain structure 108 are adjacent to the substrate 102. The gate structures 106, 107 include a gate electrode 106 and a gate insulator 107 connecting the gate electrode 106 and the channel structure 110. The source structure 104, the gate electrode 106, and the drain structure 108, and the substrate 102 are coupled to a source voltage V S to the source structure 104 and a front gate voltage V FG is supplied to the gate electrode 106, and a drain voltage V D to the drain structure 108 and a back gate voltage V BG is electrically contacted by a terminal for supplying the power to the substrate 102.

[0042] The cell 100 is adapted to encode logic states "0" and "1" by trapping holes (shown as small circles labeled "+") within the channel structure 110. S = 0V (Volts), V FG <0V, V D = 0V, and V BG1 and 2. The cell 100 is shown in a “hold” state, where a combination of V >0V is applied to maintain holes trapped in the channel structure 110. FG <0V and V BG <0V ensures that holes are collected near the gate insulator 107, and any electrons (shown as small circles labeled "-") are collected near the substrate 102. Figures 1A and 1B both show a significantly larger number of trapped electrons compared to the number of trapped holes. In the "0" state (Figure 1A), the number of holes is negligible compared to the number of electrons, while in the "1" state (Figure 1B), the number of holes and electrons both increase. Figure 1B also shows that the electrons occupy a significant amount of the volume of the channel structure 110, and thus the distributions of electrons and holes start to overlap.

[0043] Figure 1C shows the applied back-gate voltage V BG Drain-source current as a function of I DS FIG. 1C shows a diagram with two curves 130, 131 of V BG The measured curves are observed when the readout voltage V R The measured current I of curve 130 representing the "0" state is also shown to be set to DS =I0 is the measured current I of curve 131 representing the "1" state DS = Significantly lower than I1.

[0044] 1D and 1E show the cell 100 of FIGS. 1A and 1B, but with different voltage combinations applied to program the cell 100 with either a "0" state (FIG. 1D) or a "1" state (FIG. 1E). For clarity, electrons have been omitted in FIGS. 1D and 1E. The "0" state is represented by a V S = 0V, V FG >0V, V D = 0V, and V BG It is written by setting V >0V. FG >0V and V BGThe combination of >0V creates an attractive potential for electrons in the channel structure 110, allowing them to fill most of the channel structure 110 and recombine with any holes that may be present. Statistically, this corresponds to a lack of electrons at the boundaries of the channel structure 110 essentially outside of the electric field between the front gate structures 106, 107 and the substrate 102, which acts as a back gate, as well as in the source structure 104 and the drain structure 108. As a result, holes are concentrated in the source structure 104 and the drain structure 108 (indicated by arrows in FIG. 1D). In other words, the effect of the potential created inside the channel structure 110 is equivalent to a repulsive potential if holes were free charge carriers. Eventually, the "0" state is reached when the channel structure 110 is essentially depleted of holes.

[0045] 1E illustrates the injection of holes into the channel structure 110 during a write operation for a logic state "1." This state is achieved by applying a voltage V S = 0V, V FG <0V, V D >0V, and V BG >0V. The depletion region, which is devoid of free charge carriers, is indicated by the two dashed lines parallel to the boundary between the drain structure 108 and the channel structure 110 at the bottom of the drawing. V FG <0V and V D >0V causes the bound electrons in the depletion region to leave their carrying atoms, and V D >0V creates a potential that attracts electrons to tunnel into the conduction band of the drain structure 108. Similarly, the holes that are left behind are tunneled into the conduction band of the drain structure 108 by a front gate voltage V FG <0V, the holes are captured by the channel structure 110. The carrier generation process is indicated by the opposing arrows in the drawing. Eventually, the hole density in the channel structure 110 reaches saturation and a dynamic equilibrium or V D The "1" state is reached when is set back to 0V.

[0046] 2-6 each show a schematic cross-sectional view of an exemplary capacitor-less DRAM cell 200. In each figure, the illustrated cell 200 comprises a heterostructure, a gate structure 106, 107 adjacent to the heterostructure in a first direction, a drain structure 108 adjacent to the heterostructure in a second direction orthogonal to the first direction, and a source structure 104 adjacent to the heterostructure in a direction opposite the second direction. The heterostructure comprises one or more semiconductor channel layers 210, 310, 312, 410, 510, 610, 612 and one or more electrically insulating barrier layers 220, 320, 420, 520, 522, 620, 622, 624 in an alternating, stacked arrangement. Without limitation, the particular example illustrated by FIGS. 2-6 shows that the gate structures 106, 107 comprise a gate electrode 106 and a gate insulator layer 107 adjacent to the heterostructure, and that the components of the cell 200 are provided on a substrate 102. The detailed implementation of the heterostructures varies between figures and is described below.

[0047] 2, the heterostructure comprises a channel layer 210 and a barrier layer 220 connecting the channel layer 210 and the gate insulator layer 107. The insulating effect of the barrier layer 220 can hinder or prevent charge carriers (electrons or holes) that may be present in the channel layer 210 from leaving the channel layer 210 by migrating or tunneling to the gate structures 106, 107. Thus, the use of a channel layer 210 with a barrier layer 220 adjacent to the gate structures 106, 107 can result in an increased retention time of the charge carriers in the channel layer 210.

[0048] 3, the heterostructure comprises two channel layers 310, 312 and one barrier layer 320 connecting the channel layers 310 and 312. The insulating effect of the barrier layer 320 can hinder or prevent charge carriers that may be present in the channel layer 310 from leaving the channel layer 310 by migrating to the channel layer 312, and can hinder or prevent charge carriers that may be present in the channel layer 312 from leaving the channel layer 312 by migrating to the channel layer 310, and thus can hinder or prevent charge carriers that may be present in the channel layer 310 from recombining with charge carriers of the opposite charge that may be present in the channel layer 312. Thus, the utilization of two channel layers 310, 312 with one barrier layer 320 can result in an increase in the retention time of charge carriers in the channel layers 310, 312.

[0049] 4, the heterostructure comprises a channel layer 410 and a barrier layer 420 connecting the channel layer 410 and the substrate 102. The insulating effect of the barrier layer 420 can hinder or prevent charge carriers that may be present in the channel layer 410 from leaving the channel layer 410 by migrating or tunneling to the substrate 102. Thus, the use of a channel layer 410 with a barrier layer 420 adjacent to the substrate can result in an increased retention time of the charge carriers in the channel layer 410.

[0050] In general, barrier layers realized at different non-adjacent locations within the heterostructure can be combined with each other, and Figures 5 and 6 respectively show one such possible combination.

[0051] 5, the heterostructure comprises one channel layer 510, one barrier layer 522 connecting the channel layer 510 and the gate insulator layer 107, and one barrier layer 520 connecting the channel layer 510 and the substrate 102. The insulating effect of the barrier layer 522 can hinder or prevent charge carriers that may be present in the channel layer 510 from leaving the channel layer 510 by migrating or tunneling to the gate structures 106, 107. Similarly, the insulating effect of the barrier layer 520 can hinder or prevent such charge carriers from leaving the channel layer 510 by migrating or tunneling to the substrate 102. Thus, the use of one channel layer 510 with two barrier layers 520, 522 can result in an increased retention time of charge carriers in the channel layer 510.

[0052] 6, the heterostructure comprises two channel layers 610, 612, one barrier layer 624 connecting the channel layer 612 and the gate insulator layer 107, one barrier layer 622 connecting the channel layer 610 and the channel layer 612, and one barrier layer 620 connecting the channel layer 610 and the substrate 102. The insulating effect of the barrier layer 624 can hinder or prevent charge carriers that may be present in the channel layer 612 from leaving the channel layer 612 by moving or tunneling to the gate structures 106, 107. Similarly, the insulating effect of the barrier layer 620 can hinder or prevent such charge carriers from leaving the channel layer 610 by migrating or tunneling to the substrate 102, and the insulating effect of the barrier layer 622 can hinder or prevent charge carriers that may be present in the channel layer 610 from leaving the channel layer 610 by migrating to the channel layer 612, can hinder or prevent charge carriers that may be present in the channel layer 612 from leaving the channel layer 612 by migrating to the channel layer 610, and can hinder or prevent charge carriers that may be present in the channel layer 610 from recombining with charge carriers of opposite charge that may be present in the channel layer 612. Thus, the utilization of two channel layers 610, 612 with three barrier layers 620, 622, 624 can result in an increased retention time of charge carriers in the channel layers 610, 612.

[0053] 7A-7D show the effect of the width and length of the channel structure 110 on the performance of the capacitor-less DRAM cell 100 measured on prototypes implementing channel structures 110 of different dimensions. The length of the channel structure 110 is defined as the overall dimension of the channel structure 110 in a second direction, which may be equivalent to the distance between the source structure 104 and the gate structure 108. The width of the channel structure 110 is defined as the overall dimension of the channel structure 110 in a primary direction of longitudinal extent of the channel structure 110, which is orthogonal to the first direction and different from the second direction, which may be, but is not limited to, orthogonal to the second direction.

[0054] 7A shows a diagram of two input signals 700, 702 for testing a capacitor-less DRAM cell. Curve 700 shows the relationship between the front gate voltage V FG as a function of time, where curve 702 shows the drain voltage V D as a function of time. Both curves 700 and 702 show a series of rectangular pulses with a cycle time of about 40 microseconds (μs). Each pulse displaces the respective voltage from a particular bias level to a temporary constant pulse voltage level with a time duty of about 50%. The bias level is V FG About -0.5V (volts), V D The voltage is 0.0V.

[0055] In the first cycle, “Write 0” is named “W0” and V FG rises to +1.0V, and V D remains at the bias level. This causes holes to be ejected from the channel structure 110 so that a logic state "0" is prepared. In cycles 2 to 6, "read" is labeled "R" and V FG remains at the bias level, and V D V rises to +0.5 V. This allows five cycles of reading the current state of cell 100 by measuring the drain current. In cycle 7, a "write 1" is performed, labeled "W1", and V FG drops to -1.0V, and V D is increased to +1.0 V. This causes the injection of holes into the channel structure 110, thereby preparing the logic state "1". Cycles 8-12 are five more read cycles, labeled "R", with the same characteristics as cycles 2-6. This allows for a comparative observation of the time evolution of the drain current response to programming cycles W0 and W1.

[0056] 7B-7D show the drain current response of a particular capacitor-less DRAM cell prototype tested using signals 700 and 702 as input signals, respectively. All measurements are taken with a back-gate voltage VBG = 2.0V.

[0057] The prototype used for the measurements in FIG. 7B had a gate length of 90 nanometers (nm) g A nominal channel length of 1.0 μm (equal to 1.0 μm) and a channel width W of 2 micrometers (μm) were achieved. The drain current I D The response of (curve 710) is Δ I = I1-I0 = 0.7μA (microamperes), and the ratio I R The prototype used for the measurements in FIG. 7C has a nominal channel length L g = 20 nm and a channel width W of 1 μm were achieved. The drain current I D The response of (curve 712) is Δ I = 17μA, and the ratio I R = 7.9. The prototype used for the measurements in FIG. 7D has a nominal channel length L g = 10 nm and a channel width W of 1 μm were achieved. The drain current I D The response of (curve 714) is Δ I = 17μA, and the ratio I R = 4.3.

[0058] FIG. 8 shows the drain current response of a capacitor-less DRAM cell 200 tested using signals 700, 702 as input signals. The prototype used for the measurements in FIG. 8 implemented a heterostructure with one channel layer 410 and two barrier layers 420, 422. The I D = I0, and I in logic state "1" D Drain current I during five repeated read cycles at I = I DA comparison of the time evolution of (curve 800) with the respective time evolutions observed in Figures 7B-7D shows that the read current level of curve 800 has a larger relaxation time constant of spontaneous charge carrier capture or loss than those of curves 710, 712, and 714, respectively.

[0059] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The terminology used in this specification is selected to best explain the principles of the embodiments, practical applications or technical improvements over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0060] The invention will now be described again by a list of clauses highlighting some possible non-exclusive combinations of the features disclosed herein. 1. A capacitorless DRAM cell comprising a heterostructure, a gate structure adjacent to the heterostructure in a first direction, a drain structure adjacent to the heterostructure in a second direction orthogonal to the first direction, and a source structure adjacent to the heterostructure in a direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and barrier layers being alternately stacked in the first direction. 2. The DRAM cell of claim 1, wherein the heterostructure comprises a single barrier layer and a single channel layer. 3. The DRAM cell of claim 1, wherein the heterostructure comprises a single barrier layer and two channel layers. 4. The DRAM cell of claim 1, wherein the heterostructure comprises two barrier layers and a single channel layer. 5. The DRAM cell of claim 1, wherein the heterostructure comprises two barrier layers and two channel layers. 6. The DRAM cell of claim 1, wherein the heterostructure comprises three barrier layers and two channel layers. 7. A DRAM cell according to any one of clauses 1 to 6, wherein the heterostructure comprises at least two barrier layers made of different barrier layer materials. 8. A DRAM cell according to any one of clauses 1 to 7, wherein the heterostructure comprises at least two channel layers made of different channel layer materials. 9. The DRAM cell of clause 8, wherein the different channel layer materials differ in band gap energy by at least 0.5 electron volts. 10. The DRAM cell of clause 8 or clause 9, wherein the different channel layer materials differ in electron mobility by at least a factor of 10. 11. The DRAM cell of any one of claims 1 to 10, wherein the gate structure is adjacent to one of the barrier layers. 12. The DRAM cell of clause 11, wherein the gate structure comprises a gate insulator layer adjacent to the barrier layer. 13. A DRAM cell according to any one of clauses 1 to 12, wherein the cell is disposed on a substrate and the heterostructure is adjacent to the substrate. 14. The DRAM cell of clause 13, wherein the substrate comprises a substrate insulator layer, and the heterostructure is adjacent to the substrate insulator layer. 15. The DRAM cell of claim 13 or 14, wherein one of the barrier layers is adjacent to the substrate. 16. The DRAM cell of any of clauses 1 to 15, wherein the gate structure is adjacent to the heterostructure only in the first direction. 17. A DRAM cell according to any one of clauses 1 to 16, wherein the gate structure fills the heterostructure. 18. The DRAM cell of clause 17, wherein the gate structure is aligned with the heterostructure in a second direction, said direction being opposite to the second direction. 19. The DRAM cell of any of clauses 1 to 18, wherein each channel layer and each barrier layer is adjacent to both a source structure and a drain structure. 20. A DRAM cell as described in any of clauses 1 to 19, wherein each barrier layer is made of a barrier layer material, the barrier layer material being selected for each barrier layer from the group consisting of silicon, silicon oxide, indium oxide, and indium phosphide. 21. The DRAM cell of any of clauses 1 to 20, wherein each channel layer is made of a channel layer material selected from the group consisting of indium arsenide, gallium arsenide, indium gallium arsenide, indium tin oxide, germanium, and silicon germanium for each channel layer. 22. The DRAM cell of any of clauses 1 to 21, wherein the heterostructure has a total length measured in the second direction of between 1 nanometer and 75 nanometers. 23. A DRAM cell as described in any one of clauses 1 to 22, wherein a total width of the heterostructure measured in a third direction orthogonal to the first and second directions is between 20 and 200 times a total length of the heterostructure measured in the second direction. 24. A DRAM cell as described in any one of clauses 1 to 23, wherein the thickness of each channel layer measured in the first direction is between 1.5 and 5 times the thickness of each barrier layer measured in the first direction. 25. A method for manufacturing a capacitor-less DRAM cell, comprising: forming a heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternately stacked in a first direction; forming a gate structure adjacent to the heterostructure in a first direction; forming a drain structure adjacent to the heterostructure in a second direction orthogonal to the first direction; forming a source structure adjacent to the heterostructure in a direction opposite the second direction.

Claims

1. A heterostructure comprising one or more semiconductor channel layers and one or more electrically insulating barrier layers, the semiconductor channel layers and the electrically insulating barrier layers being alternately stacked in a first direction; a gate structure adjacent to the heterostructure in the first direction, the gate structure comprising a gate insulator layer adjacent to the electrically insulating barrier layer; a drain structure adjacent the heterostructure in a second direction perpendicular to the first direction; a source structure adjacent the heterostructure in a direction opposite the second direction; A capacitor-less DRAM cell comprising:

2. 2. The DRAM cell of claim 1, wherein said heterostructure comprises a single electrically insulating barrier layer and a single semiconducting channel layer.

3. 2. The DRAM cell of claim 1, wherein said heterostructure comprises two of said electrically insulating barrier layers and a single said semiconducting channel layer.

4. 2. The DRAM cell of claim 1, wherein said heterostructure comprises two of said electrically insulating barrier layers and two of said semiconducting channel layers.

5. 2. The DRAM cell of claim 1, wherein said heterostructure comprises three of said electrically insulating barrier layers and two of said semiconducting channel layers.

6. 2. The DRAM cell of claim 1, wherein said heterostructure comprises at least two of said electrically insulating barrier layers, each of said electrically insulating barrier layers being made of a different material.

7. The DRAM cell of claim 1 , wherein the heterostructure comprises at least two of the semiconductor channel layers, each of the semiconductor channel layers being made of a different material.

8. 8. The DRAM cell of claim 7, wherein the different materials of the semiconductor channel layer differ in band gap energy by at least 0.5 electron volts.

9. 8. The DRAM cell of claim 7, wherein the different materials of the semiconductor channel layer differ in electron mobility by at least a factor of 10.

10. The DRAM cell of claim 1 , wherein the gate structure is adjacent to one of the electrically insulating barrier layers.

11. The DRAM cell of claim 1 , wherein the DRAM cell is disposed on a substrate and the heterostructure is adjacent to the substrate.

12. The DRAM cell of claim 11 , wherein the substrate comprises a substrate insulator layer, and the heterostructure is adjacent to the substrate insulator layer.

13. The DRAM cell of claim 11 , wherein one of the electrically insulating barrier layers is adjacent to the substrate.

14. The DRAM cell of claim 1 , wherein said gate structure is adjacent to said heterostructure only in said first direction.

15. The DRAM cell of claim 1 , wherein said gate structure fills said heterostructure.

16. The DRAM cell of claim 15 , wherein the gate structure is aligned with the heterostructure in the second direction.

17. 2. The DRAM cell of claim 1, wherein each of said semiconducting channel layers and each of said electrically insulating barrier layers are adjacent to both said source structure and said drain structure.

18. The DRAM cell of claim 1 , wherein said heterostructure has an overall length measured in said second direction of between 1 nanometer and 75 nanometers.

19. 2. The DRAM cell of claim 1, wherein a total width of the heterostructure measured in a third direction orthogonal to the first and second directions is between 20 and 200 times a total length of the heterostructure measured in the second direction.

20. 2. The DRAM cell of claim 1, wherein a thickness of each of said semiconductor channel layers measured in said first direction is between 1.5 and 5 times a thickness of each of said electrically insulating barrier layers measured in said first direction.

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