Apparatus and method for two-stage reading of resistive random access memories - Patents.com

Abstract

To provide a device including a memory array and a control circuit.SOLUTION: A memory array includes non-volatile memory cells each including a resistive random access memory element. A control circuit is configured to receive a read instruction specifying an address of a first set of the non-volatile memory cells, execute a first read of the first set of the non-volatile memory cells using a first predetermined read reference value to supply the first read data, acquire a second predetermined read reference value corresponding to the specified address while executing the first read, and execute the second read of the first set of the non-volatile memory cells using the second predetermined read reference value in accordance with the condition satisfied with respect to the first read data to supply the second read data.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 504,665, filed May 26, 2023, and entitled "APPARATUS AND METHOD FOR TWO-STEP READ OF RESISTIVE RANDOM ACCESS MEMORY," which is incorporated by reference in its entirety. [Background technology]

[0002] Memories are widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0003] One example of a non-volatile memory is Magnetoresistive Random Access Memory (MRAM), which uses magnetization to represent stored data, as opposed to other memory technologies that use electronic charge to store data. Typically, MRAM includes many magnetic memory cells formed on a semiconductor substrate, where each memory cell represents one bit of data. A bit of data is written to a memory cell by changing the magnetization direction of a magnetic element in the memory cell, and the bit is read by measuring the resistance of the memory cell (low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit). As used herein, the direction of magnetization is the direction of orientation of the magnetic moment.

[0004] Although MRAM is a promising technology, many challenges remain. [Brief description of the drawings]

[0005] Similarly numbered elements refer to common components in different figures. [Figure 1A] FIG. 1 is a block diagram of an MRAM memory cell. [Figure 1B] FIG. 1 is a block diagram of an MRAM memory cell. [Figure 1C] FIG. 1 is a block diagram of an MRAM memory cell. [Figure 1D] FIG. 1 is a block diagram of an MRAM memory cell. [Figure 1E] FIG. 1 is a block diagram of an MRAM memory cell. [Figure 2A] 1 illustrates an exemplary current vs. voltage characteristic of an MRAM memory cell. [Figure 2B] FIG. 2 illustrates exemplary anti-parallel and parallel resistance values ​​for a set of memory cells. [Figure 2C] 1 shows a graph of bit error rate versus read criteria for a number of memory cells in a memory array. [Figure 3A] 1 is a flow chart illustrating one embodiment of a process for creating a look-up table of individual read reference values ​​for a set of codewords. [Figure 3B] 11 is a flow chart illustrating an embodiment of an alternative process for creating a look-up table of individual read reference values ​​for codewords. [Figure 4A] 11 is a table illustrating bad bit counts for example codewords and example candidate read reference values. [Figure 4B] Exemplary numerical bad bit count values ​​are shown for the table of FIG. 4A. [Figure 4C] 4B shows an example lookup table with entries created using the process of FIG. 3A using the example data of FIG. 4B and a desired maximum failing bit count of 2 bits. [Figure 4D] 4B and a desired maximum failing bit count of 5 bits, an example lookup table is shown with entries created using the process of FIG. 3A. [Diagram 5] 1 is a flow chart illustrating one embodiment of a process for reading a codeword. [Figure 6] 11 is a flow chart illustrating an embodiment of another process for reading a codeword. [Figure 7] FIG. 1 is a block diagram of a memory system utilizing the techniques described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Techniques are described for high speed two-stage reading of resistive random access memory cells, such as MRAM cells. In one embodiment, a codeword is read from a set of memory cells using a two-stage read process. As used herein, a "codeword" includes a predetermined number of bits of data (e.g., 16 bits, 64 bits, 1024 bits, etc.). In one embodiment, a codeword includes a number of bits that can be encoded and decoded by a (typically on-die) Error Correction Coding (ECC) engine. In one embodiment, a memory array includes multiple codewords, each codeword having an associated address.

[0007] In one embodiment, a first read of the codeword is performed using a first predetermined read reference value that is used to distinguish between a first state (e.g., 0) and a second state (e.g., 1) for each bit in the codeword. As used herein, the first predetermined read reference value is also referred to as a "global read reference value."

[0008] In one embodiment, a global read reference value is selected for reading all codewords of the memory array. In one embodiment, the global read reference value may be determined during wafer sort and has a value that results in the lowest number of bit errors for all codewords of the memory array.

[0009] In one embodiment, a compact, high-speed memory (e.g., a content-addressable memory) stores a table (e.g., a look-up table) of codeword addresses and corresponding second read reference values. As used herein, the second predetermined read reference values ​​are also referred to as "individual read reference values."

[0010] In one embodiment, each read reference value is selected for reading a corresponding codeword of the memory array, hi one embodiment, each read reference value may be determined during wafer sort and has a value that results in the lowest number of bit errors for the corresponding codeword.

[0011] In one embodiment, while a first read of the codeword is performed using a global read reference value, the lookup table is searched to determine whether there is an entry for the codeword address, and if such an entry exists, an individual read reference value corresponding to the codeword address is obtained from the lookup table.

[0012] In one embodiment, if the first read fails (e.g., the ECC engine cannot successfully decode the read bits) and if the lookup table contains an entry for the codeword address, a second read of the codeword is performed using the corresponding individual read reference value. However, in one embodiment, if the lookup table does not contain an entry for the codeword address, the memory controller may perform further read failure processing (e.g., utilizing a self-referencing read technique to read the specified codeword).

[0013] Without wishing to be bound by any particular theory, it is believed that the two-stage read technique described below may read more bits without having to perform a self-referencing read, which may require multiple write operations and increase write errors and reduce durability. In this regard, without being bound by any particular theory, it is believed that the two-stage read technique described below may improve read reliability.

[0014] Without wishing to be bound by any particular theory, it is believed that the two-stage read technique described below can minimize latency by using a high-speed lookup memory to obtain individual read reference values ​​during the first read operation. Without being bound by any particular theory in this regard, it is believed that the second read can be initiated very quickly if the first read fails, and therefore can be very fast.

[0015] 1A is a schematic perspective view of a conventional MRAM memory cell 10 that uses electric field induced switching. Typically, the memory cell 10 comprises a magnetic tunnel junction (MTJ) 12 that includes an upper ferromagnetic layer 14, a lower ferromagnetic layer 16, and a tunnel barrier (TB) 18, which is an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 14 is a free layer (FL) whose magnetization direction is switchable. The lower ferromagnetic layer 16 is a pinned layer (PL) whose magnetization direction does not change.

[0016] When the magnetization direction in the free layer 14 is parallel to the direction of the pinned layer 16, the end-to-end resistance (R P ) (In this specification, the parallel resistance R P When the magnetization direction in the free layer 14 is antiparallel to that of the pinned layer 16, the end-to-end resistance (R AP ) (In this specification, the anti-parallel resistance R AP The charge transport coefficient (referred to as "charge transfer coefficient") is relatively high due at least in part to spin-dependent scattering of minority and majority electrons. The memory state ("0" or "1") of the MRAM memory cell 10 is read by measuring the resistance of the MRAM memory cell 10, using electrical conductors 20 / 22 attached to the MRAM memory cell 10 to read the MRAM data.

[0017] The magnetization direction in the free layer 14 changes in response to the current 24 flowing in the digit line 26 and in response to the current 28 flowing in the write line 20, generating magnetic fields 30 and 32, respectively. Figure 1A shows the situation where the current 24 in the digit line 26 flows out of the page and the current 28 in the write line 20 flows from left to right. As a result, the magnetic fields 30 and 32 are orthogonal, switching the magnetization direction of the free layer 14 from parallel to anti-parallel to the magnetization direction of the pinned layer 16. The bit orientation is switched by reversing the polarity of the current 28 in the write line 20 while keeping the polarity of the current 24 in the digit line 26 constant.

[0018] The above-described electric field induced switching technique of the MRAM memory cell 10 of Figure 1A has several practical limitations, especially as designs call for shrinking MRAM memory cells to smaller dimensions. For example, because the technique requires two sets of magnetic field write lines, arrays of MRAM memory cells are susceptible to bit disturb (i.e., in response to a write current directed at any cell, adjacent cells may be unintentionally altered).

[0019] Furthermore, reducing the physical size of MRAM memory cells reduces their magnetic stability against magnetization switching due to thermal fluctuations. Bit stability can be increased by utilizing magnetic materials in the free layer with large magnetic anisotropy and therefore large switching fields, but the currents required to generate fields strong enough to switch the bits are impractical for existing applications.

[0020] Spin Transfer Torque (STT) switching is another technique for programming MRAM memory cells. FIG. 1B is a schematic diagram of the STT switching technique for an MRAM memory cell 50 that includes a magnetic tunnel junction 52 that includes an upper ferromagnetic layer 54, a lower ferromagnetic layer 56, and a tunnel barrier 58, which is an insulating layer between the two ferromagnetic layers. In this example, the lower ferromagnetic layer 56 is a free layer (FL), whose magnetization direction is switchable. The upper ferromagnetic layer 54 is a pinned (fixed) layer, whose magnetization direction cannot be easily changed.

[0021] When the magnetization direction in the free layer 56 is parallel to the direction of the pinned layer 54, the resistance R P When the magnetization direction of the free layer 56 is antiparallel to the magnetization direction of the pinned layer 54, the anti-parallel resistance R across the MRAM memory cell 50 is AP is relatively high. The memory state ("0" or "1") of the MRAM memory cell 50 is read by measuring the resistance of the MRAM memory cell 50 using electrical conductors 60 / 62 attached to the MRAM memory cell 50 to read the MRAM data. By design, both the parallel and anti-parallel configurations remain stable (at sufficiently low read currents) during quiescent conditions and / or read operations.

[0022] In the remaining text and figures, the direction of the write current is defined as the direction of electron flow, and therefore the term write current refers to the electron current.

[0023] To "set" an MRAM memory cell bit value (i.e., select the magnetization orientation of the free layer), an electrical write current 64 is applied from conductor 60 to conductor 62. Because pinned layer 54 is a ferromagnetic metal, the electrons in write current 64 become spin polarized as they pass through pinned layer 54. Although the conduction electrons in a ferromagnetic metal have a spin orientation collinear with the magnetization direction, a significant majority of these conduction electrons have a particular orientation that is parallel to the magnetization direction, producing a net spin-polarized current. (Electron spin refers to angular momentum, which is directly proportional to, but antiparallel to, the electron's magnetic moment, although for ease of explanation we will not proceed using this directional distinction.)

[0024] As the spin-polarized electrons pass through the tunnel barrier 58, conservation of angular momentum can result in a torque on both the free layer 56 and the pinned layer 54, but this torque is insufficient (by design) to affect the magnetization direction of the pinned layer 54. In contrast, if the initial magnetization direction of the free layer 56 is antiparallel to the pinned layer 54, then this torque is sufficient (by design) to switch the magnetization direction of the free layer 56 to be parallel to the magnetization direction of the pinned layer 54. The parallel magnetization then remains stable before and after such write current is turned off.

[0025] In contrast, if the magnetizations of the free layer 56 and the pinned layer 54 are initially parallel, then application of a write current in the opposite direction to that previously described can STT switch the magnetization orientation of the free layer 56 to be antiparallel to the pinned layer 54. Thus, given the same STT physics, by appropriate selection of the write current direction (polarity), the magnetization orientation of the free layer 56 can be deterministically set to one of two stable orientations.

[0026] The MRAM memory cell 50 of FIG. 1B uses materials in which both the pinned and free layer magnetizations are in-plane. In contrast, FIG. 1C shows a schematic diagram of an STT switching MRAM memory cell 70 in which both the pinned and free layer magnetizations are perpendicular. The memory cell 70 comprises a magnetic tunnel junction 72 including an upper ferromagnetic layer 74, a lower ferromagnetic layer 76, and an insulating layer, a tunnel barrier 78, between the two ferromagnetic layers. In this example, the lower ferromagnetic layer 76 is a free layer whose magnetization direction is switchable. The upper ferromagnetic layer 74 is a pinned (or fixed) layer, whose magnetization direction is not easily changed.

[0027] When the magnetization direction in the free layer 76 is parallel to the magnetization direction of the pinned layer 74, the resistance R across the MRAM memory cell 70 is P When the magnetization direction of the free layer 76 is antiparallel to the magnetization direction of the pinned layer 74, the anti-parallel resistance R across the MRAM memory cell 70 is AP is relatively high. The memory state ("0" or "1") of the MRAM memory cell 70 is read by measuring the resistance of the MRAM memory cell 70, whereupon electrical conductors 80 / 82 attached to the MRAM memory cell 70 are utilized to read the MRAM data. By design, both the parallel and antiparallel configurations remain stable (at sufficiently low read currents) during quiescent and / or read operations. To "set" the MRAM memory cell bit value (i.e., select the magnetization orientation of the free layer), an electrical write current 84 is applied from conductor 80 to conductor 82, and the MRAM memory cell 70 operates as described above in connection with FIG. 1B.

[0028] Compared to original MRAM memory cells that used electric fields from current-carrier conductors adjacent to the MRAM cell, the STT switching technique requires relatively low power, virtually eliminates the problem of neighboring bit disturbance, and has better scaling for higher cell densities (reduced MRAM memory cell size). The latter challenge also favors STT MRAM in which the magnetizations of the free and pinned layers are oriented perpendicular to the film plane rather than in-plane. However, in practice, STT switching requires the full write current to flow through the tunnel barrier, which adversely affects the long-term reliability of STT MRAM memory cells due to the required stress of moderate to high write voltages across the tunnel barrier.

[0029] 1D shows an alternative MRAM memory cell 100 that utilizes spin orbit torque (SOT) to switch the free layer using spin current. The spin of an electron is an intrinsic angular momentum that is separate from the angular momentum due to the electron's orbital motion. In a solid, the spins of many electrons can act together to affect the magnetic and electronic properties of a material, for example, giving the material a permanent magnetic moment, such as a ferromagnet.

[0030] In many materials, electron spin is equally present in both the up and down directions, and the amount of transport is spin independent. However, various techniques can be used to generate a population of spin-polarized electrons, resulting in an excess of spin-up or spin-down electrons, which changes the properties of the material. A spin-polarized population of electrons moving in a common direction through a common material is called a spin current. As described herein, spin current can be used to operate MRAM memory cells.

[0031] In general, the Spin Hall Effect (SHE) can be used to generate a spin current that flows in a transverse (perpendicular to the plane) direction when a charge current is applied in a longitudinal (in-plane) direction. The spin polarization direction of such a spin Hall effect spin current is in-plane, perpendicular to the flow of the charge current. The MRAM memory cell 100 includes three terminals A, B, and C, a magnetic tunnel junction 102, and a SHE material 120.

[0032] In one implementation, the magnetic tunnel junction 102 includes a free layer, a tunnel barrier, and a pinned layer. In another implementation, the magnetic tunnel junction 102 includes a pinned layer 106, an inter-layer coupling (ILC) layer 108, a reference layer (RL) 110, a tunnel barrier 112, and a free layer 114. The inter-layer coupling layer 108 promotes strong antiferromagnetic (i.e., antiparallel) coupling between the pinned layer 106 and the reference layer 110, so that the net magnetic moments of these layers are nearly canceled, thereby significantly reducing undesirable stray magnetic fields on the free layer. The spin Hall effect layer 104 includes a heavy metal such as platinum, tantalum, or tungsten, which has a strong SHE. The direction of magnetization of the free layer 114 can be switched between up and down.

[0033] The advantage of the SOT switching design utilizing the spin Hall effect is that the write current 116 passes only through the spin Hall effect layer 104 and does not flow through the tunnel barrier 112. Thus, the above-mentioned long-term degradation of the tunnel barrier 112 due to the switching current in the conventional STT switching design of MRAM memory cells is eliminated.

[0034] FIG 1E shows a schematic diagram of a voltage controlled magnetic anisotropy (VCMA) MRAM memory cell 120. The VCMA memory cell 120 has a similar structure to the STT switching MRAM memory cell 70 of FIG 1C, but with some differences. The MRAM memory cell 120 comprises a magnetic tunnel junction 122 including an upper ferromagnetic layer 124, a lower ferromagnetic layer 126, a spacer layer (SP) 128, a tunnel barrier 138, and a reference layer 140. The upper ferromagnetic layer 124 is also referred to as a bias layer 124, and the lower ferromagnetic layer 126 is also referred to as a free layer 126.

[0035] When the magnetization in the free layer 126 is parallel to the magnetization in the reference layer 140, the resistance across the MRAM memory cell 120, R P is relatively low. When the magnetization in the free layer 126 is antiparallel to the magnetization in the reference layer 140, the resistance R AP is relatively high. The memory state ("0" or "1") of the MRAM memory cell 120 is read by measuring the resistance of the MRAM memory cell 120, using electrical conductors 142 / 144 attached to the MRAM memory cell 120 to read the MRAM data. The read process is the same as that of the MRAM memory cell 70 of FIG. 1C, except that the read polarity is selected to be opposite to the write polarity.

[0036] In one embodiment, the write process for MRAM memory cell 120 is as follows: (1) MRAM memory cell 120 is read to determine its state, (2) if MRAM memory cell 120 is in the desired written state, the write process is terminated, (3) if not, a write voltage is applied to MRAM memory cell 120 with a polarity that reduces the magnetic anisotropy of the free layer to near zero (the free layer precesses around the magnetic field direction defined by magnetic bias layer 124 while the write voltage is applied), (4) the write voltage is removed after half a precession cycle, and (5) steps 1-4 are repeated until the state is correctly written or the write process times out.

[0037] In an embodiment, the materials and interfaces of the free layer 126, the spacer layer 128, and the tunnel barrier 130 are selected to provide a large VCMA coefficient for the FL 126 to maximize the change in the magnetic anisotropy of the free layer with applied voltage. This may require the use of materials that increase the resistance of the tunnel barrier 130. To achieve reliable switching, the free layer 126 typically requires a small, non-zero, in-plane bias field. In one embodiment, the bias field is generated by the bias layer 124. Alternatively, the in-plane field can be provided by an Oersted field generated by a magnet external to the MRAM memory cell 120 or by passing a current through a wire close to the memory cell.

[0038] FIG. 2A illustrates an example current vs. voltage characteristic of an MRAM memory cell, such as MRAM memory cells 10, 50, 70, and 100 of FIGS. 1A-1D, respectively. For brevity, the description of FIG. 2A refers to MRAM memory cell 50 of FIG. 1B. In one embodiment, MRAM memory cell 50 can be reversibly switched between a "parallel state" (P) (shown in FIG. 2A by solid lines) and an "antiparallel state" (AP) (shown in FIG. 2A by dashed lines). In the parallel state P, the magnetization direction of free layer 56 is parallel to the magnetization direction of pinned layer 54. In the antiparallel state AP, the magnetization direction of free layer 56 is antiparallel to the magnetization direction of pinned layer 54.

[0039] If MRAM memory cell 50 is initially in the anti-parallel state AP and an electronic write current 64 is applied from conductor 60 to conductor 62, MRAM memory cell 50 switches to the parallel state P. In the embodiment shown in FIG. 2A, MRAM memory cell 50 is driven by a write voltage V of about 1.12 V between conductor 62 and conductor 60. AP-P At this point, the state switches from the antiparallel state AP to the parallel state P.

[0040] Conversely, if MRAM memory cell 50 is initially in the parallel state P and an electronic electrical write current 64 is applied from conductor 62 to conductor 60, MRAM memory cell 50 switches to the antiparallel state AP. In the embodiment shown in FIG. 2A, MRAM memory cell 50 is switched to the antiparallel state AP by a write voltage V between conductor 62 and conductor 60 of approximately 0.36 V. P-AP The parallel state P switches to the antiparallel state AP.

[0041] The state of an MRAM memory cell, such as MRAM memory cell 50 of FIG. 1B, is determined by applying a read reference (e.g., a read reference voltage V rd ) can be determined by applying the applied read reference V rd results in a current proportional to the resistance of the MRAM memory cell. In the embodiment shown in FIG. 2A, a read reference V rd In the antiparallel state AP, the MRAM memory cell 50 has an antiparallel resistance R AP In the parallel state P, the parallel resistance R P has.

[0042] Therefore, the state of an individual MRAM memory cell is determined by the read reference V rd The resistance of the MRAM memory cell at is sensed, and the sensed resistance is then calculated as a threshold resistance value R T The sensed resistance of the MRAM memory cell can be determined by comparing it to a threshold resistance value R T If so, the MRAM memory cell is determined to be in the antiparallel state AP, and the detected resistance of the MRAM memory cell is equal to or greater than the threshold resistance value R T If it is smaller, the MRAM memory cell is determined to be in the parallel state P.

[0043] The anti-parallel resistance R of an individual MRAM memory cell AP value and parallel resistance R PThis reading technique, referred to herein as a "single reference read," is very effective for reading individual MRAM memory cells because the value remains relatively constant. However, a set of MRAM memory cells (e.g., in a memory array of MRAM memory cells) often has an anti-parallel resistance R between the MRAM memory cells. AP value and parallel resistance R P A wide variation in values ​​is shown.

[0044] Furthermore, as shown in FIG. 2B, the anti-parallel resistance R AP value and parallel resistance R P The values ​​often overlap. As a result of this overlap, a single reference read of a set of memory cells can accurately distinguish only a finite number of bits. For simplicity, the remaining description uses the term "codeword" to describe a set of memory cells that stores a predetermined number of bits of data (e.g., 16 bits, 64 bits, 1024 bits, or some other number of bits of data). In one embodiment, a codeword includes a number of bits that can be coded and decoded by a (typically on-die) error correction coding (ECC) engine.

[0045] For example, FIG. 2C shows the Bit Error Rate (BER) of a large group of memory cells (e.g., all memory cells in a memory array containing a large number of memory cells) versus the read criterion V rd FIG. 2C shows a graph of the “optimum” read reference V of about 0.73V for the entire group of memory cells. rdo It is shown that a minimum bit error rate of about 7% is achieved using

[0046] Some code words are based on a single read criterion V rdo However, for other codewords, the single read criterion V rdo The number of bit errors that occur using the ECC engine may exceed the maximum number of bit errors that can be corrected by the ECC engine. In such cases, the codeword is typically read using an alternative read technique, such as self-referencing read.

[0047] For example, in one self-referencing read technique, the memory cell is first read, then written to a first memory state, a second read is performed, and then the results of the first and second reads are compared. If the results of the two reads are the same, the memory cell is determined to have originally been in the first memory state and is maintained in the first memory state. However, if the results of the two reads are not the same, the memory cell is determined to have originally been in the second memory state but is now in the first memory state. As a result, a write operation is required to restore the memory cell to the second memory state.

[0048] Although such self-referencing read techniques may be used to successfully read codewords that could not be successfully read using a single reference read, the self-referencing read requires at least two read operations and one write operation, and may require an additional write operation, and therefore such self-referencing read techniques take a long time to complete, are susceptible to write errors, and may also reduce the endurance of the memory cells.

[0049] To overcome these shortcomings, a two-stage read technique for reading MRAM memory cells is proposed. In particular, a technique for high speed two-stage reading of resistive random access memory cells such as MRAM cells is described. In one embodiment, a codeword having a specified address is read from a set of memory cells using a two-stage read process. In one embodiment, a first read of the codeword is performed using a global read reference value.

[0050] In one embodiment, while the first read is being performed, the lookup table is searched to determine whether there is an entry corresponding to the specified address. In one embodiment, the lookup table includes a codeword address and a corresponding individual read reference value. In one embodiment, if the lookup table includes an entry for the specified address, a second read of the codeword is performed using the corresponding individual read reference value of the codeword.

[0051] In one embodiment, the global read reference value is a read reference value selected for reading all codewords of the memory array. In one embodiment, the global read reference value may be determined during wafer sort and has a value that results in the lowest number of bit errors for all codewords of the memory array.

[0052] In one embodiment, each read reference value is selected for reading a corresponding codeword in the memory array, hi one embodiment, each read reference value may be determined during wafer sort and has a value that results in the lowest number of bit errors in the codeword.

[0053] 3A is a flow chart illustrating one embodiment of a process 300a for creating a lookup table of individual read reference values ​​for a set of codewords. In one embodiment, process 300a may be performed by a system control circuit described below.

[0054] In one embodiment, the lookup table is addressed by a codeword address. In one embodiment, the set of codewords includes all of the codewords of the memory array. In another embodiment, the set of codewords includes fewer than all of the codewords of the memory array.

[0055] For simplicity, in the remaining discussion, the codeword set is defined as m codewords CW i , i=0, 1, 2, ..., m-1. Furthermore, for simplicity, in the remaining description, we use the CW i We use the term “all codewords” to mean each codeword CW in the set of m codewords. i "Each codeword CW i "The term "

[0056] In step 302, the data is all the codewords CW i In one embodiment, the codeword CW i All bits of the codeword CW are written to a first memory state (e.g., 0). i may be written to a second memory state (eg, 1).

[0057] In step 304, each codeword CW i is read out sequentially using multiple candidate read reference values. In one embodiment, each codeword CW i is n candidate reading reference values ​​v rdj , j=0, 1, 2, ..., n-1. For example, the candidate read reference value v rdj may be selected based on simulation results, empirical evidence, or a combination of the two, or by some other method.

[0058] In step 306, based on the result of reading in step 304, each codeword CW i and each candidate reading reference value v rdj About the defective bit count FB ij Alternatively, the bit error rate BER is determined. ij is the codeword CW i and each candidate reading reference value v rdj may be determined.

[0059] FIG. 4A shows in tabular form an example for m=8, n=4. In the example shown, codeword CW0 is read from candidate read reference value v rd0 Bad bit count when read using FB 00 and the codeword CW1 has a candidate read reference value v rd2 Bad bit count when read using FB 12 and the codeword CW5 has a candidate read reference value v rd1 Bad bit count when read using FB 51 and so on.

[0060] FIG. 4B shows exemplary numerical bad bit count values ​​for the table of FIG. 4A. For example, codeword CW2 has a candidate read reference value v rd2 Bad bit count when read using FB 22 = 3, and the codeword CW4 has a candidate read reference value v rd0 Bad bit count when read using FB 40 = 4, and the codeword CW6 has a candidate read reference value v rd1 Bad bit count when read using FB 61 = 2, and so on.

[0061] Referring again to FIG. 3A, in step 308, each codeword CW i The corresponding individual reading reference value v rdi In one embodiment, the codeword CW i Individual read reference values ​​v rdi is the minimum bad bit count FB for j=0, 1, 2, ..., n-1. ij Thus, using the example values ​​of FIG. 4B, the corresponding individual read reference values ​​v rdi is as follows.

[0062] [Table 1]

[0063] Referring again to FIG. 3A, in step 310, all codewords CW i Global reading reference value v rdg In one embodiment, all codewords CW i Global reading reference value v rdg is the bad bit count FB for i=0, 1, 2, ..., m-1 ij The reading reference value v that results in the smallest sum of rdj Therefore, using the example values ​​of FIG. 4B, the read reference value v rd1yields the minimum sum (20 bad bits), so in this example, all codewords CW i Global read reference value v for rdg =v rd1 results.

[0064] Referring again to FIG. 3A, in step 312, each codeword CW i Desired maximum bad bit count FB M For example, a desired maximum failing bit count FB M can be 2 bits, 3 bits, etc.

[0065] In step 314, the codeword is compared to the global read reference value v rdg The desired maximum bad bit count, FB, when read using M (i.e., F.B. ij >FB M ) Bad bit count FB ij Any codeword CW i is identified.

[0066] For example, referring again to the example values ​​of FIG. 4B, if a codeword is compared to a global read reference value v rdg =v rd1 The desired maximum bad bit count, FB, when read using M = 2 bits, code words CW2, CW5 and CW7 each have a desired maximum failing bit count FB M Bad bit count FB greater than ij Alternatively, a desired maximum failing bit count FB M = 5 bits, the global read reference value v rdg =v rd1 When the codeword is read using M Bad bit count FB greater than ij has.

[0067] Referring again to FIG. 3A, in step 316, an entry in the lookup table is created for each codeword CW identified in step 314. i In one embodiment, a lookup table entry is created for each codeword CW identified in step 314. i The address of the identified codeword CW i The corresponding individual read reference values ​​v rdi Includes.

[0068] FIG. 4C illustrates the example data of FIG. 4B and the desired maximum failing bit count FB M 4 shows an exemplary lookup table 400c including entries created in step 316 of process 300a using 1=2 bits. In particular, lookup table 400c shows the addresses of codeword CW2 and its corresponding individual read reference values ​​v rd0 The first entry contains the address of the codeword CW5 and its corresponding individual read reference value v rd3 and the address of the codeword CW7 and its corresponding individual read reference value v rd2 and a third entry including:

[0069] FIG. 4D illustrates the example data of FIG. 4B and the desired maximum failing bit count FB M Illustrated is an exemplary lookup table 400d containing entries created in step 316 of process 300a using 5 bits. In particular, lookup table 400d shows the addresses of codeword CW5 and its corresponding individual read reference values ​​v rd3 Contains a single entry containing

[0070] Thus, without wishing to be bound by any particular theory, in these examples, a desired maximum failing bit count FB M As decreases, more codewords CW i is the global read reference value v rdg The desired maximum bad bit count FB when a codeword is read usingM Bad bit count FB greater than ij , which would normally imply an increased number of lookup table entries.

[0071] In the above exemplary process 300a, all codewords CW i A bit is written to either a first memory state (e.g., 0) or a second memory state (e.g., 1). However, in some memory devices, a codeword may have a first faulty bit count when the codeword is written to the first memory state and a second faulty bit count when the codeword is written to the second memory state. In some embodiments, the first faulty bit count may be higher or lower than the second faulty bit count. That is, a codeword may have a higher faulty bit count depending on the data written to the codeword.

[0072] 3B is a flow chart of one embodiment of an alternative process 300b for creating a lookup table of individual read reference values ​​for a set of codewords. The exemplary process 300b is similar to the exemplary process 300a of FIG. 3A, except that for each codeword CW i to both the first memory state and the second memory state. In one embodiment, process 300b may be performed by a system control circuit described below.

[0073] In step 318, during the first write operation, the codeword CW i are written to a first memory state (eg, 0).

[0074] In step 320, during a first read operation, each codeword CW i is read out sequentially using multiple candidate read reference values. In one embodiment, each codeword CW i is n candidate reading reference values ​​v rdj, j=0, 1, 2, ..., n-1. For example, the candidate read reference value v rdj may be selected based on simulation results, empirical evidence, or a combination of the two, or by some other method.

[0075] In step 322, during the second write operation, the codeword CW i are written to a second memory state (eg, 1).

[0076] In step 324, during the second read operation, each codeword CW i are read sequentially using the same candidate read reference values ​​used in step 320.

[0077] In step 326, based on the results of reading in step 320 and the results of reading in step 324, each codeword CW i and each candidate reading reference value v rdj About the defective bit count FB ij In one embodiment, for each codeword CW i The bad bit count FB determined for ij is the larger of the bad bit counts from the first read operation and the second read operation. Alternatively, the bit error rate, BER ij is the codeword CW i and each candidate reading reference value v rdj In one embodiment, for each codeword CW i The bit error rate BER determined for ij is the greater of the bit error rate from the first read operation and the second read operation.

[0078] The remaining steps 308-316 of process 300b are the same as those of process 300a, except that for each codeword CW i The bad bit count FB determined in step 326 based on two separate write and read operations ijWithout wishing to be bound by any particular theory, it is believed that the process 300b may identify individual read reference values ​​that work with both the first memory state and the second memory state.

[0079] In steps 302, 318 and 322 in the above exemplary processes 300a and 300b, the codeword CW i The bits of all the codewords CW are written either to the first memory state or to the second memory state. i are written to either the first memory state or the second memory state. Those skilled in the art will appreciate that the codeword bits may alternatively be written using a predetermined random bit pattern (e.g., "0101010...," "0100010...," "11110000...," or some other predetermined random bit pattern).

[0080] In one embodiment, the above exemplary processes 300a and 300b may be performed once. For example, the above processes 300a and 300b may be performed at wafer sort, and the lookup table entries created in step 316 may be stored in a lookup table stored in memory on the memory die. In one embodiment, the lookup table may be stored in a small, fast memory structure, such as a Content Addressable Memory (CAM) or other type of memory.

[0081] In other embodiments, the above example processes 300a and 300b may be performed more than once. For example, the above example processes 300a and 300b may be performed initially at wafer sort to create initial entries in the lookup table, and then may be performed one or more additional times to create updated or additional entries in the lookup table throughout the life of the memory die.

[0082] 5 is a flow chart of one embodiment of a process 500 for reading a codeword. In one embodiment, process 500 may be performed by a system control circuitry described below.

[0083] In step 502, a read command is received. For example, a host device may send a read command to a memory controller. In one embodiment, the read command includes one or more codewords CW to be read. i For simplicity, in the following description, the received read command is assumed to be a single codeword CW i ADD a single address i Suppose you specify

[0084] In step 504, the specified address ADD i 3A or 300b of FIG. 3B. rdg Read using a global read reference value such as

[0085] In step 506, a lookup table created using process 300a of FIG. 3A or process 300b of FIG. 3B (e.g., lookup table 400c of FIG. 4C or lookup table 400d of FIG. 4D) is searched for and the lookup table is located at the specified address ADD. i Determine whether the entry contains

[0086] In step 508, the lookup table matches the address ADD i In step 508, it is determined whether the lookup table contains a matching address ADD i If it is determined that the match flag I m Set to 0.

[0087] In step 508, the lookup table matches the address ADD iIf it is determined that the address ADD i The corresponding individual read reference values ​​v of the code words in rdi is obtained from the lookup table. In step 514, the match flag I m Set to 1.

[0088] In one embodiment, steps 506-514 are performed in parallel with the read operation performed in step 504. In one embodiment, steps 506-514 are performed while the read operation is being performed in step 504. In one embodiment, the time required to complete steps 506-514 is equal to or less than the time required to complete the read operation performed in step 504.

[0089] In step 516, the read data from step 504 is decoded (e.g., using an ECC engine). The ECC engine typically performs a maximum number of bit error ECC M (For example, ECC M = 5 bits, 7 bits, or other maximum number of bits). The data read in step 504 is ECC M If the data read in step 504 contains less than or equal to 1 bit error, the ECC engine is able to successfully correct the errors and the ECC operation passes. M If it contains more than one bit error, the ECC engine will not be able to successfully correct the errors and the ECC operation will fail.

[0090] In step 518, it is determined whether the ECC operation in step 516 passed. If in step 518, it is determined that the ECC engine successfully decoded the data read in step 504, the decoded data is provided to the host in step 520.

[0091] However, if it is determined in step 518 that the ECC engine was not able to successfully decode the data read in step 504, then a match flag I mDetermine whether or not =1.

[0092] In step 522, the match flag I m If it is determined that CW is not equal to 1, then a failure handling operation may be performed in step 524. In one embodiment, the failure handling operation is i This may include performing an overwrite read operation.

[0093] However, in step 522, the match flag I m If it is determined that ADD is equal to 1, the address specified in step 526 is i The codewords CWi in are again read, but this time with the corresponding individual read reference values ​​v obtained from the look-up table in step 512. rdi Use.

[0094] In step 528, the match flag I m 0, and then process 500 loops back to step 516 to decode the data read, this time using the data read in step 526.

[0095] In step 518, it is determined whether the ECC operation in step 516 passed. If in step 518, it is determined that the ECC engine successfully decoded the data read in step 504, the decoded data is provided to the host in step 520.

[0096] However, if it is determined in step 518 that the ECC engine was not able to successfully decode the data read in step 504, then a match flag I m In step 528, it is determined whether the match flag I m Now that has been reset to 0, in step 524, failure handling operations may be performed as described above.

[0097] While not wishing to be bound by any particular theory, it is believed that the process 500 may improve or reduce the time required to read a codeword. In particular, when a specified codeword CW i First, the global read reference value v rdg Without wishing to be bound to any particular theory, it is possible to use a lookup table to determine the codeword CW i ADD address i It is believed that in many cases such a read can be performed successfully even if the entry contains

[0098] However, the first read was not successful and the lookup table was not found for the specified codeword CW i ADD address i If it contains an entry for the specified codeword CW i is the corresponding individual reading reference value v obtained from the lookup table. rdi Without wishing to be bound to any particular theory, such a second read may be performed using a designated codeword CW i Individually selected reading reference values ​​v rdi Since the second read uses

[0099] However, if the second read is not successful, the specified codeword CW i A failure handling action such as performing a read over to the codeword may be used to successfully read the codeword.

[0100] While not wishing to be bound by any particular theory, it is contemplated that a lookup table may be searched to find any matching individual read reference value v rdi is acquired in parallel with the first read operation, so that the second read operation obtains the specified codeword CW i It is believed that this can be done quickly without requiring trial and error to find alternative reading reference values ​​that can be used to successfully read the .

[0101] Additionally, while not wishing to be bound by any particular theory, it is believed that the described process may eliminate or significantly reduce the number of overwrite read operations required to read a codeword on a memory die.

[0102] 6 is a flow chart of one embodiment of a process 600 for reading a codeword. In one embodiment, process 600 may be performed by a system control circuitry described below.

[0103] In step 602, an instruction is received to read a first codeword from a memory array including a plurality of codewords collectively having a corresponding first predetermined read reference value, each codeword having a corresponding second predetermined read reference value.

[0104] In step 604, a first codeword is read using a first predetermined read reference value to provide first read data.

[0105] In step 606, while reading the first codeword, obtain a second predetermined read reference value corresponding to the first codeword from the lookup table.

[0106] In step 608, the first read data is decoded using an error correcting code algorithm.

[0107] In step 610, it is determined that the error correction code algorithm was not able to correctly decode the first read data.

[0108] In step 612, the first codeword is read using the obtained second predetermined read reference value to provide second read data.

[0109] 7 is a block diagram illustrating an example of a memory system 700 that can implement the techniques described herein. The memory system 700 includes a memory array 702 that can include any of the memory cells described above. The array dividers of the memory array 702 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations can also be implemented.

[0110] The memory system 700 includes a row control circuit 704, the outputs 706 of which are connected to each word line of the memory array 702. The row control circuit 704 receives a set of M row address signals and one or more various control signals from a system control logic circuit 708, which may typically include circuits such as a row decoder 710, an array termination driver 712, and a block selection circuit 714, for both read and write operations.

[0111] The memory system 700 also includes a column control circuit 716, whose input / output 718 is connected to each bit line of the memory array 702. The column control circuit 718 receives a set of N column address signals and one or more various control signals from the system control logic 708, and may typically include circuits such as a column decoder 720, an array termination receiver or driver 722, a block selection circuit 724, as well as read / write circuits and I / O multiplexers.

[0112] System control logic 708 receives data and instructions from the host and provides output data to the host and status. In other embodiments, system control logic 708 receives data and instructions from a separate controller circuit and provides output data to that controller circuit, which communicates with the host. System control logic 708 may include one or more state machines, registers, and other control logic that control the operation of memory system 700.

[0113] In one embodiment, system control logic 708 includes a memory structure (not shown) that stores the lookup tables described above, such as lookup tables 400c and 400d of Figures 4C and 4D, respectively. In one embodiment, the memory structure is a compact, fast memory structure. In one embodiment, the memory structure is a content-addressable memory. Other memory structures may be used.

[0114] In other embodiments, a portion of memory array 702 may be used to store lookup tables described above, such as lookup tables 400c and 400d of Figures 4C and 4D, respectively.

[0115] 7 are located on a single integrated circuit, for example, system control logic 708, column control circuitry 716, and row control circuitry 704 are formed on the surface of a substrate, and memory array 702 is formed on or above the substrate.

[0116] In one embodiment, one or more of the memory array 702, the row control circuitry 704, the column control circuitry 716, and the system control logic 708 comprise a system control circuitry including hardware and / or software configured to implement the methods 300a, 300b, 500 and 600 of Figures 3A, 3B, 5, and 6, respectively.

[0117] Although the techniques described above and the exemplary methods 300a, 300b, 500 and 600 of Figures 3A, 3B, 5 and 6, respectively, are described with reference to MRAM memory cells, those skilled in the art will appreciate that the techniques may be used with any resistive-switching memory cell, including MRAM memory cells, phase change memory cells, reversible resistive switching random access memory cells (ReRAM) memory cells, and other resistive-switching memory cells. Additionally, the techniques described above and the exemplary methods 300a, 300b, 500 and 600 of Figures 3A, 3B, 5 and 6, respectively, may be used with a block of multiple resistive-switching memory cells.

[0118] One embodiment includes an apparatus including a memory array and a control circuit. The memory array includes non-volatile memory cells each including a resistive random access memory element. The control circuit is configured to receive a read instruction specifying an address of a first set of the non-volatile memory cells, perform a first read of the first set of the non-volatile memory cells using a first predetermined read reference value to provide first read data, obtain a second predetermined read reference value from the memory corresponding to the specified address while performing the first read, and perform a second read of the first set of the non-volatile memory cells using the second predetermined read reference value to provide second read data depending on a condition satisfied for the first read data.

[0119] One embodiment includes a method, the method including: receiving an instruction to read a first codeword from a memory array including a plurality of codewords collectively including a corresponding first predetermined read reference value, each codeword including a corresponding second predetermined read reference value; reading the first codeword using the first predetermined read reference value to provide first read data; while reading the first codeword, obtaining a second predetermined read reference value corresponding to the first codeword from a lookup table; decoding the first read data using an error correcting code algorithm; determining that the error correcting code algorithm failed to correctly decode the first read data; and reading the first codeword using the obtained second predetermined read reference value to provide second read data.

[0120] One embodiment includes a system including a control circuit configured to receive instructions from a host device to read a first set of non-volatile memory cells in a memory array including a plurality of sets of memory cells, perform a first read of the first set of non-volatile memory cells using a first predetermined read reference value, obtain a second predetermined read reference value from a lookup table, and selectively perform a second read of the first set of non-volatile memory cells using the second predetermined read reference value only if data read during the first read fails to be correctly decoded. The obtaining step is performed in parallel with the first read step. The first predetermined read reference value minimizes a failing bit count across all sets of memory cells. The second predetermined read reference value minimizes a failing bit count of the first set of memory cells.

[0121] For purposes of this specification, references to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" in the specification may be used to describe different or the same embodiments.

[0122] For purposes of this specification, a connection may be a direct connection or an indirect connection (e.g., through one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element through an intervening element. When an element is referred to as being directly connected to another element, there is no intervening element between the element and the other element. Two devices are in "communication" if they are directly or indirectly connected such that they can exchange electronic signals between each other.

[0123] For purposes of this specification, the term "based on" may be read as "based at least in part on."

[0124] For purposes of this specification, the use of numerical terms such as "first" object, "second" object, and "third" object, without additional context, does not imply an ordering of the objects, but instead may be used for discriminatory purposes to distinguish between different objects.

[0125] For purposes of this specification, the term "set" of objects may refer to a "set" of one or more objects.

[0126] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments have been selected to best explain the principles of the proposed technology and its practical application, thereby enabling those skilled in the art to best utilize this technology in various embodiments, with various modifications as appropriate for the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

1. a memory array comprising a plurality of non-volatile memory cells each comprising a resistive random access memory element; and a control circuit, the control circuit comprising: receiving a read command addressing a first set of the non-volatile memory cells; performing a first read of the first set of non-volatile memory cells using a first predetermined read reference value to provide first read data; While performing the first read, obtain from memory a second predetermined read reference value corresponding to the specified address; and configured to perform a second read of the first set of non-volatile memory cells using the second predetermined read reference value in response to a condition being met for the first read data to provide second read data.

2. The apparatus of claim 1 , wherein the first predetermined read reference value is selected from a plurality of candidate read reference values.

3. the memory array includes a plurality of sets of the non-volatile memory cells; 2. The apparatus of claim 1, wherein the first predetermined read reference value is selected based on results of reading all sets of the non-volatile memory cells with a plurality of candidate read reference values.

4. The first predetermined reading reference value is determining, for each candidate read reference value, a total number of bit errors resulting from reading each set of said non-volatile memory cells; 4. The apparatus of claim 3, wherein the first predetermined read reference value is selected by setting the candidate read reference value having the lowest total number of bit errors.

5. The apparatus of claim 1 , wherein the second predetermined read reference value is selected from a plurality of candidate read reference values.

6. the memory array includes a plurality of sets of the non-volatile memory cells; 2. The apparatus of claim 1, wherein the second predetermined read reference value is selected based on results of reading the first set of non-volatile memory cells with a plurality of candidate read reference values.

7. The second predetermined reading reference value is determining, for each candidate read reference value, a total number of bit errors resulting from reading the first set of non-volatile memory cells; 7. The apparatus of claim 6, wherein the second predetermined read reference value is selected by setting the candidate read reference value having the lowest total number of bit errors.

8. The device of claim 1 , wherein the resistive random access memory element comprises a magnetoresistive random access memory element.

9. The memory array comprises: A plurality of first conductive lines; 2. The device of claim 1, further comprising a plurality of second conductive lines, each of said plurality of non-volatile memory cells being connected between one of said first conductive lines and one of said second conductive lines.

10. 2. The apparatus of claim 1, wherein the memory comprises a look-up table configured to store addresses and corresponding second predetermined read reference values.

11. The apparatus of claim 1 , wherein the memory comprises a content-addressable memory.

12. The apparatus further comprises a device configured to decode data read from the non-volatile memory cells; The apparatus of claim 1 , wherein the condition being met includes a failure to correctly decode the first read data.

13. The apparatus of claim 12 , wherein the device comprises an error correction coding engine.

14. receiving an instruction to read a first codeword from a memory array including a plurality of codewords collectively including a corresponding first predetermined read reference value, each codeword including a corresponding second predetermined read reference value; reading the first codeword using the first predetermined read reference value to provide first read data; while reading the first codeword, obtaining the second predetermined read reference value corresponding to the first codeword from a look-up table; Decoding the first read data using an error correcting code algorithm; determining that the error correction code algorithm failed to correctly decode the first read data; and reading the first codeword using the obtained second predetermined read reference value to provide second read data.

15. Decoding the second read data using the error correction code algorithm; and 15. The method of claim 14, further comprising: determining that the error correction code algorithm was able to successfully decode the second read data.

16. The method of claim 14 , wherein the lookup table comprises a content-addressable memory.

17. 15. The method of claim 14, wherein the time required to obtain the second predetermined read reference value from the lookup table is equal to or less than the time required to complete reading the first codeword.

18. 15. The method of claim 14, wherein the memory array includes a plurality of non-volatile memory cells each including a magnetoresistive random access memory element.

19. A system comprising a control circuit, the control circuit comprising: receiving an instruction from a host device to read a first set of non-volatile memory cells in a memory array including a plurality of sets of memory cells; performing a first read of the first set of non-volatile memory cells using a first predetermined read reference value; Obtaining a second predetermined read reference value from the lookup table; configured to selectively perform a second read of the first set of non-volatile memory cells using the second predetermined read reference value only if data read during the first read cannot be correctly decoded; The acquiring step is performed in parallel with the first reading step; the first predetermined read reference value minimizes a failing bit count across all sets of the memory cells; The second predetermined read reference value minimizes a failing bit count of the first set of memory cells.

20. 20. The system of claim 19, wherein each of the non-volatile memory cells comprises a magnetoresistive random access memory element.

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