Time synchronization device, time synchronization method, and program

Abstract

A time synchronization device (10) according to the present disclosure comprises: a selection unit (16) which selects one master device (1) for time synchronization from among a plurality of master devices (1); a correction value calculation unit (17) which calculates a time correction value for correcting an internal time so that said one master device (1) and the time synchronization device are synchronized; a correction value storage unit (18) which stores the immediately preceding time correction value used for correction of the internal time; and a correction value adjustment unit (19) which, when said one master device (1) is to be switched, adjusts, on the basis of the stored time correction value, the time correction value calculated for the master device (1) that is to be switched to, and corrects the internal time on the basis of the adjusted time correction value.

Description

[Technical field]

[0001] The present disclosure relates to a time synchronization device, a time synchronization method, and a program. [Background technology]

[0002] Methods for synchronizing the time of devices on a network include methods using NTP (Network Time Protocol), IEEE 1588, etc. In particular, to achieve time synchronization with an accuracy of less than a microsecond, the time synchronization protocol PTP (Precision Time Protocol) is used (Non-Patent Document 1).

[0003] A method of time synchronization using PTP in a system in which a device that distributes time (hereinafter referred to as a "master device") and a device to be synchronized with the time distributed from the master device (hereinafter referred to as a "slave device") are connected will be described with reference to FIG. 5.

[0004] The master device transmits a Sync signal to the slave device. The master device notifies the slave device of the transmission time t1 of the Sync signal by means of the Sync signal. When the slave device receives the Sync signal, it stores the reception time t2 of the Sync signal. The slave device then transmits a Delay Req signal to the master device. The slave device stores the transmission time t3 of the Delay Req signal.

[0005] When the master device receives the Delay Req signal, it stores the reception time t4 of the Delay Req signal. The master device then transmits a Delay Resp signal to the slave device. The master device notifies the slave device of the reception time t4 of the Delay Req signal by using the Delay Resp signal. By transmitting and receiving the above-mentioned time synchronization signals (Sync signal, Delay Req signal, and Delay Resp signal), the slave device can obtain information on times t1 to t4.

[0006] Assuming that the round-trip delay between the master device and the slave device is equal, the time difference Δt between the master device and the slave device is expressed by the following formula 1. The slave device adjusts its internal time so that Δt = 0. In this way, time synchronization between the master device and the slave device is achieved. Δt=((t2-t1)-(t4-t3)) / 2 Equation 1 [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] IEEE Std 1588?-2019 "IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems" Summary of the Invention [Problem to be solved by the invention]

[0008] As shown in FIG. 6, a time synchronization device that performs time synchronization with other devices is a BC (Boundary Clock) device 10 that operates as a slave to a master device 1 connected at a higher level and as a master to a slave device 2 connected at a lower level, and performs time synchronization with the lower slave device 2 based on time information distributed from the higher level master device 1.

[0009] In PTP, in case the master device cannot transmit correct time information for some reason, a redundancy method exists in which the BC device is connected to multiple master devices 1, and when an abnormality is detected in one of the master devices 1 with which time synchronization is performed, the BC device performs time synchronization with another master device 1. Non-Patent Document 1 also specifies BMCA (Best Master Clock Algorithm), which is an algorithm corresponding to such a redundancy method.

[0010] FIG. 7 is a diagram showing an example of the configuration of a conventional BC device 10a that supports a redundant system.

[0011] As shown in FIG. 7, a conventional BC device 10a includes a timer 11, a transmitter 12, a frequency adjuster 13a, an IF (Interface) 14, a plurality of IFs 15, a selector 16, and a correction value calculator 17a.

[0012] The timer 11 manages the internal time in the BC device 10a, and outputs time information to the frequency adjuster 13a.

[0013] The oscillator 12 outputs the timing at which the timer 11 keeps time.

[0014] The frequency adjustment unit 13a adjusts the frequency of transmitting and receiving time information between the BC device 10a and the slave device 2 (the frequency of transmitting and receiving the time synchronization signal described with reference to FIG. 5).

[0015] The IF 14 is connected to the slave device 2, which is a lower-level device, and transmits and receives a time synchronization signal and the like to and from the slave device 2.

[0016] The IF 15 is connected to the master device 1, which is a higher-level device, and transmits and receives signals such as time synchronization signals to and from the master device 1. A plurality of master devices 1 (master devices 1-1 and 1-2) are connected to the BC device 10a, and the IFs 15-1 and 15-2 are connected to the master devices 1-1 and 1-2, respectively.

[0017] The selector 16 selects a primary master device 1 (one master device 1 with which the BC device 10a is time-synchronized) from the multiple master devices 1-1, 1-2 based on the time synchronization signals received from the master devices 1-1, 1-2 via the IFs 15-1, 15-2.

[0018] The correction value calculation unit 17a calculates a time correction value that is a correction value for correcting the internal time managed by the timer 11, based on the time information from the master device 1 selected by the selection unit 16, so that the selected master device 1 and the BC device 10 are synchronized. The correction value calculation unit 17a corrects the internal time based on the calculated time correction value.

[0019] In the BC device 10a shown in FIG. 7, if for some reason it becomes impossible to receive a normal time synchronization signal from the time-synchronized master device 1, the selection unit 16 selects another master device 1 connected to the BC device 10a as the new master device 1 with which to synchronize time.

[0020] Fig. 8 is a diagram showing an example of the operation of a conventional BC device 10a. In Fig. 8, the horizontal axis indicates time. The interval T between times t-2, t-1, t0, t1, t2, and t3 is the period of transmission and reception of a time synchronization signal between the BC device 10a and the slave device 2. In the following, it is assumed that a switch of the master device 1 with which the BC device 10a is time-synchronized occurs between time t0 and time t1. In other words, it is assumed that the master device 1 with which the BC device 10a is time-synchronized is changed from the master device 1 of the switch source to the master device 1 of the switch destination.

[0021] In addition, in Fig. 8, the vertical axis indicates the time correction value. In the following, the time correction values ​​for the switching source master device 1 at times t-2, t-1, and t0 are denoted as A-2, A-1, and A0, respectively, and the time correction values ​​for the switching destination master device 1 at times t1, t2, and t3 are denoted as a1, a2, and a3, respectively.

[0022] As shown in FIG. 8, when the master device 1 with which the BC device 10a is time-synchronized is switched between time t0 and time t1, the time correction value used to correct the internal time of the BC device 10a changes at time t1 from the time correction value A0 (time correction value for the master device 1 before switching) at time t0 to the time correction value a1 (time correction value for the master device 1 after switching). Here, if the difference between the time correction value A0 and the time correction value a0 is large, a sudden change occurs in the time correction value. If a sudden change occurs in the time correction value, the internal time of the BC device 10a also changes significantly, and at time t1, a time synchronization signal with a large time fluctuation is transmitted to the slave device 2. The slave device 2 may erroneously recognize that an abnormality has occurred due to receiving a time synchronization signal with a large time fluctuation. As a result, the service provided by the slave device 2 may be affected.

[0023] In consideration of the above-mentioned problems, the objective of the present disclosure is to provide a time synchronization device, a time synchronization method, and a program that can suppress the occurrence of sudden changes in the time correction value that accompany switching of a higher-level device to be time-synchronized, and reduce the impact on the operation of a lower-level device. [Means for solving the problem]

[0024] In order to solve the above problems, the time synchronization device of the present disclosure is a time synchronization device that synchronizes an internal time with a time distributed from one of a plurality of higher-level devices and synchronizes a lower-level device to the internal time, and includes a selection unit that selects the one higher-level device from the plurality of higher-level devices, a correction value calculation unit that calculates a time correction value which is a correction value that corrects the internal time so that the one higher-level device and the device itself are synchronized, a correction value memory unit that stores the most recent time correction value used to correct the internal time, and, when the one higher-level device is switched, a correction value adjustment unit that adjusts the time correction value calculated for the higher-level device to which the device is switched based on the time correction value stored in the correction value memory unit, and corrects the internal time based on the adjusted time correction value.

[0025] In addition, in order to solve the above problem, the time synchronization method disclosed herein is a time synchronization method for synchronizing an internal time with a time distributed from one of a plurality of higher-level devices, and synchronizing a lower-level device with the internal time, and includes the steps of selecting the one higher-level device from the plurality of higher-level devices, calculating a time correction value that is a correction value for correcting the internal time so that the one higher-level device and the device itself are synchronized, storing the previous time correction value used to correct the internal time, and, when the one higher-level device is switched, adjusting the time correction value calculated for the higher-level device to which the device is switched based on the stored time correction value, and correcting the internal time based on the adjusted time correction value.

[0026] In order to solve the above problem, a program according to the present disclosure causes a computer to operate as the above-mentioned time synchronization device. Effect of the Invention

[0027] The time synchronization device, time synchronization method, and program disclosed herein can suppress the occurrence of sudden changes in the time correction value that accompany switching of the higher-level device to be time-synchronized, thereby reducing the impact on the operation of the lower-level device. [Brief description of the drawings]

[0028] [Figure 1] FIG. 2 is a diagram illustrating a configuration example of a BC device according to an embodiment of the present disclosure. [Diagram 2] 2 is a flowchart showing an example of the operation of the BC device shown in FIG. [Diagram 3] 2 is a diagram for explaining adjustment of a time correction value by a correction value adjustment unit shown in FIG. 1. FIG. [Figure 4] 2 is a diagram illustrating an example of a hardware configuration of the BC device illustrated in FIG. 1. [Diagram 5] FIG. 1 is a diagram for explaining time synchronization by PTP. [Figure 6] FIG. 13 is a diagram for explaining a BC device. [Figure 7]FIG. 1 illustrates an example of the configuration of a conventional BC device. [Figure 8] 8 is a diagram for explaining a change in the time correction value accompanying switching of the master device in the BC device shown in FIG. 7. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0030] FIG. 1 is a diagram showing a configuration example of a BC device 10 according to an embodiment of the present disclosure. As shown in FIG. 6, the BC device 10 according to the present disclosure operates as a slave to a master device 1, which is a higher-level device, and operates as a master to a slave device 2, which is a lower-level device. The BC device 10 according to the present embodiment is connected to a plurality of master devices 1, and synchronizes its internal time with a time distributed from one of the master devices 1. Therefore, the BC device 10 according to the present disclosure is a time synchronization device that synchronizes its internal time with a time distributed from one of the higher-level devices (master device 1) and synchronizes a lower-level device (slave device 2) with the internal time. In FIG. 1, the same components as those in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

[0031] As shown in Fig. 1, the BC device 10 according to this embodiment includes a timer 11, a transmitter 12, a frequency adjustment unit 13, an IF 14, a plurality of IFs 15, a selection unit 16, a correction value calculation unit 17, a correction value storage unit 18, and a correction value adjustment unit 19. The BC device 10 shown in Fig. 1 differs from the BC device 10a shown in Fig. 7 in that the frequency adjustment unit 13a and the correction value calculation unit 17a are changed to the frequency adjustment unit 13 and the correction value calculation unit 17, respectively, and that a correction value storage unit 18 and a correction value adjustment unit 19 are added.

[0032] The correction value calculation unit 17 calculates a time correction value, which is a correction value for correcting the internal time managed by the timer 11, based on the time information from the master device 1 selected by the selection unit 16 so that the selected master device 1 (one higher-level device) and the BC device 10 are synchronized. The correction value calculation unit 17 outputs the calculated time correction value to the correction value storage unit 18 and the correction value adjustment unit 19.

[0033] The correction value storage unit 18 stores the immediately preceding time correction value that is output from the correction value calculation unit 17 or the correction value adjustment unit 19 and that was used to adjust the internal time of the BC device 10 .

[0034] The frequency adjustment unit 13 adjusts the frequency at which time information based on the internal time is transmitted to the slave device 2, which is a lower-level device, and transmits the time information at the adjusted frequency to the slave device 2 via the IF 14. The frequency adjustment unit 13 also outputs the frequency at which the time information is transmitted to the slave device 2 to the correction value adjustment unit 19.

[0035] When the master device 1 (one higher-level device) with which the BC device 10 is time-synchronized is switched, the correction value adjustment unit 19 adjusts the time correction value calculated by the correction value calculation unit 17 for the master device 1 to be switched to, based on the time correction value stored in the correction value storage unit 18. Then, the correction value adjustment unit 19 corrects the internal time managed by the timer 11, based on the adjusted time correction value. The correction value adjustment unit 19 adjusts the time correction value at the cycle for transmitting time information to the slave device 2, which is adjusted by the frequency adjustment unit 13. The correction value adjustment unit 19 stores the adjusted correction value in the correction value storage unit 18. Note that when the master device 1 with which the BC device 10 is time-synchronized is not switched, the correction value adjustment unit 19 does not adjust the time correction value, and corrects the internal time based on the time correction value calculated by the correction value calculation unit 17.

[0036] Next, the operation of the BC device 10 according to this embodiment will be described.

[0037] FIG. 2 is a flowchart showing an example of the operation of the BC device 10 according to this embodiment, and is a diagram for explaining a time synchronization method by the BC device 10.

[0038] When the BC device 10 detects an abnormality in the master device 1 with which it is time-synchronized, the selection unit 16 selects one master device 1 (master device 1 to be switched to) from among the multiple master devices 1 with which it will newly synchronize (step S11). Just before the switching of the master device 1 to be time-synchronized, the correction value storage unit 18 stores the time correction value for the master device 1 from which it is switched.

[0039] The correction value calculation unit 17 calculates a time correction value for the master device 1 selected as the switching destination by the selection unit 16 (step S12).

[0040] The correction value storage unit 18 stores the time correction value used to correct the internal time of the BC device 10 (step S13). If the master device 1 to be time-synchronized does not change, the correction value storage unit 18 stores the time correction value calculated by the correction value calculation unit 17. Furthermore, if the correction value adjustment unit 19 adjusts the time correction value in response to a change in the master device 1 to be time-synchronized, the correction value storage unit 18 stores the adjusted time correction value. Therefore, when a new master device 1 to be time-synchronized is selected, the time correction value for the master device 1 selected as the changeover destination has not yet been used to correct the internal time, so the correction value storage unit 18 continues to store the time correction value for the master device 1 to be changed over.

[0041] When the master device 1 (one higher-level device) with which the BC device 10 is time-synchronized is switched, the correction value adjustment unit 19 adjusts the time correction value calculated for the master device 1 to be switched to by the correction value calculation unit 17 based on the time correction value stored in the correction value storage unit 18 (the time correction value for the master device 1 before the switch in the state before the switch). The correction value adjustment unit 19 corrects the internal time managed by the timer 11 based on the adjusted time correction value (step S14). Since the internal time has been corrected based on the adjusted time correction value, the correction value adjustment unit 19 stores the adjusted time correction value in the correction value storage unit 18. The correction value adjustment unit 19 adjusts the time correction value at the cycle for transmitting time information to the slave device 2, which has been adjusted by the frequency adjustment unit 13.

[0042] Next, adjustment of the time correction value by the correction value adjustment unit 19 will be described with reference to Fig. 3. In Fig. 3, as in Fig. 8, it is assumed that switching of the master device 1 with which the BC device 10 is time-synchronized occurs between time t0 and time t1. In addition, hereinafter, the time correction values ​​for the master device 1 at the switching source at times t-2, t-1, and t0 are A-2, A-1, and A0, respectively, and the time correction values ​​for the master device 1 at the switching destination at times t1, t2, and t3 are a1, a2, and a3, respectively.

[0043] When the master device 1 with which the BC device 10 is time-synchronized is switched between time t0 and time t1, the correction value calculation unit 17 calculates the time correction value at time t1 for the switched-to master device 1. As described above, the time correction value at time t1 for the switched-to master device 1 is a1.

[0044] Correction value adjustment unit 19 adjusts the time correction value a1 calculated by correction value calculation unit 17 based on the time correction value used to adjust the internal time immediately before, which is stored in correction value storage unit 18. Correction value storage unit 18 stores time correction value A0 used to correct the internal time at time t0, which is immediately before time t1. Therefore, correction value adjustment unit 19 adjusts the time correction value a0 based on time correction value A0.

[0045] Here, the correction value adjustment unit 19 adjusts the time correction value a0 so that the difference between the time correction value a0 and the adjusted time correction value is smaller than the difference between the time correction value a0 and the time correction value A0. In other words, the correction value adjustment unit 19 adjusts the time correction value for the master device 1 of the switching destination so that the difference between the time correction value for the master device 1 of the switching destination and the adjusted time correction value is smaller than the difference between the time correction value for the master device 1 of the switching destination and the immediately previous time correction value used to adjust the internal time. For example, the correction value adjustment unit 19 calculates the average (A0+a1) / 2 of the time correction value A0 and the time correction value a0 as the adjusted time correction value a1' at time t1. Then, the correction value adjustment unit 19 adjusts the internal time based on the calculated adjusted time correction value a1'. The correction value adjustment unit 19 also stores the adjusted time correction value a1' used to adjust the internal time in the correction value storage unit 18.

[0046] Similarly, at time t2, correction value calculation unit 17 calculates time correction value a2 for the switching destination master device 1. Correction value adjustment unit 19 corrects the time correction value a2 calculated by correction value calculation unit 17 based on the time correction value a1' stored in correction value storage unit 18. For example, correction value adjustment unit 19 calculates the average (a1'+a2) / 2 of time correction value a2 and time correction value a1' as the adjusted time correction value a2' at time t2.

[0047] 3 has been described using an example in which the time correction value calculated by correction value calculation unit 17 is adjusted by averaging the time correction value calculated by correction value calculation unit 17 and the time correction value stored in correction value storage unit 18, but the present invention is not limited to this. Correction value calculation unit 17 may adjust the time correction value for the switching destination master device 1 so that the difference between the time correction value for the switching destination master device 1 and the adjusted time correction value is smaller than the difference between the time correction value for the switching destination master device 1 and the time correction value immediately prior to the adjustment of the internal time.

[0048] At time t3, the correction value adjustment unit 19 finishes adjusting the time correction value calculated by the correction value calculation unit 17, and adjusts the internal time based on the calculated time correction value. That is, when the master device 1 (one higher-level device) with which the BC device 10 is time-synchronized is switched, the correction value adjustment unit 19 corrects the internal time based on the adjusted time correction value for a predetermined period, and after the predetermined period has elapsed, corrects the internal time based on the time correction value calculated for the master device 1 to which the switch is made.

[0049] Thus, the BC device 10 as a time synchronization device according to this embodiment includes a selection unit 16, a correction value calculation unit 17, a correction value storage unit 18, and a correction value adjustment unit 19. The selection unit 16 selects one higher-level device from multiple higher-level devices (master device 1) with which to synchronize the internal time of the BC device 10. The correction value calculation unit 17 calculates a time correction value that corrects the internal time so that the one higher-level device and the BC device itself are synchronized. The correction value storage unit 18 stores the time correction value used immediately before to correct the internal time. When one higher-level device is switched, the correction value adjustment unit 19 adjusts the time correction value calculated for the higher-level device to be switched to based on the time correction value stored in the correction value storage unit 18, and corrects the internal time based on the adjusted time correction value.

[0050] In addition, the time synchronization method of this embodiment includes the steps of selecting one higher-level device from multiple higher-level devices (master device 1) with which to synchronize the internal time of the BC device 10, calculating a time correction value to correct the internal time so that the one higher-level device and the BC device itself are synchronized, storing the most recent time correction value used to correct the internal time, and, when one higher-level device is switched, adjusting the time correction value calculated for the higher-level device to which the device is switched based on the stored time correction value, and correcting the internal time based on the adjusted time correction value.

[0051] When switching one of the higher-level devices with which the internal time of the BC device 10 is synchronized, the time correction value calculated for the new higher-level device is corrected based on the time correction value used to correct the internal time immediately before, thereby preventing abrupt changes in the time correction value that accompany switching of the higher-level device. As a result, the impact on the operation of the slave device 2, which is a lower-level device, can be reduced.

[0052] Next, a hardware configuration of the BC device 10 as a time synchronization device according to this embodiment will be described.

[0053] Fig. 4 is a diagram showing an example of a hardware configuration of the BC device 10 according to an embodiment of the present disclosure. Fig. 4 shows an example of a hardware configuration of the BC device 10 when the BC device 10 is configured by a computer capable of executing program instructions. Here, the computer may be a general-purpose computer, a dedicated computer, a workstation, a PC (Personal computer), an electronic notepad, etc. The program instructions may be program code, code segments, etc. for performing necessary tasks.

[0054] 4, the BC device 10 has a processor 110, a ROM (Read Only Memory) 120, a RAM (Random Access Memory) 130, a storage 140, an input unit 150, a display unit 160, and a communication interface (I / F) 170. Each component is connected to each other so as to be able to communicate with each other via a bus 190. The processor 110 is specifically a CPU (Central Processing Unit), an MPU (Micro Processing Unit), a GPU (Graphics Processing Unit), a DSP (Digital Signal Processor), a SoC (System on a Chip), or the like, and may be composed of multiple processors of the same type or different types.

[0055] The processor 110 is a controller that controls each component of the BC device 10 and executes various arithmetic processing. That is, the processor 110 reads a program from the ROM 120 or the storage 140, and executes the program using the RAM 130 as a working area. The processor 110 controls each component and executes various arithmetic processing according to the program stored in the ROM 120 or the storage 140. In this embodiment, the ROM 120 or the storage 140 stores a program for causing a computer to function as the BC device 10 according to the present disclosure. The program is read and executed by the processor 110, thereby realizing each component of the BC device 10, for example, the timer 11, the transmitter 12, the frequency adjustment unit 13, the selection unit 16, the correction value calculation unit 17, and the correction value adjustment unit 19.

[0056] The program may be provided in a form stored in a non-transitory storage medium such as a CD-ROM (Compact Disk Read Only Memory), a DVD-ROM (Digital Versatile Disk Read Only Memory), a USB (Universal Serial Bus) memory, etc. The program may also be provided in a form downloaded from an external device via a network.

[0057] The ROM 120 is a storage unit that stores various programs and various data. The RAM 130 is a storage unit that temporarily stores programs or data as a working area. The storage 140 is configured with an HDD (Hard Disk Drive) or an SSD (Solid State Drive) and is a storage unit that stores various programs including an operating system and various data. For example, the RAM 130 or the storage 140 stores the time correction value used immediately before correcting the internal time of the BC device 10.

[0058] The input unit 150 includes a pointing device such as a mouse and a keyboard, and is used to perform various input operations.

[0059] The display unit 160 is, for example, a liquid crystal display, and displays various information. The display unit 160 may function as the input unit 150 by adopting a touch panel system.

[0060] The communication interface 170 is an interface for communicating with other devices such as external devices (for example, the master device 1 and the slave device 2), and uses standards such as Ethernet (registered trademark), FDDI, and Wi-Fi (registered trademark).

[0061] A computer can be suitably used to function as each part of the above-mentioned BC device 10. Such a computer can be realized by storing a program describing the processing contents for realizing the functions of each part of the BC device 10 in a storage unit of the computer, and reading and executing the program by a processor of the computer. In other words, the program can cause the computer to function as the above-mentioned BC device 10. The program can also be recorded on a non-transitory recording medium. The program can also be provided via a network.

[0062] The following supplementary notes are further disclosed regarding the above embodiment.

[0063] (Additional note 1) A time synchronization device that synchronizes an internal time with a time distributed from one of a plurality of higher-level devices and synchronizes a lower-level device with the internal time, comprising: A controller and a memory, The controller: selecting said one host device from said plurality of host devices; calculating a time correction value that corrects the internal time so that the one higher-level device and the device itself are synchronized; storing in the memory a time correction value used immediately before correcting the internal time; When one of the higher-level devices is switched, the time correction value calculated for the new higher-level device is adjusted based on the time correction value stored in the memory, and the internal time is corrected based on the adjusted time correction value.

[0064] (Additional note 2) In the time synchronization device according to claim 1, the controller adjusts a frequency at which time information based on the internal time is transmitted to the lower-level device, and transmits the time information to the lower-level device at the adjusted frequency; A time synchronization device that adjusts the time correction value at the cycle of transmitting the time information.

[0065] (Additional note 3) In the time synchronization device according to claim 1, A time synchronization device in which, when one of the higher-level devices is switched, the controller corrects the internal time based on the adjusted time correction value for a specified period of time, and after the specified period has elapsed, corrects the internal time based on the time correction value calculated for the higher-level device to which the switch is made.

[0066] (Additional note 4) 1. A time synchronization method for synchronizing an internal time with a time distributed from one of a plurality of higher-level devices, and synchronizing a lower-level device with the internal time, comprising: selecting said one host device from said plurality of host devices; calculating a time correction value that corrects the internal time so that the one higher-level device and the device itself are synchronized; storing the immediately preceding time correction value used to correct the internal time; A time synchronization method in which, when one of the higher-level devices is switched, a time correction value calculated for the higher-level device to which the switch is made is adjusted based on the stored time correction value, and the internal time is corrected based on the adjusted time correction value.

[0067] (Additional note 5) A non-transitory storage medium storing a program executable by a computer, the non-transitory storage medium storing the program causing the computer to operate as the time synchronization device described in appended claim 1.

[0068] Although the above-mentioned embodiment has been described as a representative example, it is obvious to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present disclosure. Therefore, the present invention should not be interpreted as being limited by the above-mentioned embodiment, and various modifications or changes can be made without departing from the scope of the claims. For example, it is possible to combine multiple building blocks shown in the configuration diagram of the embodiment into one, or to divide one building block. [Explanation of symbols]

[0069] 1 Master device (upper device) 2 Slave device (lower device) 10 BC device (time synchronization device) 11. Timer 12 Transmitter 13 Frequency adjustment unit 14,15 IF 16 Selection section 17 Correction value calculation section 18 Correction value memory section 19 Correction value adjustment section 110 Processor 120 ROM 130 RAM 140 Storage 150 Input section 160 Display section 170 Communication I / F 190 Pass

Claims

1. 1. A time synchronization device that synchronizes an internal time with a time distributed from one of a plurality of higher-level devices, and synchronizes a lower-level device with the internal time, comprising: A selection unit that selects the one higher-level device from the plurality of higher-level devices; a correction value calculation unit that calculates a time correction value that corrects the internal time so that the one higher-level device and the device itself are synchronized; a correction value storage unit that stores the immediately preceding time correction value used to correct the internal time; a correction value adjustment unit that, when the one higher-level device is switched, adjusts a time correction value calculated for the higher-level device to be switched to based on the time correction value stored in the correction value storage unit, and corrects the internal time based on the adjusted time correction value, A time synchronization device in which, when one of the higher-level devices is switched, the correction value adjustment unit corrects the internal time based on the adjusted time correction value for a specified period of time, and after the specified period has elapsed, corrects the internal time based on the time correction value calculated for the higher-level device to which the switch is made.

2. 2. The time synchronization device according to claim 1, a frequency adjustment unit that adjusts a frequency at which time information based on the internal time is transmitted to the lower-level device and transmits the time information to the lower-level device at the adjusted frequency; The correction value calculation unit adjusts the time correction value at the cycle of transmitting the time information.

3. 1. A time synchronization method for synchronizing an internal time with a time distributed from one of a plurality of higher-level devices, and synchronizing a lower-level device with the internal time, comprising: selecting the one higher-level device from the plurality of higher-level devices; calculating a time correction value that corrects the internal time so that the one higher-level device and the device itself are synchronized; storing the immediately preceding time correction value used to correct the internal time; when the one higher-level device is switched, adjusting a time correction value calculated for the higher-level device to be switched to based on the stored time correction value, and correcting the internal time based on the adjusted time correction value; A time synchronization method in which, when one of the higher-level devices is switched, the internal time is corrected based on the adjusted time correction value for a specified period of time, and after the specified period has elapsed, the internal time is corrected based on the time correction value calculated for the higher-level device to which the switch is made.

4. A program for causing a computer to operate as the time synchronization device according to claim 1 or 2.

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