Efficient Hardware Implementation of Exponential Functions Using Hyperbolic Functions - Patent application

Abstract

An apparatus and associated method involves determining a natural exponent from a digital word input by splitting the digital word and retrieving a pre-calculated predetermined value from a data store at an address defined by the first word. In an exemplary embodiment, the retrieved value may be a hyperbolic sum. The hyperbolic sum may be multiplied by a second word. Scaling the hyperbolic sum and adding the result of the multiplication to it may produce a scaled exponent value. Scaling the scaled exponent value results in e X In various embodiments, the digital word input may be fixed-point or floating-point, or may be converted between them. In various embodiments, the data store may be a look-up table. Various embodiments may provide a compact and versatile architecture for determining the natural exponent with minimal hardware resources.

Description

[Technical field]

[0001] Various embodiments relate generally to an exponent calculation circuit. [Background technology]

[0002] The exponential function has the form z=m n where m is the base and n is the exponent. Exponential functions are unique because the derivative of an exponential function of a real variable is directly proportional to the value of the function. For the natural exponential function, where m is Euler's number (e), the constant of proportionality is 1, so that the function becomes its own derivative. Ubiquitous in pure and applied mathematics, exponential functions model relationships in which a constant change in an independent variable results in an equal percentage change in a dependent variable. Such relationships may arise in various natural and social sciences, for example, population growth or compound interest. Exponential relationships also commonly occur in physics, chemistry, engineering, biology, and economics.

[0003] Natural exponential function e X and e -X For certain combinations of , and , a hyperbolic function is defined. The hyperbolic sine function is

[0004]

number

[0005] The hyperbolic cosine function can be expressed as:

[0006]

number

[0007] Therefore, e X is related to hyperbolic functions as

[0008]

number

[0009] It can be expressed as: In the context of applied mathematics, an error is the difference between a true or reference value and an estimate or approximation of that value. Error analysis can be used to evaluate the propagation of numerical errors in numerical modeling or approximation of real systems and functions as the parameters of the approximation or model are changed. Error analysis can be used to evaluate the resolution or precision of a calculation. Summary of the Invention [Means for solving the problem]

[0010] An apparatus and associated method involves determining a natural exponent from a digital word input by splitting the digital word and retrieving a pre-calculated predetermined value from a data store at an address defined by a first word. In an exemplary embodiment, the retrieved value may be a hyperbolic sum. The hyperbolic sum may be multiplied by a second word. The hyperbolic sum may be scaled and the result of the multiplication may be added to it to produce a scaled exponent value. Scaling the scaled exponent value results in e X In various examples, the digital word input may be in fixed point format or floating point format, or may be converted between them. In various embodiments, the data store may be a lookup table. Various examples may provide a compact and versatile architecture for determining the natural exponent with minimal hardware resources.

[0011] Various embodiments may provide one or more advantages. For example, some embodiments may advantageously reduce the resources required to compute the natural exponent from a digital signal. Some embodiments may be configured to compress the depth of the lookup table required to compute the natural exponent by at least half. Some embodiments may be advantageously implemented as a compact and versatile architecture suitable for fitting a wide dynamic range of exponential functions with limited hardware availability. Some embodiments may enable the natural exponent to be calculated using a single digital signal processor (DSP), using only logic gates, or using a resource-optimized combination thereof. Some embodiments may be advantageously implemented using only a single multiply-accumulate unit.

[0012] In one exemplary embodiment, the natural exponent computation circuit includes a splitter circuit configured to receive a fixed-point word and split the fixed-point word into a first word and a second word; a retrieval circuit configured to retrieve a predetermined pre-calculated hyperbolic sum from a data store at an address defined by the first word; a multiplication circuit configured to multiply the hyperbolic sum by the second word and output a multiplied hyperbolic sum; a first scaling circuit configured to receive the hyperbolic sum and scale the hyperbolic sum by a first factor; an adder circuit configured to sum the scaled hyperbolic sum and the multiplied hyperbolic sum to generate a scaled second sum; and an adder circuit configured to scale the scaled second sum by a second factor and output an e.g. X and a second scaling circuit configured to output an approximation of

[0013] The multiplier circuitry and the adder circuitry may be at least partially implemented in at least one digital signal processor (DSP). At least one of the multiplier circuitry, the adder circuitry, and the data store may be at least partially implemented as logic gates. The data store may be a look-up table. The look-up table may be configured to store entries in a fixed-point format. The depth of the look-up table may be 2 B where B is the total number of bits in the first word. The data store may be configured to store the entries in floating point format.

[0014] The first coefficient is 2 B-I where B is the total number of bits in the first word, I is the total number of integer bits in the first word, and the first scaling circuit may right-zero pad the hyperbolic sum by BI bits. The second coefficient may be 1 / (2 B-I ), where B is the total number of bits and I is the total number of integer bits in the first word, and the second scaling circuit may bit-wise right shift the second sum by BI bits.

[0015] The natural exponent computation circuit may also include a floating-point to fixed-point conversion circuit prior to the splitter circuit, the conversion circuit configured to receive the floating-point input and convert the floating-point input to a fixed-point word received by the splitter circuit. The natural exponent computation circuit may also include a fixed-point to floating-point conversion circuit following the second scaling circuit, the conversion circuit configured to convert e in fixed-point format. X and outputting the output approximation in floating point format.

[0016] The second word may represent a numerical value less than 1. The circuit may be configured such that the fixed-point word is N bits long, the first word is the first B bits of the fixed-point word, the second word is the last A bits of the fixed-point word, N=A+B, and the first word contains the binary point of the fixed-point word. X B may be chosen such that the approximation of is accurate within given error limits.

[0017] In another exemplary embodiment, a method for efficiently calculating an exponent in digital circuitry includes receiving a digital fixed-point word X that is N bits long; splitting the first B bits of X into a first word Wb and the remaining A bits of X into a second word Wa, where the first word includes I integer bits and BI fractional bits, N=A+B, and X=Wb+Wa; retrieving a predetermined pre-computed hyperbolic sum representing sinh(Wb)+cosh(Wb) from a data store at an address defined by Wb; and multiplying the curve sum by Wa to generate a multiplied hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×[Wa]; scaling the hyperbolic sum by a scaling factor K to generate a scaled hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×K; adding the multiplied hyperbolic sum to the scaled hyperbolic sum to generate a scaled second sum representing [sinh(b)+cosh(b)]×[Wa+K]; and scaling the scaled second sum by 1 / K to obtain e X and generating a representation of [sinh(Wb)+cosh(Wb)]×[Wa / K+1] as an approximation of Wb. The multiplying and adding steps may be implemented at least in part in at least one digital signal processor (DSP). The data store may be a lookup table configured to store entries in a fixed-point format, the lookup table having a depth of 2. B The first word Wb may contain the binary points of X, where K is 2 B-Iscaling the hyperbolic sum by K may include right zero padding the hyperbolic sum by BI bits, and scaling the scaled second sum by 1 / K may include bitwise right shifting the second sum by BI. X B may be chosen such that the approximation of is accurate within given error limits.

[0018] In another representative embodiment, at least one non-transitory computer readable medium may provide a program of instructions that, when executed by a processor, causes an operation to calculate a natural exponent, the operation including: receiving a digital fixed-point word X that is N bits long; splitting the first B bits of X into a first word Wb and the remaining A bits of X into a second word Wa, where the first word includes I integer bits and BI fractional bits, where N=A+B, and X=Wb+Wa; retrieving a predetermined pre-calculated hyperbolic sum representing sinh(Wb)+cosh(Wb) from a data store at an address defined by Wb; and multiplying the hyperbolic sum by Wa to obtain [s generating a multiplied hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×[Wa]; scaling the hyperbolic sum by a scaling factor K to generate a scaled hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×K; adding the multiplied hyperbolic sum to the scaled hyperbolic sum to generate a scaled second sum representing [sinh(b)+cosh(b)]×[Wa+K]; and scaling the second scaled sum by 1 / K to obtain e X and generating an expression for [sinh(Wb)+cosh(Wb)]×[Wa / K+1] as an approximation of

[0019] The details of various embodiments are set forth in the accompanying drawings and the detailed description below. Other features and advantages will be apparent from the detailed description and drawings, and from the claims. [Brief description of the drawings]

[0020] [Figure 1] 1 represents a representative programmable integrated circuit (IC) in which the disclosed circuits and processes may be implemented. [Diagram 2] Represents a representative use case for natural exponential computation circuits. [Figure 3A] 1 illustrates a block diagram of an exemplary natural exponent computation circuit. [Figure 3B] 1 depicts a block diagram of a compact and versatile exponential computation circuit that accepts and outputs floating-point values. [Figure 3C] 1 illustrates a block diagram of an exemplary natural exponent computation circuit that accepts fixed-point values ​​and outputs floating-point values. [Figure 3D] 1 illustrates a block diagram of an exemplary natural exponent computation circuit provided with a hyperbolic sum floating-point data store. [Figure 4] 1 depicts a block diagram of a representative system that implements compact exponential computation using a high-level language representation in a unified architecture. [Diagram 5] 13 presents simulation results evaluating the accuracy of a representative architecture with a constant input dynamic range. [Figure 6] 13 presents simulation results evaluating the accuracy of a representative architecture as the input dynamic range is varied. [Figure 7A] 13 illustrates simulation results evaluating the accuracy of a representative architecture as the word width varies across a first input dynamic range. [Figure 7B] 13 depicts simulation results evaluating the accuracy of a representative architecture as the word width is varied over a second, wider input dynamic range. [Figure 8] This represents a typical compact and versatile way of computing exponents in circuits. [Figure 9] This shows a representative method for optimizing the configuration of a circuit for calculating an exponent. [Figure 10]1 illustrates a representative architecture for a System-on-Chip (SOC) in which the disclosed circuits and processes may be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Like reference numbers in the various drawings indicate like elements. Apparatus and associated methods for compact and versatile computation of natural exponents. For ease of understanding, this specification is organized as follows. First, with reference to FIG. 1, a representative platform suitable for performing data communication (e.g., a field programmable gate array (FPGA)) is briefly introduced. Second, with reference to FIG. 2, a representative use case for implementing the compact computation of natural exponents is described. Third, with reference to FIGS. 3A-9, representative circuits and methods illustrating various implementations of the case of compact computation of natural exponents are described. Finally, with reference to FIG. 10, another representative platform suitable for performing data communication and DSP (e.g., a system on chip (SOC)) is briefly introduced.

[0022] 1 depicts a representative programmable integrated circuit (IC) in which the disclosed circuits and processes may be implemented. The programmable IC 100 may include an FPGA logic circuit. The programmable IC 100 may be implemented with a variety of programmable resources and may be referred to as a system on a chip (SOC). Various examples of FPGA logic circuits may include an arrangement of several different types of programmable logic blocks.

[0023] For example, Figure 1 shows a programmable IC 100 that includes a number of different programmable tiles, including a multi-gigabit transceiver (MGT) 101, a configurable logic block (CLB) 102, blocks of random access memory (BRAM) 103, an input / output block (IOB) 104, configuration and clocking logic (CONFIG / CLOCKS) 105, a digital signal processing block (DSP) 106, dedicated input / output blocks (I / O) 107 (e.g., clock ports), and other programmable logic 108 (e.g., digital clock managers, analog-to-digital converters, system monitoring logic). The programmable IC 100 includes a dedicated processor block (PROC) 110. The programmable IC 100 may include internal and external reconfiguration ports (not shown).

[0024] In various examples, the MGT 101 can be used to implement a serializer / deserializer. The MGT 101 can include various data serializers and data deserializers. The data serializer can include various multiplexer implementations. The data deserializer can include various demultiplexer implementations.

[0025] In some examples of FPGA logic circuits, each programmable tile includes a programmable interconnect element (INT) 111 with standardized interconnects 124 between corresponding interconnect elements in each adjacent tile. The programmable interconnect elements taken together therefore implement a programmable interconnect structure in the illustrated FPGA logic circuit. The programmable interconnect element INT 111 includes internal connections 120 between programmable logic elements within the same tile, as shown in the example included in FIG. 1. The programmable interconnect element INT 111 includes interconnects 122 between programmable interconnect elements INT 111 within the same tile, as shown in the example included in FIG. 1.

[0026] For example, CLB 102 may include a single programmable interconnect element INT 111 in addition to configurable logic element (CLE) 112 that may be programmed to implement a user logic circuit. BRAM 103 may include BRAM logic element (BRL) 113 and one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a tile may vary depending on the height of the tile. In the depicted implementation, the height of the BRAM tile is the same as five CLBs, although other numbers (e.g., four) may be used. DSP tile 106 may include DSP logic element (DSPL) 114 and one or more programmable interconnect elements. IOB 104 may include, for example, two instances of input / output logic element (IOL) 115 and one instance of programmable interconnect element INT 111. For example, the actual I / O bond pads connected to the I / O logic elements 115 may be fabricated using metal overlaid on the various illustrated logic blocks and do not have to be confined to the area of ​​the input / output logic elements 115.

[0027] In the illustrated implementation, a columnar area near the center of the die (shown shaded in FIG. 1) is used for configuration, clocks, and other control logic. A horizontal area 109 extending from the columns distributes clock and configuration signals across the width of the programmable IC 100. Note that when referring to "column" and "horizontal" areas, the drawings are viewed vertically.

[0028] Some programmable ICs utilizing the architecture shown in Figure 1 may include additional logic blocks that interrupt the regular columnar structure that makes up most of the programmable IC. The additional logic blocks may be programmable blocks and / or dedicated logic circuits. For example, the processor block PROC 110 shown in Figure 1 spans several columns of CLBs 102 and BRAMs 103.

[0029] 1 illustrates a representative programmable IC architecture. The number of logic blocks in a column, the relative width of the columns, the number and order of the columns, the types of logic blocks contained in a column, the relative sizes of the logic blocks, and the interconnect / logic implementation are provided merely as examples. For example, an actual programmable IC may include two or more adjacent columns of CLBs 102 wherever CLB 102 is shown to facilitate efficient implementation of user logic circuitry.

[0030] For example, an integrated circuit (IC) (e.g., an FPGA) such as the programmable IC 100 may be used to determine the natural exponent. The architecture of the IC may be advantageously configured to efficiently calculate the natural exponent from a digital word input by splitting the word into a first word and a second word and using the first word to retrieve the hyperbolic sum from a data store.

[0031] 2 illustrates a representative use case 200 of a natural exponent computation circuit. The fixed-point word X 205 represents an exponent that may be intended as the power to which Euler's number (the mathematical constant denoted as "e") should be raised. e XA word X, which may be represented as: is N bits long 215[0:N-1]. Word X is divided into a first word Wb that is B bits long 220 and a second word Wa that is A bits long 225. The first word Wb contains a binary point 240, and therefore I integer bits 230 and F fractional bits 235. The remaining fractional bits of word X are in A. Thus, the number of bits in X is equal to the number of bits in Wb plus the number of bits in Wa, so N=B+A. Similarly, the number of bits in B is equal to the number of integer bits plus the number of fractional bits, so B=I+F.

[0032] The word Wb is stored in the data store 210 as X The hyperbolic trigonometric representation may be used as an address that contains a hyperbolic trigonometric representation that represents sufficient data to generate a desired representation of the result of, or result from, e.g., . The hyperbolic trigonometric representation may be used in further operations to obtain, within a desired tolerance, e.g., . x The further operations may include addition, multiplication, or a combination thereof. Further operations may also be performed on Wa, for example.

[0033] Thus, the exponential function may be advantageously implemented in a variety of compact and versatile architectures that use hyperbolic functions. For example, in some embodiments, the exponential computation circuitry may be advantageously implemented in embedded circuitry (e.g., an FPGA or ASIC).

[0034] The dynamic range of the exponential function can be quite large, making digital implementation challenging. Various embodiments can advantageously implement properties of the exponential function that compress the size of the lookup table used to calculate the exponential function and reduce the processing resources used for the calculation. Some embodiments can be implemented using a single compressed lookup table and a single multiply-accumulate unit, which can be advantageous, for example, when area and resources are limited. Some embodiments can advantageously implement compact exponential calculation circuits, for example, in convolutional neural networks (CNNs), fast Fourier transform (FFT) circuits, and digital signal processing (DSP) applications.

[0035] As an example, the digital word X can be expressed as the result (y): y=e X may be the exponent of the Euler number for which e is desired. X may be expressed as a sum of the following hyperbolic functions:

[0036] Formula 1: y = e X =cosh(X)+sinh(X) where cosh is the hyperbolic cosine function and sinh is the hyperbolic sine function.

[0037] X can be expressed as the sum of Wb and Wa scaled by a factor K, where X=Wb+Wa×K. For example, by way of illustration, Wa may be a fixed-point word A bits long. If Wa is left zero-padded to be N bits long, where the first B bits are equal to zero, the result is Wa / K, where K=2 B-I For example, K can be chosen to suit a given implementation, including values ​​of B, A, I, or F, or some combination thereof, based on whether fixed or floating point numbers are used.

[0038] Then y can be re-expressed, expanded and simplified using Wa×K and Wb.

[0039]

number

[0040] Wb can be expressed as a function of the length A of X (the number of bits in Wa), N (the number of bits in X), and I (the number of integer bits in Wb) as follows:

[0041]

number

[0042] Since the value of Wa is determined by the fractional bits of X, we can assume that Wa<1. With this assumption, sinh(Wa) and cosh(Wa) can be simplified to:

[0043]

number

[0044] As Wa approaches zero, the limit of sinh(Wa) approaches Wa, and as Wa approaches zero, the limit of cosh(Wa) approaches 1; assuming Wa<1, or especially if Wa<<1 (Wa is much less than 1), sinh(Wa) can be approximated as Wa and cosh(Wa) can be approximated as 1. Thus, equation 2C can be simplified to:

[0045]

number

[0046] 3A illustrates a block diagram of an exemplary natural exponent computation circuit. Exponent computation circuit 300A receives fixed-point word X of N bits [0:N-1]. Splitting circuit 302 splits X bit-wise into two words: a first word Wb of bits [B+1:N-1] and a second word Wa of bits [0:A-1], where A is the number of bits in Wa, B is the number of bits in Wb, and N=B+A. First word Wb is an address in data store 304 that corresponds to a value representing sinh(Wb)+cosh(Wb). Data store 304 may be implemented as, for example, a look-up table, or a portion thereof, having predetermined pre-calculated values ​​for sinh(Wb)+cosh(Wb). Data store 304 may be implemented, for example, in read-only memory (ROM) or as a lookup table in random access memory (RAM), block RAM (BRAM), static RAM (SRAM), dynamic RAM (DRAM), or other suitable data store. For example, by way of example and not limitation, data store 304 may be implemented in BRAM and contain a 2-deep CRAM where each value of Wb within a predetermined range is a predetermined pre-calculated value of [sinh(Wb)+cosh(Wb)]. B The predetermined range may be set according to a predetermined value of B. Splitting X into two words of B and A bits advantageously reduces the size of multiplier 306 from a multiplier sufficient to work on N bits to a multiplier sufficient to work on a maximum of B or A bits.

[0047] The hyperbolic sum retrieved from the data store 304 can be expressed as the following equation: Equation 6: sinh(Wb)+cosh(Wb) The hyperbolic sum is multiplied by Wa by multiplication circuit 306 to obtain a multiplied hyperbolic sum that may be expressed as:

[0048] Equation 7: [sinh(Wb)+cosh(Wb)]×Wa Scaling circuit 308 scales the hyperbolic sum retrieved from data store 304 by a factor K. In an implementation where X is a fixed point number, K may be, for example, 2 B-I where B is the number of bits in Wb and I is the number of integer bits in B. In some implementations where X is a floating point number, scaling can be accomplished in scaling circuit 338, for example, by right zero padding the hyperbolic sum by BI bits.

[0049] The multiplied hyperbolic sum and the scaled hyperbolic sum are then summed in summing circuit 310 to generate a scaled exponent calculation, which can be expressed as the following equation:

[0050]

number

[0051] Scaling circuit 312 then applies a scaling factor 1 / K to the scaled exponent calculation to generate the exponent calculation. Scaling circuit 312 may be, for example, a scaling factor of 1 / K. B-I BI bits may be right bitwise shifted, such as in a fixed-point implementation where BI bits is the bitwise shift of BI.

[0052] The exponent calculation produced by the scaling circuit 312 can be expressed as the following equation:

[0053]

number

[0054] According to Equation 5, this index calculation is e X is approximately equal to

[0055]

number

[0056] Thus, a circuit implemented as depicted in FIG. 3A can provide an e from an input X, for a given range of X, and for the sizes of N, A, and B, within acceptable error limits. X The method may be configured to advantageously calculate the value of

[0057] FIG. 3B shows a block diagram of a compact and versatile natural exponent computation circuit that accepts and outputs floating-point values. Circuit 300B may be, for example, a circuit similar to that implemented in FIG. 3A, with floating-point conversion blocks added at the inlet and outlet of the circuit that allow floating-point inputs to be received, converted to fixed-point, and exponent calculations to be generated and then converted to floating-point outputs. Typically, a floating-point value is received and converted to a fixed-point word X by a floating-point to fixed-point conversion circuit 330. Word X is split into a first word Wb and a second word Wa by a split circuit 332. A hyperbolic sum is received from a data store 334 at an address defined by Wb. The hyperbolic sum is multiplied by Wa by a multiplication circuit 336 to generate a multiplied hyperbolic sum. The hyperbolic sum is scaled by a factor K in scaling circuit 338 and the result is multiplied and added to the hyperbolic sum by summing circuit 340 to produce a scaled exponent calculation. The scaled exponent calculation is scaled by a factor 1 / K by scaling circuit 342 and the resulting fixed-point exponent calculation is converted to a floating-point value by fixed-point to floating-point conversion circuit 344. The resulting floating-point ... within acceptable error limits. X can be expressed as:

[0058] FIG. 3C shows a block diagram of a representative natural exponent computation circuit that accepts fixed-point values ​​and outputs floating-point values. Circuit 300C may be, for example, a circuit similar to that implemented in FIG. 3A, with the addition of a floating-point conversion block at the output of the circuit that allows a floating-point input to be received and an exponent calculation to be generated and converted to a floating-point output. Typically, a fixed-point word X is received and split into a first word Wb and a second word Wa by a split circuit 360. A hyperbolic sum is retrieved from a data store 362 at an address defined by Wb. The hyperbolic sum and Wa are multiplied by a multiplication circuit 364 to generate a multiplied hyperbolic sum. The hyperbolic sum is scaled by a factor K in a scaling circuit 366, and the result is added to the multiplied hyperbolic sum by a summing circuit 368 to generate a scaled exponent calculation. The scaled exponent calculation is scaled by a factor 1 / K by scaling circuit 370, and the resulting fixed-point exponent calculation is converted to a floating-point value by fixed-point to floating-point conversion circuit 372. The resulting floating-point exponent calculation is then scaled by a factor 1 / K by scaling circuit 370, and the resulting fixed-point exponent calculation is converted to a floating-point value by fixed-point to floating-point conversion circuit 372. The resulting floating-point exponent calculation is then scaled by a factor 1 / K by X can be expressed as:

[0059] FIG. 3D illustrates a block diagram of an exemplary natural exponent computation circuit with a floating-point data store of hyperbolic sums. The exponent computation circuit 300D may be, for example, a circuit similar to that implemented in FIG. 3A, with the data store configured to store floating-point values ​​and the addition of a floating-point conversion block that allows a fixed-point input to be received, an exponent computation to be generated, and a natural floating-point output to be produced by converting a second word to a floating-point word. Typically, a fixed-point word X is received and divided into a first word Wb and a second word Wa by a division circuit 380. A hyperbolic sum in floating-point format is received from a floating-point data store 382 at an address defined by Wb. The data store 382 may be provided with a pre-loaded pre-calculated hyperbolic sum representing sinh(Wb)+cosh(Wb) in floating-point format. Wa is converted from fixed-point format to floating-point format in fixed-point to floating-point conversion circuit 384 .

[0060] The hyperbolic sum is multiplied by Wa by multiplication circuit 386 to produce a multiplied exponent hyperbolic sum. In scaling circuit 388, the hyperbolic sum is scaled by a factor K and the result is added to the multiplied hyperbolic sum by circuit 390 to produce a scaled exponent calculation. The scaled exponent calculation is scaled by a factor 1 / K by scaling circuit 392. The resulting floating point calculation is scaled to e within an acceptable error range. X can be expressed as:

[0061] FIG. 4 illustrates a block diagram of an exemplary system that uses a high-level language expression to implement compact exponential computation in a unified architecture. Specifically, FIG. 4 illustrates a generic system that compiles instructions in a high-level language (HLL) to configure, for example, any or all of n programmable logic blocks (1, 2, 3, ... n). The configuration system 400A includes a deployment environment 405. A user can generate instructions at design time using an HLL (e.g., P4 language) that can, via compile-time register-transfer level (RTL) generation, produce a hardware architecture that can perform exponential computation with a compressed data store using an FPGA 465 at run time. The deployment environment 405 also includes an HLL compiler 415. The HLL compiler 415 is operatively connected to an HLL program 410 and a database 420. In the example of this depiction, the database 420 includes a user library 420a and an HLL library 420b. The HLL compiler 415 can select available library files in the database 420 and compile the HLL commands into one or more instruction sets, which may also be referred to as data structures. During deployment, the HLL compiler 415 can store the instruction sets in a data store or NVM 425 (non-volatile memory).

[0062] The configuration system 400A also includes an implementation environment 430. For example, an implementation engineer can use some compiler tools to convert the instructions stored in the NVM 425 into a hardware / software implementation 430a (e.g., RTL (register transfer logic)) that can be loaded, e.g., via a bitstream, into a target device, such as the FPGA 465. In some embodiments, the implementation environment 430 can generate data files suitable for realizing fixed hardware (e.g., in an ASIC) according to a design specified by, for example, user-input high-level language programming in the deployment environment 405.

[0063] Configuration system 400A also includes hardware environment 440. Hardware environment 440 may include, for example, a line card. In some embodiments, hardware environment 440 may include a network interface card (NIC). In the depicted example, hardware environment 440 includes a number of buffers 445a (e.g., capable of forming an I / O interface) that connect external signals to an FPGA (e.g., FPGA 465). In the depicted example, FPGA 465 includes n programmable logic blocks that represent programmable hardware resources that can be used to realize circuitry according to a design specified, for example, by user-input high-level language programming in deployment environment 405. FPGA 465 also interfaces with other devices 445b that can provide various auxiliary functions.

[0064] Figure 5 shows simulation results evaluating the accuracy of a representative architecture with a fixed input dynamic range. In various embodiments, the accuracy of the exponent calculation is determined by the number of bits B contained in Wb. In some embodiments, such as those configured for a fixed-point input X with a given number of integer bits, the accuracy is determined indirectly by B as a result of the number of fractional bits F contained in Wb, where F=BI. As F increases, A decreases, thereby decreasing the value of Wa. As the value of Wa decreases, Wa approaches zero, and simplifying assumptions in Equations 4A and 4B lead to a simplified Equation 5 that is increasingly accurate.

[0065] N=28, L f = 14, and for the example embodiment where X is in the range [-1, 1], as B varies, the maximum error graph 501 shows that the non-compressed implementation (e.g., X 3A). As B approaches 12 bits, the maximum error decreases by approximately 3.48×10 -5 From approximately 3.07 x 10-5 and remains constant through 15 bits. For B=16 bits, the error is approximately 3.1×10 -5 will increase slightly.

[0066] Average error graph 502 compares the average error between uncompressed and compressed calculations for the same implementation as graph 501. Graph 502 shows that the average error for the uncompressed calculations converged and remained stable around B=17. Thus, for example, a value or range of B can be selected and predefined according to a given error limit. Using the range of B, the width of the lookup table can be set to 2 for all addresses Wb in the data store within a word of B bits. B and the value of sinh(Wb)+cosh(Wb) can be predetermined.

[0067] Figure 6 shows simulation results evaluating the accuracy of a representative architecture as the input dynamic range is varied. The accuracy may be determined by the number of integer bits (I) in the first word Wb before the binary point, for example, if Wb is in a fixed-point format. For example, if B is held constant and I increases, the number of fractional bits (F) in Wb decreases. Thus, the precision of the represented values, and therefore the granularity of the lookup table, may decrease, resulting in a loss of accuracy.

[0068] N=16, L f = 14, B = 12, and X is in the range [-|2 I-1 |, 2 I-1 As I varies in the example embodiment in [ , the maximum error graph 601 shows the maximum error for a non-compressed implementation (e.g., X 3A ) with a compressed implementation such as the one shown in FIG. 3A. Similarly, average error graph 602 compares the average error in the same simulation scenario. Below 3 bits, the error in the compressed embedding is approximately 0.15×10 -4and remains almost indistinguishable from the uncompressed implementation. After I=3 bits, the error starts to become large. Thus, for example, the error value or range of I can be selected and predefined according to a given error limit. For example, depending on a given range of X, the value of I can be chosen to be sufficient to represent that value, and the value of B chosen will depend on I such that F is large enough to represent X with enough precision to stay within the given error limit.

[0069] FIG. 7A shows simulation results evaluating the accuracy of the representative architecture as the word width is varied across the first input dynamic range. The accuracy may be determined, for example, by the number of fractional bits in a given pre-calculated hyperbolic sum stored in a data store. The number of stored fractional bits is L f It can be expressed as L f can be determined, for example, during a configuration process and may depend, for example, on X, B, I, F, or some combination thereof.

[0070] N=16, L f In the illustrated embodiment, where A is in the range [10, 18], B is in the range [9, 12], and X is in the range [-1, 1], L f Since and B change, the maximum error graph 701 shows the maximum error for the non-compressed implementation (e.g., X 3A) with a calculation in a non-compressed implementation such as that shown in FIG. 3A. Similarly, average error graph 702 compares the average error in the same simulation scenario. The different compression series on graphs 701 and 702 are f represents the discrete values ​​of B that are plotted against the error. As can be seen, the error is mostly f As increases, the accuracy improvement is moderated by an exponential decay. f As B and L continue to increase, the error decreases. Similarly, the error is mitigated as B increases, but with diminishing returns. fThe improvement in error by increasing is more pronounced when evaluating the maximum error than the average error, and the increased B and L f Responses to and may appear indistinguishable at this level.

[0071] 7B shows simulation results evaluating the accuracy of the representative architecture as the word width is varied across a second, larger input dynamic range. The maximum error graph 703 shows that the accuracy of the uncompressed implementation (e.g., e X 703 and 704 show the maximum error between the “exact” calculation of L and the calculation in the compressed implementation. Similarly, average error graph 704 compares the average error in the same simulation scenario. The different compression series in graphs 703 and 704 show the effect of L on the error. f is varied to represent distinct values ​​of B that are plotted.

[0072] As can be seen, the error is also mostly L f As increases, the exponential decay is relaxed, and L f As B continues to increase, the improvement in accuracy decreases. Similarly, the error is mitigated as B increases, again with diminishing returns. f The improvement in error by increasing is more pronounced when evaluating the maximum error than the average error, and the increased B and L f The responses to and are often indistinguishable at this level. Most notably, as the range of X increases, B appears to have a stronger effect on the error, especially the maximum error. For example, the maximum error is roughly 2.5×10 for B=9. -4 It appears flat at L f The increase in L f After B = 13, it has little further effect. A significant improvement in both maximum and average error is seen by increasing B to 10. The compressed vs. uncompressed error appears to converge by B = 12. Thus, for a given range of X, and a given error bound, N, Lf , and the value of B depends on the computational resources (e.g., the selected L f can be advantageously chosen to balance the memory size required by the lookup table (determined by: x = 1, y ...

[0073] FIG. 8 illustrates an exemplary compact and versatile method for calculating an exponent in a circuit. The method 800 may be embodied in a circuit, such as the exemplary implementations described with reference to FIGS. 3A-3D, in computer program instructions for one or more controllers, or in a circuit design optimization system. A fixed-point digital word X, which may be N bits long, is received 805. The word X is split into two words: a first word Wb, which is the first B bits of X, and a second word Wa, which contains the last A bits of X. The word X is split into a natural exponent e, which is a digital word that is generated by dividing the natural exponent e by a digital value. X The fixed-point digital word X may, for example, have been previously converted from a floating-point value. The first word Wb may contain the binary point of X and may contain I integer bits and F fractional bits, where B=I+F. The second word Wa may be A bits long, where A=NB and X=Wb+Wa / K, where K is a scaling factor. Thus, the X bits can be addressed as [0:N-1], the Wb bits can be addressed as [B+1:N-1], and Wa can be addressed as [0:A].

[0074] The first word, Wb, may define an address in a data store. The data store may, for example, contain predetermined pre-calculated values ​​of sinh(Wb)+cosh(Wb) for a predetermined range of X and predetermined values ​​of B, and may be 2 deep. BA predetermined pre-calculated hyperbolic sum representing sinh(Wb)+cosh(Wb) is retrieved 815 from the data store. The hyperbolic sum is multiplied by Wa to represent [sinh(Wb)+cosh(Wb)]×[Wa] 825. The hyperbolic sum is scaled by K to represent [sinh(Wb)+cosh(Wb)]×K 820. The scaling can be done, for example, by K=2 B-I This can be done by right-zero padding the hyperbolic sum by BI bits so that

[0075] The scaled hyperbolic sum and the multiplied hyperbolic sum are then summed to produce a scaled exponential calculation representing 830, [sinh(Wb)+cosh(Wb)]×[Wa+K]. The result is scaled by a scaling factor of 1 / K to produce e X 835 represents [sinh(Wb)+cosh(Wb)]×[Wa / K+1] as an approximate representation of Wb. Scaling 835 is, for example, a 1 / 2 B-I may be a right shift of the fixed-point value by BI bits, corresponding to multiplying by

[0076] The method 800 may, for example, be implemented as a lookup table with a depth of 2. B Alternatively, B may be implemented using a multiply-accumulate unit in a resource-limited circuit requiring a ROM. B may be determined according to a predetermined range of values ​​for X, for example, according to a predetermined error bound.

[0077] 9 illustrates an exemplary method for optimizing the configuration of a circuit for calculating the exponent. Method 900 optimizes the exponent according to a compression calculation method such as according to exemplary method 800 illustrated in FIG. 8 together with a maximum error parameter. X The method starts by receiving 905 a range of values ​​for X and a maximum error parameter when calculating X. Next, a configuration simulation is performed 910 to simulate implementation parameters, such as, but not limited to, B, A, F, I, L, etc. f , lookup table depth, or some combination thereof.

[0078] The results are evaluated to determine if the maximum error parameter is exceeded 915. If the maximum error parameter is exceeded, the implementation parameters are varied 920 and the simulation is repeated 910. If the maximum error parameter is not exceeded, the resources required by the implementation are determined 950 for multiple hardware configurations, including logic gate implementations and DSP implementations. For example, a logic synthesis tool that produces a design implementation using the given implementation parameters can be used to determine the resources to produce the hardware implementation configurations, which can include, for example, logic gates, DSP, BRAM, other suitable hardware, or some combination thereof. The resources may be, for example, the given resources available on a given FPGA or ASIC. The required resources can include, for example, the number of logic gates, the size of the data store, and the physical footprint. The hardware implementations are compared to determine which implementation uses the least resources. If the logic gate implementation is the most resource efficient, it is selected 955. If the DSP implementation is the most resource efficient, it is selected 960.

[0079] In various embodiments, the hardware implementations compared may include implementations other than DSP and logic gates, and some implementations may omit DSP, omit logic gates, or omit both. Some embodiments may evaluate hardware implementations of a combination of DSP and logic gates, or multiple combinations thereof. Various embodiments of method 900 may be implemented at least in part in a synthesizer, which may be advantageously used, for example, to configure FPGA firmware, design ASICs, or configure circuits, program instructions, or some combination thereof. Some embodiments may be implemented in computer program instructions, which may be vendor specific, for example, that allow a user to select various parameters, including R and maximum error, or ranges thereof, and select a resource-optimized configuration. Some embodiments may allow a user to compare resources used, computation speed, error bounds, ranges of X given error bounds, other parameters of interest, or some combination thereof, based on constraints on one or more parameters of interest to the user.

[0080] FIG. 10 illustrates another example architecture for a system-on-chip (SOC) in which the disclosed circuits and processes may be implemented. SOC 1000 is an example of a programmable IC and integrated programmable device platform. In the example of FIG. 10, various different subsystems or regions of the illustrated SOC 1000 may be implemented on a single die provided within a single integrated package. In other examples, various subsystems may be implemented on two or more interconnected dies provided as a single integrated package.

[0081] In this example, SOC 1000 includes two or more regions having circuitry with various functions. In this example, SOC 1000 optionally includes a data processing engine (DPE) array 1002. SOC 1000 includes a programmable logic (PL) region 1004 (hereafter PL region or PL), a processing system (PS) 1006, a network-on-chip (NOC) 1008, and one or more hardwired circuit blocks 1010. DPE array 1002 is implemented as two or more interconnected hardwired programmable processors with interfaces to other regions of SOC 1000.

[0082] PL 1004 is circuitry that can be programmed to perform a particular function. By way of example, PL 1004 may be implemented as a field programmable gate array type of circuitry. PL 1004 may include an array of programmable circuit blocks. Examples of programmable circuit blocks in PL 1004 include, but are not limited to, configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs and / or UltraRAMs or URAMs), digital signal processing blocks (DSPs), clock managers, and / or delay lock loops (DLLs).

[0083] Each programmable circuit block in the PL 1004 typically includes both programmable interconnect circuitry and programmable logic circuitry. The programmable interconnect circuitry typically includes a number of interconnect wires of various lengths interconnected by programmable interconnect points (PIPs). Typically, the interconnect wires are configured (e.g., on a wire-by-wire basis) to provide bit-wise connectivity (e.g., where each wire carries a single bit of information). The programmable logic circuitry implements user-designed logic circuits using programmable elements, which may include, for example, look-up tables, registers, arithmetic logic circuits, and the like. The programmable interconnect and programmable logic circuitry may be programmed by loading configuration data into internal configuration memory cells that defines how the programmable elements are configured and operate.

[0084] The PS 1006 is implemented as hardwired circuitry that is manufactured as part of the SOC 1000. The PS 1006 may be implemented as or include any of a variety of different processor types, each capable of executing program code. For example, the PS 1006 may be implemented as an individual processor, e.g., a single core capable of executing program code. In another example, the PS 1006 may be implemented as a multi-core processor. In yet another example, the PS 1006 may include one or more cores, modules, co-processors, interfaces, and / or other resources. The PS 1006 may be implemented using any of a variety of different types of architectures. Example architectures that may be used to implement the PS 1006 include, but are not limited to, an ARM processor architecture, an x86 processor architecture, a GPU architecture, a mobile processor architecture, a DSP architecture, or other architectures suitable for executing computer-readable instructions or program code.

[0085] The NOC 1008 includes an interconnection network for sharing data between endpoint circuits in the SOC 1000. The endpoint circuits may be located in the DPE array 1002, the PL area 1004, the PS 1006, and / or in the hardwired circuit blocks 1010. The NOC 1008 may include high speed data paths with dedicated switching. In one example, the NOC 1008 includes horizontal paths, vertical paths, or both horizontal and vertical paths. The arrangement and number of areas shown in FIG. 10 are merely examples. The NOC 1008 is an example of a common infrastructure that may be used within the SOC 1000 to connect selected components and / or subsystems.

[0086] The NOC 1008 provides connectivity to the PL 1004, the PS 1006, and to selected ones of the hardwired circuit blocks 1010. The NOC 1008 is programmable. In the case of a programmable NOC used in conjunction with other programmable circuits, the nets to be routed through the NOC 1008 are not known until a user circuit design is created for implementation within the SOC 1000. The NOC 1008 can be programmed by loading configuration data into internal configuration registers that define how elements such as switches and interfaces within the NOC 1008 are configured and function to pass data from switch to switch and between NOC interfaces.

[0087] The NOC 1008 is manufactured as part of the SOC 1000 and is not physically modifiable, but may be programmed to establish connectivity between various master and slave circuits of a user circuit design. The NOC 1008 may include, for example, two or more programmable switches capable of establishing a packet-switched network connecting user-specified master and slave circuits. In this regard, the NOC 1008 may accommodate a variety of circuit designs, each of which may have different combinations of master and slave circuits implemented at various locations in the SOC 1000 that may be coupled by the NOC 1008. The NOC 1008 may be programmed to route data, e.g., application data and / or configuration data, between the master and slave circuits of the user circuit design. For example, the NOC 1008 may be programmed to couple various user-specified circuit mechanisms implemented within the PL 1004 to the PS 1006, and / or the DPE array 1002, various hardwired circuit blocks, and / or various circuits and / or systems external to the SOC 1000.

[0088] The hardwired circuit blocks 1010 may include input / output (I / O) blocks and / or transceivers for sending and receiving signals to circuits and / or systems external to the SOC 1000, memory controllers, etc. Examples of various I / O blocks may include single-ended and pseudo-differential I / O, and high-speed differential clock transceivers. Additionally, the hardwired circuit blocks 1010 may be implemented to perform specific functions. Examples of hardwired circuit blocks 1010 include, but are not limited to, crypto engines, digital-to-analog converters, analog-to-digital converters, etc. The hardwired circuit blocks 1010 in the SOC 1000 may sometimes be referred to herein as application-specific blocks.

[0089] In the example of FIG. 10, the PL 1004 is shown in two separate regions. In another example, the PL 1004 may be implemented as an integrated region of programmable circuitry. In yet another example, the PL 1004 may be implemented as three or more distinct regions of programmable circuitry. The particular organization of the PL 1004 is not intended to be limiting. In this regard, the SOC 1000 includes one or more PL regions 1004, a PS 1006, and a NOC 1008. In some cases, a DPE array 1002 may be included.

[0090] In other example implementations, the SOC 1000 may include two or more DPE arrays 1002 located in different areas of the IC. In yet other examples, the SOC 1000 may be implemented as a multi-die IC, where each subsystem may be implemented on a different die. The various dies may be communicatively linked using any of a variety of available multi-die IC techniques, such as stacking the dies side-by-side on an interposer, using a stacked die architecture where the IC is implemented as a Multi-Chip Module (MCM), or the like. It should be understood that in the multi-die IC example, each die may include a single subsystem, two or more subsystems, a subsystem and another partial subsystem, or any combination thereof.

[0091] A programmable integrated circuit (IC) is a type of device that includes programmable logic circuits. One example of a programmable device or IC is the field programmable gate array (FPGA). FPGAs are characterized by the inclusion of programmable circuit blocks. Examples of programmable circuit blocks include, but are not limited to, input / output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), digital signal processing blocks (DSPs), processors, clock managers, and delay-locked loops (DLLs). Modern programmable ICs have evolved to include programmable logic circuits in combination with one or more other subsystems. For example, some programmable ICs have evolved into systems-on-chips or "SoCs" that include both programmable logic circuits and hardwired processors. Other types of programmable ICs include additional and / or different subsystems.

[0092] While various embodiments may be implemented using reconfigurable programmable logic blocks (e.g., FPGAs), other embodiments may be implemented in fixed instantiations (e.g., ASICs) or combined with programmable logic in a single integrated circuit (e.g., SOCs). Dedicated hard block circuitry in an ASIC implementation may not be reconfigurable once instantiated in an integrated circuit, but for example, in some implementations, an ASIC implementation may provide the smallest platform, e.g., in terms of power consumption and / or die area.

[0093] Although various embodiments have been described with reference to figures, other embodiments are contemplated. For example, in various embodiments, the data store may be a lookup table in an FPGA stored in a BRAM and implemented using some combination of flip flops (FFs), lookup table units (LUTs) such as individual logic gates, and a DSP. In some embodiments, the multipliers and summation circuits may be implemented in the DSP. In some embodiments, the multipliers and summation circuits may be mapped to the LUTs.

[0094] Table 1 shows that N=16 bits, I=1 bit, L f 1 shows a simulation of the resources required in a representative FPGA with FFs, LUTs, BRAM36 (a 36 kilobyte (kB) BRAM unit), and a DSP for an implementation with B = 20 bits, where the number of bits (L) of each entry in the lookup table is 26, and the value of B varies in 2-bit increments over the range [10, 14]. As can be seen, different combinations of resources can provide desirable resource utilization in an implementation. For example, for B = 10, the compression calculation circuit can be fully implemented using one DSP and half of a 36 kB BRAM unit, without the need for FFs or LUTs. For B = 12, for example, the compression calculation circuit can be advantageously implemented using 48 FFs, 63 LUTs, and one BRAM unit, without the use of a DSP. For B = 14, for example, the compression calculation circuit can be advantageously implemented using fewer FFs and LUTs (36 and 33, respectively), increasing the number of BRAM units used to four, and still without the use of a DSP. These implementations are provided by way of example, not limitation, to help demonstrate the flexibility of the compression computation method across various architectural configurations. Thus, for example, the computation of natural exponents can be advantageously implemented across a variety of architectural configurations to provide desired optimization of hardware resources, computational precision, and computational speed.

[0095] [Table 1]

[0096] Table 2 shows a simulation of resources similar to those described with respect to Table 1 for an extended input range of X, where N=28 bits and B varies in 2-bit increments over the range [14, 18]. In the example implementation where B=14, a single DSP is utilized along with four BRAM units. In comparison, for B=16 and 18, a single DSP is utilized in combination with a BRAM unit and FFs and LUTs. These illustrative implementations provide further examples of the flexibility in resource combinations that can be advantageously afforded by using a compressed computation method to compute the natural exponent.

[0097] [Table 2]

[0098] In various embodiments, the compressed natural exponent calculation method and circuit described herein can advantageously replace implementations that employ Taylor series, linear interpolation, or deep lookup tables. Such implementations may, for example, use up some DSP and memory units. Some embodiments can, for example, achieve compression of at least half the lookup table size, and can reduce the DSP required to one DSP that implements multipliers and adders, or eliminate the need for a DSP by, for example, using LUTs and FFs.

[0099] Various examples may be implemented using circuitry including various electronic hardware. By way of example and not limitation, hardware may include transistors, resistors, capacitors, switches, integrated circuits, and / or other devices. In various examples, circuitry may include analog and / or digital logic circuits, discrete components, traces, and / or memory circuits fabricated on silicon substrates including various integrated circuits (e.g., FPGAs, ASICs). In some embodiments, circuitry may involve the execution of pre-programmed instructions and / or software executed by a processor. For example, various systems may include both hardware and software.

[0100] Some aspects of the embodiments may be implemented as a computer system. For example, various implementations may include digital and / or analog circuitry, computer hardware, firmware, software, or combinations thereof. The device elements may be implemented in a computer program product tangibly embodied in an information carrier, for example in a machine-readable storage device, for execution by a fixed hardware processor, where the programmable processor executes a program of instructions that performs the functions of the various embodiments by operating on input data and generating output, thereby performing the methods. Some embodiments may be advantageously implemented in one or more computer programs executable on a programmable system including at least one processor coupled to receive and transmit data and instructions to and from a data store, at least one input, and / or at least one output. The data store may include, for example, one or more registers or memory locations in a memory space. A computer program is a set of instructions that can be used directly or indirectly in a computer to perform a particular activity or bring about a particular result. The computer program may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0101] In various embodiments, a computer system may include a non-transitory memory. The memory may be coupled to one or more processors, which may be configured to store data and computer-readable instructions, including processor-executable program instructions. The data and computer-readable instructions may be accessible to the one or more processors. The processor-executable program instructions, when executed by the one or more processors, may cause the one or more processors to perform various operations.

[0102] Some of the techniques disclosed above can be illustrated in the following non-limiting examples. Example 1. A natural exponent computation circuit a splitter circuit configured to receive the fixed-point word and to split the fixed-point word into a first word and a second word; a retrieval circuit configured to retrieve a predetermined pre-calculated hyperbolic sum from the data store at an address defined by the first word; a multiplication circuit configured to multiply the hyperbolic sum by the second word and output the multiplied hyperbolic sum; a first scaling circuit configured to receive the hyperbolic sum and scale the hyperbolic sum by a first factor; a summing circuit configured to sum the scaled hyperbolic sum and the multiplied hyperbolic sum to generate a second scaled sum; Scale the second scaled sum by the second factor, e X and a second scaling circuit configured to output an approximation of

[0103] Example 2. The circuit of example 1, wherein the multiplication circuitry and the summation circuitry are at least partially implemented in at least one digital signal processor (DSP).

[0104] Example 3. The circuit of example 1, wherein at least one of the multiplier circuit, the adder circuit, and the data store is implemented at least in part as logic gates.

[0105] Example 4. The circuit of example 1, wherein the data store is a lookup table. Example 5. The circuit of example 4, wherein the lookup table is configured to store entries in a fixed-point format.

[0106] Example 6. Lookup table depth is 2 B6. The circuit of example 5, wherein B is a total number of bits in the first word.

[0107] Example 7. The circuit of example 1, wherein the data store is configured to store entries in a floating-point format.

[0108] Example 8. The first coefficient is 2 B-I where B is the total number of bits in the first word, I is the total number of integer bits in the first word, 2. The circuit of embodiment 1, wherein the first scaling circuit right zero-pads the hyperbolic sum by BI bits.

[0109] Example 9. The second coefficient is 1 / (2 B-I ), where B is the total number of bits, I is the total number of integer bits in the first word, 2. The circuit of embodiment 1, wherein the second scaling circuit bit-wise right shifts the second sum by BI bits.

[0110] Example 10. The present invention further includes a floating-point to fixed-point conversion circuit before the splitter circuit; 2. The circuit of claim 1, wherein the conversion circuit is configured to receive a floating point input and convert the floating point input to a fixed point word that is received by the splitter circuit.

[0111] Example 11. Further, a fixed-point to floating-point conversion circuit is provided after the second scaling circuit; The conversion circuit converts the fixed-point X and outputting the output approximation in a floating-point format.

[0112] Example 12. The circuit of example 1, wherein the second word represents a numerical value less than one. Example 13. The fixed-point word is N bits long, the first word being the first B bits of a fixed-point word; The second word is the last A bit of the fixed-point word, N=A+B, 2. The circuit of claim 1, wherein the first word comprises a binary point of a fixed-point word.

[0113] Example 14.e X 13. The circuit of embodiment 12, wherein B is chosen such that an approximation of is accurate within a predetermined error limit.

[0114] Example 15. A method for efficiently calculating exponents in a digital circuit, comprising: receiving a digital fixed-point word X, the word being N bits long; splitting the first B bits of X into a first word Wb and the remaining A bits of X into a second word Wa, where the first word contains I integer bits and BI fractional bits, N=A+B, and X=Wb+Wa; Retrieving a predetermined pre-calculated hyperbolic sum representing sinh(Wb)+cosh(Wb) from a data store at an address defined by Wb; multiplying the hyperbolic sum by Wa to generate a multiplied hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×[Wa]; scaling the hyperbolic sum by a scaling factor K to provide a scaled hyperbolic sum representing ×K sinh(Wb)+cosh(Wb); adding the scaled hyperbolic sum and the multiplied hyperbolic sum to generate a second scaled sum representing [sinh(b)+cosh(b)]×[Wa+K]; By scaling the second scaled sum by 1 / K, e X and generating a representation of [sinh(Wb)+cosh(Wb)]×[Wa / K+1] as an approximation of

[0115] Example 16. The method of example 13, wherein the multiplying and adding steps are at least partially implemented in at least one digital signal processor (DSP).

[0116] Example 17. the data store is a lookup table configured to store entries in a fixed-point format; The lookup table is 2 deep B The method according to Example 13,

[0117] Example 18. Wb contains the binary points of X, K is 2 B-I and Scaling the hyperbolic sum by K includes right zero padding the hyperbolic sum by BI bits; 14. The method of embodiment 13, wherein scaling the scaled second sum by 1 / K includes bit-wise right shifting the second sum by BI bits.

[0118] Example 19.e X 14. The method of claim 13, wherein B is chosen such that the approximation of is accurate within predetermined error limits.

[0119] Example 20. At least one non-transitory computer readable medium providing a program of instructions that, when executed by a processor, causes an operation to calculate a natural exponent, the operation comprising: receiving a digital fixed-point word X, the word being N bits long; splitting the first B bits of X into a first word Wb and the remaining A bits of X into a second word Wa, where the first word contains I integer bits and BI fractional bits, N=A+B, and X=Wb+Wa; Retrieving a predetermined pre-calculated hyperbolic sum representing sinh(Wb)+cosh(Wb) from a data store at an address defined by Wb; multiplying the hyperbolic sum by Wa to generate a multiplied hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×[Wa]; scaling the hyperbolic sum by a scaling factor K to generate a scaled hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×K; adding the multiplication curve sum to the scaled hyperbolic sum to generate a scaled second sum representing [sinh(b)+cosh(b)]×[Wa+K]; By scaling the scaled second sum by 1 / K, e X and generating a representation of [sinh(Wb)+cosh(Wb)]×[Wa / K+1] as an approximation of Wb.

[0120] Several implementations have been described. Nevertheless, it will be appreciated that various modifications may be made. For example, advantageous results may be obtained if the steps of the disclosed techniques are performed in a different order, or if the components of the disclosed systems are combined in a different manner, or if the components are supplemented with other components. Accordingly, the following implementations are within the scope of the following claims.

Claims

1. 1. A natural exponent computation circuit, comprising: a splitter circuit configured to receive a fixed point word and to split the fixed point word into a first word and a second word; a retrieval circuit configured to retrieve a predetermined pre-calculated hyperbolic sum from a data store at an address defined by said first word; a multiplication circuit configured to multiply the hyperbolic sum by the second word and output a multiplied hyperbolic sum; a first scaling circuit configured to receive the hyperbolic sum and scale the hyperbolic sum by a first factor; a summing circuit configured to sum the scaled hyperbolic sum and the multiplied hyperbolic sum to generate a scaled second sum; Scaling the scaled second sum by a second factor; e Ｘ and a second scaling circuit configured to output an approximation of

2. The circuit of claim 1 , wherein the multiplication circuitry and the summation circuitry are at least partially implemented in at least one digital signal processor (DSP).

3. The circuit of claim 1 , wherein at least one of the multiplier circuit, the adder circuit, and the data store are implemented at least in part as logic gates.

4. The circuit of claim 1 , wherein the data store is a look-up table.

5. The circuit of claim 4 , wherein the lookup table is configured to store entries in a fixed-point format.

6. The circuit of claim 1 , wherein the data store is configured to store entries in floating point format.

7. The first coefficient is 2 Ｂ－Ｉ where B is the total number of bits in the first word, and I is the total number of integer bits in the first word; 2. The circuit of claim 1, wherein said first scaling circuit right-zero pads said hyperbolic sum by BI bits.

8. The second coefficient is 1 / (2 Ｂ－Ｉ ), where B is the total number of bits and I is the total number of integer bits in the first word; 2. The circuit of claim 1, wherein said second scaling circuit bitwise right shifts said second sum by BI bits.

9. a floating point to fixed point conversion circuit before the splitter circuit; 2. The circuit of claim 1, wherein the conversion circuit is configured to receive a floating point input and convert the floating point input to the fixed point word received by the splitter circuit.

10. a fixed-point to floating-point conversion circuit following the second scaling circuit; The conversion circuit converts e Ｘ and outputting the output approximation in a floating point format.

11. 2. The circuit of claim 1, wherein the second word represents a numerical value less than one.

12. the fixed-point word is N bits long; the first word being the first B bits of the fixed-point word; the second word being the last A bits of the fixed-point word; N=A+B, 2. The circuit of claim 1, wherein the first word contains a binary point of the fixed-point word.

13. 1. A method for efficiently computing an exponent in a digital circuit, the method comprising: Receiving a digital fixed-point word X, the word X being N bits long; splitting the first B bits of X into a first word Wb and the remaining A bits of X into a second word Wa, said first word including I integer bits and B-I fractional bits, where N=A+B and X=Wb+Wa; Retrieving a predetermined pre-calculated hyperbolic sum representing sinh(Wb)+cosh(Wb) from a data store at an address defined by Wb; multiplying the hyperbolic sum by Wa to generate a multiplied hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×[Wa]; scaling the hyperbolic sum by a scaling factor K to generate a scaled hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×K; adding the multiplied hyperbolic sum to the scaled hyperbolic sum to generate a scaled second sum representing [sinh(b)+cosh(b)]×[Wa+K]; The scaled second sum is scaled by 1 / K to obtain e Ｘ and generating an expression of [sinh(Wb)+cosh(Wb)]×[Wa / K+1] as an approximation of

14. the multiplying and adding steps are at least partially implemented in at least one digital signal processor (DSP); Wb contains the binary points of X, K is 2 Ｂ－Ｉ and The above e Ｘ B is chosen such that the approximation of is accurate within a given error bound; Scaling the hyperbolic sum by K includes right zero padding the hyperbolic sum by B-I bits; 14. The method of claim 13, wherein scaling the scaled second sum by 1 / K comprises bit-wise right shifting the second sum by B-I bits.

15. At least one non-transitory computer readable medium providing a program of instructions that, when executed by a processor, causes an operation to calculate a natural exponent, said operation comprising: Receiving a digital fixed-point word X, the word X being N bits long; splitting the first B bits of X into a first word Wb and the remaining A bits of X into a second word Wa, said first word including I integer bits and B-I fractional bits, where N=A+B and X=Wb+Wa; Retrieving a predetermined pre-calculated hyperbolic sum representing sinh(Wb)+cosh(Wb) from a data store at an address defined by Wb; multiplying the hyperbolic sum by Wa to generate a multiplied hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×[Wa]; scaling the hyperbolic sum by a scaling factor K to generate a scaled hyperbolic sum representing [sinh(Wb)+cosh(Wb)]×K; adding the multiplied hyperbolic sum to the scaled hyperbolic sum to generate a scaled second sum representing [sinh(b)+cosh(b)]×[Wa+K]; The scaled second sum is scaled by 1 / K to obtain e Ｘ and generating a representation of [sinh(Wb)+cosh(Wb)]×[Wa / K+1] as an approximation of Wb.

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