Electrostatic clamping system and method

Abstract

The electrostatic clamping system includes a platen, an electrostatic electrode associated with the platen, and a sealing cover. The sealing cover has a concave lower surface defining a cavity and has a sealing ring extending around the periphery of the lower surface. The sealing cover is movable relative to the platen so as to move onto and away from a wafer disposed on the platen. The sealing cover further includes an inlet valve for introducing gas into a space between a cover body of the sealing cover and the wafer.

Description

[Technical field]

[0001] TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to the field of semiconductor device manufacturing, and more particularly to systems and methods that facilitate effective clamping of semiconductor wafers. [Background technology]

[0002] During ion implantation and certain other processes performed in the manufacture of semiconductor devices, a semiconductor wafer is typically placed on a flat platen. The semiconductor wafer is usually secured to the platen by electrostatic clamping. A voltage is applied to electrodes embedded in the platen, and the resulting electric field holds the semiconductor wafer to the platen. Electrostatic clamping is preferred over mechanical clamping because mechanical clamping can damage and / or contaminate the semiconductor wafer.

[0003]

[0003] The ability of the platen to reliably clamp the semiconductor wafer by electrostatic clamping depends heavily on the proximity of the bottom surface of the semiconductor wafer to the top surface of the platen. Ideally, these surfaces are planar and disposed at even, continuous contact with one another. If the semiconductor wafer is warped (e.g., deflected by as much as 20 / 1000ths of an inch (20 thou)), the gap between the bottom surface of the semiconductor wafer and the top surface of the platen will be relatively large. In this case, the electrostatic clamping may be weak and ineffective. This problem may be exacerbated when the semiconductor wafer and platen are subjected to high or cryogenic processes (e.g., during high or cryogenic ion implantation). Inconsistent deflection of the semiconductor wafer and platen may increase the size of the gap between them.

[0004]

[0004] Accordingly, to promote reliable electrostatic clamping between the semiconductor wafer and the platen, it is desirable to minimize the distance between their surfaces. With respect to these and other considerations, the present improvements may be useful. Summary of the Invention

[0005]

[0005] This Summary is intended to introduce selected concepts in a concise form. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended as an aid in determining the scope of the claimed subject matter.

[0006]

[0006] An electrostatic clamping system according to a non-limiting embodiment of the present disclosure includes a platen, an electrostatic electrode associated with the platen, and a sealing cover. The sealing cover has a concave lower surface defining a cavity and has a sealing ring extending around the periphery of the lower surface. The sealing cover is movable relative to the platen for moving onto and away from a wafer disposed on the platen. The sealing cover further has an inlet valve for introducing gas into a space between a cover body of the sealing cover and the wafer.

[0007]

[0007] In accordance with another non-limiting embodiment of the present disclosure, an electrostatic clamping system includes: A platen; an electrostatic electrode embedded in the platen; 1. A sealing cover having a concave lower surface defining a cavity and having a sealing ring extending around a periphery of the lower surface, a sealing cover coupled to the articulating support arm, the articulating support arm configured to selectively move the sealing cover onto and away from a wafer disposed on the platen; a sealing cover, the sealing cover further having an inlet valve for introducing a gas into a space between a cover body of the sealing cover and the wafer; a temperature management system integral with the sealing cover, the temperature management system comprising a temperature control element operable to vary a temperature of the sealing cover; Includes.

[0008]

[0008] A method of operating an electrostatic clamping system including a platen, an electrostatic electrode associated with the platen, and a sealing cover, the sealing cover having a concave lower surface defining a cavity and a sealing ring extending around a periphery of the lower surface, the method according to a non-limiting embodiment of the present disclosure comprising: placing a semiconductor wafer on a platen, the semiconductor wafer being warped and presenting a bottom surface that is recessed relative to the platen; lowering the sealing cover onto the semiconductor wafer such that a sealing ring engages an upper surface of the semiconductor wafer, forming a fluid-tight seal between a cover body of the sealing cover and the semiconductor wafer; and feeding gas into a space between the cover body and the semiconductor wafer through an inlet valve in the cover body; Includes.

[0009]

[0009] Various embodiments of the apparatus of the present disclosure will now be described by way of example only with reference to the accompanying drawings, in which: [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 illustrates a cross-sectional side view of an electrostatic clamping system according to an exemplary embodiment of the present disclosure. [Diagram 2] FIG. 2 is a cross-sectional side view of the electrostatic clamping system of FIG. 1 with a semiconductor wafer positioned on a platen. [Diagram 3] FIG. 2 is a cross-sectional side view of the electrostatic clamping system of FIG. 1 with the sealing cover of the system lowered into engagement with a semiconductor wafer. [Figure 4] FIG. 2 is a cross-sectional side view of the electrostatic clamping system of FIG. 1 operating to planarize a semiconductor wafer. [Diagram 5] 2 is a cross-sectional side view of the electrostatic clamping system of FIG 1 with the sealing cover of the system removed, where a semiconductor wafer is placed on a platen of the system and is planarized and electrostatically clamped for further processing. [Figure 6] FIG. 1 is a flow diagram illustrating a method of operating an electrostatic clamping system according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0016] The present embodiments will now be described in more complete detail with reference to the accompanying drawings showing several embodiments. The subject matter of the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. In the drawings, like numbers refer to like elements throughout.

[0012]

[0017] 1, a cross-sectional side view of an electrostatic clamping system 10 (hereinafter "system 10") according to an exemplary embodiment of the present disclosure is shown. As described further below, system 10 is provided to ensure a close clearance relationship between a support surface(s) of a platen 12 and a bottom surface of a warped or curved semiconductor wafer disposed on platen 12 to facilitate effective electrostatic clamping therebetween.

[0013]

[0018] Platen 12 of system 10 may be similar to conventional platens typically used to support and securely hold semiconductor wafers to be processed in ion processing systems (e.g., ion implantation systems, ion etching systems, etc.). Platen 12 may be a generally planar disk and may be disposed within processing chamber 13. In various embodiments, platen 12 may include a number of vertically extending mesas 16 for engaging a bottom surface of a semiconductor wafer disposed on platen 12. This disclosure is not limited in this respect. For example, alternative embodiments of platen 12 are contemplated in which mesas 16 are omitted and instead a platen 12 having a generally flat top surface is provided.

[0014]

[0019] In various embodiments, the platen 12 may include a backside gas seal 17 (hereinafter "BSG seal 17"). The BSG seal 17 may be an annular member (e.g., an O-ring or gasket) disposed on an upper surface of the platen 12 and adjacent the outer periphery of the platen 12. When a semiconductor wafer is placed on the platen 12 (as shown in FIGS. 3-5), the BSG seal 17 may engage a bottom surface of the semiconductor wafer to provide a fluid-tight seal between the semiconductor wafer and the platen 12. A backside gas (e.g., a cooling gas) may be provided to the sealed space between the semiconductor wafer and the platen 12 to assist in heat transfer to / from the semiconductor wafer in a manner well known to those skilled in the art. The disclosure is not limited in this respect. In various embodiments of the disclosure, the BSG seal 17 may be omitted.

[0015]

[0020] Platen 12 may further include one or more electrostatic electrodes associated with platen 12. For example, in the embodiment of platen 12 shown in FIG. 1, platen 12 may include electrostatic electrode 18 embedded within platen 12 a short distance below mesa 16. Electrostatic electrode 18 may be connected to a power source (not shown) and arranged and configured to operate in the manner of electrostatic clamping, as is well known to those skilled in the art. In particular, application of a voltage to electrostatic electrode 18 creates an electric field that may hold a semiconductor wafer to platen 12 by electrostatic forces, as described further below.

[0016]

[0021] Those skilled in the art will appreciate that platen 12 may further include any of a variety of heating elements (e.g., resistive or radiative heating elements) and / or any of a variety of cooling elements (e.g., channels, conduits, tubes, pipes, ducts, etc. embedded in or extending through platen 12 for circulating cooling fluid) for heating or cooling a semiconductor wafer disposed on platen 12. The implementation of such heating and cooling elements in platens of ion processing systems is well known in the art and will not be described in further detail.

[0017]

[0022] The system 10 may further include a movable sealing cover 26 positioned adjacent the platen 12 within the processing chamber 13. The sealing cover 26 may include a dome- or bowl-shaped cover body 27 having a concave lower surface 28 that defines a cavity. In various embodiments, the cover body 27 may be made of aluminum, stainless steel, or ceramic. The disclosure is not limited in this respect. The sealing cover 26 may further include an inlet valve 30 and an outlet valve 32 coupled to a gas supply line 34 and a vacuum line 36, respectively, to allow gas to be introduced / exhausted from the space below the cover body 27, as described in more detail below. The sealing cover 26 may further include a sealing ring 37 coupled to a lower periphery of the cover body 27. The sealing ring 37 may be an annular member (e.g., an O-ring or a gasket) similar to the BSG seal 17. When the sealing cover 26 is lowered onto the semiconductor wafer, the sealing ring 37 may engage the top surface of the semiconductor wafer to provide a fluid-tight seal between the semiconductor wafer and the cover body 27. The sealing ring 37 may be made of any material suitable for establishing a fluid-tight seal with the semiconductor wafer upon engagement therewith. Examples of such materials include, but are not limited to, nitrile rubber, fluoropolymer elastomers, thermoplastic polymers, polyimide-based plastics, silicone, ethylene propylene, propylene, and the like. In high temperature applications (e.g., where the sealing ring is exposed to temperatures in excess of 700 degrees Celsius), the sealing ring 37 may be made of, but is not limited to, ceramics, various metals, silicon, silicon carbide, glass, glass compounds, and the like.

[0018]

[0023] The sealing cover 26 may further include a temperature control system 38. The temperature control system 38 has one or more temperature control elements 39 for heating and / or cooling the cover body 27 and the sealing ring 37. In various embodiments, the temperature control element 39 may include a resistive heating element, such as a wire, cable, plate, tape, etc., embedded in the sealing cover 26 and coupled to one or more power sources (not shown). Additionally or alternatively, the temperature control element 39 may include one or more cooling elements, such as channels, conduits, tubes, pipes, ducts, etc., embedded in or extending through the sealing cover 26 for circulating a cooling fluid. The temperature control system 38 may further include a temperature sensor 40 (e.g., a thermocouple, a resistance temperature detector, etc.) for measuring the temperature of the sealing cover 26, and a controller 42 (e.g., a microcontroller, an application specific integrated circuit, etc.) coupled to the temperature sensor 40 and the temperature control element 39. The controller 42 may be configured to operate the temperature control element 39 to heat or cool the sealing cover 26 until the temperature sensor 40 measures a predetermined target temperature. For example, the controller 42 may be configured to operate the temperature control element 39 to heat or cool the sealing cover 26 until the temperature of the sealing cover 26 is equal to or approximately equal to (e.g., within 15 degrees Celsius) the temperature of the platen 12 and / or the temperature of a semiconductor wafer disposed on the platen 12. This may protect the platen 12 and / or the semiconductor wafer from thermal shock when the sealing cover 26 is moved into engagement with the semiconductor wafer as described further below.

[0019]

[0024] The sealing cover 26 may be coupled to an inner wall 44 of the processing chamber 13 by an articulating support arm 46. The support arm 46 extends between the inner wall 44 and the cover body 27. In an alternative exemplary embodiment, the articulating support arm 46 may couple the cover body 27 to the platen 12 (illustrated by the dashed portion of the support arm 46 in FIG. 1). The disclosure is not limited in this respect. In various embodiments, the support arm 46 may be replaced by any type of mechanical configuration or system capable of moving the sealing cover 26 onto and away from a semiconductor wafer disposed on the platen 12, as described further below.

[0020]

[0025] The support arm 46 may be actuated to move the cover body 27 in a direction parallel to one or more of the X, Y, and Z axes of the Cartesian coordinate system shown in Figure 1. In various embodiments, the support arm 46 may be thermally isolated from the sealing cover 26 to prevent heat transfer between the support arm 46 and the sealing cover 26. In various implementations, this may be accomplished by implementing a thermal barrier 50 made of a thermally insulating material (e.g., ceramic, glass, etc.) at or near the juncture of the support arm 46 and the cover body 27.

[0021]

[0026] In normal operation of the system 10, a semiconductor wafer is introduced into the process chamber 13 and placed on the platen 12. Ideally, the semiconductor wafer would be planar or nearly planar and would rest across the mesa 16 of the platen 12, providing the shortest possible distance between the electrostatic electrode 18 and the entire semiconductor wafer to provide a strong electrostatic coupling. A semiconductor wafer, such as the semiconductor wafer 52 (hereafter referred to as "wafer 52") shown in FIG. 2, may be warped or bowed (e.g., deflected by up to 20 thou, and in some cases greater than 20 thou) and may present a concave bottom surface relative to the platen 12 (the deflection of the wafer 52 shown in FIG. 2 is exaggerated for illustrative purposes). As a result, a gap 54 between the wafer 52 and the platen 12 attenuates the electrostatic force acting on the wafer 52, resulting in a weak electrostatic coupling between the platen 12 and the wafer 52.

[0022]

[0027] To increase the electrostatic coupling between the platen 12 and the wafer 52, the sealing cover 26 is lowered onto the wafer 52 by the support arm 46, as shown in FIG. 3. A sealing ring 37 may engage the top surface of the wafer 52 to establish a fluid-tight seal between the cover body 27 and the wafer 52. Once the sealing cover 26 is positioned and a seal is formed, a gas may be delivered to the space 56 between the cover body 27 and the wafer 52 via the gas supply line 34 and the inlet valve 30. In various embodiments, the gas may be an inert gas, such as nitrogen, argon, or a non-inert gas, such as hydrogen. The disclosure is not limited in this respect.

[0023]

[0028] As the gas fills the space 56, the pressure in the space 56 increases and exerts a downward force on the wafer 52. Eventually, the wafer 52 is flattened by the pressure, so that the wafer 52 extends flat across the mesa 16, as shown in FIG. 4. In this way, the shortest possible distance is ensured between the electrostatic electrode 18 and the entire wafer 52, facilitating a strong electrostatic bond between them. At this point, the flat engagement of the wafer 52 with the mesa 16 can be maintained by electrostatic bonding alone. In this way, gas can be vented from the space 56 through the outlet valve 32 and the vacuum line 36 to a port outside the processing chamber 13. In various embodiments, the vacuum line 36 may be omitted and the gas may be vented directly within the processing chamber 13. The disclosure is not limited in this respect. Finally, the sealing cover 26 is moved away from the wafer 52 by the support arm 46, as shown in FIG. 5, and the wafer 52 is ready for subsequent ion processing (e.g., ion implantation, ion etching, etc.).

[0024]

[0029] 6, a flow diagram illustrating an exemplary method of the system 10 of the present disclosure that facilitates effective electrostatic clamping of a warped semiconductor wafer in accordance with the present disclosure is shown. The method will now be described in conjunction with the illustrative system 10 shown in FIGS. 1-5.

[0025]

[0030] In block 100 of the exemplary method, a wafer 52 is introduced into the processing chamber 13 of the system 10 and placed on the platen 12 as shown in Figure 2. The wafer may be warped or bowed (e.g., deflected by up to or greater than 20 thou) and may present a concave bottom surface relative to the platen 12 (the deflection of the wafer 52 shown in Figure 2 is exaggerated for purposes of illustration).

[0026]

[0031] In block 110 of the exemplary method, the controller 42 may operate the temperature control elements 39 to heat or cool the sealing cover 26 until the temperature of the sealing cover 26 is equal to or approximately equal to (e.g., within 15 degrees Celsius) the temperature of the platen 12 and / or the temperature of a semiconductor wafer disposed on the platen 12. This may protect the platen 12 and / or the wafer 52 from thermal shock as the sealing cover 26 is moved to engage the wafer, as described further below.

[0027]

[0032] In block 120 of the exemplary method, the sealing cover 26 may be lowered onto the wafer 52 by the support arm 46, as shown in FIG. 3. The sealing ring 37 may engage the top surface of the wafer 52 to establish a fluid-tight seal between the cover body 27 and the wafer 52. In block 130 of the method, gas may be pumped into the space 56 between the body 27 and the wafer 52 via the gas supply line 34 and the inlet valve 30. In various embodiments, the gas may be an inert gas, such as nitrogen, argon, or a non-inert gas, such as hydrogen. The disclosure is not limited in this respect. As the gas fills the space 56, the pressure in the space 56 increases, exerting a downward force on the wafer 52. Eventually, the wafer 52 flattens under pressure, causing the wafer 52 to extend flat across the mesa 16, as shown in FIG. 4. In this way, the shortest possible distance is ensured between the electrostatic electrode 18 and the entire wafer 52, facilitating a strong electrostatic bond between the two. At this point, the flat engagement of the wafer 52 with the mesa 16 may be held solely by electrostatic bonding.

[0028]

[0033] At block 140 of the exemplary method, gases may be vented from space 56 through outlet valve 32 and vacuum line 36 to a port outside of processing chamber 13. In various embodiments, vacuum line 36 may be omitted and gases may be vented directly within processing chamber 13, although the disclosure is not limited in this respect. At block 150 of the method, support arm 46 moves sealing cover 26 away from wafer 52, as shown in FIG. 5, and wafer 52 is ready for subsequent ion processing (e.g., ion implantation, ion etching, etc.).

[0029]

[0034] As will be appreciated by those skilled in the art, the above-described system 10 and method provide significant advantages over conventional clamping configurations and methods for securing a semiconductor wafer to a platen. For example, the system 10 facilitates effective electrostatic clamping of curved and warped semiconductor wafers. As an added advantage, such clamping is accomplished with minimal mechanical contact with the semiconductor wafer, thereby protecting the wafer from damage and contamination associated with previous clamping mechanisms and methods.

[0030]

[0035] The present disclosure should not be limited in scope by the specific embodiments described herein. Indeed, other various embodiments and modifications of the present disclosure, in addition to those described herein, will be apparent to those skilled in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to be included within the scope of the present disclosure. Although the present disclosure is described herein in the context of specific implementations in particular environments for particular purposes, those skilled in the art will recognize that its usefulness is not limited thereto. The embodiments of the present disclosure may be usefully implemented in any number of environments and for any number of purposes. Thus, the claims set forth below should be construed in light of the full scope and spirit of the present disclosure as described herein.

Claims

1. 1. An electrostatic clamping system comprising: A platen, an electrostatic electrode associated with the platen; a sealing cover having a concave lower surface defining a cavity and having a sealing ring extending around the periphery of said lower surface; Equipped with the sealing cover is movable relative to the platen to move onto and away from a wafer disposed on the platen; The electrostatic clamping system, wherein the sealing cover further comprises an inlet valve for introducing a gas into a space between a cover body of the sealing cover and the wafer.

2. 2. The electrostatic clamping system of claim 1, wherein the gas is selected from one of nitrogen, argon, and hydrogen.

3. The electrostatic clamping system of claim 1 , wherein the sealing cover is coupled to an articulating support arm.

4. 4. The electrostatic clamping system of claim 3, wherein the articulating support arm is attached to an interior wall of a processing chamber.

5. The electrostatic clamping system of claim 3 , wherein the articulating support arm is attached to the platen.

6. 4. The electrostatic clamping system of claim 3, wherein the support arm is thermally insulated from the sealing cover by a thermal insulating material.

7. The electrostatic clamping system of claim 1 , wherein the sealing cover includes a thermal management system, the thermal management system comprising a temperature control element operable to vary a temperature of the sealing cover.

8. 8. The electrostatic clamping system of claim 7, wherein the thermal management system further comprises a controller, the controller coupled to the temperature control element and configured to operate the temperature control element to vary the temperature of the sealing cover until a predetermined temperature is reached, the predetermined temperature being within 15 degrees Celsius of the temperature of the platen.

9. The electrostatic clamping system of claim 1 , wherein the sealing cover includes an outlet valve for venting the gas from the space.

10. The electrostatic clamping system of claim 1 , wherein the sealing ring is selected from one of an O-ring and a gasket.

11. 1. An electrostatic clamping system comprising: A platen, an electrostatic electrode embedded in the platen; 1. A sealing cover having a concave lower surface defining a cavity and a sealing ring extending around a periphery of said lower surface, the encapsulation cover is coupled to an articulating support arm configured to selectively move the encapsulation cover onto and off of a wafer disposed on the platen; a sealing cover, the sealing cover further having an inlet valve for introducing a gas into a space between a cover body of the sealing cover and the wafer; a temperature management system integral with the sealing cover, the temperature management system comprising a temperature control element operable to vary a temperature of the sealing cover; An electrostatic clamping system comprising:

12. 1. A method of operating an electrostatic clamping system including a platen, an electrostatic electrode associated with the platen, and a sealing cover, the sealing cover having a concave lower surface defining a cavity and a sealing ring extending around a periphery of the lower surface, the method comprising: placing a semiconductor wafer on the platen, the semiconductor wafer being warped and presenting a bottom surface that is recessed relative to the platen; lowering the sealing cover onto the semiconductor wafer such that the sealing ring engages an upper surface of the semiconductor wafer, forming a fluid-tight seal between a cover body of the sealing cover and the semiconductor wafer; and feeding a gas into a space between the cover body and the semiconductor wafer via an inlet valve in the cover body; A method comprising:

13. The method of claim 12 , wherein pressure built up in the space between the cover body and the semiconductor wafer causes the semiconductor wafer to engage flatly with the platen.

14. The method of claim 12 further comprising electrostatically clamping the semiconductor wafer to the platen.

15. The method of claim 12 further comprising heating the sealing cover.

16. 16. The method of claim 15, wherein heating the encapsulating cover comprises heating the encapsulating cover to a temperature within 15 degrees Celsius of a temperature of at least one of the semiconductor wafer and the platen.

17. The method of claim 12 further comprising cooling the sealing cover.

18. 20. The method of claim 17, wherein cooling the encapsulating cover comprises cooling the encapsulating cover to a temperature within 15 degrees Celsius of a temperature of at least one of the semiconductor wafer and the platen.

19. The method of claim 12 , further comprising evacuating the gas from a space between the cover body and the semiconductor wafer through an outlet valve in the cover body.

20. The method of claim 12 , wherein the gas is selected from one of nitrogen, argon, and hydrogen.

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