Light-emitting display device

Abstract

To manufacture and provide a semiconductor device having high reliability and including a thin film transistor with stable electric characteristics.SOLUTION: In a manufacturing method for a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor film, a heating process (heating process for dehydration or dehydrogenation) for increasing the purity of the oxide semiconductor film and reducing the moisture or the like, which is the impurity, is performed. Moreover, the impurity such as moisture existing not just in the oxide semiconductor film but also in a gate insulating layer is reduced and the impurity such as moisture existing at an interface between the oxide semiconductor film and films provided in contact therewith on the upper and lower sides is reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology of constructing thin film transistors (TFTs) has been attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. There are many types of metal oxides and they are used for various purposes. Indium oxide is a well-known material that is needed for applications such as liquid crystal displays. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin-film transistors that use metal oxides as channel formation regions and that exhibit excellent semiconductor properties are already known. (Patent Documents 1 to 4, Non-Patent Document 1).

[0005] Incidentally, metal oxides include not only single-component oxides but also multi-component oxides. For example, InGaO3(ZnO) with homologous phase m (m: natural number) is In, Ga, and Zn It is known as a multi-component oxide semiconductor having the above structure (Non-Patent Documents 2 to 4).

[0006] Then, the oxide semiconductor composed of the above-mentioned In-Ga-Zn-based oxide is used as a thin film transistor. It has been confirmed that this material can be used as a channel layer for transistors (Patent Document 5, Non-Patent Document 6). References 5 and 6). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] JP 2000-150900 A [Patent Document 5] JP 2004-103957 A [Non-patent literature]

[0008] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, “A ferroelectric transparent thin-film transistor”, Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-Patent Document 4] Masaki Nakamura, Noboru Kimizuka, Takahiko Mouri, Mitsumasa Isobe, "Synthesis and crystal structure of homologous phase, InFeO3(ZnO)m (m: natural number) and its isomorphic compounds", Solid State Physics, 1993, Vol.28, No.5, pp.317-327 [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 Summary of the Invention [Problem to be solved by the invention]

[0009] To manufacture a highly reliable semiconductor device having a thin film transistor with stable electrical characteristics. One of our goals is to provide [Means for solving the problem]

[0010] A semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor film In a method for manufacturing an electronic device, the purity of an oxide semiconductor film is increased and impurities such as moisture are reduced. In addition, a heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor film. The gate insulating layer is also protected from moisture and other impurities. The present invention reduces impurities such as moisture that are present at the interface between the oxide semiconductor film and the oxide semiconductor film.

[0011] In order to reduce impurities such as moisture, the oxide semiconductor film is formed and then exposed. In the state, under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure Heat treatment is performed at 200°C or higher, preferably 400°C to 600°C under pressure to form an oxide. Reduces the moisture content of the semiconductor film. After heating, the film is heated to a temperature between room temperature and 100℃ in an inert gas atmosphere. Cool slowly to room temperature.

[0012] The film is formed by heat treatment under an inert gas atmosphere such as nitrogen or argon, or under reduced pressure. Improved electrical characteristics of thin-film transistors using oxide semiconductor films with reduced moisture content This will also realize a thin-film transistor that is both easy to mass-produce and has high performance.

[0013] Various heating temperature conditions were used to measure the temperature of the samples, which were then heat-treated under a nitrogen atmosphere. S (Thermal Desorption Spectroscopy) measurement The results are shown in Figures 2, 3, and 4.

[0014] The thermal desorption analyzer measures the gas components that are desorbed and generated from a sample while the sample is heated and heated in a high vacuum. This device detects and identifies gases and gases that desorb from the surface and interior of a sample using a quadrupole mass spectrometer. The thermal desorption analyzer manufactured by Electronic Science Corporation (product name: EMD-WA1 The measurement conditions were a temperature rise of about 10°C / min, and the temperature during measurement was about 1×10 -7 (Pa ) vacuum level. The SEM voltage was 1500V and the Dwell Time was 0. 2 [sec] and the number of channels used is 23. Note that the ionization coefficient of H2O is 1. 0, H2O fragmentation coefficient 0.805, H2O through-pass coefficient 1.5 6. The pumping rate of H2O is 1.0.

[0015] Figure 2 shows a comparison sample with only a glass substrate and a sample with a film thickness of 50 nm (actual sample) on a glass substrate. In the experiment, an In-Ga-Zn-O non-single crystal film with a thickness of about 30 nm after etching was formed. This is a graph showing the TDS results for H2O compared with that for sample 1. The measurement results are shown below. A peak is seen around 300°C, which indicates that the In-Ga-Zn-O system It can be seen that impurities such as moisture (H2O) are desorbed from the non-single crystal film.

[0016] Figure 3 shows a non-single crystal In-Ga-Zn-O film with a thickness of 50 nm on a glass substrate. The deposited sample (Sample 1) and a 50 nm thick In-Ga-Zn- After forming the O-based non-single crystal film, it was heated at 350°C in air for 1 hour. The sample (sample 2) was heated at 350°C in a nitrogen atmosphere for 1 hour. This is a comparison with the sample (sample 3) and shows the TDS measurement results for H2O. From the results in FIG. 3, it can be seen that in sample 3, a peak is observed near 300°C. The results show that the amount of water (H2O) and other substances that are released by the heat treatment in a nitrogen atmosphere is reduced compared to that of the conventional model 2. It can be seen that impurities are desorbed. Therefore, the processing in a nitrogen atmosphere is more effective than that in an air atmosphere. It can be seen that heat reduces impurities such as moisture (H2O) in the film.

[0017] Figure 4 shows a non-single crystal In-Ga-Zn-O film with a thickness of 50 nm formed on a glass substrate. The film-formed sample (sample 1) was heated at 250°C for 1 hour in a nitrogen atmosphere. The treated sample (sample 4) was heated at 350°C for 1 hour in a nitrogen atmosphere. The sample that was heat-treated (sample 3) and the sample that was heated at 450°C in a nitrogen atmosphere for 1 hour were The sample (Sample 5) was heated at 350°C in a nitrogen atmosphere. This is a comparison of the sample (sample 6) that was heated for 10 hours. 4 is a graph showing the TDS measurement results. From the results of FIG. 4, it can be seen that the heating temperature in a nitrogen atmosphere is high. The higher the value, the greater the amount of moisture (H2O) that is desorbed from the In-Ga-Zn-O non-single crystal film. It can be seen that impurities are reduced.

[0018] In addition, from the graphs in Figures 3 and 4, moisture (H2O) can be confirmed at around 200℃ to 250℃. The first peak indicates the desorption of impurities such as water (H2O) at 300°C or higher. A second peak indicating the elimination of the impurity can be confirmed.

[0019] The samples that were heat-treated at 450°C in a nitrogen atmosphere were then left in the air at room temperature for one week. Even after leaving it for about a few hours, no moisture was observed to desorb at temperatures above 200°C. It has been found that Ga-Zn-O based non-single crystal films are stabilized.

[0020] In addition, the heating temperature conditions under nitrogen atmosphere were 150℃, 175℃, 200℃, 225℃, and 25 0℃, 275℃, 300℃, 325℃, 350℃, 375℃, 400℃, 425℃, 45 The carrier concentration was measured at 100° C. and 0° C. The results are shown in FIG.

[0021] Figure 5(A) shows the physical properties (carrier concentration) of the oxide semiconductor film (In-Ga-Zn-O based non-single crystal film). The three-dimensional view of the physical property evaluation sample 510 for evaluating the optical properties (electron mobility and Hall mobility) is shown. A value sample 510 was prepared and the Hall effect was measured at room temperature to determine the carrier The physical property evaluation sample 510 was prepared by subjecting the substrate 50 to an evaluation of the concentration and Hall mobility. An insulating film 501 made of silicon oxynitride is formed on the substrate 501, and a 10 mm×1 503 to 504, each having a diameter of 1 mm, are formed thereon. The carrier concentration of the oxide semiconductor film was calculated by Hall effect measurement. is shown in FIG. 1, the Hall mobility is shown in FIG. 5(B), and the conductivity is shown in FIG. 5(C).

[0022] From the results of Figures 1, 2, 3, and 4, at temperatures above 250°C during TDS measurements, the In-Ga- Impurities such as water (H2O) are released from the Zn-O non-single crystal film, and the carrier concentration It can be seen that there is a relationship between the change in the water content and the change in the temperature. The carrier concentration increases due to the elimination of impurities such as hydrogen (HO).

[0023] In addition, TDS measurements revealed that in addition to H2O, H, O, OH, H2, O2, N, N2, and Ar When measurements were performed for each of these, H2O, H, O, and OH showed clear peaks. Peaks were observed for H2, O2, N, N2, and Ar, but no peaks were observed for the sample. is a non-single crystal In-Ga-Zn-O film with a thickness of 50 nm formed on a glass substrate. The heating conditions were 250°C for 1 hour in a nitrogen atmosphere and 350°C for 1 hour in a nitrogen atmosphere. 10 hours at 350°C and 1 hour at 450°C in a nitrogen atmosphere. The measurements were performed on the n-Ga-Zn-O non-single crystal film and on the glass substrate only. Figure 35 shows the TDS results for OH, Figure 36 shows the TDS results for OH, and Figure 37 shows the TDS results for OH. , Figure 40 shows the TDS result of H2. Note that the oxygen concentration in the nitrogen atmosphere under the above heating conditions is It is below 20 ppm.

[0024] From the above results, by heat treatment of the In-Ga-Zn-O system non-single crystal film, In other words, the heat treatment causes the In-Ga- The main cause of this is the desorption of water (H2O) from the Zn-O non-single crystal film, as shown in Fig. 37H and Fig. The measured TDS values ​​of O shown in Figure 38 and OH shown in Figure 39 indicate that the water molecules were generated by decomposition. The In-Ga-Zn-O non-single crystal film also contains hydrogen and OH. It is believed that these are also released concomitantly during heat treatment.

[0025] In this specification, under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), Alternatively, the heat treatment under reduced pressure is called a heat treatment for dehydration or dehydrogenation. The term "dehydrogenation" refers only to the process of desorption of hydrogen as H2 by this heat treatment. For convenience, this term is used to refer to the elimination of H, OH, etc. Let us assume that.

[0026] By performing heat treatment under an inert gas, impurities (HO) contained in the oxide semiconductor layer are removed. After the temperature is reduced to increase the carrier concentration, the oxide semiconductor layer is gradually cooled. In order to reduce the carrier concentration of the oxide semiconductor layer, an oxide insulating film or the like may be formed in contact with the oxide semiconductor layer. , leading to improved reliability.

[0027] The oxide semiconductor layer is heat-treated in a nitrogen atmosphere to reduce its resistance (the carrier concentration is high). Circle, preferably 1×10 18 / cm 3 The above steps are carried out to form an oxide semiconductor layer with low resistance. Then, an oxide insulating film is formed in contact with the oxide semiconductor layer having a low resistance. In the low-resistance oxide semiconductor layer, at least a region in contact with the oxide insulating film is made high-resistance ( The carrier concentration is reduced, preferably to 1×10 18 / cm 3 Less than 1×1 0 14 / cm 3 The semiconductor device can be provided with a high resistance oxide semiconductor region. During the process, heating in an inert gas atmosphere (or reduced pressure), slow cooling, and the formation of the oxide insulating film It is important to increase or decrease the carrier concentration in the oxide semiconductor layer by, for example, the formation of oxide. By subjecting the oxide semiconductor layer to heat treatment for dehydration or dehydrogenation, the oxide semiconductor layer is dehydrated. It becomes a deficient type and becomes N type (N - , N + Then, an oxide insulating film is formed. It can be said that the oxide semiconductor layer is made to have an i-type structure by making the oxide semiconductor layer into an oxygen-excess state. When an oxide insulating film is formed on an In-Ga-Zn-O based non-single crystal film, the The carrier concentration (1×10 14 / cm 3 This results in good electrical characteristics. It is therefore possible to manufacture and provide a semiconductor device having a thin film transistor with good and high reliability. become.

[0028] Note that the oxide insulating film formed in contact with the low-resistance oxide semiconductor layer is resistant to moisture and hydrogen ions. Nya, OH - In particular, a silicon oxide film or Alternatively, a silicon oxynitride film is used.

[0029] Furthermore, after forming an oxide insulating film as a protective film on the low-resistance oxide semiconductor layer, A second heating may be performed after the oxide insulating film is formed on and in contact with the oxide semiconductor layer and serves as a protective film. After forming the thin film transistor, a second heating process reduces the variation in the electrical characteristics of the thin film transistor. It is possible.

[0030] One aspect of the present invention disclosed herein is a gate electrode layer and a gate insulator on the gate electrode layer. a gate insulating layer, an oxide semiconductor layer over the gate insulating layer, and an insulating layer over the oxide semiconductor layer; A gate insulating layer, the oxide semiconductor layer, and the insulating layer, the gate insulating layer and the oxide semiconductor layer The hydrogen concentration at the interface between the oxide semiconductor layer and the insulating layer is 3×10 20 cm -3 The semiconductor device is as follows.

[0031] The oxide semiconductor layer is not only hydrogen-containing, but also water (H2O), M-OH, MH, etc. However, the average or peak hydrogen concentration, which is the absolute amount, is 3×10 20 cm -3 Less than 1×10 20 cm -3 The following is the result.

[0032] These concentration ranges were obtained by secondary ion mass spectrometry (SIMS) or by its data. The data is obtained based on the

[0033] The above configuration solves at least one of the above problems.

[0034] In addition, one embodiment of the present invention for realizing the above structure is to form a gate electrode layer, A gate insulating layer is formed on the electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and an oxide semiconductor The oxide semiconductor layer is dehydrated or dehydrogenated, and a source is formed on the dehydrated or dehydrogenated oxide semiconductor layer. A gate insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer are formed. and forming an oxide insulating film on the drain electrode layer so as to be in contact with a part of the oxide semiconductor layer. The dehydration or dehydrogenation is carried out in a nitrogen atmosphere or Heating is performed in a rare gas atmosphere or under reduced pressure.

[0035] Another embodiment of the present invention for realizing the above structure is to form a gate electrode layer and A gate insulating layer is formed on the electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and an oxide semiconductor The conductor layer is heated in an inert atmosphere to increase the carrier concentration, and then the carrier concentration is increased. A source electrode layer and a drain electrode layer are formed over the oxide semiconductor layer. The heated oxide semiconductor layer is then formed on the source electrode layer and the drain electrode layer. forming an oxide insulating film in contact with a part of the semiconductor device to reduce the carrier concentration The oxide semiconductor layer is grown in an inert atmosphere at a temperature of 400° C. or higher. The method is characterized in that the material is heated at 400° C. and then cooled slowly to a temperature above room temperature and below 100° C.

[0036] Another embodiment of the present invention for realizing the above structure is to form a gate electrode layer and A gate insulating layer is formed on the electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and an oxide semiconductor The conductor layer is heated under reduced pressure to increase the carrier concentration, and then the oxide with the increased carrier concentration is A source electrode layer and a drain electrode layer are formed on the semiconductor layer, and a gate insulating layer and a heated oxide layer are formed on the semiconductor layer. A semiconductor layer, a source electrode layer, and a drain electrode layer are heated, and a contact layer is formed on the semiconductor layer, the source electrode layer, and the drain electrode layer. A method for manufacturing a semiconductor device, comprising forming an oxide insulating film to reduce carrier concentration. It is law.

[0037] In the configuration of each of the above manufacturing methods, the carrier concentration of the oxide semiconductor layer having the increased carrier concentration is is 1 x 10 18 / cm 3 The above is the case. In addition, the oxide insulating film is formed to reduce the carrier concentration. The carrier concentration of the oxide semiconductor layer is reduced by 1×10 18 / cm 3 Less than 1x1 0 14 / cm 3 The following is the result.

[0038] The oxide semiconductor used in this specification is, for example, InMO3(ZnO). m Expressed as (m>0) A thin film is formed on the substrate, and a thin film transistor is fabricated using the thin film as a semiconductor layer. M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M can be Ga, Ga and Ni, or Ga and Fe. In addition, in the oxide semiconductor, M may contain the above-mentioned metal element other than Ga. In addition to the metal elements contained as impurities, Fe, Ni and other transition metal elements, In the present specification, InMO3(Z nO) m Among oxide semiconductor layers having a structure represented by (m>0), a structure containing Ga as M The oxide semiconductor is called the In-Ga-Zn-O oxide semiconductor, and the thin film of the In-Ga- It is also called a Zn-O based non-single crystal film.

[0039] In addition to the above, In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, In-Ga-O series, Sn-Zn-O series, Al -Zn-O, In-O, Sn-O, and Zn-O oxide semiconductors can be used. The oxide semiconductor layer may contain silicon oxide. By including silicon oxide (SiOx(x>0)) which inhibits oxidation during the manufacturing process, When a heat treatment is performed after the formation of the oxide semiconductor layer, crystallization can be suppressed. Note that the oxide semiconductor layer is preferably in an amorphous state, and even if it is partially crystallized, good.

[0040] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), It is effective to subject the mixture to a hydrogenation or dehydrogenation process.

[0041] In addition, since thin-film transistors are easily damaged by static electricity, etc., It is preferable to provide a protection circuit for protecting the driver circuit on the same substrate as the line. is preferably configured using a nonlinear element using an oxide semiconductor.

[0042] In addition, the gate insulating layer and the oxide semiconductor film are processed continuously without being exposed to the air. It may be subjected to a continuous process (also called in-situ process or continuous deposition). By performing the treatment continuously without causing the oxide semiconductor film to be damaged, the interface between the gate insulating layer and the oxide semiconductor film is protected from water and halogen. Each of these is free from contamination by atmospheric components and impurities floating in the air, such as hydrocarbons. Since a lamination interface can be formed, the variation in thin film transistor characteristics can be reduced. can be done.

[0043] In this specification, the term "continuous processing" refers to a process that starts with the first processing step performed by the PCVD method or the sputtering method and ends with the PC During the series of processes up to the second processing step performed by the VD method or sputtering method, the substrate to be processed is placed The atmosphere is always in a vacuum or inert gas without coming into contact with contaminated atmosphere such as air. This refers to the atmosphere (nitrogen or rare gas) being controlled. Continuous processing is performed. This allows the cleaned substrate to be treated without re-adhering moisture and other impurities, and allows the substrate to be treated in a film-forming or other similar manner. It is possible.

[0044] To carry out a series of processes from the first processing step to the second processing step in the same chamber In this specification, the first process is performed in a different chamber. When carrying out a series of processes from the first processing step to the second processing step, after completing the first processing step, The present specification also provides a method for transferring the substrate between chambers without exposing the substrate to the atmosphere and subjecting the substrate to the second treatment. It is assumed that the range of continuous processing is within the range of

[0045] Between the first and second processing steps, a substrate transfer step, an alignment step, and a slow cooling step are performed. or a step of heating or cooling the substrate to a temperature required for the second step. However, such a process is considered to be within the scope of the continuous process in this specification.

[0046] However, the first step involves processes that use liquids, such as cleaning, wet etching, and resist formation. If the first processing step is between the second processing step, it does not fall within the scope of continuous processing as used herein. Let's say that's not the case. Effect of the Invention

[0047] It is possible to manufacture and provide a thin film transistor having stable electrical characteristics. It is possible to provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. do. [Brief description of the drawings]

[0048] [Figure 1] 1 is a graph showing the carrier concentration of an oxide semiconductor layer versus heating temperature. [Diagram 2] 1 is a graph showing the results of TDS measurement. [Diagram 3] 1 is a graph showing the results of TDS measurement. [Figure 4] 1 is a graph showing the results of TDS measurement. [Diagram 5] 1A is a three-dimensional view of a sample for evaluating physical properties, FIG. 1B shows the results of measuring the Hall effect of an oxide semiconductor layer, and FIG. 1C is a graph showing electrical conductivity. [Figure 6] 1A to 1C are cross-sectional views illustrating a manufacturing process according to one embodiment of the present invention. [Figure 7]1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing process according to one embodiment of the present invention. [Figure 9] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a manufacturing process according to one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a manufacturing process according to one embodiment of the present invention. [Figure 12] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] Cross-section of an electric furnace [Figure 15] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 16] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 17] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 18] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 19] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 20] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 21] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 22] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Diagram 23] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 24] FIG. 2 is a diagram illustrating a configuration of a shift register. [Diagram 25] 25 is a diagram for explaining a connection configuration of the flip-flop shown in FIG. 24. [Figure 26] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 27] FIG. 1 is an external view showing an example of an electronic book. [Figure 28] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 29]FIG. 1 is an external view showing an example of a gaming machine. [Diagram 30] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Diagram 31] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 32] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 33] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 34] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 35] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 36] 1A to 1C are diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 37] 1 is a graph showing the TDS results of H. [Figure 38] 1 is a graph showing the TDS results of O. [Figure 39] 1 is a graph showing the TDS results of OH. [Diagram 40] 1 is a graph showing the TDS results of H2. [Diagram 41] 1 is a graph showing the Vg-Id characteristics of a thin film transistor before and after a BT test. [Diagram 42] 1A and 1B are diagrams illustrating a structure of an oxide semiconductor layer used in calculations. [Diagram 43] 11A and 11B are diagrams illustrating calculation results of oxygen density in oxide semiconductor layers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0050] (Embodiment 1) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0051] FIG. 7A is a plan view of a thin film transistor 470 included in the semiconductor device, and FIG. 7(A). The transistor is a gate type thin film transistor, and a gate electrode is disposed on a substrate 400 having an insulating surface. A gate insulating layer 401, a semiconductor layer 403, a source electrode layer or a drain electrode layer 4 In addition, the insulating layer 405a and the insulating layer 405b cover the thin film transistor 470 and are in contact with the semiconductor layer 403. An oxide insulating film 407 is provided.

[0052] The semiconductor layer 403 made of an oxide semiconductor is formed by removing impurities at least after the oxide semiconductor film is formed. Heat treatment to reduce moisture content (heat treatment for dehydration or dehydrogenation) is performed. Low resistance (increased carrier concentration, preferably 1×10 18 / cm 3 After the above, By forming the oxide insulating film 407 in contact with the substrate, the resistance is increased (the carrier concentration is decreased, which is preferable). Or 1×10 18 / cm 3 less than 1×10 14 / cm 3 (Below) The oxide semiconductor film can be used as a channel formation region.

[0053] In addition, impurities such as water (H2O) are removed by heat treatment for dehydration or dehydrogenation. After the desorption process, it is preferable to slowly cool the mixture in an inert atmosphere. After heat treatment for hydrogenation and gradual cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer. The carrier concentration of the oxide semiconductor layer can be reduced by performing the above steps. This leads to improved reliability.

[0054] In addition to the semiconductor layer 403, the gate insulating layer 402 and the upper and lower portions of the gate insulating layer 402 are also provided. Specifically, the interface between the gate insulating layer 402 and the semiconductor layer 403 which is an oxide semiconductor Moisture and the like present at the interface between the oxide insulating film 407 and the semiconductor layer 403 and at the interface between the oxide insulating film 407 and the semiconductor layer 403 Reduce impurities.

[0055] Here, an example showing the results of a reliability test of the thin film transistor 470 will be described with reference to FIG. .

[0056] One of the methods for investigating the reliability of thin-film transistors is the bias-thermal stress test (hereafter referred to as The BT test is a type of accelerated test, which is used to measure the deterioration of a material through long-term use. The characteristic changes of thin-film transistors that occur can be evaluated in a short time. The change in the threshold voltage of a thin-film transistor before and after the test is an important factor in determining its reliability. The smaller the change in threshold voltage before and after the BT test, the higher the reliability.

[0057] Specifically, the temperature of the substrate on which the thin film transistor is formed (substrate temperature) is kept constant. The source and drain of the thin film transistor are set to the same potential, and the gate is connected to the source and drain. A potential different from that of the tester is applied for a certain period of time. The substrate temperature can be set appropriately according to the purpose of the test. The case where the potential applied to the gate is higher than the potential of the source and drain is called +B This is called the T test, and is when the potential applied to the gate is lower than the same potential of the source and drain. -It's called the BT test.

[0058] The test strength of the BT test depends on the substrate temperature, the electric field strength applied to the gate insulating film, and the electric field application time. The electric field strength applied to the gate insulating film can be determined by the gate, source and The potential difference between the drain and the gate is divided by the thickness of the gate insulating film. If you want to apply an electric field strength of 2MV / cm to a gate insulating film of 2 nm, the potential difference should be 20V This can be done as follows.

[0059] In this embodiment, the process is performed before forming the source and drain in the manufacture of a thin film transistor. Heat treatment was performed on three types of samples at 250℃, 350℃, and 450℃ in a nitrogen atmosphere. The results of the BT test will be explained.

[0060] Generally speaking, voltage refers to the potential difference between two points, and potential refers to the potential at a certain point. The electrostatic energy (electrical potential energy) of a unit charge in a static electric field In electronic circuits, the potential at a certain point and the reference potential (for example, ground potential) In this specification, the potential difference between the potential at a certain point and the potential at the other point is often referred to as the potential at the other point. is the difference between the potential at a certain point and a reference potential (for example, ground potential) at the certain point. When the potential is shown as a potential at a certain point, unless otherwise specified, the potential at that point is also called voltage.

[0061] The BT test was performed at a substrate temperature of 150°C, with an electric field strength of 2MV / cm applied to the gate insulating film. The addition time was set to 1 hour, and both +BT and -BT tests were performed.

[0062] First, the +BT test will be explained. The initial characteristics of the thin film transistor to be subjected to the BT test are For the measurement, the substrate temperature was set to 40°C, and the source-drain voltage (hereafter referred to as drain voltage) The source-gate voltage (hereafter referred to as the gate voltage) is set to -20V to + Change in source-drain current (hereafter referred to as drain current) when the voltage is changed up to 20V The characteristics, i.e., the Vg-Id characteristics, were measured. Here, the substrate temperature was adjusted to prevent moisture absorption on the sample surface. The recommended temperature is 40°C, but if there are no particular problems, measurements can be taken at room temperature (25°C). stomach.

[0063] Next, the substrate temperature is raised to 150° C., and then the source and drain of the thin film transistor are The potential at the gate insulating film was set to 0 V. Then, the electric field strength applied to the gate insulating film was set to 2 MV / cm. A voltage was applied to the gate so that the thickness of the gate insulating film of the thin film transistor was Since the thickness was 100 nm, +20 V was applied to the gate and held there for 1 hour. The application time was set to 1 hour, but the time may be changed appropriately depending on the purpose.

[0064] Next, while applying voltage to the source, drain, and gate, the substrate temperature is lowered to 40°C. If the voltage application is stopped before the substrate temperature drops completely, the residual heat The damage done to the thin film transistor during the BT test is repaired, so the voltage is applied After the substrate temperature reaches 40°C, the voltage application is stopped. I completed it.

[0065] Next, measure the Vg-Id characteristics under the same conditions as the initial characteristics measurement, and measure the Vg-Id characteristics after the +BT test. characteristics were obtained.

[0066] Next, we will explain about the -BT test. The -BT test is conducted in the same manner as the +BT test, but The difference is that the voltage applied to the gate is set to -20 V after the substrate temperature is raised to 150°C. do.

[0067] In addition, for the BT test, thin-film transistors that have never been subjected to the BT test were used. For example, it is important to use a thin-film transistor that has already undergone a +BT test. If you perform a -BT test using a +BT test, the -BT test results may be incorrect due to the influence of the +BT test that was performed earlier. It is not possible to evaluate the +B resistance again using a thin-film transistor that has already been subjected to the +BT test. The same applies when T tests are conducted. However, taking these effects into account, BT tests are This does not apply if the above is repeated.

[0068] 41(A) to 41(C) show the Vg-Id of a thin film transistor before and after a BT test. FIG. 41(A) shows the characteristics of the heat treatment performed before the formation of the source and drain in a nitrogen atmosphere. The results of the BT test of a thin-film transistor fabricated in a soaked bath at 250°C are shown in Fig. 41(B). The heat treatment before the source and drain formation was performed at 350°C in a nitrogen atmosphere. The results of the BT test of the transistor are shown in FIG. 41(C), which is performed before the formation of the source and drain. The results are the BT test results for thin-film transistors fabricated with a heat treatment at 450°C in a nitrogen atmosphere. do.

[0069] In each figure, the horizontal axis is the gate voltage (Vg), and the vertical axis is the drain current (Id The initial characteristics 711, 721, and 731 are the thin films before the +BT test. The Vg-Id characteristics of the thin film transistors are shown in Table 1. +BT712, 722, and 732 are thin films after the +BT test. The Vg-Id characteristics of the thin film transistors are shown in Fig. 1. For -BT713, 723, and 733, the thin film transistors after -BT testing are shown in Fig. 1. The Vg-Id characteristics of the thin film transistor are shown in Fig. 1. Note that the Vg-Id characteristics of the thin film transistor before the -BT test The Vg-Id characteristics of the MOSFETs were almost the same as those before the +BT test. Not stated.

[0070] According to FIG. 41(A) to FIG. 41(C), compared with the initial characteristics 711, 721, and 731, + BT712, 722, 732 have a positive threshold voltage, -BT713, 723, 7 It can be seen that the threshold voltage of 33 is shifting in the negative direction. From FIG. 41(B), from FIG. 41(B) to FIG. 41(C), the source and drain are formed. As the temperature of the heat treatment before the test was increased to 250℃, 350℃, and 450℃, the +BT test It can be seen that the amount of change in the threshold voltage after the first period is smaller.

[0071] By setting the heat treatment temperature at 450℃ or higher, reliability at least in the +BT test is improved. Impurities such as moisture (H2O) can be removed from the In-Ga-Zn-O non-single crystal film. It can be seen that there is a relationship between the detachment of β-glucose and the results of the BT stress test.

[0072] In addition, the source electrode layer or drain electrode layer 4 05a, 405b: titanium, aluminum, manganese, magnesium, zirconium The material is selected from one or more of the elements mentioned above. An alloy film combining these may be laminated.

[0073] The semiconductor layer 403 including the channel formation region is made of an oxide material having semiconductor properties. Typically, an In-Ga-Zn-O based non-single crystal film is used.

[0074] 6A to 6D are cross-sectional views showing a manufacturing process of a thin film transistor 470. FIG.

[0075] In FIG. 6A, a gate electrode layer 401 is formed on a substrate 400 having an insulating surface. An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 401. The base film has a function of preventing the diffusion of impurity elements from the substrate 400. A laminated structure made of one or more films selected from a bare film, a silicon nitride oxide film, and a silicon oxynitride film. The gate electrode layer 401 can be formed of a material such as molybdenum, titanium, chromium, or the like. Metallic materials such as titanium, tantalum, tungsten, aluminum, copper, neodymium, and scandium Alternatively, it can be formed in a single layer or a laminated layer using an alloy material mainly composed of these. .

[0076] For example, the gate electrode layer 401 may have a two-layer laminate structure of molybdenum on an aluminum layer. A two-layer structure with a layer of copper on top of a layer of molybdenum, or a two-layer structure with a layer of molybdenum on top of a layer of copper, or The structure is a two-layer structure with a titanium nitride layer or tantalum nitride layer laminated on a copper layer, and a titanium nitride layer and a molybdenum layer. It is preferable to use a two-layer structure in which a tongue layer is laminated with a butene layer. A layer of tungsten or tungsten nitride and an alloy of aluminum and silicon or aluminum and silicon Preferably, the layer is a laminate of a titanium alloy and a titanium nitride or titanium layer.

[0077] Next, a gate insulating layer 402 is formed over the gate electrode layer 401 .

[0078] The gate insulating layer 402 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer may be formed as a single layer or a stacked layer. For example, the deposition gas can be SiH4, oxygen, and nitrogen, and the plasma CVD method can be used. A silicon oxynitride layer may be formed.

[0079] Next, an oxide semiconductor film is formed over the gate insulating layer 402.

[0080] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma Reverse sputtering is performed to generate ions, and dust adhering to the surface of the gate insulating layer 402 is removed. In reverse sputtering, the target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power source under atmospheric pressure to form plasma near the substrate and modify the surface. It is to be noted that nitrogen, helium, or the like may be used in place of the argon atmosphere. Alternatively, the treatment may be performed in an atmosphere in which oxygen, N2O, etc., has been added to the argon atmosphere. Alternatively, the treatment may be performed in an atmosphere containing Cl2, CF4, etc.

[0081] The oxide semiconductor film was formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. The oxide semiconductor film is formed by oxidizing an oxide semiconductor film under a rare gas (typically, argon) atmosphere. The sputtering is carried out under a nitrogen atmosphere or a mixture of a rare gas (typically argon) and oxygen. It can be formed by the TA method.

[0082] The gate insulating layer 402 and the oxide semiconductor film are successively formed without exposure to air. By continuously forming the film without exposing it to the air, the interface is free from water and hydrocarbons. The interfaces of each layer are formed without being contaminated by atmospheric components or impurity elements floating in the air. Therefore, the variation in the characteristics of the thin film transistors can be reduced.

[0083] The oxide semiconductor film is then subjected to a photolithography process to form an island-shaped oxide semiconductor layer, which is an oxide semiconductor layer. The resulting semiconductor layer is processed into a substrate layer 430 (first oxide semiconductor layer) (see FIG. 6(A)).

[0084] The oxide semiconductor layer is heated under an inert gas atmosphere (nitrogen, helium, neon, argon, etc.) or After the heat treatment under reduced pressure, the material is slowly cooled in an inert atmosphere (see FIG. 6(B)). The oxide semiconductor layer 430 is subjected to heat treatment in the above atmosphere, whereby the oxide semiconductor layer 43 It is possible to remove impurities such as hydrogen and water contained in 0.

[0085] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably It is preferable to keep the concentration at 0.1 ppm or less.

[0086] Heat treatment can be performed using an electric furnace or a GRTA (Gas-Reactor-Atomic-Tapered Atomic) method. Rapid Thermal Annealing (LRTA) using lamp light (La Use instantaneous heating methods such as the mp Rapid Thermal Anneal method. It is possible.

[0087] Here, as one mode of heat treatment of the oxide semiconductor layer 430, a heating method using an electric furnace 601 is used. The method will be explained with reference to FIG.

[0088] FIG. 14 is a schematic diagram of an electric furnace 601. A heater 603 is installed on the outside of a chamber 602. The chamber 602 is provided with a heating element for heating the chamber 602. A susceptor 605 for mounting a substrate 604 is provided in the chamber 602. The chamber 602 is provided with a gas supply means 606 and an exhaust means 60 7 is provided. Gas is introduced into the chamber 602 by a gas supply means 606. In addition, the inside of the chamber 602 is evacuated by the exhaust means 607, or the chamber 602 is evacuated. The inside of the electric furnace 601 is decompressed. The temperature rise characteristic of the electric furnace 601 is set to 0.1°C / min or more and 20°C / min or less. It is preferable that the temperature drop rate of the electric furnace 601 is 0.1° C. / min or more and 15 It is preferable to set the rate to .degree. C. / min or less.

[0089] The gas supply means 606 includes a gas supply source 611, a pressure regulating valve 612, a purifier 613, and a mass flow meter. In this embodiment, the gas supply source It is preferable to provide a purifier 613 between 611 and the chamber 602. By providing the gas supply source 611, the gas such as water, hydrogen, etc., introduced into the chamber 602 can be Impurities such as the above can be removed by the purifier 613, and the chamber 60 It is possible to reduce the intrusion of water, hydrogen, etc. into the fuel cell.

[0090] In this embodiment, nitrogen or a rare gas is introduced into the chamber 602 from a gas supply source 611. The inside of the chamber is filled with nitrogen or a rare gas atmosphere, and the temperature is preferably 200°C to 600°C. The substrate 604 is formed in a chamber 602 heated to 400° C. or higher and 450° C. or lower. The oxide semiconductor layer 430 thus formed is heated, whereby the oxide semiconductor layer 430 is dehydrated or Dehydrogenation can be carried out.

[0091] Alternatively, the temperature is increased by an exhaust means under reduced pressure at 200°C or higher and 600°C or lower, preferably 400°C or lower. In a chamber 602 heated to 450° C. or less, an oxide film formed on a substrate 604 is By heating the oxide semiconductor layer 430, the oxide semiconductor layer 430 is dehydrated or dehydrogenated. It is possible to do so.

[0092] The heater is then turned off and the heating chamber 602 is allowed to cool gradually. The semiconductor layer is heated in an inert gas atmosphere or under reduced pressure and then cooled slowly to obtain a low resistance (The carrier concentration is increased, preferably 1×10 18 / cm 3 (above) and the acid with low resistance The second oxide semiconductor layer 431 (second oxide semiconductor layer) can be used as the second oxide semiconductor layer.

[0093] As a result, the reliability of the thin film transistor to be formed later can be improved.

[0094] If the heat treatment is carried out under reduced pressure, an inert gas is passed through the material to return it to atmospheric pressure after heating and then cooled. You can just ignore it.

[0095] After the substrate 604 in the chamber 602 of the heating device was cooled to 300° C., 4 may be moved to a room temperature atmosphere. This can reduce the cooling time of the substrate 604. can.

[0096] In addition, if the heating device is a multi-chamber device, the heating process and the cooling process are performed in different chambers. Typically, nitrogen or a rare gas is filled and the temperature is 200°C to 600°C. In the first chamber, which is preferably heated to 400° C. or higher and 450° C. or lower, The oxide semiconductor layer on the plate is heated. Then, the plate is transferred to a transfer chamber into which nitrogen or a rare gas is introduced. A second chamber filled with nitrogen or a noble gas and at a temperature below 100° C., preferably at room temperature. The substrate that has been subjected to the above heat treatment is then moved to the substrate 100 and cooled. can improve

[0097] In addition, the heat treatment of the oxide semiconductor layer under an inert gas atmosphere or under reduced pressure can form island-shaped oxide films. It is also possible to perform this treatment on the oxide semiconductor film before processing it into an oxide semiconductor layer. In that case, an inactive After heat treatment of the oxide semiconductor film under a gas atmosphere or reduced pressure, The substrate is then removed from the heating apparatus and a photolithography process is performed.

[0098] In addition, the state of the oxide semiconductor film after the heat treatment under an inert gas atmosphere or under reduced pressure is amorphous. It is preferable that the crystal is in a crystallized state, but it may be partially crystallized.

[0099] Next, a conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 431.

[0100] The conductive film material is an element selected from Al, Cr, Ta, Ti, Mo, and W, or Examples of the thin film include an alloy containing the above-mentioned elements as components, and an alloy film of a combination of the above-mentioned elements.

[0101] In addition, when a heat treatment is performed after the formation of the conductive film, the conductive film is required to have heat resistance capable of withstanding the heat treatment. Aluminum alone has problems such as poor heat resistance and susceptibility to corrosion. Therefore, it is formed by combining it with a heat-resistant conductive material. Heat-resistant conductive material combined with Al The materials are titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M o), chromium (Cr), Nd (neodymium), Sc (scandium), or or an alloy film containing the above-mentioned elements as components, or an alloy film of a combination of the above-mentioned elements, It is formed of a nitride containing the selected elements.

[0102] The oxide semiconductor layer 431 and the conductive film are etched by an etching process, and the oxide semiconductor layer 4 32, and the source and drain electrode layers 405a and 405b are formed (FIG. 6(C) Note that the oxide semiconductor layer 432 is only partially etched to have a groove (a depression). The oxide semiconductor layer 432 is formed.

[0103] The oxide insulating film 407 is formed in contact with the oxide semiconductor layer 432 by a sputtering method. The oxide insulating film 407 formed in contact with the oxide semiconductor layer is resistant to moisture, hydrogen ions, and OH - It is an inorganic insulating film that does not contain impurities such as those listed above and blocks their intrusion from the outside. Specifically, a silicon oxide film or a silicon nitride oxide film is used.

[0104] In this embodiment, a silicon oxide film is formed as the oxide insulating film 407 to a thickness of 300 nm. The substrate temperature during film formation may be from room temperature to 300° C., and in this embodiment, it is set to 100° C. The silicon oxide film is formed by sputtering in a rare gas (typically argon) atmosphere. It can be carried out under an oxygen atmosphere or under an atmosphere of rare gas (typically argon) and oxygen. In addition, it is possible to use a silicon oxide target or a silicon target. For example, a silicon target may be used to perform sputtering in an oxygen and nitrogen atmosphere. A silicon carbide can be formed.

[0105] In contact with the oxide semiconductor layer 432 with a reduced resistance, an oxide semiconductor layer 432 is formed by sputtering or PCVD. When the oxide insulating film 407 is formed, at least the oxide semiconductor layer 432 having a low resistance is The region in contact with the oxide insulating film 407 is made highly resistive (the carrier concentration is reduced, preferably 1×10 18 / cm 3 The resistance of the oxide semiconductor region can be increased by 100% or less. During the manufacturing process, heating in an inert gas atmosphere (or reduced pressure), slow cooling, and the formation of an oxide insulating film It is important to increase or decrease the carrier concentration of the oxide semiconductor layer by forming an oxide The semiconductor layer 432 is a semiconductor layer 403 (a third oxide semiconductor) having a high resistance oxide semiconductor region. A thin film transistor 470 can be manufactured (see FIG. 6D). .

[0106] By performing the heat treatment for the dehydration treatment or the dehydrogenation treatment, After reducing impurities (H2O, H, OH, etc.) contained in the crystal and increasing the carrier concentration, the crystal is slowly cooled. After the oxide semiconductor layer is cooled slowly, an oxide insulating film is formed in contact with the oxide semiconductor layer. The carrier concentration of the conductor layer can be reduced, and the reliability of the thin film transistor 470 can be improved. do.

[0107] After the oxide insulating film 407 is formed, Then, the thin film transistor 470 is subjected to a heat treatment (preferably at 150° C. or higher and lower than 350° C.). For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The oxide semiconductor layer 432 is heated in contact with the oxide insulating film 407. The variation in electrical characteristics of the thin film transistor 470 can be reduced. (preferably 150° C. or higher and lower than 350° C.) is particularly effective after the oxide insulating film 407 is formed. Not limited to this, other processes, such as a heat treatment during resin film formation, or a process for reducing the resistance of a transparent conductive film may be used. By combining this with the heat treatment for the purpose, it is possible to carry out the process without increasing the number of steps.

[0108] (Embodiment 2) A semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The same parts or parts having similar functions and steps can be performed in the same manner as in the first embodiment. Therefore, repeated explanation will be omitted.

[0109] FIG. 9A is a plan view of a thin film transistor 460 included in a semiconductor device, and FIG. 9(A). The transistor is a gate type thin film transistor, and a gate electrode is disposed on a substrate 450 having an insulating surface. A pole layer 451, a gate insulating layer 452, a source electrode layer or a drain electrode layer 455a, 455b The thin film transistor 460 is covered with a semiconductor layer 453. The oxide insulating film 457 is provided in contact with the semiconductor layer 453. A non-single crystal film based on the GaN-based nanotube is used.

[0110] The thin film transistor 460 has a gate insulating layer in the entire region including the thin film transistor 460. A layer 452 is present between the gate insulating layer 452 and a substrate 450 that is a substrate having an insulating surface. A gate electrode layer 451 is provided. A source electrode layer or a drain electrode layer is provided on the gate insulating layer 452. The gate electrode layers 455a and 455b are provided. A semiconductor layer 453 is provided over the source or drain electrode layers 455a and 455b. Although not shown, a source electrode layer or drain electrode layer 452 is formed over the gate insulating layer 452. In addition to 5a and 455b, a wiring layer is provided, and the wiring layer extends outward from the outer periphery of the semiconductor layer 453. It exists.

[0111] The semiconductor layer 453 made of an oxide semiconductor is formed by removing impurities at least after the oxide semiconductor film is formed. Heat treatment to reduce moisture content (heat treatment for dehydration or dehydrogenation) is performed. Low resistance (increased carrier concentration, preferably 1×10 18 / cm 3 After the above, By forming the oxide insulating film 457 in contact with the semiconductor substrate, the resistance is increased (the carrier concentration is decreased, which is preferable). Or 1×10 18 / cm 3 The oxide semiconductor film is used as a channel formation region by performing a thermal treatment on the oxide semiconductor film. It is possible.

[0112] In addition, impurities such as water (H2O) are removed by heat treatment for dehydration or dehydrogenation. After the desorption process, it is preferable to slowly cool the mixture in an inert atmosphere. After heat treatment for hydrogenation and gradual cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer. The carrier concentration of the oxide semiconductor layer can be reduced by performing the above steps. This leads to improved reliability.

[0113] In addition, the source or drain electrode layer 4 55a, 455b: titanium, aluminum, manganese, magnesium, zirconium The material is selected from one or more of aluminum, beryllium, and the like.

[0114] 8A to 8D are cross-sectional views showing a manufacturing process of a thin film transistor 460. FIG.

[0115] A gate electrode layer 451 is provided over a substrate 450 having an insulating surface. An insulating film may be provided between the substrate 450 and the gate electrode layer 451. These films have the function of preventing the diffusion of impurity elements, and are used in silicon nitride films, silicon oxide films, and silicon oxynitride films. or a silicon oxynitride film. The material of the gate electrode layer 451 is molybdenum, titanium, chromium, tantalum, tungsten, etc. Metallic materials such as stainless steel, aluminum, copper, neodymium, scandium, etc., or materials that contain these as their main components The insulating film 10 can be formed as a single layer or a laminated layer using an alloy material.

[0116] A gate insulating layer 452 is formed over the gate electrode layer 451 .

[0117] The gate insulating layer 452 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer may be formed as a single layer or a stacked layer. can.

[0118] A conductive film is formed on the gate insulating layer 452, and an island-shaped source is formed by a photolithography process. The electrode or drain electrode layers 455a and 455b are formed (see FIG. 8A).

[0119] The material of the source electrode layer or the drain electrode layer 455a, 455b is Al, Cr, Ta , Ti, Mo, W, or an alloy containing the above elements, or In addition, alloy films combining the above-mentioned elements can be used. Any of these may be laminated.

[0120] The source and drain electrode layers 455a and 455b are formed of a material selected from the group consisting of SiO 2 and SiO 2 . Highly heat-resistant molybdenum that can withstand heat treatment for dehydration or dehydrogenation. It is preferable to use a film of Al, Cr, Ta, Ti, or W on the molybdenum film. The elements mentioned above, or alloys containing the above elements or combinations of the above elements A film or the like may be laminated.

[0121] Next, a gate insulating layer 452 and the source and drain electrode layers 455a and 455b are and forming an island-shaped oxide semiconductor layer 483 by a photolithography process. The resulting semiconductor layer is processed into a first oxide semiconductor layer (see FIG. 8B).

[0122] The oxide semiconductor layer 483 serves as a channel formation region. The same is formed as above.

[0123] Note that before the oxide semiconductor layer 483 was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and dust adhering to the surface of the gate insulating layer 452 is removed. It is preferable to remove

[0124] The oxide semiconductor layer 483 is subjected to heat treatment for dehydration or dehydrogenation and then heated in an inert atmosphere. The heat treatment for dehydration or dehydrogenation is carried out in an inert gas atmosphere. (nitrogen, helium, neon, argon, etc.) or under reduced pressure, 200℃ or higher Heat treatment is performed at 600° C. or lower, preferably at 400° C. or higher and 450° C. or lower. 483 is heat-treated in the above atmosphere to lower the resistance (increase the carrier concentration, favorable Preferably 1×10 18 / cm 3The resistance of the oxide semiconductor layer 484 (second oxide The layer may be a nitride semiconductor layer (see FIG. 8(C)).

[0125] In the heat treatment for dehydration or dehydrogenation, nitrogen, helium, neon, or argon are used. It is preferable that the rare gas such as argon does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the 9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1 ppm or less, preferably 0.1 ppm or less).

[0126] In addition, the heat treatment of the oxide semiconductor layer under an inert gas atmosphere or under reduced pressure can form island-shaped oxide films. It is also possible to perform this treatment on the oxide semiconductor film before processing it into an oxide semiconductor layer. In that case, an inactive After heat treatment of the oxide semiconductor film under a gas atmosphere or reduced pressure, The substrate is then removed from the heating apparatus and a photolithography process is performed.

[0127] Next, an oxide insulating film is formed on the oxide semiconductor layer 484 by a sputtering method or a PCVD method. In this embodiment, the oxide insulating film 457 is formed to a thickness of 300 nm. The substrate temperature during the film formation is set to be between room temperature and 300° C. In this embodiment, the temperature is set to 100° C. When the oxide insulating film 457, which is a silicon oxide film, is formed, the resistance of the oxide semiconductor layer 4 In 84, at least the region in contact with the oxide insulating film 457, which is a silicon oxide film, is made to have a high resistance ( The carrier concentration is reduced, preferably to 1×10 18 / cm 3(less than 10000 times) and high resistance oxide semiconductor During the manufacturing process of the semiconductor device, the semiconductor device is The carrier of the oxide semiconductor layer is formed by heating under reduced pressure, gradually cooling, and forming an oxide insulating film. It is important to increase or decrease the concentration. The oxide semiconductor layer 484 is a high resistance oxide semiconductor region. The semiconductor layer 453 (the third oxide semiconductor layer) having the insulating layer 451 is formed as a thin film transistor 460. It is possible to fabricate the semiconductor device (see FIG. 8(D)).

[0128] By performing heat treatment for dehydration or dehydrogenation, The impurities (H2O, H, OH, etc.) present in the crystal are reduced to increase the carrier concentration, and then the crystal is cooled slowly. After the oxide semiconductor layer is cooled, an oxide insulating film is formed in contact with the oxide semiconductor layer. The carrier concentration of the layer can be reduced, and the reliability of the thin film transistor 460 can be improved.

[0129] After the silicon oxide film to be the oxide insulating film 457 is formed, The thin film transistor 460 is subjected to a heat treatment (preferably 150° C. or higher, 350° C. or higher) in the atmosphere. For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The semiconductor layer 453 is heated in contact with the oxide insulating film 457. By performing this, the variation in the electrical characteristics of the thin film transistor 460 can be reduced. The heat treatment (preferably at 150° C. or higher and lower than 350° C.) is performed after the formation of the oxide insulating film 457. There are no particular limitations as long as the material is a low-resistance transparent conductive film, and other processes, such as a heat treatment during resin film formation, By combining this with the heat treatment for curing, it is possible to carry out this process without increasing the number of steps.

[0130] In addition, this embodiment mode can be freely combined with the first embodiment mode.

[0131] (Embodiment 3) A manufacturing process of a semiconductor device including a thin film transistor will be described with reference to FIGS. do.

[0132] In FIG. 10(A), a light-transmitting substrate 100 is made of barium borosilicate glass or aluminum. A glass substrate such as a borosilicate glass substrate can be used.

[0133] Next, a conductive layer is formed on the entire surface of the substrate 100, and then a first photolithography process is performed. A resist mask is formed, and unnecessary parts are removed by etching to form wiring and electrodes (gate A gate wiring including an electrode layer 101, a capacitance wiring 108, and a first terminal 121) are formed. At this time, the etching is performed so that at least the end of the gate electrode layer 101 is tapered. ng.

[0134] The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), Choose from molybdenum (Mo), chromium (Cr), Nd (neodymium), and scandium (Sc). The elements mentioned above, or alloys containing the above elements or combinations of the above elements The film is formed of a nitride containing the above-mentioned elements.

[0135] Next, a gate insulating layer 102 is formed on the entire surface of the gate electrode layer 101. For 02, a method such as sputtering or PCVD is used, and the film thickness is set to 50 to 250 nm.

[0136] For example, a silicon oxide film is formed as the gate insulating layer 102 by sputtering to a thickness of 100 nm. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film. Other insulating films such as silicon oxynitride film, silicon nitride film, aluminum oxide film, and tantalum oxide film are also used. may be used and may be formed as a single layer or a laminate structure made of these materials.

[0137] Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed on the gate insulating layer 102. After the plasma treatment, the In-Ga-Zn-O non-single crystal film is formed without exposure to the atmosphere. Deposition of the film is useful in that it prevents dust and moisture from adhering to the interface between the gate insulating layer and the semiconductor film. Here, an oxide semiconductor target ( In-Ga-Zn-O oxide semiconductor target (In2O3:Ga2O3:ZnO=1 :1:1) was used, the distance between the substrate and the target was 170 mm, the pressure was 0.4 Pa, Direct current (DC) power supply 0.5 kW, oxygen only, argon only, or argon and oxygen atmosphere If a pulsed direct current (DC) power supply is used, dust can be reduced and the film thickness distribution can be made uniform. The thickness of the In-Ga-Zn-O based non-single crystal film is preferably 5 nm to 200 nm. The oxide semiconductor film was prepared by using an In-Ga-Zn-O oxide semiconductor target. Using this, a 50 nm-thick In-Ga-Zn-O-based non-single crystal film is formed by sputtering.

[0138] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal films. It is used in.

[0139] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0140] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0141] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0142] Next, a second photolithography process is performed to form a resist mask, and the oxide semiconductor film For example, wet etching is performed using a solution of phosphoric acid, acetic acid, and nitric acid. In this manner, unnecessary portions are removed to form the oxide semiconductor layer 133 (see FIG. 10A). The etching method used here is not limited to wet etching, but may be dry etching. Good too.

[0143] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0144] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0145] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0146] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0147] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium, etc. contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0148] In order to etch the desired shape, the etching conditions (etching Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0149] Next, heat treatment is performed on the oxide semiconductor layer 133 for dehydration or dehydrogenation. The conductor layer 133 is exposed to an inert gas atmosphere (nitrogen, helium, neon, argon, etc.) or After the heating treatment is performed under reduced pressure, the mixture is slowly cooled in an inert atmosphere.

[0150] Heat treatment is preferably performed at 200°C or higher. For example, heating at 450°C for 1 hour in a nitrogen atmosphere is recommended. The heat treatment in a nitrogen atmosphere reduces the resistance of the oxide semiconductor layer 133. (The carrier concentration is increased, preferably 1×10 18 / cm 3 or more), and the conductivity increases. As a result, a low-resistance oxide semiconductor layer 134 is formed (see FIG. 10B). The electrical conductivity of the semiconductor layer 134 is 1×10 -1 S / cm or more 1×10 2 S / cm or less is preferred It is nice.

[0151] Next, a conductive film 132 made of a metal material is formed on the oxide semiconductor layer 134 by sputtering or vacuum deposition. (See FIG. 10(C).)

[0152] The material of the conductive film 132 is an element selected from Al, Cr, Ta, Ti, Mo, and W, or or an alloy film containing the above elements or a combination of the above elements. do.

[0153] When a heat treatment is performed after the formation of the conductive film 132, the conductive film 132 is required to have a heat resistance sufficient to withstand the heat treatment. It is preferable to have the

[0154] Next, a third photolithography process is performed to form a resist mask and to form a The unnecessary portions are removed to form the source electrode layer 105a, the drain electrode layer 105b, and the second The terminal 122 is formed (see FIG. 10(D)). For example, the conductive film 132 is made of aluminum. When using a membrane or an aluminum alloy membrane, a solution of phosphoric acid, acetic acid, and nitric acid is used. In addition, ammonia hydrogen peroxide (H2O2:Ammonia hydrogen peroxide) can be used for etching. The conductive film 132 is etched by wet etching using a mixture of acetic acid, acetic acid, and water (5:2:2). The source and drain electrode layers 105a and 105b may be formed. In the process, the exposed region of the oxide semiconductor layer 134 is also partially etched, and the semiconductor layer 135 Therefore, the semiconductor layer 13 between the source electrode layer or the drain electrode layer 105a and the drain electrode layer 105b is 5 is a region with a thin film thickness. In FIG. 10(D), the source electrode layer or the drain electrode layer 105a, 105b, and the semiconductor layer 135 are etched at once by dry etching. In order to achieve this, the ends of the source and drain electrode layers 105a and 105b and the semiconductor layer 135 are consistent and have a continuous structure.

[0155] In addition, in this third photolithography process, the source electrode layer or the drain electrode layer 1 The second terminal 122 made of the same material as the terminals 105a and 105b is left in the terminal portion. 122 is a source wiring (a source electrode layer including the source and drain electrode layers 105a and 105b). The power supply is electrically connected to the power supply wiring.

[0156] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a photomask, the number of resist masks can be reduced, simplifying the process and reducing costs. Cost reduction is possible.

[0157] Next, the resist mask is removed, and the gate insulating layer 102, the oxide semiconductor layer 135, and the source electrode A protective insulating layer 107 is formed to cover the electrode layers 105a and 105b. The edge layer 107 is a silicon oxynitride film formed by the PCVD method. The exposed region and the protective layer of the oxide semiconductor layer 135 provided between the doped electrode layers 105a and 105b The silicon oxynitride film, which is the insulating layer 107, is provided in contact with the insulating layer 107. A region of the oxide semiconductor layer 135 in contact with the ×10 18 / cm 3 The semiconductor layer 103 having a highly resistive channel formation region is It is possible to form (see FIG. 11(A)).

[0158] Next, before the protective insulating layer 107 is formed, heat treatment may be performed in an oxygen atmosphere. The heat treatment may be performed at a temperature of 150° C. or higher and lower than 350° C. in an atmosphere containing oxygen.

[0159] Next, after the protective insulating layer 107 is formed, heat treatment may be performed. The heat treatment may be carried out in an air or nitrogen atmosphere at a temperature of 150° C. or higher and lower than 350° C. When this is done, the semiconductor layer 103 is heated in a state where it is in contact with the protective insulating layer 107. Furthermore, the semiconductor layer 103 is made to have a high resistance, thereby improving the electrical characteristics of the transistor and This heat treatment (preferably at 150°C or higher and less than 350°C) can reduce the variation. ) is not particularly limited as long as it is after the formation of the protective insulating layer 107, and may be performed in other steps, such as a resin film formation step. This process can be used in combination with the heat treatment for the deposition of the transparent conductive film and the heat treatment for reducing the resistance of the transparent conductive film, thereby reducing the number of processes. This can be done without increasing it.

[0160] Through the above steps, the thin film transistor 170 can be fabricated.

[0161] Next, a fourth photolithography process is performed to form a resist mask, and a protective insulating layer 10 7 and the gate insulating layer 102 are etched to form a contact that reaches the drain electrode layer 105b. Also, a hole 125 is formed by etching here, which reaches the second terminal 122. A contact hole 127 and a contact hole 126 reaching the first terminal 121 are also formed. The cross section at this stage is shown in Figure 11(B).

[0162] Next, the resist mask is removed, and then a transparent conductive film is formed. Indium oxide (In2O3) and indium tin oxide alloy (In2O3-SnO 2, ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is done with a hydrochloric acid based solution. However, etching of ITO in particular Residues are easily generated, so indium oxide zinc oxide alloy is used to improve etching processability. Gold (In2O3-ZnO) may also be used. In addition, a process for reducing the resistance of the transparent conductive film is When the heat treatment is performed, the resistance of the semiconductor layer 103 is increased, and the electrical characteristics of the transistor are improved. This can also serve as a heat treatment to reduce variations in electrical characteristics.

[0163] Next, a fifth photolithography process is performed to form a resist mask and to form a Then, unnecessary portions are removed to form the pixel electrode layer 110.

[0164] In addition, in this fifth photolithography process, the gate insulating layer 102 in the capacitance section The protective insulating layer 107 serves as a dielectric, and the capacitance wiring 108 and the pixel electrode layer 110 form a storage capacitance. is formed.

[0165] In the fifth photolithography process, the first terminal 121 and the second terminal 1 22 is covered with a resist mask, leaving the transparent conductive films 128 and 129 formed on the terminal portions. The conductive films 128 and 129 serve as electrodes or wiring for connection to an FPC. The transparent conductive film 128 formed on the gate electrode 121 is a connection electrode that functions as an input terminal of the gate wiring. The transparent conductive film 129 formed on the second terminal 122 serves as a terminal electrode of the source line. This is a connection terminal electrode that functions as an input terminal.

[0166] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The plan view at this stage corresponds to FIG.

[0167] 13(A1) and 13(A2) are plan views and diagrams of the gate line terminal portion at this stage. FIG. 13(A1) is a cross-sectional view taken along line C1-C2 in FIG. 13(A2). In FIG. 13(A1), a transparent insulating film 154 is formed on the protective insulating layer 154. The conductive film 155 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, a first terminal 151 made of the same material as the gate wiring and a source A connection electrode layer 153 made of the same material as the gate wiring is overlapped with the gate insulating layer 152. The transparent conductive film 155 provides electrical continuity. The portion where the first terminal 121 contacts the transparent conductive film 155 in FIG. 13(A1) is the portion where the first terminal 121 contacts the transparent conductive film 155 in FIG. This corresponds to the portion with which terminal 151 is in contact.

[0168] FIG. 13(B1) and FIG. 13(B2) are the source wiring terminal portion shown in FIG. 11(C). 13A and 13B show a plan view and a cross-sectional view of a different source wiring terminal portion, respectively. FIG. 13(B1) corresponds to a cross-sectional view taken along the line F1-F2 in FIG. 13(B2). In the above, the transparent conductive film 155 formed on the protective insulating layer 154 functions as an input terminal. In FIG. 13B1, the terminal portion is the same as the gate wiring. An electrode layer 156 made of the same material as the first terminal 150 is electrically connected to the source line. The electrode layer 156 is electrically connected to the second terminal 150 via the gate insulating layer 152. The electrode layer 156 is not electrically connected to the second terminal 150, and is set to a different potential, for example, a floating potential. If you set it to 0V, capacitance for noise prevention or static electricity prevention The second terminal 150 is connected to the protection insulating layer 154 via the It is electrically connected to the transparent conductive film 155 .

[0169] A plurality of gate lines, source lines, and capacitance lines are provided according to the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, The terminal 2 and the third terminal of the same potential as the capacitance wiring are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0170] In this way, five photolithography steps were performed using five photomasks to produce the bottom A pixel thin film having a thin film transistor 170 which is a gate-type staggered thin film transistor. The film transistor and storage capacitor can then be completed. By forming a pixel section by correspondingly arranging them in a matrix, an active matrix type It can be one of the substrates for manufacturing a display device. Such a substrate is called an active matrix substrate.

[0171] When manufacturing an active matrix type liquid crystal display device, an active matrix substrate A liquid crystal layer is provided between the active matrix substrate and a counter substrate having a counter electrode. The counter electrode is fixed to the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for

[0172] In addition, the capacitance wiring is not provided, and the pixel electrode is connected to the gate wiring, the protective insulating layer, and the gate A storage capacitor may be formed by stacking the layers with an insulating layer interposed therebetween.

[0173] In an active matrix type liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0174] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, resulting in image retention. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0175] In addition, the video characteristics are improved by increasing the normal vertical sync frequency by 1.5 times, preferably by more than twice the normal frequency. A driving technique called double speed driving may be used.

[0176] In addition, in order to improve the video characteristics of liquid crystal display devices, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. In addition, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched according to the timing of the optical modulation of the liquid crystal layer. The timing of the LEDs can also be synchronized. This is particularly useful when displaying images with a large proportion of black areas occupying the entire screen. This has the effect of reducing power consumption.

[0177] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the conventional method.

[0178] The n-channel transistor disclosed in this specification has an oxide semiconductor film as a channel formation region. These drive technologies can be combined due to their good dynamic characteristics. do.

[0179] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0180] In addition, when manufacturing a light-emitting display device, a partition using an organic resin layer is provided between each of the organic light-emitting elements. In that case, the organic resin layer is heated, so the semiconductor layer 103 is turned into a high resistance layer. This heat treatment improves the electrical characteristics of the transistor and reduces the variation in electrical characteristics. Can cum.

[0181] By forming the thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, the heat treatment for dehydration or dehydrogenation removes the moisture, which is an impurity, In order to reduce these and increase the purity of the oxide semiconductor film, the dew point in the film formation chamber has been lowered. Excellent electrical properties without using special sputtering equipment or ultra-high purity oxide semiconductor targets Therefore, a semiconductor device having a highly reliable thin film transistor can be manufactured.

[0182] Since the semiconductor layer in the channel formation region is a high resistance region, the electrical characteristics of the thin film transistor are This stabilizes the device and prevents an increase in the off-state current. This results in good electrical characteristics and reliability. It is possible to provide a semiconductor device having a thin film transistor with good performance.

[0183] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0184] (Embodiment 4) In a display device, which is an example of a semiconductor device, at least a part of a driver circuit and a An example of manufacturing a thin film transistor disposed in a pixel portion will be described below.

[0185] The thin film transistor disposed in the pixel portion is formed according to any one of the first to third embodiments. Since the thin film transistors shown in the first to third embodiments are n-channel TFTs, the Of these, a part of the driver circuit that can be configured with n-channel TFTs is a thin-film transistor in the pixel area. The transistor is formed on the same substrate.

[0186] FIG. 2 is a block diagram of an active matrix liquid crystal display device, which is an example of a semiconductor device. The display device shown in FIG. 20A is a display device having a display element on a substrate 5300. A pixel portion 5301 having a plurality of pixels, a scanning line driver circuit 5302 for selecting each pixel, and a signal line driver circuit 5303 for controlling input of a video signal to the pixel.

[0187] The pixel portion 5301 includes a signal line driver circuit 5303 and a plurality of signal lines arranged in a column direction. The signal line driver circuit 5303 is connected to the signal line driver circuit 5303 by lines S1 to Sm (not shown). A plurality of scanning lines G1 to Gn (not shown) are arranged extending from 5302 in the row direction. The scanning line driver circuit 5302 is connected to the signal lines S1 to Sm and the scanning lines G1 to Gn. The image sensor has a plurality of pixels (not shown) arranged in a matrix. Signal line Sj (any one of signal lines S1 to Sm), scanning line Gi (any one of scanning lines G1 to Gn) Either one of them is connected.

[0188] The thin film transistors described in any of the first to third embodiments are n-channel TFTs. A signal line driver circuit configured with a channel type TFT will be described with reference to FIG.

[0189] The signal line driver circuit shown in FIG. 21 includes a driver IC 5601 and a group of switches 5602_1 to 5602_56. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor It has a transistor 5603c.

[0190] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, and a third wiring 5613. and are connected to the wirings 5621_1 to 5621_M. 5602_M are a first wiring 5611, a second wiring 5612, a third wiring 561 3 and wiring 5621_1 to 5621_5 corresponding to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to the first A thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor For example, the wiring 5621 in the Jth column is connected to three signal lines via a resistor 5603c. _J (any one of the wirings 5621_1 to 5621_M) is a switch group 5602 The first thin film transistor 5603a, the second thin film transistor 5603b, and and the third thin film transistor 5603c, the signal line Sj-1, the signal line Sj, the signal line S j+1 is connected to

[0191] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0192] It is preferable that the driver IC 5601 is formed on a single crystal substrate. The switch group 5602_1 to 5602_M is formed on the same substrate as the pixel section. Therefore, the driver IC 5601 and the switch group 5602_1 to 5602_ It is recommended to connect to M via an FPC or similar.

[0193] Next, the operation of the signal line driver circuit shown in FIG. 21 will be described with reference to the timing chart of FIG. The timing chart in FIG. 22 is explained with reference to the timing chart in FIG. Further, during the selection period of the i-th scanning line Gi, is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, when a scanning line of another row is selected, the signal line driver circuit of FIG. In this case, the same operation as in FIG. 22 is performed.

[0194] In the timing chart of FIG. 22, the wiring 5621_J in the Jth column is connected to the first thin-film transistor. a second thin film transistor 5603b, and a third thin film transistor 560 When connected to signal line Sj-1, signal line Sj, and signal line Sj+1 via 3c It shows.

[0195] In the timing chart of FIG. 22, the timing when the i-th scanning line Gi is selected, The on / off timing 5703a of the first thin film transistor 5603a, The on / off timing 5703b of the third thin film transistor 56 The on / off timing of 03c is input to 5703c and the wiring 5621_J of the Jth row. 5 shows signal 5721_J.

[0196] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the first sub-selection period T2 and the third sub-selection period T3, different video signals are input. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is The signal is input to the signal line Sj-1 and is input to the wiring 5621_J in the second sub-selection period T2. The video signal to be output is input to the signal line Sj, and the line 5621 is connected to the line Sj during the third sub-selection period T3. The video signal input to the first sub-selection period is input to the signal line Sj+1. In the period T1, the second sub-selection period T2, and the third sub-selection period T3, the wiring 5621_ The video signals input to J are Data_j-1, Data_j, and Data_j+ Let's say it's 1.

[0197] As shown in FIG. 22, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c At this time, Data_j-1 input to the wiring 5621_J is turned off. The signal is input to the signal line Sj-1 via the transistor 5603a. Second sub-selection period T2 In this case, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a is turned on. and the third thin film transistor 5603c are turned off. At this time, the input The Data_j to be output is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first The first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the third thin film transistor 56 03c and input to the signal line Sj+1.

[0198] From the above, the signal line driver circuit in FIG. 21 can achieve the following by dividing one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the pixel area is formed and the substrate on which the pixel area is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0199] As shown in FIG. 21, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, the arrangement, number, driving method, etc. of the thin film transistors are not limited.

[0200] For example, three or more signal lines are connected to one wiring during each of three or more sub-selection periods. When a video signal is input to each of them, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two or It is preferably divided into three sub-selection periods.

[0201] As another example, as shown in the timing chart of FIG. 23, one selection period is precharged. The first sub-selection period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T 3. Furthermore, in the timing chart of FIG. 23, the scanning line Gi of the i-th row is selected. the timing at which the first thin film transistor 5603a is turned on and off; 03a, the on / off timing 5803b of the second thin film transistor 5603b, The on / off timing 5803c of the thin film transistor 5603c and the wiring 5 23. As shown in FIG. 23, the pre-channel 5821_J is input to the pre-channel 621_J. During the transition period Tp, the first thin film transistor 5603a and the second thin film transistor 56 At this time, the wiring 5621_J and the third thin film transistor 5603b are turned on. The precharge voltage Vp input to the first thin film transistor 5603a and the second thin film transistor and the third thin film transistor 5603c are connected to the signal line S j-1, signal line Sj, and signal line Sj+1. The first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor At this time, the thin film transistor 5603c is turned off. ata_j-1 is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first The first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the second thin film transistor 5603 In the third sub-selection period T3, the third thin-film transistor The first thin film transistor 5603a and the second thin film transistor 5603c are turned on. At this time, Data_j+1 input to the wiring 5621_J is , and is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0202] From the above, the signal line driver circuit of FIG. 21 to which the timing chart of FIG. 23 is applied By providing a precharge period before the selection period, the signal line can be precharged. Therefore, the video signal can be written to the pixel at high speed. 22 are shown with the same reference numerals, and the same parts or parts having similar functions are shown. A detailed description of the relevant parts will be omitted.

[0203] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit has a shift register. If necessary, the scanning line driving circuit may include a level shifter, a buffer, a switch, etc. In the scanning line driver circuit, the shift register may be formed as a single unit. When a clock signal (CLK) and a start pulse signal (SP) are input to the register, The generated selection signal is buffered and amplified in a buffer. The gate electrodes of the transistors of the pixels for one line are connected to the corresponding scanning lines. Then, the transistors of the pixels in one line must be turned on at the same time. Therefore, a buffer capable of passing a large current is used.

[0204] One form of a shift register used as a part of a scanning line driving circuit is shown in FIG. 24 and FIG. 25. He explains.

[0205] The circuit configuration of the shift register is shown in Figure 24. The shift register shown in Figure 24 is a flip-flop. It is composed of multiple flip-flops 5701_1 to 5701_n. A first clock signal, a second clock signal, a start pulse signal, and a reset signal are input. It works as it is.

[0206] The connection relationship of the shift register in Fig. 24 will be described. The shift register in Fig. 24 has i-stage The first flip-flop 5701_i (flip-flops 5701_1 to 5701_n In either one of them, the first wiring 5501 shown in FIG. 25 is connected to the seventh wiring 5717_i-1. 25 is connected to the seventh wiring 5717_i+1. 25 is connected to the seventh wiring 5717_i, The sixth wiring 5506 is connected to the fifth wiring 5715 .

[0207] In addition, the fourth wiring 5504 shown in FIG. 25 corresponds to the second wiring in the odd-numbered flip-flops. 5712, and in the even-numbered flip-flops, it is connected to the third wiring 5713. The fifth wiring 5505 shown in FIG.

[0208] However, the first wiring 5501 shown in FIG. 25 of the first-stage flip-flop 5701_1 is 25 of the n-th flip-flop 5701_n in the n-th stage. The second wiring 5502 is connected to the sixth wiring 5716 .

[0209] The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 are respectively connected to the first power supply line and the third power supply line. This may also be called the power line 2.

[0210] Next, the details of the flip-flop shown in FIG. 24 are shown in FIG. The flip-flop includes a first thin film transistor 5571, a second thin film transistor 5572, A third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor a sixth thin film transistor 5575, a seventh thin film transistor 5576, and and an eighth thin film transistor 5578. A second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor a fifth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel A transistor in which the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). When this occurs, the device is in a conductive state.

[0211] Next, the connection configuration of the flip-flop shown in FIG. 24 will be described below.

[0212] A first electrode (either a source electrode or a drain electrode) of the first thin film transistor 5571 is connected to a fourth wiring 5504, and a second electrode (source) of the first thin film transistor 5571 is connected to The other of the source electrode and the drain electrode is connected to a third wiring 5503 .

[0213] A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506. A second electrode of the thin film transistor 5572 is connected to a third wiring 5503 .

[0214] A first electrode of the third thin film transistor 5573 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5573 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. will be done.

[0215] A first electrode of the fourth thin film transistor 5574 is connected to a sixth wiring 5506. The second electrode of the thin film transistor 5574 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5 It is connected to the gate electrode of 571.

[0216] A first electrode of the fifth thin film transistor 5575 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5575 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501. will be done.

[0217] A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5576 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5 It is connected to the gate electrode of 572.

[0218] A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. The second electrode of the eighth thin film transistor 5578 is connected to the gate of the second thin film transistor 5572. The gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550. Connected to 1.

[0219] The gate electrode of the first thin film transistor 5571 and the gate electrode of the fourth thin film transistor 5574 the gate electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor The connection point of the second electrode of the seventh thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 is Further, the gate electrode of the second thin film transistor 5572, the gate electrode of the third thin film transistor 5543, a second electrode of the fourth thin film transistor 5573; a second electrode of the fourth thin film transistor 5574; The gate electrode of the sixth thin film transistor 5576 and the gate electrode of the eighth thin film transistor 5578 The connection point of the two electrodes is designated as node 5544.

[0220] The first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5504 are 504 are referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 may be connected to a first power supply line, and the sixth wiring 5506 may be connected to a second power supply line. It may also be called a line.

[0221] In addition, the signal line driver circuit and the scanning line driver circuit are formed using the n-channel TF The n-channel TFTs shown in the first to third embodiments can be fabricated using only T. Since the mobility of the transistor is large, it is possible to increase the driving frequency of the driving circuit. In addition, since the parasitic capacitance of the n-channel TFT shown in any of the first to third embodiments is reduced, For example, the n-channel T The scanning line driver circuit using FT can operate at high speed, so the frame frequency can be It is also possible to increase the image quality or to insert a black screen.

[0222] Furthermore, the channel width of the transistor of the scanning line driving circuit is increased, and multiple scanning lines By arranging the driver circuit, it is possible to achieve even higher frame frequencies. When multiple scanning line driving circuits are arranged, a scanning line driving circuit for driving the even-numbered scanning lines is provided. The circuit is placed on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is placed on the opposite side. By placing multiple If signals are output to the same scanning line by the scanning line driving circuit, it is advantageous for making the display device larger. do.

[0223] In addition, when an active matrix type light emitting display device, which is an example of a semiconductor device, is manufactured, In order to arrange at least a plurality of thin film transistors in one pixel, a plurality of scanning line driving circuits are arranged. An example of a block diagram of an active matrix type light emitting display device is shown in FIG. 0(B).

[0224] The light-emitting display device shown in FIG. 20B has a plurality of pixels each having a display element over a substrate 5400. A pixel portion 5401 for selecting each pixel, a first scanning line driver circuit 5402 for selecting each pixel, and a second scanning line driver circuit 5403 for selecting each pixel. A driver circuit 5404 and a signal line driver circuit 5405 for controlling the input of a video signal to a selected pixel 403.

[0225] In the case where a video signal input to a pixel of the light-emitting display device shown in FIG. 20(B) is in a digital format, When a pixel is turned on, the transistor is switched on and off to make it either emitting light or not. Therefore, gray scale display can be performed using area gray scale or time gray scale. The stacked gray scale method divides one pixel into multiple sub-pixels, and each sub-pixel is independently driven based on a video signal. The time gray scale method is a driving method that displays gray scales by changing the time when the pixel emits light. This is a driving method that displays gradations by controlling the period during which the liquid crystal display is turned on.

[0226] Light-emitting elements have a higher response speed than liquid crystal elements, so they are more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, the light emitting element of the pixel is divided into sub-frame periods according to the video signal. By dividing the period into multiple subframes, The total length of time that pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0227] In the light-emitting display device shown in FIG. 20B, two switching TFTs are provided for one pixel. When the first scanning line, which is the gate wiring of one of the switching TFTs, is used as the first scanning line, The signal to be transmitted is generated by the first scanning line driver circuit 5402 and is input to the gate of the other switching TFT. A signal to be input to the second scanning line, which is a transmission wiring, is generated by a second scanning line driver circuit 5404. The example shows a signal input to the first scanning line and a signal input to the second scanning line. The signal and the signal may be generated by one scanning line driving circuit. The operation of the switching element is controlled by the number of switching TFTs that a pixel has. In some cases, each pixel may have a plurality of scanning lines. The signals input to the lines may all be generated by one scanning line driver circuit, or may be generated by a plurality of scanning lines. It may be generated by the drive circuit.

[0228] In addition, in the light-emitting display device, the driver circuit may be configured with n-channel TFTs. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit are formed by using the n-channel TFTs shown in the embodiments 1 to 3. It is also possible to produce it using only FT.

[0229] The above-mentioned driving circuit is not limited to liquid crystal display devices and light-emitting display devices, but may also be used in devices with switching elements and It may also be used in electronic paper, where electrically connected elements are used to drive electronic ink. Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. It is easy to read, consumes less power than other display devices, and can be made thin and light. It has advantages.

[0230] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0231] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. No polarizers are required for the display, reducing weight.

[0232] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0233] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by using transistors can be used.

[0234] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0235] Through the above steps, a display device with high reliability as a semiconductor device can be manufactured.

[0236] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0237] (Embodiment 5) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. It is possible to manufacture a semiconductor device (also called a display device) having a display function. The transistors and part or the entire driver circuit are integrated on the same substrate as the pixel section, An on-panel can be formed.

[0238] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0239] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a means for supplying a current to the display element in each of the plurality of pixels. The display element may be in a state where only the pixel electrodes of the display element are formed, or a conductive film that becomes the pixel electrodes may be formed. may be in a state after the formation of a film and before etching to form a pixel electrode, All forms apply.

[0240] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0241] The appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIG. 16(A1) and 16(A2) show the third embodiment formed on a first substrate 4001. The highly reliable thin film transistors 4010 and 4011 each including an oxide semiconductor layer shown in The liquid crystal element 4013 is disposed between the first substrate 4001 and the second substrate 4006 with a sealant 400. FIG. 16(B) is a plan view of the panel sealed with the adhesive agent 5, and FIG. 16(A1) and (A2) are similar to those of FIG. This corresponds to a cross-sectional view at MN.

[0242] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0243] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 16A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0244] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 16B, the thin film transistor included in the pixel portion 4002 A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4020 and 4021 are formed on the thin film transistors 4010 and 4011. 1 is provided.

[0245] The thin film transistors 4010 and 4011 are the signal transistors including the oxide semiconductor layer described in Embodiment 3. In addition, a highly reliable thin film transistor can be applied. In this embodiment, the thin film transistor shown in FIG. 4010 and 4011 are n-channel thin film transistors.

[0246] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0247] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Alternatively, you can use aluminum foil with a PVF film or polyester film. A sheet having a structure sandwiched between films can also be used.

[0248] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 40 to the conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0249] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0250] In addition to the transmissive LCD, the present invention can also be applied to reflective and semi-transmissive LCDs. can.

[0251] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In the example shown, the polarizing plate is disposed on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the coloring layer is not limited to the present embodiment, and the materials and The conditions may be appropriately set according to the manufacturing process conditions. A light film may also be provided.

[0252] In addition, in order to reduce the surface unevenness of the thin film transistor and to improve the reliability of the thin film transistor, In order to improve the characteristics of the thin film transistor obtained in the above embodiment, The insulating layer 4020 and the insulating layer 4021 are used to cover the insulating film 4010 and the insulating film 4021. The protective film is designed to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor suspended in the air. The protective film is preferably a silicon oxide film or a nitride film formed by sputtering. Silicon film, silicon oxynitride film, silicon oxynitride film, aluminum oxide film, aluminum nitride film, The aluminum oxide nitride film or the aluminum nitride oxide film may be formed as a single layer or a multilayer. Although an example of forming the protective film by sputtering is shown, the method is not particularly limited and may be formed by various methods. good.

[0253] Here, an insulating layer 4020 having a laminated structure is formed as a protective film. A silicon oxide film is formed by sputtering as the first layer of the 0. Silicon oxide film as a protective film By using the above, it is possible to prevent hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. It is effective in stopping.

[0254] In addition, an insulating layer is formed as the second layer of the protective film. The second layer is a silicon nitride film formed by sputtering. When the TFT is turned on, mobile ions such as sodium penetrate into the semiconductor region and change the electrical properties of the TFT. This can prevent the problem from occurring.

[0255] After forming the protective film, the protective film is heated in a nitrogen atmosphere or in air (at 300°C or less). (below) may also be performed.

[0256] In addition, an insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. are used. In addition, by stacking a plurality of insulating films made of these materials, an insulating layer can be formed. 4021 may be formed.

[0257] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0258] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed by using a fcoater or the like. By using both, a semiconductor device can be manufactured efficiently.

[0259] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0260] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0261] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0262] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0263] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0264] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0265] In FIG. 16, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0266] FIG. 26 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed herein. 1 shows an example in which a liquid crystal display module is configured as a semiconductor device.

[0267] FIG. 26 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0268] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0269] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0270] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0271] (Embodiment 6) An example of the semiconductor device is electronic paper.

[0272] Electronic paper that uses switching elements and elements that are electrically connected to drive electronic ink It may also be used for.

[0273] Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. The advantages are ease of reading, lower power consumption compared to other display devices, and the possibility of making them thin and lightweight. It has points.

[0274] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0275] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0276] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0277] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by using transistors can be used.

[0278] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0279] FIG. 15 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in the embodiment mode 1. The thin film transistor can be fabricated in the same manner as the conventional thin film transistor, and is highly reliable, including an oxide semiconductor layer. The thin film transistor shown in the second or third embodiment is also the thin film transistor 5 of this embodiment. It can also be applied as 81.

[0280] The electronic paper in FIG. 15 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0281] The thin film transistor 581 is a bottom-gate thin film transistor. The source electrode layer or the drain electrode layer of the thin film transistor 581 is covered with an insulating film 583. The electrode layer is in contact with the first electrode layer 587 through an opening formed in the insulating film 583 and the insulating layer 585. The first electrode layer 587 and the second electrode layer 588 are electrically connected to each other. 590a and white area 590b, and a cavity 594 surrounded by a liquid. The spherical particles 589 are surrounded by a filler 595 such as a resin. The first electrode layer 587 corresponds to a pixel electrode, and the second electrode The second electrode layer 588 corresponds to a common electrode. The common connection portion is electrically connected to a common potential line provided on one substrate 580. A second electrode layer 588 is connected to the second electrode layer 588 through conductive particles disposed between the substrate 580 and the substrate 596. It is possible to electrically connect to a potential line.

[0282] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display, the image that was displayed can be retained. Therefore, a semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0283] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0284] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0285] (Embodiment 7) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that uses electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0286] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0287] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0288] FIG. 18 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0289] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0290] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 64 has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate.

[0291] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0292] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as follows: A capacitance may be formed between the gate electrode and the second electrode.

[0293] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is The driving transistor 6402 is in two states, either fully on or fully off. A video signal is inputted, that is, the driving transistor 6402 is operated in a linear region. In order to operate the driving transistor 6402 in a linear region, the voltage of the power supply line 6407 must be higher than that of the driving transistor 6402. A high voltage is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied.

[0294] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 18 can be used.

[0295] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 plus the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. In addition, the video transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The gate potential of the light emitting element 6402 is set higher than that of the gate of the transistor 6403. Analog gradation drive can be performed by passing a current corresponding to a video signal through 6404.

[0296] Note that the pixel configuration shown in FIG. 18 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0297] Next, the configuration of the light emitting element will be described with reference to FIG. 19. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figure 19(A), (B), and (C). The driving TFTs used in the semiconductor device, TFTs 7001, 7011, and 7021, are The thin film transistor can be fabricated in the same manner as in the first embodiment, and has high reliability including an oxide semiconductor layer. In addition, the thin film transistor shown in the second embodiment or the third embodiment The photodiode can also be applied as TFT7001, 7011, or 7021.

[0298] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light-emitting elements with a double-sided emission structure that emits light from the side of the pixel. The present invention can also be applied to optical elements.

[0299] A light emitting element having a top emission structure will be described with reference to FIG.

[0300] In FIG. 19A, a TFT 7001 which is a driving TFT is an n-type TFT, and a light emitting element 7002 emits light. FIG. 19(A) shows a cross-sectional view of a pixel when the light incident on the pixel exits the anode 7005 side. A cathode 7003 of a light emitting element 7002 and a TFT 7001 which is a driving TFT are electrically connected. A light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. 7003 uses various materials as long as they have a small work function and are conductive films that reflect light. For example, Ca, Al, MgAg, AlLi, etc. are preferable. 004 may be composed of a single layer or may be composed of multiple layers stacked together. In the case where the cathode 7003 is composed of multiple layers, an electron injection layer, an electron transport layer, and a The light-transmitting layer, the light-emitting layer, the hole-transporting layer, and the hole-injecting layer are laminated in this order. The anode 7005 is formed using a light-transmitting conductive material. For example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Lead oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, and silicon oxide are added. A light-transmitting conductive film such as doped indium tin oxide may be used.

[0301] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 19(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0302] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. When 011 is an n-type light emitting element and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, FIG. 19B shows a cross-sectional view of a pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. When the anode 15 has a light-transmitting property, a shielding layer for reflecting or blocking light is provided so as to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 19(A), even if it is composed of a single layer, multiple layers are laminated. The anode 7015 does not need to transmit light, but as shown in FIG. As in the case of 19(A), the insulating film 19 can be formed using a light-transmitting conductive material. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment may be used.

[0303] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 19B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0304] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In this example, a conductive film 7027 having a light-transmitting property and electrically connected to the driving TFT 7021 is formed on the substrate 7022. A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023. The anode 7025 is laminated in order. The cathode 7023 is, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be configured as a single layer or as a laminate of multiple layers. 25 is formed using a conductive material having a light transmitting property, similar to FIG. It is possible.

[0305] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 19C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0306] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0307] In addition, the thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically However, a current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the input / output terminals are connected to each other.

[0308] The semiconductor device is not limited to the configuration shown in FIG. 19, and may be any of the configurations disclosed in this specification. Various modifications based on the technical concept are possible.

[0309] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 17(A). FIG. 17 shows a thin film formed on a first substrate. A panel in which the film transistor and the light emitting element are sealed between the second substrate and the film transistor and the light emitting element by a sealant. 17(B) is a plan view of the above-mentioned embodiment, and FIG. 17(B) is a cross-sectional view taken along line HI of FIG. 17(A).

[0310] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0311] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 17B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0312] The thin film transistors 4509 and 4510 are the signal transistors including the oxide semiconductor layer described in Embodiment 3. In addition, a highly reliable thin film transistor can be applied. The thin film transistors 4509 and 4510 may be n It is a channel type thin film transistor.

[0313] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown in the figure. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0314] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0315] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0316] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon oxynitride film, DLC film, etc. can be formed.

[0317] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0318] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0319] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0320] The second substrate 4506 located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or A light-transmitting material such as an acrylic film is used.

[0321] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0322] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0323] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0324] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0325] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0326] (Embodiment 8) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train rides, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 27.

[0327] FIG. 27 shows an example of an electronic book 2700. For example, the electronic book 2700 has a housing 2 The device is made up of two housings, housing 2701 and housing 2703. 03 is integrated with an axis portion 2711, and performs opening and closing operations around the axis portion 2711. This configuration makes it possible to operate like a paper book. .

[0328] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 27) and An image can be displayed on the display unit 2707 in FIG.

[0329] FIG. 27 shows an example in which a housing 2701 is provided with an operation unit and the like. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a display board, a pointing device, etc. On the front side, there is a terminal for external connection (earphone terminal, USB terminal, or AC adapter and USB cable). A terminal that can be connected to various cables such as a USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. Good too.

[0330] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0331] (Embodiment 9) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0332] FIG. 28A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In addition, the stand 9605 supports the housing 9601. This shows a configuration in which the above is supported.

[0333] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0334] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0335] FIG. 28B shows an example of a digital photo frame 9700. The photo frame 9700 includes a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example images captured by a digital camera. By displaying the image data, it can function like a normal photo frame.

[0336] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0337] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0338] FIG. 29(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 29(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and may be at least as described in the present specification. The present invention is not limited to the above, and may be applied to any configuration having the semiconductor device disclosed in the above and other auxiliary equipment. The portable game machine shown in FIG. 29(A) can be used to play a game recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 29(A) has the following functions: The functions are not limited to these, and various functions can be provided.

[0339] FIG. 29(B) shows an example of a slot machine 9900, which is a large-scale gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. The Machine 9900 also includes other operating means such as a start lever and stop switch, coin The slot machine 9900 is equipped with a slot slot, a speaker, etc. However, the present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in this specification. , and other auxiliary equipment may be provided as appropriate.

[0340] FIG. 30A is a perspective view showing an example of a portable computer.

[0341] The portable computer of FIG. 30(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display unit 9303 and a keyboard. The lower housing 9302 having the base 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to type on the keyboard, the hinge unit needs to be opened. The user can perform input operations by looking at the display portion 9303.

[0342] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the touch panel. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the USB communication standard is inserted. There are.

[0343] The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301. 07, it is possible to realize a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display unit.

[0344] The display unit 9303 or the foldable display unit 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses an image display device such as a light-emitting display panel using inorganic light-emitting elements.

[0345] The portable computer shown in FIG. 30A is configured with a receiver and the like, and is also a television. It is possible to receive broadcasts and display images on the display unit or the display unit. The hinge unit connecting the display unit 9301 and the lower housing 9302 is closed. 7. Slide the screen to expose the entire screen, and adjust the screen angle to watch TV broadcasts. In this case, the hinge unit can be opened to display the display unit 9303. Furthermore, it only activates the circuits that display TV broadcasts, so it consumes minimal power. This is useful for portable computers with limited battery capacity. do.

[0346] FIG. 30(B) shows a portable electronic device that can be worn on the user's arm like a wristwatch. FIG. 13 is a perspective view showing an example of a story.

[0347] This mobile phone is a main body having at least a communication device having a telephone function and a battery. A band for attaching the body to the arm, and an adjustment unit 92 for adjusting the state of fixation of the band to the arm 05, it is composed of a display unit 9201, a speaker 9207, and a microphone 9208.

[0348] The main body also has an operation switch 9203, which serves as a power input switch and a display switching switch. In addition to the camera start switch and the image capture start switch, there is also a button that starts an Internet program when pressed. Each function can be assigned to a switch.

[0349] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 30(B) shows a display button 9202 displayed on a display unit 9201. Input can be made by touching the screen with a finger or other object.

[0350] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0351] The mobile phone shown in FIG. 30(B) is equipped with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory, etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0352] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 30(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0353] Although FIG. 30B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around.

[0354] (Embodiment 10) In this embodiment, an example in which some steps are different from those in the first embodiment is shown. After the formation of the source electrode layer or drain electrode layer 405a, 405b, heating for dehydration or dehydrogenation is performed. An example of the process is shown in Fig. 31. Note that the same parts as in Fig. 6 will be described using the same reference numerals.

[0355] As in the first embodiment, a gate electrode layer 401 and a gate insulator layer 402 are formed on a substrate 400 having an insulating surface. An insulating layer 402 and an oxide semiconductor layer 430 are formed (see FIG. 31A).

[0356] The source and drain electrode layers 405a and 405b are formed over the oxide semiconductor layer 430. Then, a part of the oxide semiconductor layer 430 is etched to form an oxide semiconductor layer 441 (FIG. 31 See (B). ).

[0357] Next, the oxide semiconductor layer 441 and the source and drain electrode layers 405a and 405b are Under inert gas atmosphere (nitrogen, helium, neon, argon, etc.) or reduced pressure By this heat treatment, the oxide semiconductor layer 441 is dehydrated. The resistance of the oxide semiconductor layer 432 is reduced by thermal treatment or dehydrogenation. (See FIG. 31C). Note that the source or drain electrode layer 405a The material of 405b is a material that can withstand the heat treatment here, such as tungsten, molybdenum, etc. It is preferable to use the following.

[0358] After the heat treatment and slow cooling, the oxide semiconductor layer 432 was contacted with The oxide insulating film 407 is formed by sputtering or PCVD. An oxide insulating film 407 is formed on the oxide semiconductor layer 432 by a sputtering method or a PCVD method. When the oxide insulating film 407 is formed, the resistance of the oxide semiconductor layer 432 is reduced. The area in contact with the substrate is made highly resistive (the carrier concentration is reduced, preferably to 1×10 18 / cm 3 less than , and more preferably 1×10 14 / cm 3 (hereinafter) to form a high-resistance oxide semiconductor region. Therefore, the oxide semiconductor layer 432 can be a semiconductor having a high-resistance oxide semiconductor region. This becomes a layer 403 (a third oxide semiconductor layer), and a thin film transistor 470 can be manufactured. (See Figure 31(D)).

[0359] By performing the heat treatment for the dehydration treatment or the dehydrogenation treatment, After reducing impurities (H2O, H, OH, etc.) contained in the crystal and increasing the carrier concentration, the crystal is slowly cooled. After the oxide semiconductor layer is cooled slowly, an oxide insulating film is formed in contact with the oxide semiconductor layer. The carrier concentration of the conductor layer can be reduced, and the reliability of the thin film transistor 470 can be improved. do.

[0360] In addition, this embodiment mode can be freely combined with the first embodiment mode.

[0361] (Embodiment 11) A semiconductor device and a manufacturing method thereof will be described with reference to FIG. The parts or parts having similar functions and steps can be performed in the same manner as in embodiment 1, A repeated explanation will be omitted.

[0362] The thin film transistor 471 shown in FIG. In this example, a conductive layer 409 is provided so as to overlap with the insulating film.

[0363] 32 is a cross-sectional view of a thin film transistor 471 included in the semiconductor device. 471 is a bottom gate type thin film transistor, and 472 is a substrate having an insulating surface. 00, a gate electrode layer 401, a gate insulating layer 402, a semiconductor layer 403, and a source electrode The conductive layer 409 includes a gate electrode layer 405a, a drain electrode layer 405b, and a conductive layer 409. The second electrode layer 402 is provided over the oxide insulating film 407 so as to overlap with the second electrode layer 401 .

[0364] The conductive layer 409 is a gate electrode layer 401, a source electrode layer or a drain electrode layer 405a, It can be formed by using the same material and method as 5b. When a pixel electrode layer is provided, The conductive layer 409 may be formed using the same material and method as the electrode layer. A stack of a titanium film, an aluminum film, and a titanium film is used as the insulating film.

[0365] The conductive layer 409 may have a potential equal to or different from that of the gate electrode layer 401. The conductive layer 409 can also function as a gate electrode layer of the floating gate electrode 402. It may be in a state.

[0366] By providing the conductive layer 409 in a position overlapping with the semiconductor layer 403, In the bias-thermal stress test (hereinafter referred to as BT test) to check the reliability, The change in the threshold voltage of the thin film transistor 471 before and after the T test can be reduced. In particular, after the substrate temperature is raised to 150°C, the voltage applied to the gate is set to -20V. This makes it possible to suppress the fluctuation of the threshold voltage in the BT test.

[0367] This embodiment mode can be freely combined with the first embodiment mode.

[0368] (Embodiment 12) A semiconductor device and a manufacturing method thereof will be described with reference to FIG. The parts or parts having similar functions and steps can be performed in the same manner as in embodiment 1, A repeated explanation will be omitted.

[0369] The thin film transistor 472 shown in FIG. A conductive layer 419 is provided so as to overlap with the insulating region with the oxide insulating film 407 and the insulating layer 410 interposed therebetween. This is an example.

[0370] 33 is a cross-sectional view of a thin film transistor 472 included in the semiconductor device. 472 is a bottom gate type thin film transistor, and 473 is a substrate having an insulating surface. 00, a gate electrode layer 401, a gate insulating layer 402, a semiconductor layer 403, a source region or The drain regions 404a and 404b and the source or drain electrode layers 405a and 405b are 05b includes a conductive layer 419. The conductive layer 419 is formed by depositing an oxide film on the gate electrode layer 401. The insulating layer 407 is disposed on the insulating film 410 .

[0371] In this embodiment, an insulating layer 410 functioning as a planarizing film is stacked over the oxide insulating film 407. The oxide insulating film 407 and the insulating layer 410 are formed on the source or drain electrode layer 405b. An opening is formed in the insulating layer 410, the oxide insulating film 407, and the insulating layer 410. A conductive film is formed in the opening and etched into a desired shape to form the conductive layer 419 and the pixel electrode layer 41 In this manner, the pixel electrode layer 411 is formed by using the same material and method. In this embodiment mode, the pixel electrode layer 411 and the conductive layer 419 can be formed. The layer 419 is an indium oxide tin oxide alloy containing silicon oxide (In-Sn -O-based oxides) are used.

[0372] The conductive layer 419 is formed on the gate electrode layer 401 and the source or drain electrode layer 405a. , 405b may be formed using the same material and method.

[0373] The conductive layer 419 may have a potential equal to or different from that of the gate electrode layer 401. The conductive layer 419 can also function as a gate electrode layer of the floating gate electrode 414. It may be in a state.

[0374] By providing the conductive layer 419 in a position overlapping with the semiconductor layer 403, In the bias-thermal stress test (hereinafter referred to as BT test) to check the reliability, The change in the threshold voltage of the thin film transistor 472 before and after the T test can be reduced. Cut.

[0375] This embodiment mode can be freely combined with the first embodiment mode.

[0376] (Embodiment 13) In this embodiment, an example of a channel stop type thin film transistor 1430 will be described with reference to FIG. 4(A), 34(B) and 34(C). Also, FIG. 34(C) shows a thin film transistor. The cross-sectional view taken along the chain line Z1-Z2 in the figure is shown in Figure 34(B). In addition, the oxide semiconductor layer of the thin film transistor 1430 is formed of an oxide semiconductor material that does not contain gallium. An example using a solid semiconductor material is shown below.

[0377] In FIG. 34A, a gate electrode layer 1401 is provided on a substrate 1400. An oxide semiconductor layer is formed on a gate insulating layer 1402 that covers the gate electrode layer 1401 .

[0378] In this embodiment, a Sn-Zn-O oxide semiconductor layer is formed by sputtering. By not using gallium in the oxide semiconductor layer, expensive target This reduces costs because it is not necessary to use a kit.

[0379] Immediately after the oxide semiconductor film is formed or after the oxide semiconductor film is patterned, the oxide semiconductor film is dehydrated or dehydrated. Perform elementalization.

[0380] For dehydration or dehydrogenation, use an inert gas atmosphere (nitrogen, helium, neon, Heat treatment is performed under argon or reduced pressure, and then cooled slowly in an inert atmosphere. The heat treatment is carried out at a temperature of 200°C to 600°C, preferably 400°C to 450°C. The oxide semiconductor layer is formed by heat treatment in an inert gas atmosphere or under reduced pressure and then slowly cooled. , low resistance (high carrier concentration, preferably 1×10 18 / cm 3 or more) and low resistance The oxide semiconductor layer 1403 can be formed by etching (see FIG. 34A).

[0381] Next, a channel protective layer 1418 is provided over and in contact with the oxide semiconductor layer 1403. By providing the oxide semiconductor protective layer 1418, Damage during the process (film loss due to plasma or etching agent during etching, etc.) Therefore, the reliability of the thin film transistor 1430 can be improved. can.

[0382] After the dehydration or dehydrogenation, the channel protection layer 141 is continuously formed without being exposed to the air. By continuously treating the film without exposing it to air, the interface It can be contaminated by atmospheric components such as water and hydrocarbons, or by impurities suspended in the air. Since each lamination interface can be formed without any trouble, the variation in thin-film transistor characteristics is reduced. It is possible.

[0383] In addition, a method such as sputtering or PCVD is applied to the oxide semiconductor layer 1403 having a low resistance. When the channel protection layer 1418, which is an oxide insulating film, is formed, the resistance of the oxide semiconductor is reduced. At least the region of the dielectric layer 1403 in contact with the channel protection layer 1418 is made highly resistive (capacitor). The rear concentration is reduced, preferably to 1×10 18 / cm 3 less than 1×10 1 4 / cm 3 A high-resistance oxide semiconductor region can be obtained by the above-described process. During the process, heating in an inert gas atmosphere (or reduced pressure), slow cooling, and the formation of the oxide insulating film It is important to increase or decrease the carrier concentration in the oxide semiconductor layer by, for example, the composition of the oxide semiconductor layer.

[0384] The channel protection layer 1418 is made of an inorganic material containing oxygen (silicon oxide, silicon oxynitride, nitride, etc.). The material used for the thin film is silicon oxide. The method of fabrication is plasma CVD or thermal CVD. The channel protection layer 1418 can be formed by a vapor deposition method or a sputtering method such as After the film is formed, the shape is processed by etching. Here, the silicon oxide film is formed by sputtering. The channel is formed by etching using a photolithographic mask. A protective layer 1418 is formed.

[0385] Next, n + Layer 1406a, 1 In this embodiment, the n-type semiconductor layer 406b serving as a source region or a drain region is formed. + The layers 1406a and 1406b are Al-Zn-O-based non-single crystal films, and the oxide semiconductor layer 1 The oxide semiconductor layer 403 is formed under different deposition conditions from those of the oxide semiconductor layer 403 and has a lower resistance. Also, n + The layers 1406a and 1406b are nitrogen-containing Al-Zn-O-based non-single crystal films. That is, an Al-Zn-ON non-single crystal film (also called an AZON film) may be used.

[0386] Next, n + On the layer 1406a, source electrode layers 1405a, + Drain on layer 1406b An electrode layer 1405b is formed on each of the electrodes to fabricate a thin film transistor 1430 (FIG. 34(B) The source electrode layer 1405a and the drain electrode layer 1405b are made of Al, Cr, Ta , Ti, Mo, W, or an alloy containing the above elements, or An alloy film or the like made up of a combination of elements is used. Layer 1405b may use a laminate of these.

[0387] n + By providing layers 1406a and 1406b, the source electrode layer 1405, which is a metal layer, a, the drain electrode layer 1405b and the oxide semiconductor layer 1403 are in good contact with each other. It has thermally stable operation compared to Schottky junctions. In addition, it supplies carriers to the channel. (source side) or stably absorbs the carriers in the channel (drain side), or In order to avoid creating resistance components at the interface with the wiring, + It is effective to provide layers In addition, the low resistance makes it possible to maintain good mobility even at high drain voltages.

[0388] In addition, the above-mentioned n + The structure is not limited to having layers 1406a and 1406b, and may be, for example, + A structure without layers may also be used.

[0389] After the channel protection layer 1418 is formed, the channel protection layer 1418 is heated in a nitrogen atmosphere or in an air atmosphere (in the air). The thin film transistor 1430 is subjected to heat treatment (preferably at least 150° C. and less than 350° C.) in the For example, heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. In this case, the oxide semiconductor layer 1403 is heated in a state of being in contact with the channel protection layer 1418. This can reduce the variation in electrical characteristics of the thin film transistor 1470. The heat treatment (preferably at 150° C. or more and less than 350° C.) is performed after the formation of the channel protection layer 1418. There are no particular limitations on the type of material, and other processes, such as heat treatment during resin film formation and low resistance of the transparent conductive film, may be used. By combining this with the heat treatment for resistance, it is possible to carry out this without increasing the number of steps.

[0390] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0391] (Embodiment 14) A semiconductor device and a manufacturing method thereof will be described with reference to FIGS. 35(A) and 35(B). The same parts as those in the 13th embodiment or parts and steps having similar functions are the same as those in the 13th embodiment. This can be done in the same manner as in 3, and a repeated explanation will be omitted.

[0392] A thin film transistor 1431 shown in FIG. 35A includes a gate electrode layer 1401 and an oxide semiconductor A channel protection layer 1418 and an insulating layer 1407 are formed so as to overlap the channel region of the layer 1403. In this example, a conductive layer 1409 is provided through the insulating film 1404 .

[0393] FIG. 35A is a cross-sectional view of a thin film transistor 1431 included in a semiconductor device. The transistor 1431 is a bottom-gate type thin film transistor, and is mounted on a substrate with an insulating surface. A gate electrode layer 1401, a gate insulating layer 1402, an oxide semiconductor layer 1403, and a gate insulating layer 1404 are formed on a substrate 1400. 1403, source or drain regions 1404a, 1404b, and a source electrode layer or The drain electrode layers 1405a and 1405b and the conductive layer 1409 are included. It is provided on the insulating layer 1407 so as to overlap the base electrode layer 1401 .

[0394] The conductive layer 1409 includes the gate electrode layer 1401, the source electrode layer or the drain electrode layer 1405a, The pixel electrode layer 1405b can be formed using the same material and method as the pixel electrode layer 1405b. In this case, the conductive layer may be formed using a material and a method similar to those of the pixel electrode layer. The layer 1409 is a stack of a titanium film, an aluminum film, and a titanium film.

[0395] The conductive layer 1409 may have the same potential as the gate electrode layer 1401 or may have a different potential. The conductive layer 1409 can also function as a second gate electrode layer. The device may be in a ring state.

[0396] By providing the conductive layer 1409 so as to overlap with the oxide semiconductor layer 1403, a thin film transistor Bias-thermal stress test (hereinafter referred to as BT test) is used to check the reliability of transistors. In this test, the change in the threshold voltage of the thin film transistor 1431 before and after the BT test is reduced. It is possible.

[0397] Also, Fig. 35(B) shows an example that is partially different from Fig. 35(A). Parts and steps having similar functions can be carried out in the same manner as in FIG. 35(A), and the process can be repeated. The explanation will be omitted.

[0398] A thin film transistor 1432 shown in FIG. 35B includes a gate electrode layer 1401 and an oxide semiconductor A channel protection layer 1418, an insulating layer 1407, and a In this example, a conductive layer 1409 is provided with an insulating layer 1408 interposed therebetween.

[0399] In FIG. 35B, an insulating layer 1408 functioning as a planarizing film is laminated over the insulating layer 1407. do.

[0400] In addition, in FIG. 35B, a source region or a drain region is not provided, and the oxide semiconductor layer 14 03 and the source electrode layer or the drain electrode layer 1405a, 1405b are in direct contact with each other. is.

[0401] In the structure of FIG. 35B, the conductive layer 1409 is By providing the BT test for checking the reliability of thin film transistors, The change in the threshold voltage of the thin film transistor 1432 before and after the T test can be reduced. can.

[0402] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0403] (Embodiment 15) In this embodiment, an example in which the structure is partially different from that of the first embodiment is shown in FIG. The same parts or parts having similar functions and steps can be performed in the same manner as in the first embodiment. Therefore, repeated explanation will be omitted.

[0404] In this embodiment, after the first oxide semiconductor layer is patterned, an inert gas atmosphere (nitrogen After heat treatment under nitrogen, helium, neon, argon, etc. or reduced pressure The first oxide semiconductor layer is then gradually cooled in an inert atmosphere. In this way, impurities such as hydrogen and water contained in the oxide semiconductor layer 403 can be removed. .

[0405] Next, a source region and a drain region ( n + After forming a second oxide semiconductor film to be used as a conductive layer or a buffer layer, Form.

[0406] Next, the first oxide semiconductor layer, the second oxide semiconductor film, and the conductive film are subjected to an etching process. By etching more selectively, the oxide semiconductor layer 403 and the source or drain region ( n + a buffer layer 404a and a source electrode layer or a drain electrode layer 404b; Note that the oxide semiconductor layer 403 is only partly etched. As a result, an oxide semiconductor layer having a groove (depression) is formed.

[0407] Next, a silicon oxide film is formed on the oxide semiconductor layer 403 by a sputtering method or a PCVD method. The oxide insulating film 407 is formed in contact with the low-resistance oxide semiconductor layer. The insulating film 407 is resistant to moisture, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film is used to block the intrusion of oxygen from the inside of the material. Specifically, a silicon oxide film or a nitride film is used. A silicon oxide film is used.

[0408] In contact with the low-resistance oxide semiconductor layer 403, an oxide film is formed by sputtering or PCVD. When the oxide insulating film 407 is formed, at least the oxide semiconductor layer 403 having a low resistance is The region in contact with the oxide insulating film 407 is made highly resistive (the carrier concentration is reduced, preferably 1×10 18 / cm 3 less than 1×10 14 / cm 3 (See below) and high resistance oxide semiconductor The oxide insulating film 407 is formed in contact with the insulating film 407 to increase resistance. The semiconductor layer 403 having an oxide semiconductor region is formed, and a thin film transistor 473 is manufactured. (See Figure 36.)

[0409] In the structure in FIG. 36, the source or drain region (n + Also called a buffer layer. c) An In-Ga-Zn-O based non-single crystal film is used as 404a and 404b.

[0410] A source region is formed between the semiconductor layer 403 and the source electrode layer, and a drain region is formed between the semiconductor layer and the drain electrode layer. The drain region is between the source region and the drain region. A semiconductor layer is used.

[0411] In addition, the source region or drain region 404a, 404b of the thin film transistor 473 The second oxide semiconductor film used is a second oxide semiconductor film that is a second oxide semiconductor film used as a channel formation region. It is preferable that the thickness is thinner than the film thickness and has a higher electrical conductivity (electrical conductivity).

[0412] The first oxide semiconductor layer used as the channel forming region has an amorphous structure, and the source region The second oxide semiconductor film used as the drain region has an amorphous structure with crystal grains (nanocrysts). The second oxide used as the source and drain regions may include a silicon nitride film. The crystal grains (nanocrystals) in the semiconductor film have a diameter of 1 nm to 10 nm, typically 2 nm to It is about 4nm.

[0413] After the oxide insulating film 407 is formed, Then, the thin film transistor 473 is subjected to a heat treatment (preferably at 150° C. or higher and lower than 350° C.). For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The oxide semiconductor layer 403 is heated in contact with the oxide insulating film 407. Variation in the electrical characteristics of the thin film transistor 473 can be reduced.

[0414] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0415] The present invention having the above configuration will be described in more detail with reference to the following examples. It is decided. EXAMPLES

[0416] Here, in an oxide semiconductor layer including a region with high oxygen density and a region with low oxygen density, The results of calculating the change in oxygen density before and after the heat treatment were shown in Figures 42 and 43. The calculation software used here is Fujitsu Ltd.'s Mater ials Explorer 5.0 was used.

[0417] FIG. 42 shows a model of the oxide semiconductor layer used in the calculation. Here, the oxide semiconductor layer 12 01 is a laminated structure of a layer 1203 with low oxygen density and a layer 1205 with high oxygen density. Ta.

[0418] Here, the low oxygen density layer 1203 is composed of 15 In atoms, 15 Ga atoms, and 1 The amorphous structure was composed of 5 Zn atoms and 54 O atoms.

[0419] The oxygen-rich layer 1205 is made of 15 In atoms, 15 Ga atoms, and 15 The amorphous structure was composed of 100 Zn atoms and 66 O atoms.

[0420] The density of the oxide semiconductor layer 1201 is set to 5.9 g / cm 3 It was decided.

[0421] Next, the oxide semiconductor layer 1201 was subjected to the NVT ensemble at a temperature of 250° C. Classical MD (molecular dynamics) calculations were performed. The time step size was set to 0.2 fs, and the total calculation time was 20 The potential was set to 0 ps. The metal-oxygen bond and the oxygen-oxygen bond were set to Bo The upper end of the oxide semiconductor layer 1201 is and the movement of the atoms at the bottom end is fixed.

[0422] Next, the calculation results are shown in Figure 43. The area from 0 nm to 1.15 nm on the z-axis coordinate is the layer with low oxygen density. 1203, and the region from 1.15 nm to 2.3 nm on the z-axis coordinate is the oxygen-rich layer 1205. The oxygen density distribution before the MD calculation is shown by the solid line 1207, and the oxygen density distribution after the MD calculation is shown by the solid line 1208. is indicated by dashed line 1209.

[0423] The solid line 1207 indicates the boundary between the low oxygen density layer 1203 and the high oxygen density layer 1205. The oxygen density is higher in the layer 1205 with higher oxygen density than in the surface. In the low oxygen density layer 1203 and the high oxygen density layer 1205, It can be seen that the is homogeneous.

[0424] From the above, it is considered that the layer 1203 having a low oxygen density and the layer 1205 having a high oxygen density are stacked in a similar manner. When there is a bias in the distribution of oxygen density, the oxygen density is shifted from high to low by heat treatment. It can be seen that the oxygen diffuses and the oxygen density becomes uniform.

[0425] That is, as described in Embodiment 1, the oxide insulating film 407 is formed over the oxide semiconductor layer 432. As a result, the oxygen density is high at the interface between the oxide semiconductor layer 403 and the oxide insulating film 407. Therefore, the oxygen diffuses to the oxide semiconductor layer 403 in a region with a low oxygen density. The layer 403 becomes highly resistive. From the above, it is possible to improve the reliability of the thin film transistor. can be done. [Explanation of symbols]

[0426] 10 Dotted Line 100 Substrates 101 Gate electrode layer 102 Gate insulating layer 103 Semiconductor layer 105a Source electrode layer 105b Drain electrode layer 107 Protective insulation layer 108 Capacitance wiring 109 Oxide semiconductor film 110 Pixel electrode layer 121 Terminal 122 Terminal 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Transparent Conductive Film 129 Transparent conductive film 132 Conductive Film 133 Oxide Semiconductor Layer 134 Oxide semiconductor layer 135 Semiconductor Layer 150 Terminals 151 Terminal 152 Gate Insulation Layer 153 Connection electrode layer 154 Protective Insulation Layer 155 Transparent conductive film 156 Electrode layer 170 Thin-film transistor 400 Substrates 401 Gate electrode layer 402 Gate insulating layer 403 Semiconductor Layer 404a, 404b Source electrode layer or drain electrode layer 405a, 405b Source electrode layer or drain electrode layer 407 Oxide insulating film 409 Conductive Layer 410 Insulating layer 411 Pixel electrode layer 419 Conductive Layer 430 Oxide semiconductor layer 431 Oxide Semiconductor Layer 432 Oxide semiconductor layer 441 Oxide Semiconductor Layer 450 Substrate 451 Gate electrode layer 452 Gate insulation layer 453 Semiconductor Layer 455a Drain electrode layer 457 Oxide insulating film 460 Thin Film Transistor 470 Thin Film Transistor 471 Thin-film transistor 472 Thin Film Transistor 473 Thin Film Transistor 483 Oxide Semiconductor Layer 484 Oxide Semiconductor Layer 500 boards 501 Insulating film 502 Oxide semiconductor film 503 Electrode 510 Physical property evaluation samples 580 Substrate 581 Thin Film Transistor 583 Insulating Film 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 Board 601 Electric furnace 602 Chamber 603 Heater 604 Substrate 605 Susceptor 606 Gas Supply Means 607 Exhaust means 611 Gas supply source 612 Pressure Regulating Valve 613 Purifier 614 Mass Flow Controller 615 Stop valve 701 Oxide semiconductor layer 711 Initial Characteristics 712+BT 713-BT 721 Initial Characteristics 722+BT 723-BT 731 Initial Characteristics 732+BT 733-BT 1201 Oxide semiconductor layer 1203 Low oxygen density layer 1205 Oxygen-dense layer 1207 Solid Line 1209 Dashed Line 1400 Board 1401 Gate electrode layer 1402 Gate insulation layer 1403 Oxide semiconductor layer 1404a, 1404b Source or drain region 1405a, 1405b Source electrode layer or drain electrode layer 1406a, 1406b n+ layer 1407 Insulating layer 1408 Insulating layer 1409 Conductive layer 1418 Channel Protection Layer 1430 Thin-film transistor 1431 Thin-film transistor 1432 Thin-film transistor 1470 Thin-film transistor 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4501 Board 4502 Pixel section 4503a, 4503b Signal line driver circuit 4504a, 4504b Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a, 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Signal line driver circuit 5400 Board 5401 Pixel unit 5402 Scanning line driver circuit 5403 Signal line driver circuit 5404 Scanning line driver circuit 5501 Wiring 5502 Wiring 5503 Wiring 5504 Wiring 5505 Wiring 5506 Wiring 5543 nodes 5544 nodes 5571 Thin-film transistor 5572 Thin Film Transistor 5573 Thin Film Transistor 5574 Thin Film Transistor 5575 Thin Film Transistor 5576 Thin Film Transistor 5577 Thin Film Transistor 5578 Thin Film Transistor 5601 Driver IC 5602 Switches 5603a Thin Film Transistor 5603b Thin Film Transistor 5603c Thin Film Transistor 5611 Wiring 5612 Wiring 5613 Wiring 5621 Wiring 5701 Flip-flop 5711 Wiring 5712 Wiring 5713 Wiring 5714 Wiring 5715 Wiring 5716 Wiring 5717 Wiring 5721 Signal 5821 Signal 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7011 Driving TFT 7012 Light emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7021 Driving TFT 7022 Light emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 9201 Display section 9202 Display button 9203 Operation switch 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Mike 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Input means (operation keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section

Claims

1. a first scanning line driver circuit, a second scanning line driver circuit, and a pixel portion located between the first scanning line driver circuit and the second scanning line driver circuit, The pixel unit includes: a first conductive layer on the substrate; a first insulating layer having a region overlying the first conductive layer; a first oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of a first transistor; a second insulating layer having a region located on the first oxide semiconductor layer; a third insulating layer having a region located on the second insulating layer; a second conductive layer having a region located on the second insulating layer and functioning as a gate electrode of the first transistor; a third conductive layer having a region located on the third insulating layer and functioning as a pixel electrode layer of a light-emitting element; the first scanning line driver circuit and the second scanning line driver circuit have a function of outputting a signal to the same scanning line; the first scanning line driving circuit and the second scanning line driving circuit each have at least a second transistor and a third transistor; the second transistor includes a second oxide semiconductor layer including a channel formation region; the third transistor includes a third oxide semiconductor layer including a channel formation region; one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and to a power supply line; the other of the source and the drain of the second transistor is electrically connected to a wiring; a gate electrode of the second transistor is electrically connected to a gate electrode of the third transistor; the first conductive layer is applied with the same potential as the second conductive layer; In a cross-sectional view of the first transistor in a channel length direction, a width of the first conductive layer in the channel length direction is smaller than a width of the first oxide semiconductor layer in the channel length direction; a width of the second conductive layer in the channel length direction is larger than a width of the first oxide semiconductor layer in the channel length direction in a cross-sectional view of the first transistor in the channel length direction.

2. In claim 1, The first conductive layer has a single layer structure containing molybdenum.

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