Semiconductor Device

Abstract

To provide a highly productive fabrication process capable of obtaining semiconductor devices having semiconductor elements such as transistors at low cost.SOLUTION: It is a method for fabricating a laminated oxide material in which an oxide member is formed on a base member, a first oxide crystal member is formed by heat treatment to grow crystal from a surface toward an interior, and a second oxide crystal member is provided by stacking a second oxide crystal member on the first oxide crystal member. In particular, the first oxide crystal member and the second oxide crystal member share a common c-axis. It is the coaxial (axial) growth of homo or hetero crystal growth.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention is used in the manufacture of semiconductor devices by forming a laminated film by sputtering and performing a crystallization heat treatment thereon. The present invention relates to a laminated oxide material suitable for semiconductor applications such as transistors and diodes. In addition, the present invention provides a semiconductor device having a circuit composed of semiconductor elements such as transistors. The present invention relates to a semiconductor device and a method for manufacturing the same. Semiconductor integrated circuits including memories, thyristors, converters, image sensors, etc., and liquid crystal displays Equipped with electro-optical devices such as panels and light-emitting display devices with organic light-emitting elements as components This relates to electronic devices.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] The most typical semiconductor material is Si, but other materials such as SiC and GaN are also being developed. However, these require temperatures of over 1500°C to process single crystal components. , it cannot be used for thin film devices or three-dimensional devices.

[0004] On the other hand, in recent years, semiconductor thin films (thicknesses of several micrometers) formed at relatively low temperatures on substrates with insulating surfaces have been developed. The technology of constructing transistors using nanometer-sized semiconductors (up to several hundred nanometers) is attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. Development of this technology as a switching element is being rushed.

[0005] Metal oxides are available in a wide variety of forms and are used for a variety of purposes. Indium oxide is It is a well-known material and is used as an electrode material with the translucency required for liquid crystal displays, etc. Some metal oxides exhibit semiconducting properties. Examples of the metal oxide include tungsten oxide, tin oxide, indium oxide, and zinc oxide. There are transistors that use metal oxides that exhibit such semiconducting properties as the channel formation region. The gyroscope is already known (Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0007] One embodiment of the present invention is a method for producing a material suitable for semiconductor applications such as transistors and diodes by sputtering. One of the objectives is to provide the following.

[0008] Another embodiment of the present invention is to provide a transistor having high field-effect mobility and low off-state current. Another object of the present invention is to realize a so-called normally-off switching element and to achieve low power consumption. Another object of the present invention is to provide a semiconductor device having high transistor performance. Another object of the present invention is to provide a transistor which has high reliability.

[0009] Another embodiment of the present invention is a method for producing a semiconductor device including a semiconductor element such as a transistor at low cost. Another object is to provide a highly productive manufacturing process capable of achieving the above-mentioned object.

[0010] Another object of one embodiment of the present invention is to provide a highly reliable transistor. do. [Means for solving the problem]

[0011] One embodiment of the present invention disclosed in this specification is a method for forming an oxide member on a base member and performing a heat treatment. A first oxide crystal member is formed by crystal growth from the surface toward the inside of the first oxide crystal member. A method for producing a laminated oxide material, comprising laminating a second oxide crystal member on a first oxide crystal member. In particular, the first oxide crystal member and the second oxide crystal member have a common c-axis, that is, a homocrystalline structure. The advantage of this method is that it allows coaxial (axial) growth of long or hetero crystals.

[0012] The first oxide crystal member has a c-axis aligned in a direction perpendicular to the surface of the first oxide crystal member. In particular, the first non-single crystal thin film undergoes epitaxial growth (growth of a single crystal structure). The film is used as a seed to grow the second oxide crystal. In the ab plane, the elements of adjacent planes are the same. The c-axis direction of the crystal member coincides with the depth direction or the upward direction.

[0013] The greatest feature of the above fabrication method is that it can be used to fabricate amorphous insulators (e.g. oxide) with any desired surface. The structure is such that crystals are grown on a substrate.

[0014] In another aspect of the present invention, an oxide member is formed on a base member, and a heat treatment is performed to form a metal oxide layer on the surface. A first oxide crystal member is formed, the crystal growth of which is from the surface of the base member toward the inside of the base member. The amorphous component remains on the first oxide crystal member, and the first oxide crystal member is made of the same material and is homocrystalline. The present invention relates to a method for producing a laminated oxide material, in which a second oxide crystal member having the above structure is laminated.

[0015] In another aspect of the present invention, an oxide member is formed on a base member, and a heat treatment is performed to form a metal oxide layer on the surface. A first oxide crystal member is formed, the crystal growth of which is from the surface of the base member toward the inside of the base member. The amorphous component remains on the first oxide crystal member, and a hetero-crystalline material of a different material is formed on the first oxide crystal member. A method for producing a laminated oxide material by laminating a growing second oxide crystal member. .

[0016] In each of the above-mentioned manufacturing methods, the homo-crystal growth or hetero-crystal growth is performed by increasing the temperature to 200 It is characterized by being obtained by growing crystals while heating at temperatures between 0°C and 600°C.

[0017] In the above-mentioned methods, the first oxide crystal member and the second oxide crystal member are made of high purity oxide. It is characterized by being an intrinsic conductivity type.

[0018] In each of the above manufacturing methods, the carrier concentration of the laminated oxide material is 1.0×10 12 c m -3 Less than 1.45 x 10 10 cm -3 It is characterized by being less than .

[0019] In each of the above-mentioned manufacturing methods, the crystal oriented lower interface of the first oxide crystal member is The thickness of the oxide member or the conditions of the heat treatment are appropriately adjusted. By adjusting the crystal orientation of the first oxide crystal member, the lower interface of the first oxide crystal member and the underlying member are intentionally aligned. The amorphous region of the oxide material is left between the crystalline region and the amorphous region to function as a buffer. When a device is fabricated, the scattering at the interface with the base material occurs. For example, the above-mentioned laminated oxide material can be used as a semiconductor layer to reduce the effect of the gate insulation. When a bottom-gate type transistor is fabricated on an insulating layer, the channel forming region is formed on the insulating layer. The gate insulating layer is not formed at the interface with the gate insulating layer, but in a polycrystalline layer spaced apart from the surface of the gate insulating layer. The effect of scattering at the interface between the gate insulating layer and the oxide crystal member is reduced. The transistor having a crystalline layer spaced apart from the gate insulating layer surface has a buried channel (Bu They can also be called lead channel transistors.

[0020] One of the technical ideas of the present invention is to add a second metal to the oxide semiconductor. By intentionally removing the impurities such as water and hydrogen, the oxide semiconductor itself can be made highly pure. In other words, the water or hydrogen that constitutes the donor level is removed, and then the oxide is formed. By reducing the oxygen vacancy and providing sufficient oxygen to the main component material that constitutes the oxide semiconductor, The first object is to highly purify the oxide semiconductor.

[0021] By forming an oxide semiconductor film, 20 cm -3 Hydrogen at this level is detected by SIMS (secondary ion This is measured by mass spectrometry. The water or hydrogen that causes this donor level is intentionally removed, In addition, oxygen (one of the components of oxide semiconductors) is also reduced when water or hydrogen is removed. ) is added to the oxide semiconductor to purify it and make it electrically i-type (intrinsic). ) semiconductor.

[0022] In addition, one of the technical concepts of the present invention is that the amount of water and hydrogen in the oxide semiconductor should be small. The fewer the number, the better. The fewer the carriers, the better. In other words, the carrier density is 1×10 12 cm -3 less than the measurement limit, more preferably 1.45 × 10 10 cm - 3 Furthermore, the technical concept of the present invention is close to zero or ideally zero. In particular, oxide semiconductors are heated in oxygen, nitrogen, or ultra-dry air (water content of 20 ppm or less). , preferably 1 ppm or less, preferably 10 ppb or less) in air atmosphere at 450°C or higher By performing a heat treatment at 850°C or less, preferably at 550°C to 750°C, Impurities such as water or hydrogen can be removed to achieve high purification. By removing impurities such as silicon, the oxide semiconductor is highly purified, and the carrier density is increased. 1×10 12 cm -3 less than the measurement limit, more preferably 1.45 × 10 10 cm -3 It can be less than.

[0023] Furthermore, the heat treatment is performed at a high temperature of 450°C to 850°C, preferably 600°C to 700°C. In this case, the oxide semiconductor can be highly purified and crystallized. Crystal growth from the surface of a semiconductor toward the inside occurs, and the crystal has a non-single crystal region with a c-axis direction. It becomes a compound semiconductor.

[0024] The present invention uses an oxide semiconductor having a non-single crystal region with a c-axis direction as a seed crystal, and providing a second oxide semiconductor thereon at a temperature of 450° C. or higher and 850° C. or lower, preferably 550° C. or higher. By performing heat treatment at 750° C. or less, the second oxide semiconductor is grown to have a c-axis orientation similar to that of the seed crystal. That is, the c-axes of the seed crystal and the second oxide semiconductor can be aligned in a non-single crystal region. Coaxial, ideal axial growth or epitaxial growth can be achieved. .

[0025] In addition, the second oxide semiconductor, which is coaxial with the seed crystal, can be grown by solid phase growth only by heat treatment after film formation. However, the temperature is not limited to 200°C or more and not more than 600°C, and preferably not more than 200°C or more and not more than 550°C. A second oxide semiconductor is formed on the first oxide semiconductor layer, typically by a sputtering method. The crystal can be grown while the

[0026] Furthermore, by reducing, and preferably eliminating, carriers in the oxide semiconductor, In the transistor, the oxide semiconductor functions as a path through which carriers pass. As a result, oxide semiconductors are highly purified i-type (intrinsic) semiconductors, and have no carriers. By making the amount of the transistor extremely small, the off-state current of the transistor is extremely low. This is one of the technical ideas of the present invention.

[0027] In addition, the oxide semiconductor functions as a path and does not have carriers. If the i-type (intrinsic) is highly purified so that there is no or very little carriers, the carriers The electron affinity χ and Fermi level of the oxide semiconductor are Ideally, the Fermi level coincides with the intrinsic Fermi level, and the source and drain potentials are By appropriately selecting the work function of the electrode, carriers can be injected from the source electrode and the drain electrode. This makes it possible to fabricate n-type and p-type transistors appropriately. can.

[0028] The oxide crystal member and the oxide member are all metal oxides and are quaternary metal oxides. In-Sn-Ga-Zn-O films and ternary metal oxide In-Ga-Zn-O films , In-Sn-Zn-O based film, In-Al-Zn-O based film, Sn-Ga-Zn-O based film, Al-Ga-Zn-O-based films, Sn-Al-Zn-O-based films, and binary metal oxide In -Zn-O film, Sn-Zn-O film, Al-Zn-O film, Zn-Mg-O film, Sn -Mg-O based film, In-Mg-O based film, In-O based film which is a single element metal oxide, Sn- Metal oxide films such as O-based films and Zn-O-based films can be used. In-Sn-Ga-Zn-O film is a thin film of indium (In), tin (Sn), and gallium (G a) means an oxide film containing zinc (Zn), and the stoichiometric ratio is not particularly important. do not have.

[0029] The oxide crystal member and the oxide member are InMO3(ZnO). m (m>0, and It can also be expressed as a material expressed by the formula m (where m is not a natural number). Here, M is Ga, Al, It represents one or more metal elements selected from Mn and Co. For example, M is Ga, G Examples include Al and Ga, Mn and Ga, and Co.

[0030] Alternatively, an oxide semiconductor material represented by In-ABO may be used, where A is Group 13 elements such as gallium (Ga) and aluminum (Al), silicon (Si) and germanium (Ge) Represents one or more elements selected from the group 14 elements, such as germanium (Ge). In addition, B is one or more elements selected from the group 12 elements represented by zinc (Zn). Represents an element. The contents of In, A, and B are optional, including the case where the content of A is zero. On the other hand, the contents of In and B are not zero. That is, the above notation includes In-Ga In the present specification, the term In-Ga-Zn-O and In-Zn-O is used. The oxide semiconductor material represented by O is InGaO3(ZnO). m (m>0 and m is natural The fact that m is not a natural number can be confirmed by using ICP-MS analysis and RBS analysis. It can be confirmed.

[0031] Conventional oxide semiconductors are generally n-type, and even if the gate voltage is 0V, the source electrode and drain electrode Current flows between the electrodes, which is called a normally-on state. If the transistor is normally on, it is difficult to control it as a circuit. The Fermi level when the conductor is n-type (E F ) is the intrinsic ferroelectric in the center of the band gap. Elmi level (E i ) and is located closer to the conduction band. It is known that hydrogen is a donor and is one of the factors that causes n-type. It is known that this is also one of the factors that causes n-type semiconductors.

[0032] Therefore, in order to make the oxide semiconductor layer i-type, hydrogen, which is an n-type impurity, is removed from the oxide semiconductor. The oxide semiconductor is highly purified so that it contains as few impurities as possible other than the main component of the oxide semiconductor, and is free of oxygen. It is made true (type i) by removing the defect, or made true type, i.e., by adding impurities. Instead of adding hydrogen and water to make it i-type, we remove impurities such as hydrogen and water, and oxygen vacancies as much as possible. It is characterized by being highly purified i-type (intrinsic semiconductor) or close to it. This results in the Fermi level (E F ) to the intrinsic Fermi level (E i ) to the same level as It is possible.

[0033] By highly purifying the oxide semiconductor layer, the threshold voltage of the transistor can be increased. Thus, a so-called normally-off switching element can be realized.

[0034] As one of the processes for increasing the purity, a process for increasing the purity before or after the formation of an oxide semiconductor film is performed. It is preferable to remove moisture and the like from within the sputtering apparatus during or after the film formation. To remove moisture from inside the device, it is preferable to use an adsorption type vacuum pump. For example, It is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. The exhaust means may be a turbo pump with a cold trap added. The deposition chamber of the sputtering device evacuated using a cryopump is filled with hydrogen atoms, water, etc. Since compounds containing hydrogen atoms such as (H2O) are exhausted, the oxide film formed in the film formation chamber The concentration of impurities in the semiconductor film can be reduced. The relative density of the oxide semiconductor is 80% or more, preferably 95% or more, and more preferably 99. It is preferable that the relative density is 9% or more. When a target with a high relative density is used, the oxide formed The impurity concentration in the semiconductor film can be reduced.

[0035] If impurities are mixed into the oxide semiconductor film to be formed, the oxide semiconductor film may be damaged during heat treatment for crystallization to be performed later. In this case, there is a risk of inhibiting unidirectional crystal growth, i.e., crystal growth downward from the surface, so oxidation is It is reasonable to assume that there are no impurities (impurities that create p-type or n-type) in the semiconductor film. In addition, impurity elements such as heavy metals, Fe, and Ni that do not constitute semiconductors are also included in the 1×10 15 cm -3 The oxide semiconductor is dehydrated and dehydrogenated to the following temperature. It is not possible to purify the oxide semiconductor or to crystallize the oxide semiconductor while performing this step particularly strongly. It is extremely important.

[0036] In addition, before the oxide semiconductor film is formed, the inner wall of the sputtering apparatus, the surface of the target, and the A preheating treatment may be performed to remove moisture or hydrogen from the sheet material. An effective method for the deposition process is to heat the deposition chamber to 200℃ to 600℃ under reduced pressure. In addition, the substrate to be processed is heated while the film is formed, and moisture and the like are adsorbed to the inner wall of the chamber. In this case, it is better to use oil or fat as the target coolant instead of water. Repeated nitrogen introduction and exhaust without heating can produce a certain effect, but After the preheating process is completed, the substrate or the sputtering device is cooled and the oxide semiconductor The body membrane is formed.

[0037] In addition, the oxide semiconductor film or a material film formed in contact therewith is formed using an aluminum alloy. The sputtering gas, such as argon or oxygen, also contains impurities such as hydrogen, water, compounds containing hydroxyl groups, or hydrides. The substance is removed to a concentration expressed in ppm or ppb. It is preferable to use high purity gases that have been subjected to

[0038] In addition, the substrate is heated to 200° C. or higher and 600° C. or lower during the deposition of the oxide semiconductor film by sputtering. If the substrate is heated to a temperature between 200° C. and 600° C., the first non-single crystal layer may be preheated. If the crystals are formed in the same direction as the film is formed, the crystals will grow in the same direction (especially in the c-axis direction). We can expect this.

[0039] In addition, one of the processes for high purification is to use an atmosphere that contains almost no hydrogen or moisture. Under air (nitrogen atmosphere, oxygen atmosphere, dry air atmosphere (for example, moisture dew point -40℃ Hereinafter, the first heat treatment is preferably performed at a temperature of −50° C. or lower (dew point). This process is also called dehydration or dehydrogenation, in which H, OH, and the like are eliminated from the oxide semiconductor layer. The heating process can be performed by increasing the temperature in an inert atmosphere and then switching to an oxygen-containing atmosphere midway. When the heat treatment is performed in an oxygen atmosphere, it can be called an oxidation treatment.

[0040] The first heat treatment is a heating method using an electric furnace, and a GRTA (Gas Tunneling and Atomic Radiation) method using heated gas. Rapid Thermal Annealing (LRTA) using lamp light (La Use instantaneous heating methods such as the mp Rapid Thermal Anneal method. In addition, the first heat treatment can be performed simultaneously with heating by irradiating light of 450 nm or less. The first heat treatment for purification may be performed on the oxide semiconductor layer after the first heat treatment. In contrast, TDS (Thermal Desorption Spectroscopy) Even when measurements are taken up to 450°C, the two peaks for water appear at least near 300°C. The conditions are such that one peak is not detected. Therefore, heat treatment for high purification is performed. The transistors using the oxide semiconductor layer were measured up to 450℃ by TDS. However, the water peak that appears at around 300°C is not detected.

[0041] The first heat treatment is performed at a high temperature for a short period of time in order to grow crystals without any seeds for crystal growth. It is preferable to perform the above-mentioned process so that crystal growth only proceeds from the surface to the inside. If the surface of the nitride semiconductor layer is flat, a good plate-like non-single crystal layer can be obtained. It is desirable that the base material, for example the insulating layer or the substrate, be as flat as possible. The surface roughness is the same as that of commercially available silicon wafers. For example, the surface roughness is 1 μm square. The height difference in AFM measurement is set to 1 nm or less, preferably 0.2 nm or less.

[0042] The non-single crystal layer is formed by the In electron clouds in the oxide semiconductor overlapping and connecting with each other. Therefore, the transistor with the non-single crystal layer has a high field effect. As a result, high mobility can be achieved.

[0043] One method for further crystal growth using the non-single crystal layer formed by the first heat treatment as a seed is This is shown below with reference to Figures 1(A), 1(B), and 1(C).

[0044] The process sequence is as follows: after a first oxide semiconductor layer is formed on a base member, a high-purity The first heat treatment is carried out for the purpose of purifying the material, and the second heat treatment is carried out in the same process as the first heat treatment for the purpose of purifying the material. A non-single crystal layer having a relatively uniform crystal orientation is formed on the surface of the first oxide semiconductor layer. A second oxide semiconductor layer is then stacked on the first oxide semiconductor layer. As a result, the second oxide semiconductor layer is crystallized using the non-single crystal layer on the surface of the first oxide semiconductor layer as a seed. The process is carried out in the order of

[0045] In the first heat treatment, crystal growth occurs from the surface without any seeds for crystal growth, whereas in the second heat treatment, The second heat treatment is performed at the lowest temperature at which crystal growth is possible because there is a plate-shaped non-single crystal layer that serves as a seed. It is preferable to heat the film for a long time at 200° C., since good crystallinity can be obtained by the second heat treatment. The direction of crystal growth is from bottom to top, from the substrate side to the surface side (recrystallization direction). This is different from the crystal growth direction in the first heat treatment. The non-single crystal layer obtained by the treatment is heated again in a second heat treatment, which further improves the crystallinity. do.

[0046] FIG. 1A shows a first oxide semiconductor layer formed on a base member 520. The first oxide semiconductor layer and the base member are in a state after the first heat treatment for the purpose of preventing the formation of the oxide semiconductor layer. Although it depends on the material of 520, the heating temperature, the heating time, and other conditions, the surface is Even if the crystal grows from the first oxide crystal member 521b, the tip of the first oxide crystal member 521b does not reach the interface with the base member 520. However, the crystalline region 521a does not reach the crystalline region 521a, and an amorphous region 521a remains.

[0047] FIG. 1B is a cross-sectional view of the second oxide member 522 immediately after the film formation. The member 522 is formed by a sputtering method, and the metal oxide target is In2O3:Ga Metal oxide targets with a molar ratio of 2O3:ZnO=1:1:2 and In2O3:G A metal oxide target with a molar ratio of A2O3:ZnO = 1:1:4 may be used.

[0048] During the deposition of the second oxide member 522 by sputtering, the substrate is heated to a temperature of 200° C. or higher and 600° C. When the film is formed at this substrate temperature, the second oxide member 522 is pre-arranged. It is also possible to grow epitaxially directly.

[0049] A structure corresponding to Fig. 1(B) was actually fabricated, and a TEM photograph of the cross section is shown in Fig. 4(A). A schematic diagram is shown in Figure 4(B). The TEM photographs were taken at an accelerating voltage of 300 kV. The results were observed using a high-resolution transmission electron microscope (Hitachi H9000-NAR: TEM). This is a high-magnification photograph (4 million times). The sample in Figure 4(A) is an insulating film on a glass substrate. A first In-Ga-Zn-O film having a thickness of 5 nm was then formed on the first In-Ga-Zn-O film. The second In-Ga-Z layer was then deposited at 650°C for 6 minutes in air. The insulating layer was formed by laminating a 100 nm thick nO film using a high density plasma device. A silicon oxynitride film (also called SiOxNy, where x>y>0) is used. ) the first In-Ga-Zn-O film is The c-axis is oriented vertically and the interface of the first In-Ga-Zn-O film with the insulating layer is It can be seen that the crystallization has not occurred in the near future.

[0050] The metal oxide semiconductor layer is InGa x Zinc y O z The material represented by the formula Here, x, y, and z are arbitrary numbers. Also, x, y, and z do not have to be integers. It may be a non-integer. Note that x may be 0, but y is preferably not 0. For example, the notation includes In-Zn-O where x is 0. It also includes In-Zn-O where x=1 and y=1. In addition, oxide semiconductors are also known as In order to obtain a crystal with a c-axis oriented in a direction perpendicular to the conductor layer surface, for example a non-single crystal, high purification is required. It is preferable to use an oxide semiconductor having a low impurity content. By this process, a non-single crystal with high crystallinity can be obtained. The plate-like crystals in the layer are In2Ga2ZnO7 (In:Ga:Zn:O=2:2 The carrier of the metal oxide semiconductor layer having the flat crystal structure is The concentration is 1×10 12 cm -3 Less than 1.45 x 10 10 cm -3 is less than .

[0051] In addition, the first In-Ga-Zn-O film and the second In- The Ga-Zn-O film was sputtered using the same sputtering equipment with an oxide semiconductor target (In-Ga -Zn-O oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] was used, the pressure was 0.6 Pa, the direct current (DC) power was 0.5 kW, and oxygen and argon were The substrate temperature was 20 The film was formed at 0°C and a film formation rate of 4 nm / min. For example, the target of In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] When using this method, it is easy to obtain non-single crystals of In2Ga2ZnO7.

[0052] The crystal structure of In2Ga2ZnO7 contains either In, Ga, or Zn and has an a-axis (aa It can be considered as a stacking structure of layers parallel to the x-axis and b-axis. The electrical conductivity of the In2Ga2ZnO7 crystal is mainly controlled by In. The electrical properties of the In-containing layer in the directions parallel to the a-axis and b-axis are excellent. In the In2Ga2ZnO7 crystal, the electron clouds of In overlap and connect with each other, Apus is formed.

[0053] In addition, instead of the above target, In2O3:Ga2O3:ZnO=2:1:8 [mol A metal oxide target having a ratio of 1:1 or less may be used.

[0054] In addition, a metal oxide target containing no Ga, In2O3:ZnO=1:2 [molar ratio] In the case of a bottom gate type transistor, the oxide of Ga is an insulator. Therefore, the In-Zn-O film is more effective than the first In-Ga-Zn-O film. In this case, the field effect mobility can be increased.

[0055] FIG. 1C is a cross-sectional view after the second heat treatment. The non-single crystal layer of the oxide crystal member 521b is used as a seed to guide the oxide crystal member 521 toward the surface of the second oxide member 522. The crystal grows upwards, forming the second oxide crystal member 523b. It has a crystal axis.

[0056] The materials of the first oxide member and the second oxide member have a c-axis orientation perpendicular to the surface. As long as a non-single crystal having the same structure can be obtained, there is no particular limitation. Different materials may be used, or the same material may be used. Materials containing the same components may be used. "Containing the same components" means having the same elements.

[0057] In addition, the first oxide member and the second oxide member are made of an oxide semiconductor material containing the same components. In this case, as shown by the dotted line in FIG. 1(C), the first oxide crystal member 523a and the second oxide The boundaries of crystal members 523b become unclear.

[0058] In FIG. 1C, a region 520 is in contact with the base member 520 and remains in an amorphous state. 3c, a first oxide crystal member 523a, and a second oxide crystal member 523b are laminated in this order. It can be said to have a three-layer structure.

[0059] The second heat treatment also serves to remove H, OH, and the like from the oxide semiconductor layer. This can also be called hydrogenation, and the temperature is raised under an inert atmosphere, and then the atmosphere is switched to oxygen-containing atmosphere. When performing heat treatment in an atmosphere containing oxygen or in an oxygen atmosphere, the amount of added oxygen is It can also be called processing.

[0060] The hydrogen concentration in the oxide semiconductor layer is 1×10 18 cm -3 Below, 1×10 16 cm -3 below, Further, it is preferable that the carrier density of the oxide semiconductor layer is substantially 0. 1 2 cm -3 less than the measurement limit, more preferably 1.45 × 10 10 cm -3 Less than That is, the carrier density of the oxide semiconductor layer is close to zero. The energy gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. The hydrogen concentration in the oxide semiconductor layer was measured using secondary ion mass spectrometry (SIMS). This can be done by using the ion mass spectroscopy (Ion Mass Spectroscopy). The degree of charge transport can be measured by Hall effect measurements. The measurement is CV measurement (Capacitance-Voltage-Measurement ) and the formula 1.

[0061]

number

[0062] Thus, a laminate of the first oxide crystal member 523a and the second oxide crystal member 523b is obtained. The non-single crystal layer can be grown in two separate steps.

[0063] In addition, after the formation of the second In-Ga-Zn-O film, the film was heated at 650°C for 6 minutes in a nitrogen atmosphere. The heat treatment was performed, and the TEM photograph of the cross section is shown in FIG. 5(A). In FIG. 5(A), the entire second In-Ga-Zn-O film is crystallized. The non-single crystal layer of the second In-Ga-Zn-O film is It can be seen that the c-axis is oriented perpendicular to the surface of the a-Zn-O film. Even after the heat treatment in step 2, the vicinity of the interface between the insulating layer and the first In-Ga-Zn-O film was not crystallized. It can be confirmed that

[0064] In FIG. 1A, the surface of the first oxide semiconductor layer is a non-uniform crystal structure having a relatively uniform crystal orientation. The crystal layer grows from the surface in the depth direction, so it is formed without being affected by the underlying material. It is possible.

[0065] The first oxide semiconductor layer, for example, an In-Ga-Zn-O film, has a relatively uniform crystal orientation on its surface. The mechanism by which the non-single crystal layer is formed is explained below using an example. The zinc contained in the Zn-O film diffuses and gathers near the surface, becoming the seeds for crystal growth. The crystal growth is more rapid in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface). Since the crystal growth in the ab direction is stronger than that in the ab direction, a flat non-single crystal layer is formed. The ab plane direction is easier to crystallize than the c axis direction. In addition, the area above the surface of the In-Ga-Zn-O film is free space. These results indicate that the TDS measurement was performed up to 450°C. When the experiment was carried out, In and Ga were not detected, but zinc was found to be pin-like under vacuum heating conditions, especially around 300°C. This is inferred from the fact that it has been confirmed that the peaks are detected. The experiment was carried out at 200°C, and it has been confirmed that zinc release can be detected at around 200°C.

[0066] As a comparative example, a 50 nm thick In-Ga-Zn-O film was formed and then heated at 700° C. The TEM photograph of the cross section of the sample that was heated for 1 hour is shown in FIG. A schematic diagram is shown in FIG. 6(B). The TEM photograph in FIG. 6(A) was taken at an accelerating voltage of 300 kV. The samples were then observed using a high-resolution transmission electron microscope (Hitachi H9000-NAR: TEM). In Fig. 6(A), the In-Ga-Zn-O film is About 5 nm of the In-Ga-Zn-O film is crystallized, and there are many amorphous parts and oriented It can be seen that multiple crystals with different sizes are randomly present. After forming a 50 nm thick film, it is heated at 700℃ (higher than 650℃) for 1 hour (longer than 6 minutes). It is difficult to make the entire 50 nm thick layer into a non-single crystal layer with high orientation even by performing the treatment once. It can be said that it is difficult.

[0067] Based on these experimental results, the film was formed in two steps to form a non-single crystal layer that serves as the seed for crystal growth. After that, a thick non-single crystal layer can be formed by forming a film again and then growing the crystal. It is possible, and the method disclosed in this specification proves to be extremely useful. After the deposition, two heat treatments are performed to obtain a highly oriented non-single crystal layer, i.e., an oxidized layer. It is possible to obtain a thick non-single crystal layer with the c-axis oriented perpendicular to the surface of the solid crystal material. Cut.

[0068] In addition, one embodiment of the present invention disclosed in this specification is a method for manufacturing a semiconductor device comprising the steps of: forming a first oxide crystal member on a base member; A first oxide crystal member having crystal growth from a surface toward the inside, and a The second oxide crystal member is laminated to form a laminated oxide material. The first oxide crystal member, which grows as a crystal, grows in a direction perpendicular to the surface of the first oxide crystal member. The c-axis is oriented in the direction.

[0069] In the above-mentioned configuration, an oxide member containing amorphous matter is disposed between the base member and the first oxide crystal member. In addition, the amorphous material is intentionally formed between the base member and the first oxide crystal member. By disposing an oxide member containing the oxide, the crystal does not grow until it reaches the surface of the base member. Since the heat treatment can be performed under suitable conditions, the productivity can be improved.

[0070] In addition, one embodiment of the present invention disclosed in this specification is a method for forming a crystal structure of a first oxide crystal member on a first oxide crystal member. growing a second oxide crystal member at least partially above the surface of the first oxide crystal member; The laminated oxide material is characterized in that

[0071] Another aspect of the present invention is a method for manufacturing a semiconductor device, the method comprising: forming a gate electrode layer having a flat surface; forming a gate insulating layer on the gate electrode layer; A first oxide semiconductor layer is formed over the insulating layer, and a first heat treatment is performed to form the first oxide semiconductor layer. A first non-single crystal layer is formed by crystal growth from the surface of the solid layer toward the inside, and the first non-single crystal layer is formed by crystal growth from the surface of the solid layer toward the inside. A second oxide semiconductor layer is formed on the first non-single-crystal layer, and a second heat treatment is performed to convert the first non-single-crystal layer into a forming a second non-single crystal layer by growing crystals toward a surface of the second oxide semiconductor layer thereon; A source electrode layer or a drain electrode layer is formed on the stack of the first non-single crystal layer and the second non-single crystal layer. The first non-single crystal layer has a crystal-oriented lower interface spaced apart from a surface of the gate insulating layer. The present invention relates to a method for manufacturing a semiconductor device.

[0072] In the above-mentioned structure, the first non-single crystal layer is It is characterized by its c-axis orientation.

[0073] Another aspect of the present invention is a semiconductor device, the configuration of which is a flat surface on a surface of a base member. a gate electrode layer having a gate insulating layer on the gate electrode layer; A metal oxide layer containing amorphous material and a metal oxide layer containing amorphous material are formed on the metal oxide layer with c-axis orientation perpendicular to the surface. a first non-single crystal layer having a first non-single crystal layer and a second non-single crystal layer extending in a direction perpendicular to the surface of the first non-single crystal layer; A second non-single crystal layer having a c-axis orientation in the first direction and a stack of the first non-single crystal layer and the second non-single crystal layer. a source electrode layer or a drain electrode layer on the first non-single crystal layer and a second non-single crystal layer The semiconductor device is characterized in that the crystal layer is a metal oxide layer.

[0074] In the above structure, the height difference of the region of the surface of the second non-single crystal layer overlapping with the gate electrode layer is 1n It is characterized in that the thickness is 0.05 nm or less, preferably 0.2 nm or less.

[0075] In addition, devices using metal oxides, typically In-Ga-Zn-O films, are not suitable for single-crystal Si This is completely different from devices that use silicon carbide, silicon carbide, or GaN. It is.

[0076] Known wide-gap semiconductors are SiC (3.26 eV) and GaN (3.39 eV). However, SiC and GaN are expensive materials. In addition, SiC has a low resistance region. In order to selectively form the region, phosphorus or aluminum is doped and then activated. In other words, SiC and GaN require a temperature of 1000°C or higher. The processing temperature is 1000°C, and the thin film is formed on the glass substrate or on the substrate on which the LSI is formed. Film formation is virtually impossible.

[0077] In addition, SiC and GaN are only available as single crystals, and control by PN junction is required, making it possible to obtain a more complete single crystal. Therefore, there is a possibility that trace amounts of impurities may be mixed in during the manufacturing process. By introducing the electrons, they become donors or acceptors, so there is no lower limit to the carrier concentration. On the other hand, metal oxides can exist in any crystal structure, whether amorphous, polycrystalline, or single crystal. It is possible to use φ without using PN junction control. MS Against χ OS +1 / 2E g OS , φ MD Against χ OS +1 / 2Eg OS and the work functions of the source and drain, and the metal oxide. By utilizing the electron affinity and the energy band width of the compound, a bandgap equivalent to a PN junction can be realized. One of the characteristics of metal oxides is that they act as a control.

[0078] The band gap of metal oxides, typically In-Ga-Zn-O films, is also approximately equal to that of single crystal silicon. It is three times wider and is a cheaper material than SiC, with lower manufacturing costs.

[0079] The band gap of In-Ga-Zn-O is 3.05 eV. The electron energy distribution f(E) in a solid is given by the following formula: It is known to follow the Mi-Dirac statistics.

[0080]

number

[0081] In ordinary semiconductors where the carrier density is not extremely high (not degenerate), the following relationship holds: do.

[0082]

number

[0083] Therefore, the Fermi-Dirac distribution in equation (1) can be expressed as the Boltzmann distribution in the following equation: is approximated.

[0084]

number

[0085] Using equation (3), we calculate the intrinsic carrier density (n i ) gives the following formula:

[0086]

number

[0087] Then, in equation (4), we add the effective densities of state (Nc, Nv) of Si and In-Ga-Zn-O, The intrinsic carrier density was calculated by substituting the value of the gate gap (Eg). The results are shown in Table 1. .

[0088] [Table 1]

[0089] It can be seen that In-Ga-Zn-O has an extremely low intrinsic carrier density compared to Si. In addition, the carrier density of oxide semiconductors is 1×10 12 cm -3 Less than or equal to 1000 μm, more preferably less than 1000 μm Below the limit: 1.45 x 10 10 cm -3 It is preferable that the IGZO band gap is less than 100 nm. When the gap is set to 3.05 eV, the intrinsic carrier Assuming that the Fermi-Dirac distribution law is approximately correct for the arsenic concentration, the former is larger than the latter. The carrier density is about 10 17 I'd say it's twice as big.

[0090] In addition, metal oxides can be used to form thin films by sputtering at temperatures ranging from room temperature to 450°C. The maximum process temperature can be 300°C or higher and 800°C or lower. If the degree of adhesion is set to the distortion point of the glass or lower, it can be formed on a large glass substrate. Therefore, for industrialization, the maximum process temperature must be between 300°C and 800°C, and the band gap must be It is important to be able to prepare metal oxides with a wide range of properties.

[0091] In addition, even when silicon integrated circuits are made three-dimensional, the processing temperature for metal oxides is too low. The temperature is between 300℃ and 800℃, which is lower than the temperature that breaks the bond (silicon side). It can also be applied to integrated circuits that have been made three-dimensional by forming a metal oxide FET layer above the integrated circuit. It is Noh.

[0092] Metal oxides reported so far are either amorphous or polycrystalline. In the past, only single crystals were obtained by treatment at high temperatures of about 1500°C. As described above, after forming a non-single crystal of a metal oxide, the metal oxide is A method for growing non-single crystal thin films with c-axis orientation at relatively low temperatures using a non-single crystal as a seed. If a thin film can be made, and if a thick non-single crystal can be made, it will open up a wider range of industrial applications. To obtain a thick non-single crystal film, it is preferable for the substrate to be highly flat and smooth. This is because: A slight unevenness in the substrate causes a localized c-axis deviation, and as the crystal growth progresses, the adjacent This is because the orientation of the c-axis of the crystal differs from that of the crystal to be grown, resulting in defects such as crystal dislocations. Effect of the Invention

[0093] The metal oxide film is formed in two separate steps and then heated in two separate steps, Regardless of the material, such as oxide, nitride, or metal, the surface of the material (insulating surface or oxide A thick non-single-crystalline layer is formed on a silicon substrate (a nitride or metal surface), i.e., the c-axis is aligned perpendicular to the film surface. Therefore, a non-single crystal layer having a good crystallinity can be obtained.

[0094] Note that a transistor using an oxide semiconductor layer having a c-axis oriented non-single-crystal layer has a high current In addition, it is possible to realize a transistor with a low off-state current. In addition, a so-called normally-off switching element can be realized, and a semiconductor device with low power consumption can be realized. A body device can be provided.

[0095] In addition, a transistor using an oxide semiconductor layer having a c-axis oriented non-single-crystal layer was This suppresses the change in the transistor threshold voltage before and after testing, resulting in high reliability. In addition, the use of an oxide semiconductor layer having a c-axis-oriented non-single-crystal layer can realize The transistors were tested by irradiating light continuously on the transistors before and after the BT test. A transistor having stable electrical characteristics and capable of reducing the amount of change in threshold voltage of the transistor. can be produced.

[0096] The first heat treatment can be performed under conditions that enable a thin non-single-crystal layer to be formed on a surface of the first oxide semiconductor layer, Even if the crystal growth is not allowed to reach the surface of the base material, the second oxide semiconductor is formed on it. and forming a thin non-single crystal layer on the second oxide semiconductor layer using the thin non-single crystal layer as a seed. The temperature of the first heat treatment temperature condition can be lowered, or the heating time can be shortened. Therefore, it is suitable for a manufacturing process for forming a film on a large-area substrate. If the second heating temperature is set to 600° C. or less, the amount of glass shrinkage can be suppressed. This makes it possible to provide a manufacturing process that can be achieved at low cost and has high productivity.

[0097] In addition, the crystal oriented lower interface of the first oxide crystal member is intentionally spaced from the surface of the base member. This can reduce the effect of interface scattering with the underlying material when a device is fabricated. By using the crystal layer separated from the gate insulating layer as the channel forming region, Buried channel transistors can be realized. [Brief description of the drawings]

[0098] [Figure 1]1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Diagram 2] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Diagram 3] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional TEM photograph and its schematic diagram. [Diagram 5] 4A to 4C are a cross-sectional TEM photograph and a schematic diagram thereof after a second heat treatment. [Figure 6] 1A and 1B are cross-sectional TEM photographs and schematic diagrams of a comparative example. [Figure 7] FIG. 1 is a longitudinal cross-sectional view of a bottom-gate transistor including an oxide semiconductor. [Figure 8] FIG. 8 is an energy band diagram (schematic diagram) taken along the line A-A' in FIG. [Figure 9] (A) shows the state when a positive voltage (VG>0) is applied to the gate (GE1), and (B) shows the state when a negative voltage (VG<0) is applied to the gate (GE1). [Figure 10] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 11] 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view showing one embodiment of the present invention. [Figure 15] FIG. 1 illustrates an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0099] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and those skilled in the art will recognize that the present invention may be modified in various ways in form and detail. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0100] (Embodiment 1) In this embodiment, an example of manufacturing a transistor will be described with reference to FIGS.

[0101] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a photomask is applied. A gate electrode layer 401 is provided by a photolithography process using a photoresist.

[0102] Examples of the substrate 400 include a semiconductor substrate, a sapphire substrate, a quartz substrate, and a ceramic substrate. Among them, it is preferable to use a glass substrate, which can be mass-produced. The glass substrate used as No. 400 has a distortion point of 730 when the temperature of the subsequent heat treatment is high. The substrate 400 may be made of, for example, aluminosilicate glass. Glass materials such as quartz, aluminoborosilicate glass, and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide, Therefore, glass substrates containing more BaO than B2O3 are used. It is preferable to use:

[0103] In addition, an insulating layer serving as a base layer may be provided between the substrate 400 and the gate electrode layer 401. The layer has a function of preventing the diffusion of impurity elements from the substrate 400, and is made of silicon nitride, silicon oxide, A laminate structure of one or more layers selected from silicon nitride oxide or silicon oxynitride. It can be formed.

[0104] A metal conductive layer can be used as the gate electrode layer 401. The elements are selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the elements mentioned above. It is preferable to use an alloy containing the above elements or an alloy combining the above elements. For example, A three-layer stack of an aluminum layer on a titanium layer, and a titanium layer on the aluminum layer. A layer structure, or an aluminum layer on a molybdenum layer and a molybdenum layer on the aluminum layer. Of course, the metal conductive layer may be a single layer or It may be a two-layer structure or a laminated structure of four or more layers. It is preferable to select a material for the pole layer 401 that can withstand the heat treatment temperature.

[0105] Next, a gate insulating layer 402 is formed on the gate electrode layer 401. The gate insulating layer 402 is A silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, etc. are formed by using a plasma CVD method or a sputtering method. A silicon oxynitride layer, a silicon nitride oxide layer, or a silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, a silicon nitride film and a silicon oxide film are stacked. The thickness of the gate insulating layer 402 is 50 nm or more. The upper limit is 200 nm.

[0106] In this embodiment mode, the gate insulating layer 402 is formed by a high density plasma apparatus. Here, the high-density plasma device is 1×10 11 / cm 3 A plasma density of more than For example, a device that applies microwave power of 3kW to 6kW to generate plasma. This allows the deposition of an insulating film.

[0107] The chamber is filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gas as material gases. A gas is introduced to generate high-density plasma at a pressure of 10 Pa to 30 Pa, and the plasma is then applied to insulating materials such as glass. An insulating film is formed on a substrate having a surface. Then, the supply of monosilane gas is stopped and the substrate is exposed to air. Nitrous oxide (N2O) and rare gases are introduced to perform plasma treatment on the insulating film surface without exposing it to heat. It may be performed on the surface of the insulating film by introducing at least nitrous oxide (N2O) and a rare gas. The plasma treatment is performed after the formation of the insulating film. It is an insulating film that can ensure reliability even if it is thin, for example, less than 100 nm. .

[0108] When forming the gate insulating layer 402, monosilane gas (SiH4) and nitrogen are introduced into the chamber. The flow ratio of nitrogen oxide (N2O) should be in the range of 1:10 to 1:200. The rare gases introduced into the bar are helium, argon, krypton, xenon, etc. Among them, it is preferable to use argon, which is inexpensive.

[0109] In addition, the insulating film obtained by the high-density plasma device can be formed with a consistent thickness. The insulating film obtained by the high-density plasma device has excellent step coverage. The thickness can be precisely controlled.

[0110] The insulating film obtained by the above process sequence is different from the insulating film obtained by the conventional parallel plate type PCVD apparatus. The etching rates are significantly different when comparing the etching rates using the same etchant. The insulating film obtained by the parallel plate type PCVD equipment is 10% or more or 20% slower and more efficient. The insulating film obtained using a high-density plasma device can be said to be a dense film.

[0111] In this embodiment, the gate insulating layer 402 is formed using a high density plasma apparatus. A 100 nm silicon oxynitride film (also called SiOxNy, where x>y>0) is used.

[0112] Next, a first oxide semiconductor layer having a thickness of 2 nm to 15 nm is formed on the gate insulating layer 402. The first oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere. The gas is spatulated under an oxygen atmosphere or a mixture of a rare gas (typically argon) and oxygen. It can be formed by the TA method.

[0113] In addition, before, during, or after the formation of the oxide semiconductor film, In order to remove moisture from inside the sputtering device, it is necessary to use an adsorbent. It is preferable to use a vacuum pump of this type. For example, a cryopump, an ion pump, a titanium It is preferable to use a sublimation pump. A cryopump with a cold trap may be used. The deposition chamber of the sputtering device is filled with, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2O). Since compounds containing impurities are exhausted from the deposition chamber, impurities contained in the oxide semiconductor film formed in the deposition chamber are The concentration can be reduced.

[0114] The first oxide semiconductor layer is made of a quaternary metal oxide, In-Sn-Ga-Zn-O system. films, In-Ga-Zn-O films, In-Sn-Zn-O films, which are ternary metal oxides, In-Al-Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, S n-Al-Zn-O based films, binary metal oxide In-Zn-O based films, Sn-Zn- O-based film, Al-Zn-O-based film, Zn-Mg-O-based film, Sn-Mg-O-based film, In-Mg- O-based films, and single-element metal oxide films such as In-O-based films, Sn-O-based films, and Zn-O-based films A nitride semiconductor film can be used.

[0115] The first oxide semiconductor layer is made of InMO3(ZnO). m (m>0 and m must be a natural number. A thin film represented by the formula (I) can also be used, where M is Ga, Al, Mn, and C. o represents one or more metal elements selected from the group consisting of Ga, Ga and Al, Examples include Ga and Mn, or Ga and Co.

[0116] In this embodiment, a target for an oxide semiconductor (for an In-Ga-Zn-O-based oxide semiconductor) is Using a target (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]), The distance between the substrate and the target was 170 mm, the pressure was 0.4 Pa, and the DC power supply was 0.5 The first step was performed under an atmosphere of oxygen only, argon only, or argon and oxygen with a thickness of 10 nm. An oxide semiconductor layer is formed. In addition, In2O3:Ga2 A target with a composition ratio of O3:ZnO=1:1:1 [molar ratio] or In2O A target with a composition ratio of 3:Ga2O3:ZnO=1:1:4 [molar ratio] was used. In this embodiment, the crystallization is intentionally performed by performing a heat treatment later. It is preferable to use an oxide semiconductor target which is prone to crystallization.

[0117] The relative density of the oxide semiconductor in the oxide semiconductor target is 80% or more, preferably It is preferable that the relative density is 95% or more, and more preferably 99.9% or more. By using the get, the impurity concentration in the oxide semiconductor film to be formed can be reduced, and Therefore, a transistor having excellent thermal properties and high reliability can be obtained.

[0118] In addition, before the first oxide semiconductor layer was formed, the inner wall of the sputtering apparatus, the surface of the target, and the It is advisable to perform a preheat treatment to remove moisture or hydrogen from the target material. The deposition process involves heating the deposition chamber to 200°C to 600°C under reduced pressure. One method is to repeatedly introduce and exhaust nitrogen or inert gas while heating. After the substrate or the sputtering apparatus is cooled, the oxide semiconductor film is formed without being exposed to the air. In this case, it is better to use oil or fat as the target cooling liquid instead of water. Repeated nitrogen introduction and exhaust can produce a certain effect, but it is even better to do this while heating. stomach.

[0119] Next, the first oxide semiconductor layer is subjected to a first heat treatment to be at least partially crystallized. The temperature of the first heat treatment is 450° C. or higher and 850° C. or lower, preferably 550° C. or higher and 750° C. or lower. The heating temperature is set to 1 minute or more and 24 hours or less. A first oxide semiconductor layer 403 having a non-single crystal layer at least on the surface is formed (FIG. 2(A) ) The non-single crystal layer formed on the surface grows from the surface toward the inside, and the crystal grows at a rate of 2n The surface is a non-single crystal with an average thickness of 10 nm or more. The non-single crystal layer has a c-axis orientation perpendicular to the surface. The first heat treatment removes most of the first oxide semiconductor layer except for the vicinity of the gate insulating layer interface. Here is an example of polycrystal.

[0120] In the first heat treatment, nitrogen, oxygen, helium, neon, argon, or the like is used. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon is 6N (99.99 99%) or more, preferably 7N (99.99999%) or more (i.e. impurity concentration of 1pp It is preferable that the concentration of H2O is 20ppm or less, preferably 0.1ppm or less. The first heat treatment may be performed in ultra-dry air with a temperature of 0.1 to 1.5 m or less. The atmosphere inside the furnace is changed to nitrogen during heating and oxygen during cooling. After dehydration or dehydration is performed in a nitrogen atmosphere, the atmosphere is switched to an oxygen atmosphere. By paying attention to the above, oxygen can be supplied to the inside of the first oxide semiconductor layer to make it an i-type oxide semiconductor layer.

[0121] The heat treatment device used in the first heat treatment is not particularly limited, and may be a heat treatment device that uses a heat source such as a resistance heating element. The apparatus may include a device for heating the object to be treated by thermal conduction or thermal radiation from the object. For example, , electric furnaces, GRTA (Gas Rapid Thermal Anneal) equipment, L RTA (Lamp Rapid Thermal Annealing) equipment, etc. The LRTA device is a Halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps The light (electromagnetic waves) emitted by lamps such as high-pressure sodium lamps and high-pressure mercury lamps The GRTA device uses high-temperature gas to heat the object to be treated. This is a device that performs this function.

[0122] Next, a first oxide semiconductor layer 403 having a non-single crystal layer on at least the surface thereof was A second oxide semiconductor layer 404 having a thickness larger than that of the oxide semiconductor layer 403 is formed (FIG. 2 Note that the thickness of the second oxide semiconductor layer 404 may vary depending on the device to be manufactured. For example, when a bottom gate type transistor is fabricated, In this case, the total thickness of the first oxide semiconductor layer 403 and the second oxide semiconductor layer 404 is 10 The second oxide semiconductor layer is formed by emitting a rare gas (typically, In an atmosphere of rare gas (typically argon), in an atmosphere of oxygen, or in an atmosphere of rare gas (typically argon) and oxygen The film can be formed by a sputtering method.

[0123] The second oxide semiconductor layer 404 is made of a quaternary metal oxide, In-Sn-Ga-Zn -O-based films, ternary metal oxide films such as In-Ga-Zn-O-based films, In-Sn-Zn-O film, In-Al-Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film films, Sn-Al-Zn-O-based films, binary metal oxide In-Zn-O-based films, Sn- Zn-O based film, Al-Zn-O based film, Zn-Mg-O based film, Sn-Mg-O based film, In- Mg-O-based films, In-O-based films that are single-component metal oxides, Sn-O-based films, Zn-O-based films, etc. Any oxide semiconductor film can be used.

[0124] The first oxide semiconductor layer and the second oxide semiconductor layer 404 are made of materials containing the same components. or have the same crystal structure and close lattice constants (mismatch of 1% or less). When materials containing the same components are used, it is preferable to use the first Crystal growth can be easily performed using the non-single crystal layer of the oxide semiconductor layer of 1 as a seed. In the case of a material containing the above, the interface properties such as adhesion and electrical properties are also good.

[0125] Next, a second heat treatment is performed, and crystals are grown using the non-single crystal layer of the first oxide semiconductor layer as a seed. The temperature of the second heat treatment is 450° C. or higher and 850° C. or lower, preferably 550° C. or higher. The heating temperature is 750℃ or less. The heating time is 1 minute or more and 24 hours or less. Thus, the second oxide semiconductor layer is crystallized. Note that the oxide semiconductor stack 430 and the gate insulating film 440 are intentionally formed. The vicinity of the interface of the layer 402 is prevented from being crystallized. In this case, the non-crystalline layer in contact with the gate insulating layer is A single-crystal layer and a crystalline layer (here, a single-crystal layer of the first oxide semiconductor layer and a single-crystal layer of the second oxide semiconductor layer) are in contact therewith. If the non-single crystal stack of the nitride semiconductor layer is considered as one layer, it becomes a two-layer structure.

[0126] When the heating temperature of the second heat treatment is 550° C. or higher, the second oxide semiconductor layer 404 becomes thick. In this case, a crystal layer grows downward from the surface, and a crystal layer grows upward from the first oxide semiconductor layer as a seed. In this case, an amorphous layer may be formed between the gate insulating layer and the amorphous layer. It has a four-layer structure: an crystalline layer, a crystalline layer on top of that, an amorphous layer on top of that, and a crystalline layer on top of that. In the present embodiment, a stack of the non-single-crystal first oxide semiconductor layer and the non-single-crystal second oxide semiconductor layer is regarded as one layer. This is referred to as a four-layer structure.

[0127] Depending on the material of the second oxide semiconductor layer 404, the heating temperature of the second heat treatment may be set to 50 If the temperature is less than 0° C., crystal growth from the surface does not proceed, and the crystal grows upward using the first oxide semiconductor layer as a seed. In this case, a crystalline layer may be formed on the gate insulating layer. The first oxide semiconductor layer is a crystalline layer, and the second oxide semiconductor layer is an amorphous layer. The stack of the non-single-crystal oxide semiconductor layer and the non-single-crystal oxide semiconductor layer is regarded as one layer and is called a three-layer structure. In this manner, the material of the second oxide semiconductor layer 404, the thickness thereof, and the second heat treatment Since various lamination structures can be obtained by changing the heating conditions, the practitioner can select the desired lamination structure. In addition, the material of the second oxide semiconductor layer 404, the thickness thereof, and the temperature of the second heat treatment are It is important to adjust the conditions appropriately.

[0128] Note that the region of the oxide semiconductor stack 430 that overlaps with the irregularities of the gate insulating layer has a grain boundary. In addition, the region to be the channel formation region of the oxide semiconductor stack 430 is The region has at least a flat surface, and the first oxide semiconductor layer and the second oxide semiconductor layer are the same c The oxide semiconductor stack 430 is a non-single-crystal structure having an axial alignment. In the grown region, the a-axis and b-axis of the polycrystal are also misaligned.

[0129] In FIG. 2A, FIG. 2B, and FIG. 2C, the uncrystallized gate insulating layer 402 and The interface between the gate insulating layer and the semiconductor layer is not shown in the figure, but the interface with the gate insulating layer is clearly explained. In order to clarify the above, the enlarged schematic diagrams of Fig. 1(A), Fig. 1(B), and Fig. 1(C) are shown. 1A, where the base member 520 corresponds to the gate insulating layer 402. FIG. 2B corresponds to FIG. 1B, and shows the second oxide member 522 immediately after deposition. FIG. 2(C) corresponds to FIG. 1(C) and is a cross-sectional view after the second heat treatment. FIG.

[0130] In the second heat treatment, nitrogen, oxygen, helium, neon, argon, etc. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gas such as helium, neon, or argon is preferably 6N or more. At most 7N or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). It is also preferable to carry out the second heat treatment in ultra-dry air with an H2O content of 20 ppm or less. In addition, the inside of the furnace may be in a nitrogen atmosphere during the heating of the second heat treatment, and in a nitrogen atmosphere during the cooling of the furnace. The atmosphere inside may be changed to an oxygen atmosphere.

[0131] The heat treatment device used for the second heat treatment is not particularly limited, and may be a heat treatment device that uses a heat source such as a resistance heat source. The apparatus may include a device for heating the object to be treated by thermal conduction or thermal radiation from the object. For example, An electric furnace or an RTA device such as a GRTA device or an LRTA device can be used.

[0132] Next, an oxide semiconductor stack 43 including a first oxide semiconductor layer and a second oxide semiconductor layer is formed. 0 is processed into an island-shaped oxide semiconductor stack 431 by a photolithography process (FIG. 2(D) ). In addition, a resist mask for forming the island-shaped oxide semiconductor stack 431 was If the resist mask is formed by the inkjet method, the photoresist can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0133] Next, the gate insulating layer 402 and the island-shaped oxide semiconductor stack 431 are formed by a sputtering method or the like. After forming a metal conductive film, a resist mask is formed by a photolithography process. Selective etching is performed to form the metal electrode layer.

[0134] Metal conductors that will later become source and drain electrodes (including wiring formed in the same layer) The material of the conductive film is a metal material such as Al, Cu, Cr, Ta, Ti, Mo, or W, or The metal layer is made of an alloy material containing the metal material. A high melting point metal layer such as Cr, Ta, Ti, Mo, or W is laminated on one or both sides of the upper surface. In addition, Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y, etc. l) Uses an Al material that contains elements that prevent the formation of hillocks and whiskers in the film. This makes it possible to improve heat resistance.

[0135] For example, the metal conductive film may be a titanium layer, an aluminum layer on the titanium layer, and a titanium film on the aluminum layer. A three-layer laminate structure in which a titanium layer is laminated on a molybdenum layer, or an aluminum layer on a molybdenum layer and the aluminum layer on the molybdenum layer It is preferable to use a three-layer laminate structure in which a molybdenum layer is laminated on a gold layer. The metal conductive film is a two-layer laminated structure of an aluminum layer and a tungsten layer, and the other is a copper layer and a tungsten layer. Two-layer laminated structure with a tin layer and a molybdenum layer, two-layer laminated structure with an aluminum layer and a molybdenum layer It is also possible to use a laminated structure. Of course, the metal conductive film may be a single layer or a laminated structure of four or more layers. It is also possible to use the following.

[0136] Also, the metal that will become the source electrode and drain electrode (including the wiring formed in the same layer as these) The conductive film may be made of a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide Zinc oxide alloy (In2O3-ZnO) or the above metal oxide materials with silicon or oxide Silicon-containing materials can be used.

[0137] Next, the resist mask is removed, and a resist mask is formed by a photolithography process. Then, the source electrode layer 405a and the drain electrode layer 405b are formed by selectively etching the source electrode layer 405a and the drain electrode layer 405b. After the formation, the resist mask is removed (see FIG. 2(E)). In the roughening process, only a part of the island-shaped oxide semiconductor stack 431 is etched, and the groove (concave) is formed. In some cases, the oxide semiconductor layer may have a gate insulating film.

[0138] As shown in FIG. 2E, the gate electrode layer 401 is connected to a source electrode layer 405a (or Another feature is that the source electrode layer has a region overlapping with the drain electrode layer 405b. The edge of 405a and the step of the gate insulating layer 402, that is, the flat surface of the gate insulating layer in the cross-sectional view, The area between the point where the flat surface changes to the tapered surface (here, the L shown in Figure 2(E)) OV territory The oxide semiconductor stack 432 has a L region. OV The region is the unevenness of the edge of the gate electrode layer. This is important to prevent carriers from flowing through the grain boundaries that arise in the

[0139] In addition, the source electrode layer 405a or the drain electrode layer 405b is formed on the side surface of the oxide semiconductor stack 432. The non-single crystal layer in contact with the electrode layer 405b may be in an amorphous state.

[0140] In addition, a resist pattern for forming the source electrode layer 405a and the drain electrode layer 405b was formed. The resist mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0141] In order to reduce the number of photomasks and steps used in the photolithography process, The resist pattern is formed by a multi-tone mask, which is an exposure mask that allows the light to be projected at multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. This allows for multiple etching processes to be performed to create different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0142] Next, an oxide insulating layer 407 serving as a protective insulating film in contact with part of the oxide semiconductor layer is formed. .

[0143] The oxide insulating layer 407 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The layer 407 can be formed by appropriately using a method that does not allow impurities such as water and hydrogen to be mixed into the layer 407 . In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as the oxide insulating layer 407 by a sputtering method. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower. The temperature is set to 100°C in this embodiment. The deposition of silicon oxide film by sputtering method is performed using rare gas (typically a In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering in air. The oxide insulating layer 407 formed in contact with the - Impurities such as It uses an inorganic insulating film that does not contain any substances and blocks the intrusion of these substances from the outside. Silicon oxide film, silicon nitride film, aluminum oxide film, aluminum oxynitride film, etc. Further, a protective insulating film such as a silicon nitride film or an aluminum nitride film is formed on the oxide insulating layer 407. A border layer may be formed.

[0144] In addition, before the oxide insulating layer 407 is formed, the inner wall of the sputtering apparatus, the surface of the target, and the It is advisable to perform a preheating process to remove moisture or hydrogen from the getter material. After the sputtering process is completed, cool the substrate or the sputtering device and then immerse it in an oxide insulator without exposing it to the air. In this case, it is better to use oil or fat as the target cooling liquid instead of water. Repeated nitrogen introduction and exhaust without heating can produce a certain effect, but And even better.

[0145] After the oxide insulating layer 407 is formed, a nitride semiconductor layer is formed by a sputtering method without exposure to air. A structure in which silicon nitride films are laminated may be formed.

[0146] In addition, the oxide insulating layer 407 and the gate insulating layer 402 are A contact hole is formed through the gate electrode layer 401, and the contact hole is electrically connected to the gate electrode layer 401 to apply a gate potential. A connection electrode for forming the gate insulating layer 402 may be formed over the oxide insulating layer 407. After that, a contact hole is formed to reach the gate electrode layer 401, and a source electrode layer or A connection electrode is formed from the same material as the drain electrode layer, and an oxide insulating layer 407 is formed on the connection electrode. Then, a contact hole reaching the connection electrode is formed in the oxide insulating layer 407. An electrode for applying a gate potential is formed on the oxide insulating layer 407. It may be possible to do so.

[0147] Through the above steps, a transistor 470 is formed (see FIG. 3B). 3B illustrates an example of a top view of the transistor 470. Note that FIG. 3B illustrates the transistor 470 along the dashed line C in FIG. This corresponds to the cross-sectional view taken along line 1-C2.

[0148] In the transistor 470, the upper surface of the gate electrode layer in the channel formation region is flattened. The oxide member has a c-axis oriented perpendicular to the surface of the source electrode layer or the drain electrode. One of the features of the electrode layer is that it overlaps even the unevenness caused by the edge of the gate electrode layer. The oxide member (the oxide semiconductor stack 432 in this embodiment) is formed on the substrate side when the substrate side has unevenness. In this case, the region where the recesses collide will be polycrystalline with grain boundaries. By forming the Lov region, the crystal grain boundary generated by the unevenness at the edge of the gate electrode layer is filled with Therefore, in the transistor 470, the carrier is prevented from flowing. The source electrode layer or the drain electrode layer is provided over the flat portion of the gate electrode. The electrode layer has an overlap.

[0149] Note that the surface of the gate insulating layer overlapping the channel formation region of the transistor 470 is uneven. The difference is 1 nm or less, preferably 0.2 nm or less. The channel forming region is non-single crystal.

[0150] In the transistor 470 shown in FIG. 3B, a crystal layer is intentionally provided at a distance from a gate insulating layer. Therefore, the channel formation region is not formed at the interface with the gate insulating layer, but at the interface between the gate insulating layer and the The effect of scattering at the interface between the gate insulating layer and the oxide member is reduced. is reduced.

[0151] The first and second heat treatments are used to crystallize the semiconductor and oxidize hydrogen, which is an n-type impurity. It is a high-purity material that is removed from semiconductors and contains as few impurities as possible other than the main components of oxide semiconductors. In other words, impurities are added to the By removing impurities such as hydrogen and water as much as possible, the product is highly purified. By purifying the oxide semiconductor layer, the The threshold voltage of the transistor can be set to a positive value, making it a so-called normally-off transistor. It is possible to achieve Star 470.

[0152] It is needless to say that the structure of the transistor 470 shown in FIG. As long as it is a bottom gate type transistor, for example, the source electrode layer in FIG. In order to protect the channel formation region from etching damage during the formation of the drain electrode layer, A channel stop type transistor in which an oxide insulating layer overlapping the It can also be used as a star.

[0153] In addition, an electrode layer capable of functioning as a back gate is provided over the oxide insulating layer 407. The potential of the back gate may be a fixed potential, for example, 0 V or a ground potential. In addition, gate electrodes may be provided above and below the oxide semiconductor layer. The bias-thermal stress test (BT) is used to check the reliability of transistors. In this test, the change in the threshold voltage of a transistor before and after the BT test is measured. That is, by providing gate electrodes above and below the oxide semiconductor layer, The reliability can be improved. In addition, the gate voltage applied to the back gate can be controlled. The threshold voltage can be controlled by the In addition, the threshold voltage can be set to negative. For example, the enhancement transistor can be used as a depletion transistor. The inverter circuit (hereafter called the The driver circuit can be configured as an EDMOS circuit. The logic circuit section includes at least one of a switch section and a buffer section. The circuit configuration includes an OS circuit.

[0154] The operating principle of a bottom-gate transistor using an oxide semiconductor is described below. Reveal.

[0155] FIG. 7 is a cross-sectional view of a transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the gate insulating film (GI) and a source A source electrode (S) and a drain electrode (D) are provided. The oxide insulating layer covering the gate electrode (D) is overlapped with the channel formation region of the oxide semiconductor layer (OS). The back gate (GE2) is

[0156] FIG. 8 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. (A) shows the case where the voltage between the source and drain is equipotential (VD=0V), as shown in Fig. 8( B) shows the case where a positive potential (VD>0) is applied to the drain with respect to the source.

[0157] FIG. 9 shows an energy band diagram (schematic diagram) in a cross section taken along line B-B′ in FIG. 7; The gate voltage is 0V. Figure 9(A) shows the state when a positive voltage ( VG>0) is applied, and carriers (electrons) exist between the source and drain electrodes. FIG. 9B shows the ON state when a negative voltage is applied to the gate electrode (GE1). When (VG<0) is applied and the device is in the off state (no minority carriers flow) Shows.

[0158] The thickness of the oxide semiconductor is about 50 nm, and the oxide semiconductor is highly purified. Donor concentration is 1 x 10 18 / cm 3 If the depletion layer is less than 100%, the depletion layer will be In other words, it can be considered as a fully depleted state.

[0159] Figure 10 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Indicates the relationship.

[0160] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are generally n-type, and the Fermi level (E F ) is a band The intrinsic Fermi level (E i ) and is located closer to the conduction band. In addition, part of hydrogen in an oxide semiconductor becomes a donor, which is one of the reasons for its n-type nature. It is known that...

[0161] In contrast, the oxide semiconductor according to the present invention can remove n-type impurities, such as hydrogen, from the oxide semiconductor. By removing impurities from the oxide semiconductor, the oxide semiconductor is highly purified so that it contains as few impurities as possible other than the main component. It is more intrinsic (type i) or is intended to be intrinsic. By removing impurities such as hydrogen and water as much as possible, the product is highly purified. The feature is that it is an i-type (intrinsic semiconductor) or close to it. Elmi level (E F ) is the intrinsic Fermi level (E i ) can be brought to the same level.

[0162] The oxide semiconductor has a band gap (Eg) of 3.05 eV to 3.15 eV. When the band gap (Eg) of an oxide semiconductor is 3.15 eV, the electron affinity (χ) is The specification of titanium (Ti) that constitutes the source and drain electrodes is 4.3 eV. The charge function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, At the interface between the two layers, no Schottky barrier is formed for electrons.

[0163] That is, the work function of the metal (φ M ) is equal to the electron affinity (χ) of the oxide semiconductor, When the two come into contact, an energy band diagram (schematic diagram) like that shown in FIG. 8(A) is displayed.

[0164] In FIG. 8(B), black circles (●) represent electrons. When a positive potential is applied to the drain, The electrons cross the barrier (h) and are injected into the oxide semiconductor, where they flow toward the drain. In this case, the barrier height (h) changes depending on the gate voltage and the drain voltage. When a bias voltage is applied, the barrier height, i.e., the barrier height in FIG. 8(A) without voltage application, The barrier height (h) is smaller than half the gate gap (Eg).

[0165] At this time, the electrons pass through the gate insulating film and the highly purified oxide semiconductor as shown in FIG. The electrons move through the lowest energetically stable portion on the oxide semiconductor side at the interface with the oxide semiconductor.

[0166] In FIG. 9B, a negative potential (reverse bias) is applied to the gate electrode (GE1). When the current is increased, the number of holes, which are minority carriers, is essentially zero, so the current approaches zero. The value becomes

[0167] In this way, the oxide semiconductor is highly purified so that impurities other than the main component are not included as much as possible. By making it intrinsic (i-type) or substantially intrinsic, the interface characteristics with the gate insulating film can be improved. Therefore, it is necessary to consider the gate insulating film separately from the bulk characteristics. For example, the VHF band to Insulating film produced by CVD using high-density plasma generated at power supply frequencies in the microwave range Alternatively, it is preferable to use an insulating film formed by a sputtering method.

[0168] The oxide semiconductor is highly purified while maintaining a good interface between the oxide semiconductor and the gate insulating film. By doing so, the transistor characteristic channel width W is 1×10 4 Channel length in μm Even with a 3 μm element, the off-current is 10 -13 A or less, and subthreshold The switching value (S value) is 0.1V / dec. (gate insulating film thickness 100nm) is expected.

[0169] In this way, the oxide semiconductor is highly purified so that impurities other than the main component are not included as much as possible. This allows a non-single crystal to be formed, and the operation of the transistor can be improved.

[0170] (Embodiment 2) In the first embodiment, the first oxide member and the second oxide member contain the same component. In this embodiment, a case where an oxide semiconductor material having a different composition is used is described. Indicates the combination.

[0171] As in the first embodiment, the first heat treatment causes crystal growth from the surface, but the first oxide crystal does not grow. The tip of the crystal member 521b does not reach the interface with the base member 520, and the region is in an amorphous state. 521a is left (see FIG. 11(A)). In FIG. 11(A), the same as FIG. The same parts will be described using the same reference numerals.

[0172] Next, in FIG. 11(B), a second oxide member 532 is formed on the first oxide crystal member 521b. The second oxide member 532 is a cross-sectional view of the first oxide crystal member 521. b is made of a different material.

[0173] After the second oxide member 532 is formed, a second heat treatment is performed. As shown in FIG. 11(C), the crystal growth is performed. The non-single crystal layer of the oxide member 521b is used as a seed to grow upward toward the surface of the second oxide member. The crystal grows to form a second oxide crystal member 533b. In order to use an oxide semiconductor material having a different composition from that of the first oxide crystal member 521b, As shown in FIG. 1C, the first oxide crystal member 521b and the second oxide crystal member 533b The second heat treatment also forms a boundary between the first and second gate electrodes, except for the gate insulating layer interface. Most of the oxide semiconductor layer 1 is a crystalline region.

[0174] The structure of FIG. 11C includes a region 533c that is in contact with the base member 520 and remains in an amorphous state, The first oxide crystal member 533a is stacked on top of the first oxide crystal member 533a, and the second oxide crystal member 533b is stacked on top of the first oxide crystal member 533a. It can be said to have a layered three-layer structure.

[0175] In addition, when the second oxide crystal material to be grown is the same as the first oxide crystal material to be the base, This is called homoepitaxy (homo crystal growth). Also, the second oxide crystal material to be grown When the first oxide crystal material is different from the first oxide crystal material, heteroepitaxy (hetero crystal growth) is used. In the present embodiment, either of these is possible depending on the selection of the respective materials.

[0176] The conditions of the first heat treatment and the second heat treatment are within the ranges of conditions described in the first embodiment. Note that the region 533c that is intentionally left in an amorphous state is in contact with the surface of the base member 520. The practitioner should appropriately select the conditions that will remain.

[0177] In addition, this embodiment mode can be freely combined with the first embodiment mode.

[0178] (Embodiment 3) In this embodiment, a transistor including a laminated oxide material having a crystal layer in which a plurality of crystals are c-axis oriented is used. A transistor is manufactured, and the transistor is used in a pixel portion and further in a driver circuit to provide a display function. A case of manufacturing a semiconductor device (also called a display device) using a transistor will be described. The driver circuit and the pixel section are integrated on the same substrate, forming a system on a panel. A cell can be formed.

[0179] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0180] The display device includes a panel in which a display element is sealed, and a controller for the panel. The display device further includes a module in which an IC or the like including the display device is mounted. In the process of manufacturing the display device, the element substrate corresponds to a form before the display device is completed. The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, only the pixel electrodes of the display element may be formed, or the pixel electrodes and After forming the conductive layer, and before etching to form the pixel electrode, is fine, and all forms apply.

[0181] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0182] In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device which is one embodiment of the present invention. First, the appearance and cross section of a liquid crystal display panel, which corresponds to one embodiment of a semiconductor device, will be described with reference to FIG. FIG. 12 shows a semiconductor device having a c-axis oriented crystal layer formed on a first substrate 4001. Transistors 4010 and 4011 including a stacked oxide material as a semiconductor layer, and a liquid crystal element The panel is formed by sealing the first substrate 4013 with a second substrate 4006 using a sealant 4005. FIG. 12(B) is a top view, and corresponds to a cross-sectional view at MN in FIG. 12(A1) and (A2). do.

[0183] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is a circuit including a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor or a polycrystalline semiconductor is mounted.

[0184] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 12A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0185] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 12B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4011 included in the scanning line driver circuit 4004. Insulating layers 4020 and 4021 are provided on the transistors 4010 and 4011. There are.

[0186] The transistors 4010 and 4011 have a c-axis oriented crystal layer as described in the first embodiment. A transistor including a stacked oxide material can be used. The transistors 4010 and 4011 are n-channel transistors.

[0187] The oxide semiconductor layer of the transistor 4011 for the driver circuit is formed over the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping the panel formation region. By providing the semiconductor layer at a position overlapping the channel formation region, It is possible to reduce the amount of change in the threshold voltage of the transistor 4011. The potential of the gate electrode layer of the transistor 4011 may be the same as that of the gate electrode layer of the transistor 4011 or may be different. The conductive layer 4040 may also function as a second gate electrode layer. The potential may be GND, 0V, or may be floating.

[0188] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 is formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between layers 4032 and 4033 .

[0189] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Alternatively, you can use aluminum foil with a PVF film or polyester film. A sheet having a structure sandwiched between films can also be used.

[0190] Also, 4035 is a columnar spacer obtained by selectively etching the insulating layer. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031, A spherical spacer may be used. 1 is electrically connected to a common potential line provided on the same substrate as the transistor 4010. In addition, the common connection portion is used to connect the opposing electrode layer via conductive particles disposed between the pair of substrates. The conductive particles can be used as a sealing material. Include in 4005.

[0191] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0192] In addition, if a liquid crystal that exhibits a blue phase is used, rubbing treatment of the alignment film is not required. This prevents electrostatic damage caused by the soldering process, and prevents the LCD display from being damaged during the manufacturing process. This reduces the number of defects and damages to the device, thereby improving the productivity of liquid crystal display devices. In particular, a transistor including an oxide semiconductor layer can be easily damaged by static electricity. The electrical characteristics of the transistor may vary significantly and deviate from the design range. A liquid crystal display device having a transistor using a blue phase liquid crystal material is provided. is more effective.

[0193] Note that the liquid crystal display device shown in this embodiment is an example of a transmission type liquid crystal display device. The device can be applied to both a reflective liquid crystal display device and a semi-transmissive liquid crystal display device.

[0194] In the liquid crystal display device shown in this embodiment mode, a polarizing plate is provided on the outer side (the viewing side) of the substrate. In this example, a colored layer and an electrode layer for use in a display element are provided on the side of the substrate in this order. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and the polarizing plate may be provided in the same manner. The thickness may be appropriately set depending on the material of the colored layer and the manufacturing process conditions. A light-shielding layer that functions as a light-shielding matrix may be provided.

[0195] In this embodiment, in order to reduce the surface unevenness of the transistor and To improve reliability, the transistor is covered with an insulating layer ( The insulating layer 4020 and the insulating layer 4021 are used to cover the insulating layer. It is designed to prevent the intrusion of airborne organic matter, metals, water vapor and other contaminating impurities. The protective layer is preferably a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like, which is formed by sputtering. A silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer The insulating film 11 may be formed of a single layer of aluminum oxide or a single layer of aluminum nitride oxide. Although the protective layer is formed by sputtering in the example shown, the method is not particularly limited and may be formed by various methods. stomach.

[0196] Here, an insulating layer 4020 having a laminated structure is formed as a protective layer. A silicon oxide layer is formed as the first layer of the first insulating film by sputtering. By using the above, it is possible to prevent hillocks on the aluminum layer used as the source electrode layer and the drain electrode layer. It is effective in stopping.

[0197] In addition, an insulating layer is formed as the second layer of the protective layer. A silicon nitride layer is formed by sputtering. When a silicon nitride layer is used as a protective layer, Prevents ions such as thorium from penetrating the semiconductor region and changing the electrical characteristics of the TFT. It can be controlled.

[0198] In addition, an insulating layer 4021 is formed as a planarizing insulating layer. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. are used. In addition, by laminating multiple insulating layers made of these materials, 4021 may be formed.

[0199] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0200] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, In the step of bonding, the semiconductor layer may be annealed (at 300° C. to 400° C.) at the same time. By combining the firing process of the edge layer 4021 with the annealing process of the semiconductor layer, a semiconductor device can be efficiently manufactured. It becomes possible to do so.

[0201] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0202] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0203] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0204] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0205] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. 30, and the terminal electrode 4016 is formed from the same conductive layer as the transistors 4010, 4011. The source electrode layer and the drain electrode layer are formed from the same conductive layer as the source electrode layer and the drain electrode layer.

[0206] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive layer 4019. The electrodes are electrically connected to each other.

[0207] In FIG. 12, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0208] If necessary, a color filter is provided for each pixel. A polarizing plate and a diffusing plate are provided on the outside of the first and second substrates 4001 and 4006. The source is composed of cold cathode fluorescent lamps and LEDs, forming a liquid crystal display module.

[0209] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0210] Through the above steps, a highly reliable liquid crystal display device can be manufactured.

[0211] In addition, the method for producing a laminated oxide material having a c-axis oriented crystal layer shown in the first embodiment is used. By fabricating a transistor for a driving circuit of a liquid crystal display device using the This allows the starter to be normally off, thereby saving power.

[0212] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0213] (Embodiment 4) The appearance and cross section of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of a semiconductor device This will be described with reference to FIG. 13. FIG. 13 shows a c-axis oriented crystal formed on a first substrate. A transistor and a light-emitting element including a laminated oxide material having a crystal layer are formed between a second substrate and the transistor and the light-emitting element. FIG. 13(B) is a plan view of the panel sealed with a sealing material, and FIG. 13(A) is a plan view of the panel sealed with a sealing material. This corresponds to the cross-sectional view in I.

[0214] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0215] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. In FIG. 13B, a transistor 4510 included in a pixel portion 4502 and a signal line driver A transistor 4509 included in the circuit 4503a is illustrated.

[0216] The transistors 4509 and 4510 have a c-axis oriented crystal layer as described in the first embodiment. A highly reliable transistor including a laminated oxide material can be applied. In this figure, the transistors 4509 and 4510 are n-channel transistors.

[0217] A channel of an oxide semiconductor layer of a transistor 4509 for a driver circuit is formed over an insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the hole formation region. By placing the conductor layer at a position overlapping the channel formation region, The amount of change in the threshold voltage of the transistor 4509 can be reduced. 40 may have the same potential as the gate electrode layer of the transistor 4509 or may have a different potential. Alternatively, the conductive layer 4540 may function as a second gate electrode layer. may be GND, 0V, or floating.

[0218] The transistor 4509 is in contact with a semiconductor layer including a channel formation region as an insulating layer. The insulating layer 4541 is the oxide insulating layer 4441 described in Embodiment 1. The same materials and methods as those used in 07 may be used. In this embodiment, the insulating layer 4544 is covered with the insulating layer 4544, which functions as a planarizing insulating layer. As the edge layer 4541, a silicon oxide layer is formed by sputtering.

[0219] The insulating layer 4544 is formed using a material and a method similar to those of the insulating layer 4021 described in Embodiment 3. Here, acrylic is used as the insulating layer 4544.

[0220] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. The light emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer 45 12, the second electrode layer 4513 has a stacked structure, but is not limited to the structure shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from 4511. This can be done.

[0221] The partition 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0222] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0223] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective layer may be formed over 4513 and the partition wall 4520. The protective layer may be a silicon nitride layer, A silicon oxynitride layer, a DLC layer, or the like can be formed.

[0224] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0225] The connection terminal electrode 4515 is a conductive layer that is the same as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source voltages of the transistors 4509 and 4510. The positive electrode layer and the drain electrode layer are formed from the same conductive layer.

[0226] The connection terminal electrode 4515 is connected to a terminal of the FPC 4518a via an anisotropic conductive layer 4519. The electrodes are electrically connected to each other.

[0227] The substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or an acrylic film A light-transmitting material such as film is used.

[0228] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0229] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0230] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driver circuit formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate. Also, only the signal line driver circuit, or a part of the scanning line driver circuit, Only one or a part of the components may be separately formed and mounted, and the configuration is not limited to that shown in FIG.

[0231] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured.

[0232] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0233] (Embodiment 5) An example of electronic paper will be shown as one mode of a semiconductor device.

[0234] The present invention includes a laminated oxide material having a c-axis oriented crystal layer obtained by the method shown in the first embodiment. The transistors used in the design use switching elements and electrically connected elements to drive electronic ink. The electronic paper may be used for an electrophoretic display device (electrophoretic display). It is also called a digital display, and has the same readability as paper, low power consumption compared to other display devices, This has the advantage that it can be made thin and lightweight.

[0235] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. In addition, the first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0236] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0237] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0238] In addition, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. For example, the c-axis oriented liquid crystal of the first embodiment Active matrix obtained by transistors including laminated oxide materials having crystalline layers A substrate can be used.

[0239] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0240] FIG. 14 shows an active matrix type electronic paper as an example of a semiconductor device. The transistor 581 used in the device is the same as the transistor described in Embodiment 1. The transistors can be fabricated easily and have high reliability, including stacked oxide materials with c-axis oriented crystal layers. It is.

[0241] The electronic paper in FIG. 14 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0242] The transistor 581 is a bottom-gate transistor and is in contact with an oxide semiconductor layer. The source electrode layer or the drain electrode layer of the transistor 581 is covered with an insulating layer 583. The first electrode layer 587 is in contact with the insulating layers 583, 584, and 585 through openings. The first electrode layer 587 and the second electrode layer 588 are electrically connected to each other. 0a and white area 590b, and includes a cavity 594 filled with liquid therearound. A spherical particle 589 is provided between a pair of substrates 580 and 596. The surrounding area is filled with a filler 595 such as resin (see FIG. 14).

[0243] The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common potential line provided over the same substrate as the transistor 581. The common connection portion is electrically connected to the pair of substrates via conductive particles disposed between the pair of substrates. The second electrode layer 588 and the common potential line can be electrically connected to each other through this.

[0244] Also, instead of the element using the twist ball, an electrophoretic element can be used. A transparent liquid is enclosed in a 1 mm diameter tube containing positively charged white particles and negatively charged black particles. Microcapsules with a size of about 0 μm to 200 μm are used. The microcapsules placed between the first and second electrode layers are subjected to an electric field. When the light is turned on, the white particles and black particles move in opposite directions, resulting in a white or black display. A display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, the auxiliary lines No light is required, the power consumption is low, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display unit, the image once displayed is retained. Therefore, it is possible to transmit a signal from a radio wave source to a semiconductor device with a display function (simply a display device or a display). The displayed image is preserved even if the device (also called a semiconductor device having a display device) is moved away. It is possible to keep it.

[0245] Through the above steps, highly reliable electronic paper can be manufactured.

[0246] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0247] (Embodiment 6) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0248] In this embodiment, an electronic device equipped with the display device obtained in any one of the third to fifth embodiments is provided. An example of the device will be described with reference to FIG.

[0249] FIG. 15(A) shows a notebook-type PC manufactured by mounting at least a display device as one component. A personal computer, comprising a main body 3001, a housing 3002, a display unit 3003, and a keyboard. The liquid crystal display device shown in the third embodiment is configured as a notebook PC. The type of personal computer has

[0250] FIG. 15B shows a portable information terminal ( The main body 3021 is a display unit 3023 and an external interface 3025. , operation buttons 3024, etc. are provided. In addition, a stylus 302 is provided as an accessory for operation. Note that the portable information terminal has the light-emitting display device described in Embodiment 4.

[0251] FIG. 15C shows an electronic device manufactured by mounting the electronic paper shown in the embodiment 5 as one component. FIG. 15C shows an example of an electronic book. For example, electronic book 2700 The device is composed of two housings, a housing 2701 and a housing 2703. The housing 2703 is integrated with a shaft portion 2711 and opens around the shaft portion 2711. This configuration allows the book to be operated like a paper book. It becomes possible.

[0252] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2705 in FIG. 15C) and An image can be displayed on the display portion (the display portion 2707 in FIG. 15C).

[0253] FIG. 15C shows an example in which an operating unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. A keyboard and a pointing device may be provided on the rear of the housing. On the front or side of the device, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB Equipped with a terminal that can be connected to various cables such as USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to function as an electronic dictionary. It is also possible to use the following.

[0254] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0255] FIG. 15(D) shows a mobile phone manufactured by mounting at least a display device as a component. The device is made up of two housings, a housing 2800 and a housing 2801. The housing 2801 has a front A display panel 2802, a speaker 2803, a microphone 2804, a pointing device The camera includes a seat 2806, a camera lens 2807, and an external connection terminal 2808. The housing 2800 includes a solar cell 2810 for charging the portable information terminal, an external memory storage The antenna is built into the housing 2801. .

[0256] The display panel 2802 is equipped with a touch panel, and in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also implements a boost circuit to boost the input voltage to the voltage required for each circuit.

[0257] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera 2802, so video calls are possible. The speaker 2803 and the microphone 2804 are not limited to voice calls, but can also be used for video calls. , recording, playback, etc. are possible. Furthermore, the housing 2800 and the housing 2801 can be slid apart, As shown in Figure 15(D), the device can be folded from the unfolded state to the overlapped state, making it easy to carry. Suitable miniaturization is possible.

[0258] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. A recording medium can be inserted into the memory slot 2811 to accommodate larger amounts of data storage and transfer. do.

[0259] In addition to the above functions, it also has infrared communication function, TV reception function, etc. Good too.

[0260] FIG. 15(E) shows a digital camera manufactured by mounting at least a display device as one component. There is a main body 3051, a display unit (A) 3057, an eyepiece unit 3053, an operation switch 3054, It is composed of a display unit (B) 3055, a battery 3056, and the like.

[0261] This embodiment mode can be freely combined with any one of the embodiment modes 1 to 5. EXAMPLES

[0262] In this example, an experiment was conducted to stack oxide members with different target compositions, and cross-sectional observation was performed. I did.

[0263] The sample was a 30 nm thick silicon oxynitride film (undercoat film) formed on a glass substrate by PCVD. After that, an In-Ga-Zn-O film is formed with a thickness of 5 nm, and a first heat treatment is performed. After that, an In-Ga-Zn-O film was formed with a thickness of 30 nm, and a second heat treatment was performed.

[0264] In sample 1, the deposition conditions for the 5 nm In-Ga-Zn-O film were In2O3:Ga2O 3: A metal oxide target of ZnO = 1:1:2 [molar ratio] was used, and the pressure was 0.6 Pa. , DC power supply 5kW, oxygen and argon mixed atmosphere (oxygen flow rate 50sccm, Ar The film was deposited at a deposition rate of 13.4 nm / min under a substrate temperature of 200°C and a gas flow rate of 50 sccm. The first heat treatment was performed in a nitrogen atmosphere at 650° C. for 6 minutes. The conditions for forming the 30 nm In-Ga-Zn-O film after the treatment were In2O3:Ga A metal oxide target of 2O3:ZnO = 1:1:1 [molar ratio] was used, and the pressure was 0.6 P a, DC power supply 0.5 kW, oxygen atmosphere (oxygen flow rate 20 sccm), substrate temperature The film was formed at room temperature at a film formation rate of 13.4 nm / min. The second heat treatment was performed in a nitrogen atmosphere. The heating was performed at 650°C for 6 minutes in an atmospheric environment.

[0265] When the cross section of the sample 1 thus obtained was observed, it was found that the thickness of the sample 1 was 3.5 nm to 5 nm from the surface of the base film. It was confirmed that the In-Ga-Zn-O film had crystallized to a thickness of 0.2 nm, and the In-Ga-Zn-O film underneath had a surface It was confirmed that the surface was crystallized from 1.2 to 1.5 nm. The region from 6 nm to 34 nm from the surface was in an amorphous state.

[0266] The interface between the In-Ga-Zn-O film and the undercoat film is not crystallized and is in an amorphous state. I was able to confirm something.

[0267] In addition, as a comparative example, a cross-section of Sample 2, which was not subjected to the second heat treatment, was observed. Furthermore, the lower In-Ga-Zn-O film was crystallized from the surface to 0.5 to 1.5 nm. In sample 2, a 5 nm In-Ga-Zn-O film was added to the 5 nm In-Ga-Zn-O film of sample 1. The In-Ga-Zn-O film was deposited under the same deposition conditions as the In-Ga-Zn-O film in The deposition conditions for the O film were: In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] metal Using an oxide target, the pressure was 0.6 Pa, the direct current (DC) power was 5 kW, and oxygen and argon were mixed. Mixed atmosphere (oxygen flow rate 50sccm, argon flow rate 50sccm), substrate temperature 200℃ The film was formed at a film formation rate of 13.4 nm / min.

[0268] In addition, the sample was prepared under the same conditions as sample 2, and then heated at 650°C for 6 minutes in a nitrogen atmosphere. When the cross section of sample 3, which had been subjected to the heat treatment of 2, was observed, the upper I It was confirmed that crystallization proceeded with orientation up to the surface of the n-Ga-Zn-O film. The crystallized film thickness was 28 nm to 30 nm. The interface between the n-Ga-Zn-O film and the undercoat film is not crystallized and is in an amorphous state. was confirmed.

[0269] Sample 4 was prepared by forming a silicon oxynitride film (undercoat film) with a thickness of 30 nm on a glass substrate. After forming it by PCVD method, In-Ga-Zn-O film was formed at 3 nm setting, and the first After the heat treatment, an In-Ga-Zn-O film was formed with a thickness of 30 nm, and a second heat treatment was performed. The deposition conditions for the 3 nm and 30 nm In-Ga-Zn-O films were In A metal oxide target of 2O3:Ga2O3:ZnO=1:1:2 [molar ratio] was used. , pressure 0.6 Pa, direct current (DC) power supply 5 kW, oxygen and argon mixed atmosphere (oxygen flow rate 50sccm, argon flow rate 50sccm), substrate temperature 200℃, deposition rate 13.4nm The film was formed at 1000 nm / min.

[0270] In addition, in sample 4, both the first and second heat treatments were performed in a nitrogen atmosphere at 670°C for 6 minutes. It was decided.

[0271] When the cross section of the sample 4 thus obtained was observed, the In-Ga-Zn-O film and the underlayer It was confirmed that the interface of the film was also crystallized, and furthermore, in the upper In-Ga-Zn-O film, It can be seen that crystallization has partially occurred along the orientation of the undercoat film side. Crystallization is also observed from the surface of the In-Ga-Zn-O film, and orientation can be confirmed.

[0272] In this way, the composition of the oxide semiconductor film, the thickness of the oxide semiconductor film, and the film formation conditions of the oxide semiconductor film In addition, the region to be crystallized varies depending on the heat treatment conditions after the oxide semiconductor film is formed. It is preferable for the person skilled in the art to adjust the device fabrication conditions appropriately. [Explanation of symbols]

[0273] 400 Substrates 401 Gate electrode layer 402 Gate insulating layer 403 First oxide semiconductor layer 404 Second oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Oxide insulating layer 430 Oxide Semiconductor Stacking 431 Oxide Semiconductor Stacking 432 Oxide Semiconductor Stacking 470 Transistors 501 Oxide materials 520 Base material 521a Amorphous region 521b Oxide crystal material 522 Oxide Materials 523a Oxide crystal materials 523b Oxide crystal materials 523c Regions that remain amorphous 532 Oxide Materials 533b Oxide crystal materials 580 Substrate 581 Transistor 583 Insulating Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 2800 Chassis 2801 Case 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 Solar Cell 2811 External memory slot 3001 Main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main unit 3022 Stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 Board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Second Board 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4501 First board 4502 Pixel section 4503a, 4503b Signal line driver circuit 4504a, 4504b Scanning line driver circuit 4505 Sealing material 4506 Second Board 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a, 4518b FPC 4519 Anisotropic conductive layer 4520 Bulkhead 4540 Conductive layer 4541 Insulation layer 4544 Insulation layer

Claims

1. A first conductive layer; and an insulating film having a region on the first conductive layer; an oxide semiconductor film on the insulating film, the first conductive layer has a region that functions as a gate electrode of a transistor; the insulating film has a region that functions as a gate insulating film of the transistor, the oxide semiconductor film includes a channel formation region of the transistor, the oxide semiconductor film includes a first layer and a second layer having a region on the first layer, an interface between the first layer and the second layer is provided away from a surface of the insulating film, the second layer has a first region overlapping an upper surface of the first conductive layer, a second region not overlapping the first conductive layer, and a third region between the first region and the second region in a plan view; a surface of the third region is not parallel to a surface of the first region; the first region includes a first crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the first region, the second region includes a second crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the second region, the third region includes a third crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the third region, the first crystalline region is non-single crystalline; the second crystalline region is non-single crystalline; The semiconductor device, wherein the third crystalline region is non-single crystalline.

2. A first conductive layer; and an insulating film having a region on the first conductive layer; an oxide semiconductor film on the insulating film, the first conductive layer has a region that functions as a gate electrode of a transistor; the insulating film has a region that functions as a gate insulating film of the transistor, the oxide semiconductor film includes a channel formation region of the transistor, the oxide semiconductor film includes a first layer and a second layer having a region on the first layer, the first layer comprises In, Ga, and Zn; the second layer comprises In, Ga, and Zn; an interface between the first layer and the second layer is provided away from a surface of the insulating film, the second layer has a first region overlapping an upper surface of the first conductive layer, a second region not overlapping the first conductive layer, and a third region between the first region and the second region in a plan view; a surface of the third region is not parallel to a surface of the first region; the first region includes a first crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the first region, the second region includes a second crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the second region, the third region includes a third crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the third region, the first crystalline region is non-single crystalline; the second crystalline region is non-single crystalline; The semiconductor device, wherein the third crystalline region is non-single crystalline.

3. A first conductive layer; and an insulating film having a region on the first conductive layer; an oxide semiconductor film on the insulating film, the first conductive layer has a region that functions as a gate electrode of a transistor; the insulating film has a region that functions as a gate insulating film of the transistor, the oxide semiconductor film includes a channel formation region of the transistor, the oxide semiconductor film includes a first layer and a second layer having a region on the first layer, the first layer comprises In, Ga, and Zn; the second layer comprises In, Ga, and Zn; The second layer has a Zn composition ratio greater than an In composition ratio, an interface between the first layer and the second layer is provided away from a surface of the insulating film, the second layer has a first region overlapping an upper surface of the first conductive layer, a second region not overlapping the first conductive layer, and a third region between the first region and the second region in a plan view; a surface of the third region is not parallel to a surface of the first region; the first region includes a first crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the first region, the second region includes a second crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the second region, the third region includes a third crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the third region, the first crystalline region is non-single crystalline; the second crystalline region is non-single crystalline; The semiconductor device, wherein the third crystalline region is non-single crystalline.

4. A first conductive layer; and an insulating film having a region on the first conductive layer; an oxide semiconductor film on the insulating film; a second conductive layer having a region over the oxide semiconductor film; and a third conductive layer having a region over the oxide semiconductor film, the first conductive layer has a region that functions as a gate electrode of a transistor; the insulating film has a region that functions as a gate insulating film of the transistor, the oxide semiconductor film includes a channel formation region of the transistor, the second conductive layer has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive layer has a region functioning as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor film includes a first layer and a second layer having a region on the first layer, an interface between the first layer and the second layer is provided away from a surface of the insulating film, the second layer has a first region overlapping an upper surface of the first conductive layer, a second region not overlapping the first conductive layer, and a third region between the first region and the second region in a plan view; a surface of the third region is not parallel to a surface of the first region; the second conductive layer has a region that contacts the first region in a region that overlaps the first region, the third conductive layer has a region that contacts the first region in a region that overlaps the first region, the first region includes a first crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the first region, the second region includes a second crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the second region, the third region includes a third crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the third region, the first crystalline region is non-single crystalline; the second crystalline region is non-single crystalline; The semiconductor device, wherein the third crystalline region is non-single crystalline.

5. A first conductive layer; and an insulating film having a region on the first conductive layer; an oxide semiconductor film on the insulating film; a second conductive layer having a region over the oxide semiconductor film; and a third conductive layer having a region over the oxide semiconductor film, the first conductive layer has a region that functions as a gate electrode of a transistor; the insulating film has a region that functions as a gate insulating film of the transistor, the oxide semiconductor film includes a channel formation region of the transistor, the second conductive layer has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive layer has a region functioning as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor film includes a first layer and a second layer having a region on the first layer, the first layer comprises In, Ga, and Zn; the second layer comprises In, Ga, and Zn; an interface between the first layer and the second layer is provided away from a surface of the insulating film, the second layer has a first region overlapping an upper surface of the first conductive layer, a second region not overlapping the first conductive layer, and a third region between the first region and the second region in a plan view; a surface of the third region is not parallel to a surface of the first region; the second conductive layer has a region that contacts the first region in a region that overlaps the first region, the third conductive layer has a region that contacts the first region in a region that overlaps the first region, the first region includes a first crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the first region, the second region includes a second crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the second region, the third region includes a third crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the third region, the first crystalline region is non-single crystalline; the second crystalline region is non-single crystalline; The semiconductor device, wherein the third crystalline region is non-single crystalline.

6. A first conductive layer; and an insulating film having a region on the first conductive layer; an oxide semiconductor film on the insulating film; a second conductive layer having a region over the oxide semiconductor film; and a third conductive layer having a region over the oxide semiconductor film, the first conductive layer has a region that functions as a gate electrode of a transistor; the insulating film has a region that functions as a gate insulating film of the transistor, the oxide semiconductor film includes a channel formation region of the transistor, the second conductive layer has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive layer has a region functioning as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor film includes a first layer and a second layer having a region on the first layer, the first layer comprises In, Ga, and Zn; the second layer comprises In, Ga, and Zn; The second layer has a Zn composition ratio greater than an In composition ratio, an interface between the first layer and the second layer is provided away from a surface of the insulating film, the second layer has a first region overlapping an upper surface of the first conductive layer, a second region not overlapping the first conductive layer, and a third region between the first region and the second region in a plan view; a surface of the third region is not parallel to a surface of the first region; the second conductive layer has a region that contacts the first region in a region that overlaps the first region, the third conductive layer has a region that contacts the first region in a region that overlaps the first region, the first region includes a first crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the first region, the second region includes a second crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the second region, the third region includes a third crystalline region in which layers parallel to an a-axis and a b-axis are stacked in a thickness direction of the oxide semiconductor film in the third region, the first crystalline region is non-single crystalline; the second crystalline region is non-single crystalline; The semiconductor device, wherein the third crystalline region is non-single crystalline.

7. In any one of claims 1 to 6, A semiconductor device, wherein the surface of the first region has a region having a height difference of 1 nm or less in an area of ​​1 μm square measured by AFM.

8. In any one of claims 1 to 7, The insulating film is a laminate of a first silicon oxide layer and a first silicon nitride layer.

9. In any one of claims 1 to 8, a second silicon oxide layer over the oxide semiconductor film; a second silicon nitride layer on the second silicon oxide layer;

10. In any one of claims 1 to 9, a planarization insulating layer having a region on the oxide semiconductor film; a pixel electrode on the planarization insulating layer; The pixel electrode is electrically connected to the transistor.

11. In any one of claims 1 to 9, a planarization insulating layer having a region on the oxide semiconductor film; a pixel electrode having an area on the planarization insulating layer; a fourth conductive layer having an area on the planarizing insulating layer; a liquid crystal layer having an area on the pixel electrodes; A scanning line driver circuit, the pixel electrode is electrically connected to the transistor; the scanning line driver circuit includes a second transistor; the fourth conductive layer has a region overlapping with a channel formation region of the second transistor.

12. In any one of claims 1 to 9, a planarization insulating layer having a region on the oxide semiconductor film; and a light-emitting element on the planarization insulating layer.

13. In any one of claims 1 to 9, a planarization insulating layer having a region on the oxide semiconductor film; a light emitting device on the planarization insulating layer; a fourth conductive layer having an area on the planarizing insulating layer; A scanning line driver circuit, the scanning line driver circuit includes a second transistor; the fourth conductive layer has a region overlapping with a channel formation region of the second transistor.

14. In any one of claims 1 to 13, a fifth conductive layer having a region over the oxide semiconductor film; the fifth conductive layer has a region that functions as a second gate electrode of the transistor.

15. In any one of claims 1 to 14, the first conductive layer has a region that functions as a scan line; The region functioning as the scanning line extends in a first direction, A semiconductor device, wherein a channel length direction of the transistor is the first direction.

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