Semiconductor device and electronic device

Abstract

To provide a minute semiconductor device with low consumption power.SOLUTION: A second insulator is formed on a first insulator. A third insulator is formed on the second insulator. An opening part reaching the second insulator is formed in the third insulator. On the third insulator and in the opening part, a first conductor is formed. After a second conductor is formed on the first conductor, a polishing process is performed so that the second conductor and the first conductor existing at a position higher than an upper surface of the third insulator are removed. At an end of the opening part, an end part of the first conductor is as high as or lower than the end part of the opening part. The height of an upper surface of the second conductor is as high as or lower than the height of the end part of the first conductor. Thus, a wiring layer is formed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. , manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, or a memory device. In particular, one aspect of the present invention relates to an acid The present invention relates to a semiconductor device, a display device, or a light-emitting device having a compound semiconductor.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices The vessel may include a semiconductor device. [Background technology]

[0003] Silicon used as a semiconductor in transistors is classified into amorphous silicon and polycrystalline silicon depending on the application. For example, transistors that make up large display devices are It is preferable to use amorphous silicon, for which a film formation technique for a large-area substrate has been established. The transistors that make up a highly functional display device in which the driver circuit and pixel section are integrated have high current It is preferable to use polycrystalline silicon, which allows the fabrication of transistors with field effect mobility. Polycrystalline silicon is made by subjecting amorphous silicon to high temperature heat treatment or laser light treatment. Methods for forming such structures are known.

[0004] In recent years, the development of transistors using oxide semiconductors (typically In-Ga-Zn oxide) has become The development of oxide semiconductor transistors is becoming more and more active. It has different characteristics from transistors using polycrystalline silicon. For example, a display device including a transistor including an oxide semiconductor has low power consumption. It is known.

[0005] In addition, a transistor including an oxide semiconductor has an extremely low leakage current in an off-state. For example, it is known that the leakage current of a transistor using an oxide semiconductor is low. A low-power CPU that utilizes this characteristic has been disclosed (see Patent Document 1). .

[0006] In order to reduce power consumption by power gating, a transistor using an oxide semiconductor is required. It is preferable that the transistor has normally-off electrical characteristics. One method for controlling the threshold voltage of a transistor to achieve normally-off electrical characteristics is to A floating gate is disposed in a region overlapping with the oxide semiconductor. A method for injecting negative fixed charges has been disclosed (see Patent Document 2).

[0007] Since oxide semiconductors can be deposited by sputtering or the like, they can be used to form large display devices. In addition, a transistor using an oxide semiconductor can be Because of its high field effect mobility, it is suitable for the manufacture of high-performance display devices that integrate driver circuits and pixel sections. In addition, it is possible to realize a transistor using amorphous silicon or a transistor using polycrystalline silicon. It is possible to improve and use some of the existing transistor production equipment, reducing capital investment. There are also benefits to being able to reduce costs.

[0008] The history of oxide semiconductors is long, and in 1985, the synthesis of crystalline In-Ga-Zn oxide was reported. (See Non-Patent Document 1.) In 1995, In-Ga-Zn oxide was Homologous structure, InGaO 3 (ZnO) m (m is a natural number.) It has been reported that this is the case (see Non-Patent Document 2).

[0009] In 1995, a transistor using an oxide semiconductor was invented, and its electrical properties Its characteristics are disclosed (see Patent Document 3).

[0010] In 2014, a transistor using a crystalline oxide semiconductor was reported. (See Non-Patent Documents 3 and 4.) Here, the CAAC-OS (C-Axis Aligned C) with excellent electrical characteristics and reliability Transistor using Rystalline Oxide Semiconductor It has been reported that

[0011] As integrated circuits become finer, the resistance of wiring layers is becoming lower and the number of layers is increasing, making it necessary to flatten the wiring layers. To solve these problems, a dummy method is being developed in which the wiring layer is embedded in the interlayer insulating film. The ion beam method is widely used (see Non-Patent Document 5). [Prior art documents] [Patent documents]

[0012] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2013-247143 A [Patent Document 3] Special Publication No. 11-505377

Non-licensed literature

[0013] [Non-licensed document 1] N. Kimizuka, and T. Mohri: Journal of Solid State Chemistry, 1985, volume 60, p.382-p.384 [Non-licensed document 2] N. Kimizuka, M. Isobe, and M. Nakamura: Journal of Solid State Chemistry, 1995, volume 116, p.170-p.178 [Non-licensed document 3] S. Yamazaki, T. Hirohashi, M. Takahashi, S. Adachi, M. Tsubuku, J. Koezuka, K. Okazaki, Y. Kanzaki, H. Matsukizono, S. Kaneko, S. Mori, and T. Matsuo: Journal of the Society for Information Display, 2014, Volume 22, issue 1, p.55-p.67

Non-licensed Document 4

Non-licensed Document 5

[0014] An object of one embodiment of the present invention is to provide a miniaturized semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a semiconductor device with high reliability. Another object of the present invention is to provide a semiconductor device having a small off-state current. The object of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. Another object of one embodiment of the present invention is to provide a novel semiconductor device. An object of one embodiment of the present invention is to provide a display device that is gentle on the eyes. An object of one embodiment of the present invention is to provide a semiconductor device including a transparent semiconductor.

[0015] The description of these problems does not preclude the existence of other problems. The embodiment does not necessarily solve all of these problems. Problems other than these may be solved by the description. The above will become apparent from the description, drawings, claims, etc. From descriptions such as these, it is possible to extract other issues. [Means for solving the problem]

[0016] (1) In one embodiment of the present invention, a second insulator is formed on a first insulator, and a third insulator is formed on the second insulator. A film of an insulating material is formed, an opening is formed in the third insulating material so as to reach the second insulating material, and a wiring is formed on the third insulating material. A first conductor is formed in the opening, and a second conductor is formed on the first conductor, followed by polishing. By performing the polishing process, the second conductor and the first conductor, which are located at a position higher than the upper surface of the third insulator, are The first conductor is removed, and the end of the first conductor is at the end of the opening. The height of the upper surface of the second conductor is equal to or lower than the height of the end of the first conductor. The method for producing a wiring layer is characterized in that (2) Alternatively, one embodiment of the present invention is a method for forming a second insulator on a first insulator, and forming a second insulator on the second insulator. A third insulator is formed, an opening is formed in the third insulator so as to reach the second insulator, and the third insulator is A first conductor is deposited on the edge and the opening, and a second conductor is deposited on the first conductor. Then, the second conductive material is polished to a position higher than the top surface of the third insulator. The first conductor is removed, and a third conductor is formed on the second conductor and the third insulator. The third conductor is polished until it reaches the third insulator, and the end of the first conductor is At the edge of the opening, the height of the upper surface of the second conductor is equal to or lower than the height of the edge of the opening. The height of the third conductor is equal to or lower than the height of the end of the first conductor, and the third conductor is in contact with the upper surface of the second conductor. and a first conductor is in contact with the first conductive body at an end of the opening. This is the manufacturing method. (3) Alternatively, one embodiment of the present invention is a semiconductor device having a second insulator on a first insulator, and a first insulating film on the second insulator. The third insulator has an opening that reaches the second insulator, and the opening is The container has a first conductor in contact with the side and bottom surfaces of the mouth, and a second conductor on the first conductor. The end of the first conductor is at the same height as or lower than the end of the opening, The height of the upper surface of the second conductor is equal to or lower than the height of the end of the first conductor. This is the wiring layer. (4) Alternatively, one embodiment of the present invention is a semiconductor device having a second insulator on a first insulator, and a first insulating film on the second insulator. The third insulator has an opening that reaches the second insulator, and the opening is A first conductor in contact with the side and bottom surfaces of the mouth, a second conductor on the first conductor, and a second and a third conductor on the first conductor, the end of the first conductor being at an end of the opening. The height of the upper surface of the second conductor is equal to or lower than the height of the edge of the opening, and the height of the upper surface of the second conductor is equal to or lower than the height of the edge of the first conductor. The third conductor is in contact with the upper surface of the second conductor and is at the edge of the opening. The wiring layer is characterized in that it contacts an end of the first conductor. (5) Alternatively, in one embodiment of the present invention, the first conductor is less permeable to oxygen than the second conductor. The wiring layer according to (3) is characterized in that (6) Alternatively, in one aspect of the present invention, the first conductor and the third conductor are more acidic than the second conductor. The wiring layer according to (4) is characterized in that it is difficult for the substrate to penetrate. Effect of the Invention

[0017] It is possible to provide a fine semiconductor device. Alternatively, it is possible to provide a semiconductor device with low power consumption. Alternatively, a highly reliable semiconductor device can be provided. It is possible to provide a semiconductor device with a small leakage current. Alternatively, a semiconductor device capable of supporting the above-mentioned characteristics can be provided. Or, a display device that is easy on the eyes can be provided. Or, a transparent display device can be provided. It is possible to provide a semiconductor device having a transparent semiconductor.

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0019] [Figure 1] 1 is a cross-sectional view of an interconnect layer according to one embodiment of the present invention. [Diagram 2] 1A to 1C illustrate a method for forming a wiring layer according to one embodiment of the present invention. [Diagram 3] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 4] 1A to 1C are a top view, a cross-sectional view, and an example of a band of a transistor according to one embodiment of the present invention. [Diagram 5] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 6] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 7] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 8] Electron diffraction pattern of CAAC-OS. [Figure 9]FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 10] 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 18] 1 shows an example of the configuration of an RF tag according to an embodiment of the present invention. [Figure 19] FIG. 1 is a block diagram of a semiconductor device according to one embodiment of the present invention. [Figure 20] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 21] 1A to 1C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 22] 1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Diagram 23] 1A to 1C are diagrams illustrating examples of electronic devices according to one embodiment of the present invention. [Figure 24] 1 shows an example of use of an RF tag according to an embodiment of the present invention. [Diagram 25] 1 is a cross-sectional STEM photograph of an embodiment. [Figure 26] FIG. 13 is a graph showing Id-Vg characteristics of an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not to be construed as being limited to the description in the form of the above.

[0021] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals may be used in common between different drawings, and repeated explanations may be omitted. In addition, when referring to similar functions, the hatch pattern will be the same and no particular symbol will be added. There is.

[0022] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It is possible to use it in a variety of ways.

[0023] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of illustration only and are not intended to be limiting.

[0024] In each figure described in this specification, the size, layer thickness, or area of ​​each component is not clearly indicated. may be exaggerated for clarity and are not necessarily limited to scale .

[0025] A transistor is a type of semiconductor device that amplifies current and voltage and controls conduction or non-conduction. In this specification, the transistor can realize a switching operation such as IGFET(Insulated Gate Field Effect Transi) stor) and thin film transistor (TFT) Includes.

[0026] The words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0027] Unless otherwise specified, in this specification, the off-state current refers to the current that flows when a transistor is in an off state. (also called non-conducting or cut-off state). The off state is Unless otherwise specified, for n-channel transistors, the voltage between the gate and source, Vgs is lower than the threshold voltage Vth. In a p-channel transistor, the gate and source This refers to a state in which the voltage Vgs between the gates is higher than the threshold voltage Vth. For example, The off-state current of a transistor is the time when the voltage between the gate and source, Vgs, is lower than the threshold voltage, Vth. It may refer to the drain current when it is lower than the

[0028] The off-state current of a transistor may depend on Vgs. The current is I or less if there is a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the off-state current at a given Vgs. Off-state at Vgs within a given range or sufficiently reduced off-current is obtained It may refer to the off-state current at Vgs, etc.

[0029] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -13 A, and the drain current at Vgs of -0.5 V is 1×10 -19 A and Vgs The drain current at -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: Or, when Vgs is in the range of -0.5V to -0.8V, 1×10 -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 There are cases where it is below A. The drain current of the transistor is 1×10 -22 Because there exists a Vgs below A , the off-state current of the transistor is 1×10 -22 There are cases where it is A or lower.

[0030] In this specification, the off-state current of a transistor having a channel width W is expressed as It may be expressed as the current value that flows. It may also be expressed as the current that flows per a given channel width (for example, 1 μm). In the latter case, the unit of the off-state current is a unit with the dimensions of current / length. It is sometimes expressed in units (e.g., A / μm).

[0031] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the off-state current is measured at room temperature, 60℃, 85℃, 95℃, or 125℃. Or, the reliability of the semiconductor device containing the transistor may be in doubt. or the temperature at which a semiconductor device or the like that includes the transistor is used (for example, For example, the off-state current at any one of temperatures from 5°C to 35°C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of a semiconductor device including the transistor is guaranteed, or the temperature at which the transistor is The temperature at which the semiconductor device containing the transistor is used (for example, any one of 5°C to 35°C) (temperature), there exists a value of Vgs at which the off-state current of the transistor is equal to or less than I. There are cases where it is pointed out.

[0032] The off-state current of a transistor may depend on the voltage Vds between the drain and source. In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1 V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or It may represent the off-state current at 20 V. Or, the semiconductor including the transistor Vds that guarantees the reliability of devices, etc., or semiconductor devices that include the transistor The off-state current of a transistor may be expressed as the off-state current at the Vds used in the The current is less than I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2 .5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device or semiconductor device that includes the transistor Vds used in semiconductor devices, etc., where the off-state current of the transistor is I or less This may refer to the existence of a gs value.

[0033] In this specification, the term "leakage current" may be used to mean the same thing as the off-state current.

[0034] In this specification, the off-state current is, for example, the current that flows through a source when a transistor is in an off state. It can also refer to the current that flows between the source and drain.

[0035] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0036] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0037] (Embodiment 1) In this embodiment, a method for manufacturing a wiring layer will be described with reference to FIGS. do.

[0038] First, an insulator 302 is formed on an insulator 301, and an insulator 303 is formed on the insulator 302. (See FIG. 2(A)). Next, a groove is formed in the insulator 303 so as to reach the insulator 302. The grooves include holes and openings (see Fig. 2(B)). The grooves are formed by wet Etching may be used, but dry etching is preferred for fine processing. The insulator 302 is an etching strip when the insulator 303 is etched to form a groove. It is preferable to select an insulator that functions as a protective film. For example, When a silicon oxide film is used for the insulating layer 303, the insulating layer 302 is a silicon nitride film or an aluminum oxide film. A minium film is preferably used.

[0039] In this embodiment, the insulator 302 is used. However, depending on the application, the insulator 302 may be replaced with A conductor or a semiconductor may be used.

[0040] After the grooves are formed, the conductor 310 is formed. The conductor 310 has a function of being difficult for oxygen to permeate. Alternatively, it is desirable that the conductive material 311 has a function of being less permeable to oxygen than the conductive material 311. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. The conductor 310 can be formed by using a sputtering method, a CVD method, an ALD method, or the like. Next, a conductor 311 is formed on the conductor 310 (see FIG. 2(C)). It is desirable for the material to have low resistivity. For example, tantalum, tungsten, titanium, molybdenum, etc. The following materials can be used: molybdenum, aluminum, copper, molybdenum-tungsten alloy, etc. The conductor 311 can be formed using a method similar to that for the conductor 310.

[0041] Next, Chemical Mechanical Polishing The conductor 311 and the conductor 310 on the insulator 303 are removed by performing a chemical mechanical polishing (CMP). As a result, the conductor 311 and the conductor 310 remain only in the grooves, resulting in the structure shown in FIG. It is possible to form the wiring layer shown in FIG.

[0042] The end of the conductor 310 is at the same height or lower than the height of the groove at the end of the groove. The top surface of the conductive body 311 is at the same height as or lower than the end of the conductive body 310. This is formed by the difference in polishing speed between the conductive body 310 and the conductive body 311. In the example, the polishing rate of the conductor 311 is faster than that of the conductor 310 .

[0043] When a conductor is used as a wiring layer or an electrode layer, the surrounding oxide film, e.g., silicon oxide, It is necessary to be careful of the oxidation of the conductor caused by the oxygen contained in the conductive film. If the resistivity is increased, the function of the wiring layer or electrode layer may be deteriorated. Or, the film of the conductor itself may peel off or crack due to an increase in volume, or the film around the conductor may peel off. This can lead to peeling and cracking, so it is important to prevent this.

[0044] According to the present invention, as shown in FIG. 1A, the conductor 310 is connected to the bottom and side surfaces of the conductor 311. This structure covers the conductor 311 and does not directly contact the oxide film. Therefore, the serious problems such as film peeling caused by the volume increase due to the oxidation of the conductor 311 can be prevented. This can prevent the occurrence of major problems.

[0045] In this embodiment, the substrate is not shown, but may be a single material such as silicon or germanium. Solid semiconductor substrates, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of materials such as tungsten oxide, zinc oxide, and gallium oxide can be used. Alternatively, an insulating substrate such as quartz or glass can be used, and the present embodiment can be formed on the insulating substrate. Alternatively, a wiring layer manufactured in the above-mentioned form can be used. The above-mentioned substrate having the above structure can be used.

[0046] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0047] (Embodiment 2) In this embodiment mode, a method for manufacturing a wiring layer as shown in FIG.

[0048] In the first embodiment, CMP is performed to cover the bottom and side surfaces of the conductor 311 with the conductor. In this embodiment, a conductor 312 is further formed on the conductor 311. It is desirable that the conductor 312 has a function of being difficult to transmit oxygen, similar to the conductor 310. Alternatively, it is preferable that the conductor 312 has a function of being less permeable to oxygen than the conductor 311. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, the same conductor as conductor 310 may be used.

[0049] Next, CMP is performed on the conductor 312 until it reaches the insulator 303, as shown in FIG. A wiring layer having a structure in which a conductor 310, a conductor 311, and a conductor 312 are embedded in a groove. can be formed.

[0050] In the wiring layer shown in FIG. 1B, a conductor 310 and a conductor 312 are connected to a bottom surface of a conductor 311. This structure surrounds and covers the side and top surfaces, and can prevent the conductor 311 from being oxidized. Furthermore, in this embodiment, CMP is performed one more time compared to the first embodiment. Therefore, the upper surface of the wiring layer is more flat, and the coverage of the film above the wiring layer is more excellent. This is favorable and preferable.

[0051] In this embodiment, as in the first embodiment, the substrate is not shown. For example, a silicon A single semiconductor substrate such as silicon carbide, silicon germanium, gallium, etc. Compound semiconductors made from materials such as gallium oxide, indium phosphide, zinc oxide, and gallium oxide. Alternatively, an insulating substrate such as quartz or glass may be used. The wiring layer formed in this embodiment mode can be used above the transistor. The above-mentioned substrate having elements such as a resistor and a capacitor can be used.

[0052] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0053] (Embodiment 3) In this embodiment mode, an example in which the wiring layer described in Embodiment 1 is used for a transistor will be described. 3A is a top view of a transistor according to the present invention. The cross section of 1-X2 is shown in FIG. 3(B), which is a cross section of the transistor in the channel length direction. The cross-sectional view of the line Y1-Y2 is shown in FIG. 3(C), which corresponds to the cross-sectional view of the transistor in the channel width direction. do.

[0054] The substrate 300 may be, for example, a single semiconductor substrate such as silicon, germanium, or silicon carbide. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Compound semiconductor substrates made of materials such as silicon can be used. An insulating substrate such as a SiO 2 film may also be used.

[0055] An insulator 301 is formed on a substrate 300. The insulator 301 may be a silicon oxide film, an oxide Silicon nitride film, silicon oxynitride film, silicon nitride film, aluminum oxide film, aluminum nitride film The film can be formed by thermal oxidation, CV, or other methods. The D method, sputtering method, ALD method, plasma oxidation method, plasma nitridation method, etc. can be used. do.

[0056] Next, the insulator 302 is formed on the insulator 301. Next, the conductor 3 10 deposits a wiring layer that covers the bottom and side surfaces of the conductor 311. A wiring layer made of a conductor 310 and a conductor 311 is used as a gate electrode.

[0057] An insulator 304 is formed on the conductor 311 and on the insulator 303. The insulating film 302 may be formed by the same film as the insulating film 301 described above, and the same film forming method may be used. It is preferable to use an insulator that is difficult for oxygen to pass through. For example, An aluminum oxide film or an aluminum nitride film can be used. The bottom and sides of the 11 are covered with a conductor 310, and the top is covered with an insulator 304. As a result, the oxidation of the conductor 311 is suppressed, and the conductor 311 or This can prevent serious problems such as film lifting and peeling of the surrounding film.

[0058] An insulator 305 is formed on the insulator 304. Note that the insulator 305 is an insulator containing excess oxygen. It is preferable that:

[0059] For example, an insulator containing excess oxygen is an insulator that has the function of releasing oxygen by heat treatment. For example, a silicon oxide film containing excess oxygen will release oxygen when subjected to heat treatment or the like. Therefore, the insulator 305 is a silicon oxide film through which oxygen can move. That is, the insulator 305 may be an insulator having oxygen permeability. For example, the insulator 305 may be an insulator having a higher oxygen permeability than the semiconductor 320 .

[0060] The insulator containing excess oxygen may function to reduce oxygen vacancies in the semiconductor 320. In the semiconductor 320, oxygen vacancies become hole traps, etc. When hydrogen enters, it can generate electrons, which act as carriers. By reducing oxygen vacancies in the body 320, it is possible to impart stable electrical characteristics to the transistor. This can be done.

[0061] Here, the insulators that release oxygen when heated are those that, as determined by TDS analysis, are those that are heated to 100°C or higher and 70°C or lower. 1×10 in the range of surface temperatures below 0℃ or between 100℃ and 500℃ 18 atoms / cm 3 That's it, 1×10 19 atoms / cm 3 or more than 1×10 20 atoms / cm 3 It may even release more than this amount of oxygen (calculated as the number of oxygen atoms).

[0062] Here, a method for measuring the amount of released oxygen using TDS analysis will be described below.

[0063] The total amount of gas released when the measurement sample was subjected to TDS analysis was calculated based on the integral value of the ion intensity of the released gas. By comparison with a standard sample, the total amount of gas released can then be calculated.

[0064] For example, the results of a TDS analysis of a silicon substrate containing a given density of hydrogen as a standard sample, From the TDS analysis results of the measured sample, the amount of oxygen molecules released from the measured sample (N O2 ) is expressed as follows: Here, the gas detected with a mass-to-charge ratio of 32 obtained by TDS analysis is Assume that all of the CH 3 The mass-to-charge ratio of OH is 32, but The possibility of this is low, so it is not considered here. The abundance of oxygen atoms and oxygen molecules containing the oxygen atom with mass number 18 in nature is also The rate is so small that it is not taken into consideration.

[0065] N O2 =N H2 / S H2 ×S O2 ×α.

[0066] N H2 is the density of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let us assume that S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Gakushugaku Co., Ltd. was used. For example, 1×10 16 atoms / cm 2 The measurement was performed using a silicon substrate containing hydrogen atoms. .

[0067] In addition, some of the oxygen is detected as oxygen atoms in the TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen molecules is included in the calculation, the amount of oxygen atoms released can be calculated by evaluating the amount of oxygen molecules released. It is possible to estimate even if

[0068] In addition, N O2 is the amount of oxygen molecules released. The amount of oxygen released in terms of oxygen atoms is This is twice the amount released.

[0069] Alternatively, an insulator that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to the peroxide radical is 5×10 17 spins / cm 3 Insulators that contain peroxide radicals have an ESR g value of 2. It may also have an asymmetric signal near 01.

[0070] Alternatively, an insulator containing excess oxygen can be called silicon oxide (SiO X (X>2) Silicon oxide (SiO X (X>2) is the number of silicon atoms It contains more than twice as many oxygen atoms per unit volume as silicon atoms per unit volume. The number of electrons and oxygen atoms was measured by Rutherford backscattering (RBS). The values ​​were measured using ion scattering spectrometry (ICS).

[0071] The insulator 305 functions as a gate insulator of the transistor. The same film and the same film formation method as those of the insulator 301 described above can be used. In (C), the insulator 305 is a single layer, but a multi-layer film may also be used. For example, A hafnium oxide film is formed on the silicon oxide film, and then a silicon oxide film is formed on the hafnium oxide film. A three-layer structure can also be formed with a hafnium oxide film as an electron capture layer, The threshold voltage of the transistor may be controlled, or it may be further multi-layered. The combination of films can be any combination similar to the insulator 301 described above. do.

[0072] A semiconductor 320 is formed on an insulator 305, and a conductor is formed on the semiconductor 320. The conductor in the panel forming region is etched to form a channel forming region. The semiconductor 320 is etched to form a pair of source and drain electrodes 312. A laminated island region consisting of layers 312a, 312b and semiconductor 320 is formed.

[0073] Alternatively, the conductor or semiconductor 320 may be etched before the channel formation region is formed. After forming the island region of the stack consisting of the dielectric and the semiconductor 320, The conductor is etched to form a channel forming region and a pair of source and drain electrodes. In addition, a pair of electrodes 312a and 312b may be formed.

[0074] The source or drain electrode 312a and the source or drain electrode 312b are , Tantalum, Tungsten, Titanium, Molybdenum, Aluminum, Copper, Molybdenum Tungsten Stainless alloys, tungsten nitride, titanium nitride, tantalum nitride, etc. can be used. Alternatively, a multi-layer structure can be used. The film formation method includes sputtering, CVD, and AL. Method D, etc. can be used.

[0075] Next, the source or drain electrode 312a and the source or drain electrode 3 An insulator 306 is formed so as to cover the transistor 12b and the channel forming region. The insulator 306 functions as a second gate insulator for the transistor. To pour drinks.

[0076] By arranging semiconductors above and below the semiconductor 320, the electrical characteristics of the transistor can be improved. In the following, the semiconductor 320 and the semiconductors arranged above and below it will be described. This will be described in detail with reference to FIG. 4(A) and FIG. 4(B).

[0077] FIG. 4A shows the semiconductor 32 in the channel length direction of the transistor shown in FIG. FIG. 4B is an enlarged cross-sectional view of the transistor shown in FIG. 3 is an enlarged cross-sectional view of the vicinity of the semiconductor 320 in the channel width direction.

[0078] In the transistor structure shown in FIG. 4(A) and FIG. 4(B), an insulator 305 and a semiconductor 32 0, a semiconductor 320a is disposed. A semiconductor 320 c is disposed between the insulator 306 and the electrodes 312 a and 312 b.

[0079] The semiconductor 320 is, for example, an oxide semiconductor containing indium. For example, if indium is included, the carrier mobility (electron mobility) increases. 0 preferably contains the element M. The element M is preferably aluminum, gallium, yttrium, Thorium or tin. Other elements that can be used for M include boron, Silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum , cerium, neodymium, hafnium, tantalum, tungsten, etc. However, the elements In some cases, M may be a combination of the above elements. The element M may be, for example, an acid. For example, the bond energy with oxygen is Alternatively, the element M may be, for example, an element having an energy gap In addition, the semiconductor 320 preferably contains zinc. When an oxide semiconductor contains zinc, it may be easily crystallized.

[0080] However, the semiconductor 320 is not limited to an oxide semiconductor containing indium. For example, zinc-containing oxides that do not contain indium, such as zinc tin oxide and gallium tin oxide, are used. an oxide semiconductor containing gallium, an oxide semiconductor containing tin, etc. That's fine.

[0081] The semiconductor 320 is made of, for example, an oxide having a large energy gap. The energy gap is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV. The excitation voltage is set to 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0082] For example, the semiconductor 320a and the semiconductor 320c are made of elements other than oxygen that constitute the semiconductor 320. The semiconductor 320 is an oxide semiconductor composed of one or more elements. The semiconductor 320a and the semiconductor 320c are made of one or more elements other than oxygen. Therefore, the interface between the semiconductor 320a and the semiconductor 320 and the interface between the semiconductor 320 and the semiconductor At the interface with 320c, defect levels are unlikely to be formed.

[0083] The semiconductor 320a, the semiconductor 320, and the semiconductor 320c contain at least indium. It is preferable that the sum of In and M is 1 when the semiconductor 320a is an In-M-Zn oxide. When the atomic percentage of In is 0.00, it is preferable that In is less than 50 atomic percent and M is less than 50 atomic percent. %, and more preferably In is less than 25 atomic % and M is 75 atomic % or more. When the semiconductor 320 is an In-M-Zn oxide, In and When the sum of In and M is 100 atomic %, In is preferably 25 atomic % or more. and M is less than 75 atomic %, and more preferably In is more than 34 atomic %. The semiconductor 320c is an In-M-Zn oxide. When the sum of In and M is 100 atomic %, In is preferably 50 atomic %, M is higher than 50 atomic %, and more preferably In is 25 atomic %. % or less, and M is higher than 75 atomic %. The same oxide as that of the conductor 320a may be used. However, the oxide of the semiconductor 320a and / or In some cases, semiconductor 320c does not need to contain indium. The semiconductor 320a and / or the semiconductor 320c may be gallium oxide. The number of atoms of each element contained in 20a, semiconductor 320, and semiconductor 320c is a simple integer ratio. It doesn't matter if it doesn't become like that.

[0084] The semiconductor 320 is an oxide having a higher electron affinity than the semiconductors 320a and 320c. For example, the semiconductor 320 is a semiconductor 320a having a higher current density than the semiconductor 320c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less More preferably, an oxide having a larger electron energy than the electron transport energy is used, the larger energy being 0.15 eV or more and 0.4 eV or less. The affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0085] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor 320c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and Preferably, the ratio is 90% or more.

[0086] At this time, when a gate voltage is applied, the semiconductor 320a, the semiconductor 320, and the semiconductor 320c Of these, a channel is formed in the semiconductor 320 having the larger electron affinity.

[0087] Here, between the semiconductor 320a and the semiconductor 320, In addition, a semiconductor 320 may be provided between the semiconductor 320 and the semiconductor 320c. In some cases, the inter-layer may have a mixed region of the semiconductor 320 and the semiconductor 320c. The mixed region has a defect state density of Therefore, the stack of the semiconductor 320a, the semiconductor 320, and the semiconductor 320c is In the vicinity of each interface, the energy changes continuously (also called a continuous junction). The diagram is a block diagram (see FIG. 4(C)). 320c, the boundaries between the two may not be clearly distinguishable.

[0088] At this time, the electrons are not in the semiconductor 320a and the semiconductor 320c but in the semiconductor 320. As described above, the semiconductor 320a and the semiconductor 320 at the interface and the defect state density at the interface between the semiconductor 320 and the semiconductor 320c. By this, the movement of electrons in the semiconductor 320 is not hindered, and the transistor The on-state current can be increased.

[0089] The on-current of a transistor can be increased by reducing the factors that inhibit the movement of electrons. For example, if there are no factors that impede the movement of electrons, it is assumed that electrons will move efficiently. The movement of electrons is also hindered, for example, when the channel formation region has large physical irregularities. will be done.

[0090] In order to increase the on-current of the transistor, for example, the upper or lower surface ( The root mean square of the surface to be formed (here, the semiconductor 320a) in an area of ​​1 μm×1 μm (RMS: Root Mean Square) roughness is less than 1 nm, preferably less than 0.6 nm m, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in an area of ​​1 μm × 1 μm is preferably less than 1 nm. Preferably less than 0.6 nm, more preferably less than 0.5 nm, even more preferably less than 0.4 nm The maximum height difference (PV) in the area of ​​1 μm x 1 μm should be less than 1 μm. ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably The RMS roughness, Ra and PV are measured by SII Nanotech. Measurements are performed using a scanning probe microscope system such as SPA-500 manufactured by Nology Corporation. It is possible.

[0091] Alternatively, for example, when the density of defect states in the region where the channel is formed is high, the electron transfer Movement is hindered.

[0092] For example, if the semiconductor 320 has an oxygen vacancy (V O ) at the site of oxygen vacancy. Hydrogen can enter the donor level. In the following, water can enter the oxygen vacancy site. The state where the element is inserted is called V. O It may be written as H. V O H scatters electrons, so This causes a decrease in the on-state current of the transistor. The oxygen vacancy site is designed to accommodate hydrogen. Therefore, by reducing the oxygen vacancies in the semiconductor 320, In some cases, the on-state current of a transistor can be increased.

[0093] In addition, if the density of defect states in the region where the channel is formed is high, the electrical characteristics of the transistor are adversely affected. For example, when a defect level is a carrier generation source, The threshold voltage may be varied.

[0094] In order to reduce oxygen vacancies in the semiconductor 320, for example, excess oxygen contained in the insulator 305 is In this case, the semiconductor 320a is moved to the semiconductor 320. The body 320a is preferably an oxygen-permeable layer (a layer that allows oxygen to pass through or permeate). I wish.

[0095] In addition, in order to increase the on-current of the transistor, the thickness of the semiconductor 320c is preferably as small as possible. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the semiconductor 320c may be a semiconductor having a channel region. The semiconductor 320 to be implanted is provided with an element other than oxygen (hydrogen, silicon, etc.) that constitutes the adjacent insulator. ) to prevent the intrusion of the semiconductor 320c. For example, the thickness is 0.3 nm or more, preferably 1 nm or more, and More preferably, the semiconductor 320c has a region with a thickness of 2 nm or more. The conductor 320c is made of an oxygen-containing material to suppress outward diffusion of oxygen released from the insulator 305 and the like. It is preferable that the polyimide has a property of blocking oxygen.

[0096] In order to increase reliability, the semiconductor 320a is thick and the semiconductor 320c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. The semiconductor 320a may have a region with a thickness of 60 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor 320a, the semiconductor 320a can be prevented from being heated at the interface between the adjacent insulator and the semiconductor 320a. The distance from the semiconductor 320 where the channel is formed can be increased. For example, the thickness is set to 200 nm or less, preferably 120 nm or less, because this may reduce the productivity of the device. More preferably, the semiconductor 320a has a region with a thickness of 80 nm or less. .

[0097] For example, between the semiconductor 320 and the semiconductor 320a, for example, secondary ion mass spectrometry (SI In MS (Secondary Ion Mass Spectrometry), 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Hereinafter, preferably 1×10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 The following are more preferred Or 1×10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 The following series In addition, a region having a high concentration of SiO2 is formed between the semiconductor 320 and the semiconductor 320c. In, 1×10 16atoms / cm 3 More than 1×10 19 atoms / cm 3 below, Preferably 1 x 10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 below, More preferably, 1×10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 The silicon concentration in the region is as follows:

[0098] In order to reduce the hydrogen concentration in the semiconductor 320, the semiconductor 320a and the semiconductor 320c are It is preferable to reduce the hydrogen concentration in the semiconductor 320a and the semiconductor 320c. Put it, 1×10 16 atoms / cm 3 More than 2×10 20 atoms / cm 3 Below is good Preferably 1×10 16 atoms / cm 3 5×10 or more 19 atoms / cm 3 Below, More preferably 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 below , and more preferably 1×10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 In addition, in order to reduce the nitrogen concentration in the semiconductor 320, In particular, it is preferable to reduce the nitrogen concentration in the semiconductor 320a and the semiconductor 320c. a and semiconductor 320c are 1×10 15 atoms / cm 3Over 5 ×10 19 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 Over 5 ×10 18 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 Below top 1×10 18 atoms / cm 3 Less than 1×10, more preferably 15 atoms / c m 3 5×10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0099] The three-layer structure described above is an example. For example, a two-layer structure without semiconductor 320a or semiconductor 320c Alternatively, the semiconductor 320a may be disposed above or below the semiconductor 320c. Above and below, the semiconductors exemplified as semiconductor 320a, semiconductor 320, and semiconductor 320c are Alternatively, a four-layer structure may be used in which the semiconductor 320a is on the upper side of the semiconductor 320b and the semiconductor 320c is on the lower side of the semiconductor 320a. At least two of the following locations are located below the conductor 320a, above the semiconductor 320c, and below the semiconductor 320c: Any one of the semiconductors exemplified as the semiconductor 320a, the semiconductor 320, and the semiconductor 320c. Alternatively, the layer may have an n-layer structure (n is an integer of 5 or more).

[0100] The structure of an oxide semiconductor will be described below.

[0101] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Examples of the oxide semiconductor include a conductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor.

[0102] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors.

[0103] First, let me explain about CAAC-OS. xis aligned nanocrystals) It is also possible.

[0104] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0105] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0106] The following describes the CAAC-OS observed by TEM. The high-resolution TEM image of the cross section of CAAC-OS observed from a direction approximately parallel to the sample surface is shown. For high-resolution TEM image observation, spherical aberration correction is required. The spherical aberration corrector function was used. The acquisition of Cs-corrected high-resolution TEM images is carried out by, for example, This is carried out using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Denshi Co., Ltd. can be done.

[0107] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 5(A) is shown in Figure 5(B). From (B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each atomic layer is determined by the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). It reflects the unevenness of the surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0108] As shown in Figure 5(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines. The size of each pellet is about 1 nm to 3 nm, and the inclination of the pellets The size of the gap that is generated by the pellet is about 0.8 nm. , they can also be called nanocrystals (nc).

[0109] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 5(D)). The inclination between the pellets observed in FIG. 5(C) The location where this occurs corresponds to the region 5161 shown in FIG.

[0110] In addition, Fig. 6(A) shows the Cs compensation of the plane of the CAAC-OS observed from a direction almost perpendicular to the sample surface. The positive high-resolution TEM images are enlarged views of areas (1), (2), and (3) in Fig. 6(A). The Cs-corrected high-resolution TEM images are shown in Fig. 6(B), Fig. 6(C), and Fig. 6(D), respectively. As shown in Fig. 6(B), Fig. 6(C) and Fig. 6(D), the pellet has metal atoms arranged in a triangular shape. However, it can be seen that the different pentagons are arranged in a square, rectangular or hexagonal shape. There is no regularity in the arrangement of metal atoms between the reds.

[0111] Next, the CA analyzed by X-ray diffraction (XRD) Explain AC-OS. For example, InGaZnO 4 CAAC-OS with crystals of When structural analysis is performed using the out-of-plane method, the result is as shown in Figure 7(A). A peak may appear at a diffraction angle (2θ) of around 31°. This peak is due to the InGaZn O 4 Since the crystal orientation of CAAC-OS is attributed to the (009) plane of the crystal, it is considered that the crystal of CAAC-OS has a c-axis orientation. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0112] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0113] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In GaZnO 4 In the case of CAAC-OS, the 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. , InGaZnO 4 In the case of a single crystal oxide semiconductor, 2θ is fixed at around 56° and φ is When the ion beam was scanned, a peak was observed that was assigned to a crystal plane equivalent to the (110) plane, as shown in FIG. Therefore, the structure analysis using XRD shows that CAAC-OS has a-axis It can be seen that the orientation of the b axis is irregular.

[0114] Next, we will explain the CAAC-OS analyzed by electron diffraction. nO 4 For CAAC-OS with a crystal of 100 nm, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction pattern) like that shown in Figure 8(A) is generated. This diffraction pattern may show a pattern of InGaZnO 4 The result The spots due to the (009) plane of the crystal are included. Therefore, the electron diffraction also shows that The pellets contained in the AAC-OS have a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the film is formed or the upper surface. On the other hand, for the same sample, the probe diameter is perpendicular to the sample surface. The diffraction pattern when an electron beam of 300 nm is incident is shown in FIG. 8(B). A ring-shaped diffraction pattern is observed. Therefore, CAA is also confirmed by electron diffraction. It can be seen that the a-axis and b-axis of the pellets contained in the C-OS do not have any orientation. The first ring in FIG. 8(B) is InGaZnO 4 The (010) and (10 0) plane. The second ring in FIG. 8(B) is the (110) This is thought to be due to factors such as the surface.

[0115] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects include impurity-induced defects and oxygen vacancies. C-OS can also be considered an oxide semiconductor with a low impurity concentration. It can also be said that the oxide semiconductor has few oxygen vacancies.

[0116] Impurities contained in an oxide semiconductor can act as carrier traps or carrier generation sources. In addition, oxygen vacancies in an oxide semiconductor may become carrier traps or may cause hydrogen By capturing atoms, they can become a carrier generation source.

[0117] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0118] In addition, an oxide semiconductor with a low density of defect states (few oxygen vacancies) can reduce the carrier density. Such an oxide semiconductor can be obtained by using a high-purity intrinsic or substantially high-purity intrinsic oxide. CAAC-OS has a low impurity concentration and a low density of defect states. It is easy to obtain a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. A transistor using C-OS has electrical characteristics in which the threshold voltage is negative (normal In addition, the acid is highly pure or substantially pure. The oxide semiconductor has fewer carrier traps. The charge takes a long time to be discharged and behaves like a fixed charge. Therefore, transistors using oxide semiconductors with high impurity concentrations and high defect state densities are On the other hand, transistors using CAAC-OS may have unstable electrical characteristics. The resulting transistor has small fluctuations in electrical characteristics and is highly reliable.

[0119] In addition, because the density of defect states in CAAC-OS is low, the capacitive coupling generated by light irradiation can be suppressed. Therefore, the transistor using CAAC-OS is less likely to be captured by the defect level. The electrical characteristics of a transistor vary little when exposed to visible or ultraviolet light.

[0120] Next, a microcrystalline oxide semiconductor will be described.

[0121] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often found. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline- The nc-OS is called the "High Resolution Oxide Semiconductor." In some cases, the grain boundaries cannot be clearly seen in the TEM images. Therefore, in the following, we will refer to the pellets in nc-OS as the pellets of the same origin. The crystalline part of S is sometimes called a pellet.

[0122] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peaks were detected. Also, for nc-OS, the probe diameter (e.g. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size. When the electron diffraction pattern is applied to the nc-OS, a spot is observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a patchy region.

[0123] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0124] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS is The defect level density is higher than that of AC-OS.

[0125] Next, the amorphous oxide semiconductor will be described.

[0126] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystal parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0127] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0128] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction is performed, no spots are observed, and only a halo pattern is observed. It is measured.

[0129] There are various views on amorphous structures. For example, A structure that does not have a completely amorphous structure is called a completely amorphous structure. In addition, although it does not have long-range order, the order of the nearest neighbors from a given atom is called a "cture." A structure that may have order in the range of an atom or the second nearest neighboring atom is called an amorphous structure. Therefore, according to the strictest definition, a material that has even a slight degree of order in its atomic arrangement is called a An oxide semiconductor having such a structure cannot be called an amorphous oxide semiconductor. An oxide semiconductor having distance order cannot be called an amorphous oxide semiconductor. Since the CAAC-OS and nc-OS have crystalline parts, for example, they are classified as amorphous oxide semiconductors. It cannot be called a conductor or a completely amorphous oxide semiconductor.

[0130] Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called

[0131] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portion can be identified.

[0132] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0133] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0134] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0135] The determination of which part is regarded as one crystal part can be made as follows. For example, InGaZnO 4 The unit cell of this crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing is 0.28 nm or more and 0.30 nm or less are InGaZnO 4 The crystal part of The lattice fringes can be formed by InGaZnO 4 This corresponds to the ab plane of the crystal.

[0136] Figure 9 shows an example of an investigation into the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of the OS grows larger according to the cumulative amount of electron irradiation. As shown by (1) in Fig. 9, the size of the particles was about 1.2 nm in the early stage of TEM observation. The crystal part (also called the initial nucleus) was exposed to a cumulative irradiation dose of 4.2 × 10 8 e - / nm 2 To In the case of nc-OS and CAAC-OS had a cumulative electron irradiation dose of 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals in the range from As shown in (2) and (3), the nc-OS and CAA were significantly increased regardless of the cumulative electron dose. The sizes of the crystal parts of C-OS are approximately 1.4 nm and 2.1 nm, respectively. You can understand.

[0137] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0138] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0139] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, Single-crystal InGaZnO with a helical crystal structure 4 The density of is 6.357g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0140] In some cases, single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0141] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a semiconductor and a CAAC-OS.

[0142] A conductor is deposited on the insulator 306, and unnecessary portions of the conductor are etched away to form a second gate. The second gate electrode 331 is formed of tantalum, tungsten, titanium, molybdenum, etc. Tungsten, aluminum, copper, molybdenum tungsten alloy, tungsten nitride, titanium nitride The material may be tantalum nitride, tantalum carbide, etc. Alternatively, a multi-layer structure may be used. The film formation method may be a sputtering method, a CVD method, an ALD method, or the like.

[0143] Next, an insulator 307 is formed to cover the insulator 306 and the second gate electrode 331. The insulator 307 can be formed of a film similar to that of the insulator 305 described above, and the same film formation method can be used. It is preferable to use an insulator that is difficult for oxygen to pass through. For example, an aluminum oxide film may be used.

[0144] An insulator 308 is deposited on the insulator 307. The insulator 308 is formed in the same manner as the insulator 301 described above. The insulator 308 may be formed by a similar method. CMP is performed to planarize the insulator 308 .

[0145] Next, the insulators 308, 307, and 306 are connected to the source electrode or the drain electrode. Contact holes reaching the top surfaces of the electrodes 312a and 312b are formed.

[0146] Next, a conductor 314 is formed, and a conductor 315 is formed on the conductor 314. The conductor 315 is made of tantalum, tungsten, titanium, molybdenum, aluminum, Copper, molybdenum tungsten alloy, tungsten nitride, titanium nitride, tantalum nitride, etc. The film can be formed by sputtering, CVD, ALD, etc. It is possible.

[0147] Next, CMP is performed until the top surface of the insulator 308 is reached, and the conductors 314 and 315 are This forms a plug.

[0148] Next, a conductor 316 is formed on the conductor 315 and the insulator 308. are tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum tungsten Tungsten alloy, tungsten nitride, titanium nitride, tantalum nitride, etc. can be used. Alternatively, it can be a multi-layer film. The film formation method includes sputtering, CVD, and AL. Next, the unnecessary portion of the conductor 316 is etched to remove the conductor. The electrode is formed from the body 316 .

[0149] Through the above steps, a semiconductor device including a transistor of one embodiment of the present invention can be manufactured. can.

[0150] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0151] (Embodiment 4) In this embodiment, the back gate electrode and wiring that are prevented from being oxidized as described in the third embodiment are An example of a semiconductor device using a transistor having layers will be described.

[0152] FIG. 10A shows an example of a circuit of a memory device, and FIG. 10B shows a cross-sectional view thereof.

[0153] The substrate 350 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide. Substrates made of silicon germanium and other materials, and compound semiconductor substrates made of silicon on insulator (SOI) It is also possible to use a substrate such as a GaN-GaN on Insulator (GaN-GaN on Insulator) substrate.

[0154] The transistor 100 is formed on the substrate 350. The transistor 100 is the same as that shown in FIG. Thus, a planar transistor having sidewalls 355 can be used. The transistor is STI351 (Shallow Trench Isolation). The transistor 100 is also formed by forming a fin as shown in FIG. Alternatively, the transistor 100 may be a p-channel transistor. Alternatively, a n-channel transistor may be used. Alternatively, both may be used. good.

[0155] In this embodiment, the transistor 100 uses single crystal silicon for a channel formation region. However, for example, an oxide semiconductor may be used for the channel formation region, and a silicon single crystal may be used. In addition, the insulator 354 having the function of a gate insulator may be For example, silicon oxide obtained by thermally oxidizing silicon single crystal may be used. Silicon film, silicon oxynitride film, silicon oxynitride film, silicon nitride film, aluminum oxide The film may be an aluminum film, an aluminum nitride film, a hafnium oxide film, or the like. , thermal oxidation method, CVD method, sputtering method, ALD method, plasma oxidation method, plasma nitridation method, etc. Alternatively, a laminated film can be formed by appropriately selecting from the above-mentioned films. .

[0156] An insulator 360 is formed on the transistor 100, the STI 351, and the diffusion layer 353. CMP is performed to flatten the surface of the insulator 360. The insulator 360 is a silicon oxide film. , silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, nitrogen The film may be formed by thermal oxidation. , CVD method, sputtering method, ALD method, plasma oxidation method, plasma nitridation method, etc. Planarization can be achieved by other processes, or by combining CMP and etching (dry It is also possible to combine the above-mentioned processes with other processes such as etching, wet etching, plasma treatment, etc.

[0157] A contact hole is formed in the insulator 360, the contact hole reaching the top surface of the gate electrode 330 of the transistor 100. Then, a contact hole is formed to reach the upper surface of the diffusion layer 353, and a conductor is inserted through the contact hole. Then, CMP is performed until the top surface of the insulator 360 is exposed. The plug 370, the plug 371, and the plug 372 are formed. For example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum Tungsten alloys and the like can be used. Alternatively, a laminate film can be formed by appropriately selecting a plurality of the above. The film may be formed by sputtering, CVD, ALD, plating, or the like. The laminated film may be formed by using a plurality of the above-mentioned forming methods.

[0158] Next, a conductor is formed on the insulator 360 to form wiring layers 373, 374, and 375. The wiring layer 373, the wiring layer 374, and the wiring layer 375 are formed by the above-mentioned plug 370, the plug The same film and film formation method as those for the gap 371 and the plug 372 can be used.

[0159] An insulator 361 is formed on the insulator 360 and on the wiring layer 373, the wiring layer 374, and the wiring layer 375. The surface of the insulator 361 is planarized by CMP. The same film and film formation method as those in 360 can be used.

[0160] The insulator 361 is provided with a wiring layer 373, a wiring layer 374, and a wiring layer 375. A contact hole and a groove are formed, and a conductor is embedded in the contact hole and the groove. Then, CMP is performed until the top surface of the insulator 361 is exposed, and a wiring layer serving as both a plug and a wiring layer is formed. 376, a wiring layer 377, and a wiring layer 378 are formed. The plug 378 is a film formed by the same method as the plugs 370, 371, and 372 described above. can be used.

[0161] Next, an insulator 362 is formed on the insulator 361, the wiring layer 376, the wiring layer 377, and the wiring layer 378. A wiring layer 37 serving as both a plug and a wiring layer is formed in the same manner as the insulator 361 described above. 9, wiring layer 380 and wiring layer 381 are formed. The insulator 362 is the same as the insulator 360 described above. The same films and film forming methods can be used. 1 uses the same film and film formation method as the plugs 370, 371, and 372 described above. The formation of the wiring layer, which also serves as the plug, can be performed by a method such as the above-mentioned. The above-described method can be repeated to fabricate a highly integrated semiconductor device. .

[0162] Next, an insulator 363 is formed on the insulator 362, the wiring layer 379, the wiring layer 380, and the wiring layer 381. The insulator 363 is formed by using the same film and film formation method as the insulator 360 described above. The insulator 363 preferably has a function of being difficult to permeate by hydrogen. Alternatively, the insulator 363 does not need to be formed.

[0163] The insulator 302 is formed on the insulator 363, and the transistor 1 is formed by the method described in the third embodiment. Form 10.

[0164] Next, an insulator 308 is formed, and a plug 382, ​​a plug 383, and a plug 384 are formed. A wiring layer 385 is formed on the plug 382, ​​the plug 383, and the plug 384, respectively. The wiring layer 386 and the wiring layer 387 are formed.

[0165] Next, an insulating layer is formed on the insulator 308, the wiring layer 385, the wiring layer 386, and the wiring layer 387. The insulator 364 is formed, and the surface of the insulator 364 is planarized by CMP. The same film and film formation method as those for the insulator 360 described above can be used.

[0166] Contact holes are formed in the insulator 364, reaching the upper surfaces of the wiring layers 386 and 387. Then, the conductor is embedded in the contact hole, and CMP is performed until the top surface of the insulator 364 is exposed. The plugs 388 and 389 are formed by: The same films and film formation methods as those for the plugs 370, 371, and 372 described above are used. This can be done.

[0167] Next, a conductor is formed on the insulator 364, and one electrode 341 of the capacitor element 130 and a wiring layer The electrode 341 and the wiring layer 390 are connected to the plug 370 and the plug 3 The same film and film formation method as those for the plug 372 can be used. The other electrode 342 is formed so as to overlap the electrode 341 via an insulator. Then, an insulator 365 is formed, and the surface of the insulator 365 is planarized by CMP. For the insulator 5, the same film and film formation method as those for the insulator 360 described above can be used.

[0168] A contact hole is formed in the insulator 365 so as to reach the top surface of the other electrode 342 of the capacitor element 130. On the other hand, a contact hole is formed to reach the upper surface of the wiring layer 390, and a conductor is inserted into the contact hole. The plug 391 is embedded in the hole and CMP is performed until the top surface of the insulator 365 is exposed. The plug 391 and the plug 392 are the same as the plug 37 described above. 0, the plug 371, and the plug 372 can be formed by the same film and film formation method.

[0169] Next, a conductor is deposited on the insulator 365 to form a wiring layer 393 and a wiring layer 394. The line layer 393 and the wiring layer 394 are formed by the above-mentioned plugs 370, 371, and 372. The same films and film formation methods can be used.

[0170] In addition, the planar type capacitance element 130 shown in FIG. 10 is replaced with a cylindrical type capacitance element shown in FIG. The capacitor element 140 may be formed as shown in FIG. This is more preferable since it allows the capacitor to be fabricated in a smaller area than the capacitor 130.

[0171] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0172] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0173] (Embodiment 5) <Imaging device> An imaging device according to an aspect of the present invention will be described below.

[0174] FIG. 13A is a plan view illustrating an example of an imaging device 200 according to one embodiment of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) have a plurality of pixels 211 arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 each include a plurality of The pixel 211 is connected to the pixel 211 and has a function of supplying a signal for driving the pixel 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 may be considered a part of the peripheral circuit.

[0175] The imaging device 200 preferably also includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0176] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the same substrate as the pixel portion 210. Also, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuits. The peripheral circuits are a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. Any one or more of these may be omitted.

[0177] As shown in FIG. 13B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel size in the row direction and the pixel size in the pixel area can be increased. The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the captured images.

[0178] <Pixel configuration example 1> The imaging device 200 has a pixel 211 that is composed of a plurality of sub-pixels 212. The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By this, it is possible to obtain information for realizing a color image display.

[0179] FIG. 14A is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 14(A) is provided with a color filter that transmits the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") transmits light in the green (G) wavelength band. A subpixel 212 (hereinafter also referred to as "subpixel 212G") provided with a color filter A subpixel 212 (hereinafter, referred to as a “subpixel”) is provided with a color filter that transmits light in the blue (B) wavelength band. The sub-pixel 212 can function as a photosensor. This can be done.

[0180] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, The wiring 248 and the wiring 249 are respectively represented as wiring 248[n] and wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the mth column is designated as wiring 253[m]. In FIG. 14A, the sub-pixel 212R of the pixel 211 in the m-th column is written as The wiring 253 connected to the subpixel 212G is disposed as wiring 253[m]R. The wiring 253 connected to the line 253[m]G and the subpixel 212B is referred to as a wiring 253[m]B. The subpixel 212 is electrically connected to the peripheral circuit via the wiring.

[0181] In addition, the imaging device 200 has color filters that transmit the same wavelength band for adjacent pixels 211. The sub-pixels 212 in which the transistors are provided are electrically connected to each other via switches. 14(B), arranged in n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q) A sub-pixel 212 of the pixel 211 and a sub-pixel 213 arranged in the n+1th row and the mth column adjacent to the pixel 211 14B shows an example of a connection of the sub-pixels 212 of the pixel 211. The sub-pixel 212R arranged in the n+1th row and the mth column is switched In addition, the sub-pixel 212G arranged in the nth row and the mth column is connected via the n+1 The sub-pixels 212G arranged in rows and columns m are connected via the switches 202. The sub-pixel 212B arranged in row m and column m and the sub-pixel 212B arranged in row (n+1) and column m are switched. The two are connected via a switch 203.

[0182] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 211 may have three sub-pixels for detecting light of different wavelength bands. By providing 212, a full color image can be obtained.

[0183] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are provided. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Alternatively, pixel 211 may be used with pixel 212, or with cyan (C), yellow (Y In addition to the subpixel 212 provided with a color filter that transmits light of red (A) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. A single pixel 211 may include sub-pixels 211 for detecting light of four different wavelength bands. By providing the second filter 12, the color reproducibility of the captured image can be further improved.

[0184] Also, for example, in FIG. 14A, a sub-pixel 212 detects the red wavelength band, The ratio of the number of sub-pixels 212 that detect the blue wavelength band and the number of sub-pixels 212 that detect the blue wavelength band ( or light receiving area ratio) does not have to be 1:1:1. For example, The Bayer array may be used with red:green:blue=1:2:1. The light area ratio may be red:green:blue=1:6:1.

[0185] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the device 200.

[0186] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0187] In addition, ND (Neutral Density) filters are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows the dynamic range of the device to be increased.

[0188] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described with reference to a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 15A, a lens 255 and a filter 25 are formed in a pixel 211. 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0189] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is Therefore, as shown in FIG. 15(B), A lens 255 and a filter 254 are disposed on the conversion element 220 side. It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, the imaging device 200 with high detection sensitivity is provided. can be done.

[0190] The photoelectric conversion element 220 shown in FIG. 15 has a pn-type junction or a pin-type junction. A photoelectric conversion element may also be used.

[0191] In addition, the photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be a sintered material. Iron, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0192] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0193] Here, one pixel 211 included in the imaging device 200 has, in addition to the sub-pixel 212 shown in FIG. 2, may include a subpixel 212 having a first filter.

[0194] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of forming a pixel using the above will be described.

[0195] 16(A) and 16(B) are cross-sectional views of elements constituting an imaging device. The imaging device shown in FIG. 1 includes a silicon transistor 55 provided on a silicon substrate 500. 1. Transistor 55 using an oxide semiconductor stacked over transistor 551 2 and a transistor 553, and a photodiode provided on the silicon substrate 500. Each transistor and photodiode 560 is connected to a different plug 570. and is electrically connected to the wiring 571. 61 has an electrical connection to plug 570 via low resistance region 563 .

[0196] The imaging device includes a transistor 551 and a photodiode 552 provided on a silicon substrate 500. A layer 510 having an electrode 560 and a layer 571 having wiring 571 provided in contact with the layer 510. 20 and a layer 520, and includes a transistor 552 and a transistor 553. A layer 530 is provided in contact with the layer 530 and has wiring 572 and wiring 573. It has 40.

[0197] In the example of the cross-sectional view of FIG. 16A, the transistor 55 is disposed on the silicon substrate 500. The light receiving surface of the photodiode 560 is located on the surface opposite to the surface on which the photodiode 1 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. This makes it possible to form pixels with a high aperture ratio. The light receiving surface of 560 may be the same as the surface on which the transistor 551 is formed.

[0198] In the case where a pixel is formed using a transistor including an oxide semiconductor, the layer 530 Alternatively, the layer 510 may be omitted and an oxide semiconductor may be used. A pixel may be formed by only the transistor.

[0199] When a pixel is constructed using a silicon transistor, the layer 530 is omitted. An example of a cross-sectional view in which the layer 530 is omitted is shown in FIG.

[0200] The silicon substrate 500 may be an SOI substrate. Instead, germanium, silicon germanium, silicon carbide, gallium arsenide, and aluminum arsenide The substrate has a gallium nitride, indium phosphide, gallium nitride or organic semiconductor. You can also be there.

[0201] Here, a layer 510 having a transistor 551 and a photodiode 560, An insulator 580 is provided between the layer 530 having the resistor 552 and the transistor 553. However, the position of the insulator 580 is not limited.

[0202] The hydrogen in the insulator provided near the channel formation region of the transistor 551 is converted into silicon diaphragm. This has the effect of terminating the ring bond and improving the reliability of the transistor 551. , hydrogen in an insulator provided near the transistor 552 and the transistor 553, etc. This is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in reliability of the transistor 52 and the transistor 553. Therefore, a transistor using an oxide semiconductor is placed on top of a transistor using a silicon semiconductor. When the capacitors are stacked, an insulator 580 having a function of blocking hydrogen is provided between them. It is preferable to provide the insulator 580. By confining hydrogen below the insulator 580, the transistor The reliability of the insulator 551 can be improved. Since hydrogen diffusion to layers above 580 can be suppressed, the transistor 552 and the transistor This can improve the reliability of the transistor 553 and the like.

[0203] For the insulator 580, for example, the description of the insulator 363 can be referred to.

[0204] In addition, in the cross-sectional view of FIG. 16A, a photodiode 560 provided in the layer 510 and a The transistor 530 can be formed so as to overlap with the transistor 530. In other words, the resolution of the imaging device can be increased.

[0205] As shown in FIG. 17(A1) and FIG. 17(B1), a part or the whole of the imaging device may be 17(A1) shows the imaging device in the direction of the dashed line X1-X2 in the figure. FIG. 17(A2) shows the curved state. FIG. 17(A3) is a cross-sectional view of the portion indicated by the dashed line Y1-2 in FIG. This is a cross-sectional view of the portion indicated by Y2.

[0206] FIG. 17(B1) shows a case where the imaging device is bent in the direction of the dashed line X3-X4 in the same figure, and FIG. 17B2 shows a state where the wire is bent in the direction of the dashed line Y3-Y4 in the figure. FIG. 17(B3) is a cross-sectional view of a portion indicated by a dashed line X3-X4 in FIG. 17(B1) is a cross-sectional view of a portion indicated by dashed dotted line Y3-Y4 in FIG.

[0207] By curving the imaging device, it is possible to reduce the field curvature and astigmatism. This makes it easier to design the lenses and other components used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, which contributes to the miniaturization of electronic devices that use imaging devices. It is possible to realize a lighter weight and a smaller camera. It is also possible to improve the quality of the captured image. .

[0208] (Embodiment 6) In this embodiment, an RF device including the transistor or memory device described in the above embodiment will be The tag will be described with reference to FIG.

[0209] The RF tag in this embodiment has a memory circuit therein and stores necessary information in the memory circuit. In addition, information is exchanged with the outside world using non-contact means, such as wireless communication. Due to these characteristics, RF tags are used as individual devices to identify items by reading their individual information. It can be used for biometric authentication systems, etc. High reliability is required.

[0210] The structure of an RF tag will be described with reference to FIG. 18. FIG. 18 is a block diagram showing an example of the structure of an RF tag. FIG.

[0211] As shown in FIG. 18, an RF tag 800 includes a communicator 801 (also called an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the 04. The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectifying effect included in the demodulation circuit 807 is sufficiently suppressed. A material capable of suppressing the electric field, for example, an oxide semiconductor, may be used. This suppresses the deterioration of the rectification effect caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and communication is carried out by mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses radio waves to communicate, The RF tag 800 shown in this embodiment can be used with any of these methods. It is also possible to use it for.

[0212] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 is a rectifier for an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side of the rectifier circuit 805. A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent a certain amount of power from being input to the downstream circuit. This is a circuit for controlling the

[0213] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may include a reset signal generating circuit. The reset signal generating circuit uses the stable rise of the power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0214] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit that performs modulation based on the

[0215] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. This is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 also stores a unique number (ID) and outputs it according to the processing. This is a circuit for this purpose.

[0216] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0217] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. The memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required to write data is significantly smaller than that of conventional non-volatile memory. It is also possible to eliminate the difference in maximum communication distance during reading and writing. To prevent malfunction or erroneous writing caused by a power shortage when writing data can be done.

[0218] In addition, the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must input the data to ROM811. A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF tag that is produced, only good products that are shipped will be assigned a unique number. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0219] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0220] (Embodiment 7) In this embodiment, at least the transistors described in the embodiment can be used. A CPU including the storage device described in the above embodiment will be described.

[0221] FIG. 19 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 1 is a block diagram showing a configuration of an example.

[0222] The CPU shown in FIG. 19 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, etc. A glass substrate or the like is used. The ROM 1199 and the ROM interface 1189 are Of course, the CPU shown in FIG. 19 is a simplified version of the configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, The configuration including the CPU or arithmetic circuit shown in FIG. 19 is regarded as one core, and includes multiple such cores, The cores may be configured to operate in parallel. The number of bits that can be handled by the data bus is, for example, 8 bits, 16 bits, 32 bits, and 64 bits. It can be, for example,

[0223] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0224] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates addresses and reads and writes to register 1196 depending on the state of the CPU.

[0225] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. An internal clock generating unit is provided, which supplies an internal clock signal to the various circuits described above.

[0226] In the CPU shown in FIG. 19, a register 1196 is provided with a memory cell. The transistors shown in the above embodiment can be used as the memory cells of 1196. do.

[0227] In the CPU shown in FIG. 19, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, a power supply voltage is applied to the memory cells in the register 1196. If data retention is selected in the capacitive element, rewriting data to the capacitive element This allows the supply of the power supply voltage to the memory cells in the register 1196 to be stopped. .

[0228] FIG. 20 is an example of a circuit diagram of a storage circuit that can be used as the register 1196. The memory circuit 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory circuit 1200 may include a diode, a resistor, an inductor, etc., as necessary. The semiconductor device may further include other elements such as a capacitor.

[0229] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory circuit 1200 is stopped, the transistor 120 The gate of the transistor 9 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the gate of the transistor 1209 is connected through a load such as a resistor. The configuration will be based on the above.

[0230] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The other drain of the switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., truncation) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0231] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection portion is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. One of the source and drain of the transistor 1210 is connected to a low power supply potential. The other is electrically connected to a wiring (e.g., a GND line) that can supply a 203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) The first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ) is electrically connected to the second terminal of the switch 1204 (the source of the transistor 1214). The other of the source and drain is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) and a first terminal of the switch 1204 (one of the source and drain of the transistor 1214). The input terminal of the logic element 1206 and one of the pair of electrodes of the capacitor 1207 are The connection point is referred to as a node M1. The other of the electrodes may be configured to have a constant potential input thereto. For example, A potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1207 is a wiring that can supply a low power supply potential. (for example, a GND line) is electrically connected to the other of the pair of electrodes of the capacitor 1208. For example, a low power supply potential (GND, etc.) can be input to the Alternatively, a high power supply potential (such as VDD) can be input. The other of the pair of electrodes is a wiring that can supply a low power supply potential (for example, a GND line ) is electrically connected to

[0232] The capacitors 1207 and 1208 are formed by accumulating parasitic capacitances of transistors and wirings. It is possible to omit it by using it in an extreme manner.

[0233] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD that is different from the control signal WE. Thus, a conductive state or a non-conductive state between the first terminal and the second terminal is selected, and one of the switches When the first and second terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a conductive state. There is no continuity between the terminals.

[0234] The other of the source and drain of the transistor 1209 is connected to a data register 1204. In FIG. 20, the signal output from the circuit 1201 corresponds to the The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0235] In FIG. 20, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is fed to the logic element 1206 and the circuit 1220. 1201 is shown as an example, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted in logic value. For example, the input may be input to the circuit 1201 without being If there is a node that holds a signal with the logic value of the signal input from the input terminal inverted, , the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the input terminal can be input to the node.

[0236] In addition, in FIG. 20, among the transistors used in the memory circuit 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed at 0 can be used. The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory circuit 1200 may include a transistor other than the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be a transistor having a capacitance of 100 .mu.m.

[0237] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0238] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory circuit 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0239] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor The off-current is significantly lower than that of transistors with a channel formed in silicon. By using this transistor as the transistor 1209, The signal held in the capacitance element 1208 is maintained for a long period of time even while the power supply voltage is not supplied to the In this way, the memory circuit 1200 can retain the stored contents (data) even when the supply of the power supply voltage is stopped. ) can be held.

[0240] In addition, by providing the switches 1203 and 1204, the precharge operation Since this is a memory circuit characterized by performing the above, after the supply of the power supply voltage is resumed, the circuit 1201 is restored to its original state. This can shorten the time it takes to re-store the data.

[0241] In the circuit 1202, the signal held by the capacitor 1208 is 1210. Therefore, the supply of the power supply voltage to the memory circuit 1200 is resumed. After that, the signal held by the capacitance element 1208 is converted into the state of the transistor 1210 ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal can be read out accurately.

[0242] Such a memory circuit 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0243] In the present embodiment, the memory circuit 1200 is used as a CPU. The 200 is equipped with a DSP (Digital Signal Processor), custom L SI, PLD (Programmable Logic Device) and other LSIs, R Can also be used for F-tags (Radio Frequency Identification) It is Noh.

[0244] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0245] (Embodiment 8)

[0246] A display device according to one embodiment of the present invention will be described below with reference to FIGS. 21 and 22. do.

[0247] Display elements used in display devices include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, etc. The light-emitting element can be a light-emitting display element. Therefore, the category includes elements whose luminance can be controlled, specifically inorganic EL (Electroluminescent) The following is an example of a display device. Display devices using EL elements (EL display devices) and display devices using liquid crystal elements (liquid crystal display devices) This section explains the display device.

[0248] The display device described below is a panel in which a display element is sealed, and a control circuit is attached to the panel. This includes modules in which ICs including controllers are mounted.

[0249] The display device described below refers to an image display device or a light source (including a lighting device). Also, connectors, such as FPC, modules with TCP attached, and TCP with printers A module or display element with a printed wiring board has an IC (integrated circuit) mounted on it by the COG method. The display device also includes all modules mounted on the display device.

[0250] 21A and 21B are diagrams illustrating an example of an EL display device according to one embodiment of the present invention. FIG. 21(B) is a top view showing the entire EL display device. FIG. 21C is a cross section of the MN corresponding to a part of the dashed line MN in FIG. 21B. .

[0251] FIG. 21A is an example of a circuit diagram of a pixel used in an EL display device.

[0252] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of devices (capacitive elements, resistive elements, etc.), the connection destination is not specified. However, a person skilled in the art may be able to configure one aspect of the invention. Even if the destination is not specified, one aspect of the invention is clear. When the contents are described in this specification, etc., one aspect of the invention that does not specify a connection destination is the same as the embodiment of the present specification. In particular, if the terminal is connected to multiple When multiple locations are anticipated, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistive elements) By specifying the connection destinations of only some of the terminals on It may be possible to configure a clear embodiment.

[0253] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art can identify an invention by at least specifying the function. In other words, if the function is specified, one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0254] The EL display device shown in FIG. 21A includes a switch element 743, a transistor 741, and a capacitor. The light emitting element 719 includes a capacitance element 742 and a light emitting element 719 .

[0255] Note that FIG. 21A is an example of a circuit configuration, and therefore, if a transistor is further added, Conversely, at each node in FIG. It is also possible to avoid adding passive elements.

[0256] The gate of the transistor 741 is connected to one end of the switch element 743 and one end of the capacitance element 742. The source of the transistor 741 is electrically connected to the other electrode of the capacitor 742. and is electrically connected to one electrode of the light-emitting element 719. The drain of the switch element 741 is supplied with a power supply potential VDD. The other end of the switch element 743 is connected to the signal line 7 The other electrode of the light-emitting element 719 is electrically connected to the light-emitting element 44. A constant potential is applied to the other electrode of the light-emitting element 719. The constant potential is the ground potential GND or a potential lower than that.

[0257] It is preferable to use a transistor as the switch element 743. This allows the pixel area to be reduced, resulting in an EL display device with high resolution. The switch element 743 is a transistor manufactured through the same process as the transistor 741. By using the transistor 74, the productivity of the EL display device can be improved. As the switch element 743, for example, the above-mentioned transistor is applied. It is possible.

[0258] 21B is a top view of the EL display device. The EL display device is made up of a substrate 700 and a substrate 7 50, a sealant 734, a driving circuit 735, a driving circuit 736, a pixel 737, and an FP The sealing material 734 includes the pixel 737, the driving circuit 735, and the driving circuit The driving circuit 735 is disposed between the substrate 700 and the substrate 750 so as to surround the driving circuit 736. Alternatively / and the driving circuit 736 may be disposed outside the sealing material 734 .

[0259] FIG. 21C is a cross-sectional view of an EL display device corresponding to a part of the dashed line MN in FIG. 21B. It is.

[0260] In FIG. 21C, a transistor 741 is shown having an insulator 708 and an insulator 708, and a conductor 704a embedded in the insulator 708 and the conductor 704a an insulator 712a on the insulator 712a, an insulator 712b on the insulator 712a, and an insulator 712b on the insulator 712b. A semiconductor 706 overlapping the conductor 704a, a conductor 716a in contact with the semiconductor 706, and a conductor conductor 716b, and insulator 716 on semiconductor 706, conductor 716a, and conductor 716b. 18a, an insulator 718b on the insulator 718a, and an insulator 718c on the insulator 718b. 7 shows a structure having a conductor 714a on an insulator 718c overlapping a semiconductor 706. Note that the structure of the transistor 741 is just an example, and a structure different from that shown in FIG. The conductor 704a may be a wiring layer formed by the method described in the first embodiment. It may be used.

[0261] Therefore, in the transistor 741 shown in FIG. The insulators 712a and 712b function as gate insulators. The conductor 716a functions as a source electrode, and the conductor 716b functions as a drain electrode. The insulators 718a, 718b, and 718c function as gate electrodes. The conductor 714a functions as a gate insulator, and the conductor 714b functions as a gate electrode. The electrical characteristics of the semiconductor 706 may change when exposed to light. At least one of the conductor 704a, the conductor 716a, the conductor 716b, and the conductor 714a is shielded. It is preferable that the photosensitive material has a photoresist property.

[0262] The interface between the insulator 718a and the insulator 718b is shown by a dashed line. For example, insulators 718a and 718b may not be clearly defined. Therefore, when the same type of insulator is used, it may be difficult to distinguish between the two depending on the observation method.

[0263] In FIG. 21C, an insulator 708 on a substrate and a capacitor buried in the insulator 708 are used as a capacitor 742. The embedded conductor 704b, the insulator 708, and the insulator 712a on the conductor 704b. , an insulator 712b on the insulator 712a, and a conductor 704b on the insulator 712b. A conductor 716a is connected to the insulator 718a. An insulator 718a is connected to the insulator 718a. 718b, an insulator 718c on the insulator 718b, and a conductor 71 6a and conductor 714b overlapping each other, and the overlapping portion of conductor 716a and conductor 714b In the region, a portion of the insulator 718a and the insulator 718b are removed. The conductor 704b may be a wiring layer formed by the method described in the first embodiment.

[0264] In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode. The conductor 716a serves as the other electrode.

[0265] Therefore, the capacitor 742 can be formed using a film common to the transistor 741. In addition, it is preferable that the conductor 704a and the conductor 704b are made of the same type of conductor. In this case, the conductor 704a and the conductor 704b can be formed through the same process. In addition, the conductor 714a and the conductor 714b are preferably made of the same type of conductor. In this case, the conductor 714a and the conductor 714b can be formed through the same process. .

[0266] A capacitor 742 shown in FIG. 21C has a large capacitance per occupied area. Therefore, the EL display device shown in FIG. 21C has high display quality. The illustrated capacitive element 742 is formed by thinning the overlapping area of ​​the conductor 716a and the conductor 714b. Therefore, the insulator 718a and the insulator 718b are partially removed. The capacitive element according to one embodiment is not limited to this. For example, the conductors 716a and A structure in which a part of the insulator 718c is removed to thin the overlapping area of ​​the conductor 714b. It is okay to have one.

[0267] An insulator 720 is provided over the transistor 741 and the capacitor 742. The insulator 720 extends to a conductor 716a which serves as a source electrode of the transistor 741. The insulator 720 may have an opening. A conductor 781 is disposed on the insulator 720. The conductor 78 1 may be electrically connected to transistor 741 through an opening in insulator 720.

[0268] A partition 784 having an opening reaching the conductor 781 is disposed over the conductor 781. A light-emitting layer 782 is disposed on the wall 784 so as to be in contact with the conductor 781 at the opening of the partition wall 784. A conductor 783 is disposed over the light-emitting layer 782. The overlapping region of the conductor 783 becomes the light-emitting element 719 .

[0269] So far, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described. do.

[0270] FIG. 22A is a circuit diagram showing an example of the configuration of a pixel of a liquid crystal display device. The pixel shown in FIG. A transistor 751, a capacitor element 752, and an element in which liquid crystal is filled between a pair of electrodes (liquid crystal The liquid crystal element 753 is also included.

[0271] In the transistor 751, one of the source and the drain is electrically connected to a signal line 755. The gate is electrically connected to a scan line 754 .

[0272] In the capacitor 752, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential.

[0273] In the liquid crystal element 753, one electrode is electrically connected to the other of the source and drain of the transistor 751. The other electrode is electrically connected to a wiring that supplies a common potential. A common potential applied to a wiring to which the other electrode of the capacitor 752 is electrically connected, The common potential applied to the other electrode of the liquid crystal element 753 may be a potential different from that.

[0274] The liquid crystal display device will be described assuming that the top view is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dotted-chain line MN is shown in FIG. In this case, the FPC 732 is connected to the wiring 733a via the terminal 731. 3a is a conductor or a semiconductor of the same type as the conductor or semiconductor that constitutes the transistor 751. Alternatively, a semiconductor may be used.

[0275] For the transistor 751, refer to the description of the transistor 741. For 752, refer to the description of the capacitor 742. Although the structure of the capacitor 752 corresponding to the capacitor 742 in (C) is shown, the present invention is not limited to this. stomach.

[0276] Note that when an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current is extremely small. Therefore, the charge held in the capacitor 752 can be Therefore, the voltage applied to the liquid crystal element 753 can be maintained for a long period of time. Therefore, when displaying a moving image or a still image with little movement, the transistor 751 is turned off. This eliminates the need for power to operate the transistor 751, and the liquid crystal display has low power consumption. In addition, the area occupied by the capacitor 752 can be reduced; It is possible to provide a liquid crystal display device with a high aperture ratio or a high-definition liquid crystal display device.

[0277] An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening that reaches the transistor 751. The conductor 791 is disposed on the insulator 721. The conductor 791 is connected to the transistor Electrically connect to 751.

[0278] An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is disposed on the liquid crystal layer 793. An insulator 794 that functions as an alignment film is disposed on the liquid crystal layer 793. 94 is disposed on the insulator 794. A spacer 795 is disposed on the insulator 794. A conductor 796 is disposed on the insulator 794. The substrate 79 7 is placed.

[0279] By using the above-mentioned structure, it is possible to provide a display device having a capacitance element with a small occupancy area. Alternatively, a display device with high display quality can be provided. It is possible to provide a display device.

[0280] For example, in this specification and the like, the term "display element," "display device having a display element," "light-emitting element," A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various A display element, a display device, a light-emitting element, or a light-emitting device may include, for example, For example, EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (current-dependent transistors that emit light when exposed to light, electron emitters, liquid crystal elements, electronic ink, electrophoretic elements, graphene rating light valve (GLV), plasma display (PDP), MEMS Display element using microelectromechanical system, digital micromirror DMD (Digital Micro Shutter), DMS (Digital Micro Shutter), IMOD (Interface Modulation Device) Optical interference, optical shutter-type MEMS display element MEMS display element, electrowetting element, piezoelectric ceramic display , a display element using carbon nanotubes, etc. In addition, contrast, brightness, reflectance, transmittance, etc. can change due to electrical or magnetic effects. The display device may have a display medium that changes the display mode.

[0281] An example of a display device using an EL element is an EL display. An example of a display device using this method is a field emission display (FED). is a flat panel display using the SED method (SED: Surface-conduction E LCD displays are used in the following applications: An example of the device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). play, reflective LCD, direct-view LCD, projection LCD) Display devices using electronic ink, electronic liquid powder, or electrophoretic elements An example of such a display is electronic paper. When realizing a liquid crystal display, a part or all of the pixel electrodes are used as reflective electrodes. For example, a part or the whole of the pixel electrode may be made of aluminum. In this case, the reflective electrode may have a thickness of 100 nm or less, and the reflective electrode may have a thickness of 100 nm or less. This can further reduce power consumption. can be done.

[0282] When using an LED, graphene or graphene is placed under the LED electrode or nitride semiconductor. Graphene and graphite can be arranged in layers to form a multilayer film. In this way, by providing graphene or graphite, it is possible to form a nitride on the graphene or graphite. Semiconductors, such as n-type GaN semiconductors having crystals, can be easily formed into films. Furthermore, a p-type GaN semiconductor having crystals can be placed on top of it to form an LED. It is possible to fabricate a crystalline n-type GaN semiconductor using graphene or graphite. An AlN layer may be provided. The GaN semiconductor in the LED is formed by MOCVD. However, by providing graphene, the GaN semiconductor of the LED can be It is also possible to form the film by a tar deposition method.

[0283] (Embodiment 9) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, audio playback devices (car audio, digital audio players, copiers, fax machines, printers, printer-combiners, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0284] FIG. 23A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation key 907, stylus 908 The portable game machine shown in FIG. 23A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0285] FIG. 23B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit 9 13, a second display unit 914, a connection unit 915, an operation key 916, etc. The first display unit 911 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. 12. Also, the first display unit 913 and A display device in which a function as a position input device is added to at least one of the second display units 914 The function as a position input device may be realized by using a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photo It can also be added by providing a photoelectric conversion element, also called a sensor, in the pixel section of the display device. can.

[0286] FIG. 23C shows a notebook personal computer, which includes a housing 921, a display unit 922, and a keyboard. The display device 922 includes a keyboard 923, a pointing device 924, and the like.

[0287] FIG. 23(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 93. Holds 3rd place.

[0288] FIG. 23E shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 45 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. The angle may be switched according to the angle between the above and the above.

[0289] FIG. 23(F) shows an automobile, which includes a body 951, wheels 952, a dashboard 953, and lights. 954 etc.

[0290] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together.

[0291] (Embodiment 10) In this embodiment, a usage example of an RF tag according to one embodiment of the present invention will be described with reference to FIG. RF tags are used in a wide range of applications, including banknotes, coins, securities, and anonymous documents. Bonds, certificates (driver's licenses, resident cards, etc., see Figure 24 (A)), recording media (DVDs and videos (See Fig. 24(B)), packaging containers (wrapping paper, bottles, etc., See Fig. 24(C) ), vehicles (bicycles, etc., see Figure 24(D)), personal belongings (bags, glasses, etc.), food, plants Objects, animals, the human body, clothing, daily necessities, medicines and medical products including drugs, or electronic devices (liquids LCD display devices, EL display devices, television devices, or mobile phones) or other items It can be used by attaching it to tags attached to goods (see Figure 24(E) and Figure 24(F)). Cut.

[0292] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of an object. For example, in a book, the sensor is embedded in the paper, and in a package made of organic resin, the sensor is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, and even after it is attached to an object, it does not change the design of the object. In addition, the security of banknotes, coins, securities, bearer bonds, or certificates is not lost. By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to various items, such as items of clothing, recording media, personal belongings, food, clothing, household goods, and electronic devices. By attaching RF tags related to the above, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RF tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0293] As described above, the RF tag according to one aspect of the present invention is used for each of the applications described in this embodiment. This reduces the power required for operations, including writing and reading information, thereby extending the maximum communication distance. It is also possible to store information for an extremely long period of time even if the power is cut off. Since the data can be retained for a long time, it can be used for applications where the frequency of writing and reading is low. Cut.

[0294] This embodiment may be appropriately combined with at least a part of other embodiments described in this specification. It can be implemented together. EXAMPLES

[0295] In this Example 1, the wiring layer of the first embodiment was fabricated and examined with a scanning transmission electron microscope (STEM). ing Transmission Electron Microscope:STE Cross-sectional observation was performed using a microscope (M).

[0296] A thermal oxide film was formed on a silicon single crystal wafer with a thickness of 400 nm. The silicon oxide nitride film was then deposited on the substrate with a thickness of 50 nm by plasma CVD. The film was formed to a thickness of 150 nm using the Zuma CVD method.

[0297] Next, in order to form grooves in the silicon oxynitride film, a resist pattern is formed by electron beam exposure. Using this resist pattern as a mask, dry etching was performed. A groove was formed in the silicon oxynitride film.

[0298] After removing the resist, a conductive film was formed by metal CVD. First, titanium nitride was deposited on the A film having a thickness of 200 nm was then formed on the substrate, followed by the deposition of tungsten to a thickness of 200 nm.

[0299] Next, CMP is performed using a slurry containing silica to remove the tongue on the silicon oxynitride film. The stainless steel and titanium nitride were removed.

[0300] After CMP, the substrate was cleaned to remove any slurry or particles remaining on the substrate. The cleaning conditions were immersion in ozone water, followed by brush cleaning, and then immersion in diluted hydrofluoric acid. The sample was then washed with water and finally dried.

[0301] The cross section of this sample was observed in two perpendicular directions using STEM. FIG. 25B) and FIG. 25C are cross-sectional STEM images taken in two perpendicular directions.

[0302] As a result of the observation, it was found that the edge of the first conductor, titanium nitride, was close to the edge of the groove, as in the first embodiment. In the case of FIG. 1, the height of the groove is the same as or lower than that of the second conductor W, and the top surface of the second conductor W is It was also confirmed that the height of the tungsten was the same as or lower than that of the It was confirmed that defects such as membrane peeling were suppressed. EXAMPLES

[0303] In this embodiment, a transistor having the wiring layer of the first embodiment as a first gate electrode, as shown in FIG. A transistor was fabricated and its transistor characteristics were measured.

[0304] The fabricated transistor had a channel length L of 59 nm and a channel width W of 67 nm. First, the initial characteristics of the transistor were measured.

[0305] The initial characteristics were measured at room temperature with the source grounded and the drain voltage (Vd) set to 0.1 V. The second gate voltage (Vg) is changed from -3.0V to +3.0V in 0.1V increments. The drain current (Id) was measured and the variation curve was recorded. Next, the drain voltage was The drain current curve was recorded at 1.8 V. The first gate electrode was grounded. The results are shown in FIG. 26(A). Excellent transistor characteristics were obtained.

[0306] Next, using the same transistor as above, a voltage is applied to the first gate electrode, which is the back gate. The transistor characteristics were measured by applying a first gate potential (Vb g) is changed to -4V, -2V, 0V, +2V, +4V in 2V intervals, and the initial characteristics are compared with those described above. The change curve of the drain current was recorded under the same measurement conditions. The first gate potential, which is the back gate when the voltage is +0.1V, is set to -4V, -2V, 0V, + The drain current curves when the voltage is changed to +2V and +4V are shown in Fig. 26(C). The first gate potential, which is the back gate when the gate voltage is +1.8V, is set to -4V, -2V, and 0V. , +2V, and +4V.

[0307] When the voltage of the first gate, which is the back gate, is changed in the negative direction, the drain current The change curve shifts to the positive direction, and when the first gate voltage is changed in the positive direction, the drain It was confirmed that the change curve of the gate current shifted in the negative direction. It was confirmed that the electrode functions as a back gate and that the threshold voltage can be controlled normally. [Explanation of symbols]

[0308] 100 transistors 110 Transistor 130 Capacitive element 140 Capacitive element 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 Pixel Circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 Substrates 301 Insulators 302 Insulators 303 Insulators 304 Insulators 305 Insulators 306 Insulators 307 Insulators 308 Insulator 310 Conductors 311 Conductors 312 Conductors 312a Source electrode or drain electrode 312b Source electrode or drain electrode 314 Conductors 315 Conductors 316 Conductors 320 Semiconductors 320a Semiconductor 320c Semiconductor 330 Gate electrode 331 Gate electrode 341 Electrode 342 Electrode 350 Substrate 351 STI 353 Diffusion Layer 354 Insulators 355 Sidewall 360 Insulator 361 Insulators 362 Insulators 363 Insulators 364 Insulators 365 Insulator 370 Plug 371 Plug 372 Plug 373 Wiring layer 374 Wiring layer 375 Wiring layer 376 wiring layer 377 Wiring layer 378 Wiring layer 379 Wiring layer 380 wiring layer 381 Wiring layer 382 Plug 383 Plug 384 Plug 385 wiring layer 386 wiring layer 387 Wiring layer 388 Plug 389 Plug 390 wiring layer 391 Plug 392 Plug 393 Wiring layer 394 Wiring layer 500 Silicon substrate 510 layers 520 layers 530 layers 540 layers 551 Transistor 552 Transistor 553 Transistor 560 Photodiode 561 Anode 563 Low resistance region 570 Plug 571 Wiring 572 Wiring 573 Wiring 580 Insulator 700 Substrates 704a Conductor 704b Conductor 706 Semiconductors 708 Insulator 712a Insulator 712b Insulator 714a Conductor 714b Conductor 716a Conductor 716b Conductor 718a Insulator 718b Insulator 718c Insulator 719 Light emitting element 720 Insulator 721 Insulators 731 Terminal 732 FPC 733a Wiring 734 Sealing material 735 Drive Circuit 736 Drive Circuit 737 pixels 741 Transistor 742 Capacitive element 743 Switching element 744 Signal Line 750 Substrate 751 Transistor 752 Capacitive element 753 Liquid crystal element 754 scan lines 755 Signal Line 781 Conductors 782 Light-emitting layer 783 Conductors 784 Bulkhead 791 Conductors 792 Insulators 793 Liquid crystal layer 794 Insulators 795 Spacer 796 Conductors 797 Circuit Board 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 Memory circuit 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 4000 RF tags 5100 pellets 5120 Circuit Board 5161 area

Claims

1. A semiconductor device having a plurality of insulating films, a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor, the insulating films each have a first opening; the second conductor is provided below the plurality of insulating films; the first conductor has a region in contact with the second conductor at a bottom of the first opening, the third conductor is provided in the plurality of insulating films; the fourth conductor is provided above the plurality of insulating films; the first conductor has a region in contact with a side surface of the third conductor; the first conductor has a region in contact with the fourth conductor; the first conductor does not have a region in contact with the fifth conductor; the plurality of insulating films include at least a first insulating film, a second insulating film, and a third insulating film; the second insulating film has a region in contact with an upper surface of the first insulating film and a region in contact with a first side surface of the fifth conductor; the third insulating film has a region in contact with an upper surface of the second insulating film, a region in contact with a second side surface of the fifth conductor, and a region in contact with an upper surface of the fifth conductor.

2. A semiconductor device having a silicon substrate, a plurality of insulating films, a first conductor, a second conductor, a third conductor, a fourth conductor, and a fifth conductor, the silicon substrate is provided with a channel formation region of a transistor; the insulating films are provided above the silicon substrate, the insulating films each have a first opening; the second conductor is provided above the silicon substrate and below the insulating films; the first conductor has a region in contact with the second conductor at a bottom of the first opening, the third conductor is provided in the plurality of insulating films; the fourth conductor is provided above the plurality of insulating films; the first conductor has a region in contact with a side surface of the third conductor; the first conductor has a region in contact with the fourth conductor; the first conductor does not have a region in contact with the fifth conductor; the plurality of insulating films include at least a first insulating film, a second insulating film, and a third insulating film; the second insulating film has a region in contact with an upper surface of the first insulating film and a region in contact with a first side surface of the fifth conductor; the third insulating film has a region in contact with an upper surface of the second insulating film, a region in contact with a second side surface of the fifth conductor, and a region in contact with an upper surface of the fifth conductor.

3. 3. An electronic device comprising the semiconductor device according to claim 1.

Images