Architecture for computational memories and memory systems

Abstract

To provide a method for reducing processor utilization and / or bus bandwidth utilization, such as in computer solid state drive (SSD) technology.SOLUTION: A computational system uses resources of a computational SSD, instead of processors and / or bus resources, to perform computational techniques (for example, searching, computing, and / or accessing), reducing or minimizing information movement between processing elements and storage devices.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to memory capable of performing computations, including memory that enables computational solid-state drives (SSDs). [Background technology]

[0002] Increasing amounts of data increase the processing, storage, and bandwidth requirements for managing, organizing, selecting, and analyzing data in real time. Techniques are needed to address these increasing requirements.

[0003] In an exemplary conventional system, data is stored in a storage device accessible to a processor through a bus. Prior to processing, the data is transferred from the storage device to the processor (and / or memory directly accessible to the processor) through the bus. The data is then manipulated by the processor, and optionally the results are returned to the storage device through the bus. Thus, as the amount of data increases, processor utilization and / or bus bandwidth utilization increases. In some usage scenarios, throughput is limited by the bandwidth and / or latency between the processor and the storage device. Techniques are needed to reduce, for example, processor utilization and / or bus bandwidth utilization. Summary of the Invention

[0004] One or more computer systems may be configurable to perform particular operations and / or actions by having software, firmware, hardware, or a combination thereof installed on the system that, during operation, causes the system to perform and / or control the operations and / or actions. One or more computer programs may be configurable to perform particular operations and / or actions by containing instructions that, when executed by a data processing device, cause the device to perform the operations and / or actions.

[0005] A first aspect of a method for operating a memory system comprises first sensing a first portion of memory strings of a memory array according to (i) a first voltage driven on a word line of the memory array and (ii) a predetermined operating condition of the first portion of the memory strings; second sensing a second portion of the memory strings of the memory array according to (i) a second voltage driven on the word line of the memory array and (ii) a dynamic operating condition of the second portion of the memory strings; and providing a result of the second sensing, wherein the second voltage is based on the result of the first sensing. Other embodiments of this aspect comprise corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0006] The variant optionally includes one or more of the following features: In a first aspect, the dynamic operating condition is generated by manipulating a bit line circuit terminal of the second portion of the memory string according to a dynamic value. The second sensing step optionally includes counting approximate matches between a value stored in the second portion of the memory string and the dynamic value. The second sensing step optionally includes summing according to a current in the second portion of the memory string. The dynamic value is an analog value, the value stored in the second portion of the memory string is an analog value, and the summing is according to analog techniques. The second sensing step optionally includes scaling and then summing the current in the second portion of the memory string. The dynamic operating condition is based on the dynamic value and a mask value that allows the dynamic value to match any value stored anywhere in the second portion of the memory string. The dynamic operating condition is based on the dynamic value and a mask value that prevents the dynamic value from matching any value stored anywhere in the second portion of the memory string. A result of the second sensing step indicates a multiply-accumulate operation, a first operand of the multiply-accumulate operation being a dynamic value, a dynamic operating condition being determined according to the dynamic value, and a second operand of the multiply-accumulate operation corresponding to a value to be programmed into the second portion of the memory string. The dynamic operating condition is determined according to the dynamic value, and a result of the second sensing indicates a search operation for the dynamic value among the values ​​programmed into the second portion of the memory string. Implementations of the described techniques optionally include hardware, methods or processes, or computer software on a computer-accessible medium.

[0007] A second aspect of the memory system optionally comprises a memory array including first and second portions of memory strings, wherein one or more of the memory strings of the first portion of memory strings and one or more of the memory strings of the second portion of memory strings each include a plurality of serially connected memory devices; word line circuitry having terminals coupled to respective control inputs of respective rows in which the memory strings are organized; bit line circuitry having terminals coupled to respective bit line terminals of the memory strings; sense amplifier circuitry having terminals coupled to respective sense amplifier terminals of the memory strings; wherein the bit line terminals of the first portion of memory strings The terminals of the line circuit are capable of providing identical predetermined operating conditions to the bit line terminals of a first portion of the memory strings; wherein the terminals of the bit line circuit coupled to the bit line terminals of a second portion of the memory strings are capable of providing respective dynamic values ​​to the bit line terminals of the second portion of the memory strings; wherein the word line circuit is capable of selectively driving its control inputs in accordance with one of first and second word line control values, the first word line control value corresponding to the provided value and the second word line control value corresponding to a result produced by the sense amplifier circuit based on information provided via the terminals coupled to the bit line terminals of the first portion of the memory strings. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0008] Variations optionally include one or more of the following features. A second aspect optionally comprises a counting circuit coupled to the sense amplifier circuit and capable of counting exact matches between values ​​stored in the second portion of the memory string and the respective dynamic values. The system optionally comprises a summing circuit coupled to the sense amplifier circuit and capable of summing according to currents in the second portion of the memory string. The respective dynamic values ​​are analog values, and the values ​​stored in the second portion of the memory string are analog values, and the summing circuit is operable according to analog techniques. The summing circuit is further capable of scaling the currents before summing. The system optionally includes one or more processors capable of accessing the memory array. Terminals of the bit line circuit coupled to the bit line terminals of the second portion of the memory string further optionally include a page cache circuit coupled to the sense amplifier circuit and capable of providing identical predetermined operating conditions to the bit line terminals of the second portion of the memory string and capable of caching resulting pages read from the values ​​stored in the second portion of the memory string. Implementations of the described techniques optionally include hardware, methods or processes, or computer software on a computer-accessible medium.

[0009] A third aspect of the system optionally comprises a memory array including first and second portions of memory strings, wherein one or more of the memory strings of the first portion of the memory strings and one or more of the memory strings of the second portion of the memory strings each include a plurality of serially connected memory devices; word line circuits having terminals coupled to respective control inputs of respective rows in which the memory strings are organized; bit line circuits having terminals coupled to respective bit line terminals of the memory strings and operable to provide identical predetermined operating conditions to the bit line terminals; and sense amplifier circuits having terminals coupled to respective sense amplifier terminals of the memory strings, the word line circuits operable to selectively drive their control inputs according to one of first and second word line control values, the first word line control value corresponding to a provided value and the second word line control value corresponding to a result produced by the sense amplifier circuit based on information provided via the terminals coupled to the bit line terminals of the first portion of the memory strings. Other embodiments of this aspect comprise corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0010] The variant optionally includes one or more of the following features: In a third aspect, the provided values ​​optionally include a key and a mask, and selectively driving the control inputs optionally includes selectively driving the control inputs in respective pairs according to a plurality of encodings respectively determined from respective bits of the key and corresponding respective bits of the mask, wherein (i) a first one of the encodings enables selectively matching a stored zero value in response to the provided value being zero, (ii) a second one of the encodings enables selectively matching a stored one value in response to the provided value being one, (iii) a third one of the encodings enables selectively matching a stored zero value or a stored one value in response to the provided value being zero or one, and (iv) a No. of 4 thing disables selectively matching any stored value to the provided value. The system optionally includes one or more processors that enable access to a computational solid-state drive (SSD), optionally including at least one memory device, optionally including a memory array. Implementations of the described techniques optionally include hardware, methods or processes, or computer software on a computer-accessible medium.

[0011] Variations of the above aspects optionally include hardware, methods or processes, or computer software on a computer-accessible medium.

[0012] Other aspects and features of the present disclosure will be apparent from the drawings, detailed description, and claims. [Brief explanation of the drawings]

[0013] [Figure 1] 1 illustrates an exemplary hardware system based on one or more computational solid-state drives (SSDs).

[0014] [Figure 2] 1 illustrates an exemplary computational memory for performing a coarse search followed by a fine search responsive to the results of the coarse search.

[0015] [Figure 3] 1 illustrates an exemplary computational memory for performing a coarse search followed by calculations dependent on the results of the coarse search.

[0016] [Figure 4] 1 illustrates an exemplary computational memory for performing a coarse search followed by an access operation depending on the results of the coarse search.

[0017] [Figure 5] 1 illustrates an example flow diagram of a technique for operating a computational memory.

[0018] [Figure 6A] 1 summarizes the search through information provided on a word line. [Figure 6B] 1 summarizes the search through information provided on a word line.

[0019] [Figure 6C] 1 summarizes the search through the information provided on the bit lines. [Figure 6D] 1 summarizes the search through the information provided on the bit lines.

[0020] [Figure 7] 1 illustrates an exemplary computational SSD.

[0021] [Figure 8] 1 illustrates an exemplary hardware system having a computational SSD. DETAILED DESCRIPTION OF THE INVENTION

[0022] A detailed description of an architectural technique for a computational solid-state drive (SSD) is provided with reference to FIGS.

[0023] One or more flow diagrams are described herein. The processes described by the flow diagrams can be implemented and / or directed using a processor programmed using a computer program stored in memory accessible to the computer system, can be executed by a processor using special purpose logic hardware (including field programmable integrated circuits), and various combinations thereof. Various actions can be combined, performed in parallel, and / or performed in different sequences without affecting the processing achieved. In some cases, rearrangement of actions achieves the same results only if certain other changes are also made. In other cases, rearrangement of actions achieves the same results only if certain conditions are met. Moreover, for clarity, some of the flow diagrams herein omit some actions that are not necessary for understanding the disclosed techniques. Various additional actions can be performed before, after, and / or between the actions shown.

[0024] Examples of selected acronyms, mnemonics, and abbreviations used in the description are as follows: [Table 1] JPEG0007646974000002.jpg70128

[0025] An exemplary key-value store (e.g., a key-value SSD) is an object-based storage that receives an object description (e.g., a key) and, in response, accesses an object identifiable by the object description (e.g., a value corresponding to the key). In some key-value stores, a translation layer translates between the object description and a corresponding reference to the underlying data block in non-volatile storage. The Concept of Computational SSD

[0026] Systems based on the computational SSD technology described herein reduce processor utilization and / or bus bandwidth utilization. The system uses computational SSD resources rather than processor and / or bus resources to perform computational techniques (e.g., search, calculation, and / or access), thus reducing or minimizing information movement between processing elements and storage devices. Computational SSD technology enables ever-increasing amounts of data to be managed, organized, selected, and analyzed in real time. Computational SSDs (sometimes referred to as "smart SSDs") can, for example, use computational SSD resources to store and manipulate data locally, run CIM, IMC, and / or IMS, etc. Thus, using computational SSDs reduces the processing, storage, and bandwidth requirements of a system.

[0027] Additionally, the use of computational SSDs allows for the use of CPU and / or GPU resources for other tasks, enabling faster results. In some usage scenarios, the use of computational SSDs reduces the need to purchase additional processors and / or servers. In some usage scenarios, the use of computational SSDs reduces the need to purchase additional power and / or cooling resources. In some usage scenarios, the use of computational SSDs enables new insights and opportunities to use self-processing technology to accelerate various applications. Exemplary applications to which computational SSD technology is applicable include video processing, database management, and artificial intelligence.

[0028] An exemplary computational SSD enables execution of a coarse search function followed by a second function responsive to the coarse search function. The exemplary computational SSD is based on a single memory array available in two portions: (1) a portion dedicated to the coarse search function and (2) a portion dedicated to the second function. The exemplary second function includes a fine search (e.g., IMS) function, a calculation (e.g., IMC) function, and an access (e.g., value for a key / value pair) function.

[0029] As one specific example, a key-value SSD can be implemented using the computational SSD described herein.

[0030] A computational SSD is comprised of one or more computational memories. A computational SSD may perform multiple functions using the same computational memories. For example, a first function may be performed on a particular computational memory, and then a second function (e.g., based on the results of the first function) may be performed on the particular computational memory. In some cases, multiple functions may be performed on the same memory array of the same computational memory.

[0031] For example, for a search operation, the first function includes a coarse filter and / or search function, and the second function includes a fine filter and / or search function. For example, for a calculation operation, the first function includes a coarse filter and / or search function, and the second function includes an in-memory calculation function. For example, for an access operation, the first function includes a coarse filter and / or search function, and the second function includes a data access function.

[0032] In some scenarios, a coarse filter and / or search function can be used to reduce or eliminate processing of uninteresting or unnecessary portions of the database. For example, in response to a coarse filter function, word lines determined by the coarse filter and / or search function are activated for use in subsequent actions. In the example of search, computation, and access operations, the subsequent actions include a fine filter and / or search function, an in-memory computation function, and a data access function, respectively.

[0033] In some variations, the coarse filter and / or search function uses search information provided on word lines, e.g., similar to a ternary CAM. In some variations, the fine search function uses search information provided on bit lines, e.g., for hyper-dimensional searches. In some variations, the calculation function uses calculation information provided on bit lines. In some variations, the access function is usable to provide a value corresponding to a key of a key-value pair, e.g., for use by a CPU and / or GPU. Exemplary Computational SSD System

[0034] In some computational SSD systems, one or more computational SSDs are capable of performing a first function followed by a second function dependent on the results of the first function. In a first example, the first function is a coarse search function and the second function is a fine search function. In a second example, the first function is a coarse search function and the second function is a calculation function. In a third example, the first function is a coarse search function and the second function is an access function.

[0035] In some configurable computational SSD systems, one or more computational SSDs enable execution of a first function followed by a second configurable function depending on the results of the first function. In various examples, the granularity of the configuration of the second function varies, for example, from the entire SSD to a single memory array of the configurable computational SSD. For example, an SSD may be configured as a specialized search computational SSD, with the entire SSD configured with the first function as a coarse search function and the second function as a fine search function. For example, another SSD may be configured with a first portion of the memory array configured for a computation function and a second portion of the memory array configured with an access function.

[0036] 1 illustrates an exemplary hardware system based on one or more computational SSDs as computational SSD system 100. The system includes hardware blocks CPU 110, GPU 120, DRAM 130, and one or more instances of computational SSD 140 coupled by hardware block PCIe bus 180. Each instance of computational SSD 140 includes one or more computational SSDs, such as one or more instances of computational SSD 700 of FIG. 7. The instances of computational SSD 140 are capable of performing computational SSD-related functions indicated by functions: coarse, fine, compute, access 126.

[0037] CPU 110 includes one or more processing units, such as a microprocessor, signal processor, AI processor, or any combination of hardware units capable of executing programmed instructions. GPU 120 includes one or more processing units, such as any combination of units capable of accelerating processes that undergo relatively high parallelism, such as graphics processing, signal processing, and / or AI processing. DRAM 130 includes one or more DRAM devices for storing instructions and / or data in a volume larger than the internal storage of CPU 110 and / or GPU 120. PCIe bus 180 enables communication between elements coupled thereto (e.g., CPU 110, GPU 120, and instances of computational SSD 140) using one or more PCIe buses 180. Instances of computational SSD 140 are variously capable of performing coarse search, fine search, calculation, and access functions on data stored on the respective computational SSDs without transferring the data to CPU 110, DRAM 130, and / or GPU 120.

[0038] Computational SSD system 100 enables a reduction or minimization of data movement between conventional processing elements (e.g., CPU 110 and / or GPU 120) and computational storage elements (e.g., one or more instances of computational SSD 140). Various computational operations are performed on the computational SSD using locally stored data available on the SSD.

[0039] Other compartmentalizations of elements, couplings between elements, and capabilities and / or capacities of elements shown in the figures, as well as additional elements, are contemplated according to usage requirements. Computational Memory

[0040] Three examples of computational memory are described. The first example is a coarse search followed by two consecutive IMS operations, e.g., a fine search depending on the results of the coarse search. The second example is a coarse search followed by an IMS operation, e.g., a calculation operation, followed by an IMC operation depending on the results of the coarse search. The third example is a coarse search followed by an access operation depending on the results of the coarse search and a consecutive IMS operation, e.g., an access operation. Computational Memory - IMS => IMS

[0041] Returning to the first example of computational memory (two consecutive IMS operations), a single computational memory array has two portions (one for each IMS operation) each capable of performing a coarse search (e.g., operating as a TCAM) followed by a fine search depending on the results of the coarse search. Conceptually, the coarse search portion implements a filter (e.g., via word line inputs) to reduce the calculations performed by the fine search portion (e.g., a hyperdimensional search via bit line inputs).

[0042] As an example of operation, selected coarse search information (e.g., all or any portion of the key, optionally together with key mask information) is used to generate (coarse search) values ​​for word lines of a single computational memory array ("array"). Bit lines of the coarse search portion are manipulated to allow matching of word line values ​​to the coarse search information stored in the memory devices of the coarse search portion. The memory devices are arranged in contiguous groups of devices called memory strings. Each memory string allows matching of word line values ​​to the coarse search information stored in the memory string. The memory string indicates a match, for example, by changing impedance. The change in impedance is then reflected by a change in voltage on the bit line to which the memory string is coupled. For example, the memory string indicates a match by discharging the bit line. Sense amplifiers in the coarse search portion detect bit line voltage changes (if any) and generate a match result in response. An exact match and / or an approximate match corresponds to a high degree of similarity between the word line values ​​and the coarse search information stored in the memory devices of the coarse search portion. For example, in one-hot encoding, a match is coded as a "1" and a mismatch is coded as a "0."

[0043] The matches are then used to generate values ​​for the word lines of the array (fine search). In an exemplary one-hot encoding (single match), a single word line is driven to "read" and the remaining word lines are driven to "pass," enabling a fine search according to the coarse match results. Simultaneously, the bit lines of the fine search section are operated according to matching selected fine search parameters (e.g., all or any portion of one or more hyperdimension search parameters, optionally in conjunction with hyperdimension mask information), and the fine search information is stored in the memory device of the fine search section. Sense amplifiers in the fine search section detect the bit line changes and generate match results indicating a high degree of similarity between the fine search parameters and the fine search information stored in the memory device, which are then combined (e.g., counted) across one or more bit lines to determine one or more overall results. For example, the highest overall result corresponds to the best match.

[0044] The coarse search portion accommodates "match 1" and "match 0" match operations through pairs of word lines and pairs of consecutive memory devices in the first portion, and optionally "match anything" (e.g., "don't care" or alternatively, "wildcard") and "match none" (e.g., "invalid value" or alternatively, "invalid search") match operations. Similarly, the fine search portion accommodates similar encodings through pairs of bit lines and corresponding pairs of memory devices in the second portion.

[0045] FIG. 2 illustrates an exemplary computational memory for performing a coarse search followed by a fine search depending on the results of the coarse search as computational memory 200.

[0046] Computational memory 200 includes two portions: coarse portion 210 for performing a coarse search and fine portion 220 for performing a fine search. Coarse portion 212 and fine portion 222 are portions of the same memory array, array 250. Word line circuitry 252 enables the results of the coarse search to be provided to the fine search.

[0047] The course 210 includes a bit line circuit 211, a course portion 212, and a sense amplifier circuit 214. The course portion 212 includes a plurality of memory strings, each including a plurality of serially coupled memory devices. The memory strings are conceptually coupled to the bit line circuit 211 and the sense amplifier circuit 214, and are therefore serially coupled in the vertical direction of the diagram. The memory strings are conceptually replicated in the horizontal direction of the diagram, with word lines coupling each corresponding device in the memory string in the horizontal dimension. For each memory string, one end of the memory string (e.g., a bit line terminal) is coupled to the bit line circuit 211, and the other end of the memory string (e.g., a sense line terminal) is coupled to the sense amplifier circuit 214.

[0048] The bit line circuit 211 includes bit line circuitry capable of operating each of the bit line terminals according to a predetermined value. For example, the bit line circuit 211 includes a precharger for each of the bit line terminals of the coarse portion 212. The precharger operates (in conjunction with other circuitry, e.g., the word line circuit 252 and / or the sense amplifier circuit 214) to precharge the memory strings of the coarse portion 212.

[0049] Sense amplifier circuit 214 includes sense circuitry capable of determining current and / or voltage changes at each of the sense amplifier terminals of coarse portion 212 according to one or more predetermined thresholds. For example, sense amplifier circuit 214 includes a sense amplifier for each of the sense amplifier terminals. The sense amplifier operates (in conjunction with other circuits, e.g., word line circuit 252 and / or bit line circuit 211) to determine current and / or voltage changes in the memory strings of coarse portion 212. Sense amplifier circuit 214 provides the results of the changes to word line circuit 252 via coarse search results 215.

[0050] The current and / or voltage changes in the memory strings of the course portion 212 result from, for example, the selective discharging of the memory strings based on the stored values ​​of the serially coupled memory devices of the memory strings and the values ​​provided to the word lines by the word line circuitry 252.

[0051] Fine 220 includes bit line circuitry 221, fine portion 222, sense amplifier circuitry 224, and post-processing (counting) 225. Fine portion 222 (similar to coarse portion 212) includes multiple memory strings, each including multiple serially coupled memory devices. The memory strings are coupled to bit line circuitry 221 and sense amplifier circuitry 224 and are therefore conceptually coupled in series in the vertical direction of the diagram. The memory strings are conceptually replicated in the horizontal direction of the diagram, with word lines coupling each corresponding device in the memory string in the horizontal dimension. For each memory string, one end of the memory string (e.g., a bit line terminal) is coupled to bit line circuit 221, and the other end of the memory string (e.g., a sense line terminal) is coupled to sense amplifier circuit 224.

[0052] Bitline circuit 221 (similar in some respects to bitline circuit 211) includes bitline circuitry that is capable of operating each of the bitline terminals according to dynamic values ​​provided by fine search parameters 229 (rather than predetermined values ​​in bitline circuit 211). For example, bitline circuit 221 includes a conditional precharger for each of the bitline terminals in fine portion 222. Bitline circuit 221 operates pairs of bitline terminals, as conceptually represented by IMS cell (fine) 227. The conditional precharger operates (in conjunction with other circuitry, e.g., wordline circuit 252 and / or sense amplifier circuit 224) to conditionally precharge memory strings in fine portion 222.

[0053] Sense amplifier circuit 224 includes sense circuitry capable of determining current and / or voltage changes at each of the sense amplifier terminals of fine portion 222 according to one or more predetermined thresholds. For example, sense amplifier circuit 224 includes a sense amplifier for each of the sense amplifier terminals. The sense amplifier operates (in conjunction with other circuits, e.g., word line circuit 252 and / or bit line circuit 221) to determine current and / or voltage changes in memory strings of fine portion 222. Sense amplifier circuit 224 provides change results, such as a single binary digit for each of the sense amplifiers, to post-processing (counting) 225. Each single binary digit indicates one of two mutually exclusive conditions: (1) the change is less than or equal to the threshold, and (2) the change is greater than the threshold.

[0054] The current and / or voltage changes in the memory strings in the fine portion 222 result from the selective discharging of conditionally precharged memory strings based, for example, on the stored values ​​of the serially coupled memory devices of the memory strings and the values ​​provided to the word lines by the word line circuitry 252.

[0055] Post-processing (count) 225 includes a counting circuit capable of counting the number of sense amplifiers in sense amplifier circuit 224 that indicate a change greater than (or alternatively, less than or equal to) a threshold value. The count indicates a relative match of coarse search parameters 219 and / or fine search parameters 229 compared to various values ​​stored in coarse portion 212 and / or fine portion 222, respectively, which are provided (e.g., to a host) via fine search results 226. In another example, the outputs of a first portion of sense amplifiers in sense amplifier circuit 224 are counted together as a first result provided via fine search results 226, and the outputs of the remaining portions of sense amplifiers in sense amplifier circuit 224 are counted together with a second result provided via fine search results 226. Various configurations of sense amplifiers and counts can be used to enable comparison of various portions of fine search parameters 229, e.g., one or more hyperdimensions.

[0056] Thus, the fine search results 226 include the course search parameters 219 information stored in the course portion 212, information based on the fine search parameters 229, information stored in the fine portion 222, and information based on counting as performed by post processing (counting) 225.

[0057] Wordline circuit 252 includes wordline translation and drive circuitry capable of conditionally operating in two modes, e.g., a first mode during a first phase of operation and then a second mode during a second phase of operation. In the first mode, one or more search parameters, coarse search parameters 219 (e.g., a key and optionally a mask), are translated into voltages suitable for performing a coarse search function using memory strings in coarse portion 212 (e.g., for parallel comparison against respective instances of key information 218). In the first mode, wordline circuit 252 translates paired voltages conceptually represented by IMS cells (coarse) 217. In the second mode, one or more results from operation in the first mode, coarse search results 215, are translated into voltages suitable for performing a fine search function using memory strings in fine portion 222. In some variations, in the second mode, circuits not used in the second mode are not activated (e.g., bitlines in the coarse search portion are not activated in the second mode).

[0058] In some variations and / or usage scenarios, during a first phase of operation, coarse 210 functions as a TCAM that enables an exact match, and at most one sense amplifier in sense amplifier circuit 214 detects a change corresponding to the exact match. During a second phase of operation (responsive to detecting the exact match), fine 220 operates once. Wordline circuit 252 drives a single wordline of array 250 (corresponding to the exact match represented on coarse search result 215) for reading (e.g., provides a voltage Vread). Wordline circuit 252 activates the remaining wordlines of array 250 for passing (e.g., provides a voltage Vpass).

[0059] The coarse 210 and / or the fine 220 can be independently implemented according to various characteristics. The characteristics include the match type (e.g., exact and / or approximate), the number of matches (zero, one, and / or multiple), and the order of the coarse matches (parallel or sequential). Exemplary match types include exact and approximate matches. An exact match corresponds to a full bit match, e.g., every bit of the search parameter matches every bit of the value stored in the memory string. An approximate match corresponds to a less-than-full bit match, e.g., a full bit match except for one bit, a full bit match except for two bits, or alternatively, a percentage of bit matches, e.g., 90% bit match (e.g., 9 out of 10 bits). For example, the coarse 210 can perform an exact match, and the fine 220 can perform an approximate match. In another example, both the coarse 210 and the fine 220 can perform an exact match (or can perform an approximate match). Exemplary numbers of matches include at most one match and at most multiple matches. For example, coarse 210 may detect at most one match (either exact or approximate), and fine 220 may detect at most one match (either exact or approximate). In another example, coarse 210 may detect at most multiple matches (either exact or approximate), and fine 220 may detect at most multiple matches (either exact or approximate). An example of a coarse match order includes parallel processing of all matches (exact or approximate), such as a single use of fine portion 222. Another example of a coarse match order includes serial processing of each match (exact or approximate) in a respective single use of fine portion 222. For example, if there are two coarse matches, then in response, fine portion 222 is used twice in succession, once for each of the coarse matches. Below is a description of some exemplary combinations of match types, number of matches, and coarse match order.

[0060] In some similar variations and / or usage scenarios, multiple sense amplifiers in sense amplifier circuit 214 detect a corresponding multiple exact matches. According to one technique, in response to the multiple matches, the second phase of operation is successively repeated for each exact match, and counting as performed by post-processing (counting) 225 is performed over the successive iterations. For example, each of the first, second, and third sense amplifiers in sense amplifier circuit 214 detects an exact match. In response, the second phase of operation is repeated three times (i.e., three iterations including a first iteration, a second iteration, and a third iteration), and counting is performed over the three iterations. The first iteration begins counting. The second phase of operation is performed a first time using the match detected by the first sense amplifier that detected the match in the first phase of operation. Post-processing (counting) 225 begins counting using the result of the second phase of operation as performed in the first iteration to begin counting. The second iteration continues counting. The second phase of operation is performed a second time using the match detected by the second sense amplifier that detected the match in the first phase of operation. Post-processing (counting) 225 continues counting using the results of the second phase of operation as performed in the second iteration to continue counting by counting the results of the first iteration using the results counted before the results of the first iteration. The third iteration completes counting. The second phase of operation is performed a third time using the match detected by the third sense amplifier that detected the match in the first phase of operation. Post-processing (counting) 225 completes counting using the results of the second phase of operation as performed in the third iteration to complete counting by counting the results of the third iteration using the results counted before the first and second iterations. According to another technique, the second phase of operation is performed once in response to multiple matches, and multiple word lines of array 250 are activated (corresponding to multiple exact matches). For example, each of the first, second, and third sense amplifiers of sense amplifier circuit 214 detects an exact match.In response, the second phase of the operation is performed once. Post-processing (counting) 225 performs counting, using the results of the second phase of the operation to perform the counting.

[0061] In some variations and / or usage scenarios, the course 210 can operate as an exact and approximate match TCAM. During a first phase of operation, the course 210 operates as a TCAM that enables exact and approximate matches. Thus, zero or more of the sense amplifiers in the sense amplifier circuit 214 detect a match. In response, the second phase of operation is repeated successively for each match, and counting, as performed by post-processing (counting) 225, is performed over successive iterations. For one approximate match technique, the sense amplifiers in the sense amplifier circuit 214 can detect changes according to more than one threshold (e.g., serially via different sensing periods or in parallel via parallel operation of multiple detection mechanisms). For example, one threshold corresponds to an exact match and another threshold corresponds to an approximate match (e.g., a match of all but one or two bits). Each amount of approximate matching can be implemented via a respective threshold (e.g., via a respective sensing period). For example, a first amount of approximate matching (corresponding to a mismatch of 2 or fewer bits) is implemented via a first threshold (e.g., via a first sensing period), and a second amount of approximate matching (corresponding to a mismatch of 4 or fewer bits) is implemented via a second threshold (e.g., via a second sensing period that is greater than the first sensing period).

[0062] In some variations and / or usage scenarios, the fine 220 can operate to match stored information exactly and approximately to search parameters according to word line values. During a second phase of operation, the fine 220 operates to detect exact and approximate matches, so that zero or more of the sense amplifiers in the sense amplifier circuit 224 detect a match. Each detection indicates whether the respective match is exact or approximate. Furthermore, techniques such as those described with respect to approximate matches for the course 210 can be applied to the fine 220. The post-processing (counting) 225 can appropriately count exact and approximate matches. For example, exact matches count higher than approximate matches.

[0063] The dimensions of array 250 and the allocation between coarse portion 212 and fine portion 222 vary according to usage. For example, coarse portion 212 may have N memory strings and fine portion 222 may have M memory strings, resulting in a total of N+M memory strings. Each memory string has L memory devices (consecutively) in each memory string, for a total of L×(N+M) memory devices in array 250. There are L word lines in word line circuit 252 coupled to array 250. Each word line conceptually couples N+M memory devices (in parallel) across the entire “width” of “array 250.” Each of the N memory strings in coarse portion 212 is coupled to a respective bit line circuit in bit line circuit 211 and a respective sense amplifier in sense amplifier circuit 214. Thus, there are N bit line circuits in bit line circuit 211 and N sense amplifiers in sense amplifier circuit 214. Similarly, each of the M memory strings in fine portion 222 is coupled to a respective bit line circuit in bit line circuit 221 and a respective sense amplifier in sense amplifier circuit 224. Thus, there are M bit line circuits in bit line circuit 221 and M sense amplifiers in sense amplifier circuit 224. As a specific example, N=48, M=128K-48, and L=48. As another specific example, N=232, M=128K-232, and L=232.

[0064] In some variations, the course search results 215 are selectively provided elsewhere, for example, via an interface circuit to a host.

[0065] The division of functionality between sense amplifier circuitry 224 and post-processing (counting) 225 is arbitrary. For example, variations are envisioned that have some or all of the functionality of post-processing (counting) 225 incorporated into sense amplifier circuitry 224, and vice versa.

[0066] An example implementation of the IMS cell (coarse) 217 ​​is described with respect to Figures 6A and 6B. An example implementation of the IMS cell (fine) 227 is described with respect to Figures 6C and 6D. In some variations, the pair of devices in the IMS cell (coarse) 217 ​​and / or the IMS cell (fine) 227 are implemented using a pair of SONOS devices. Computational Memory - IMS => IMC

[0067] Continuing with the second example of computational memory (an IMS operation followed by an IMC operation), similar to the first example, a single computational memory array has two portions (one for an IMS operation and one for an IMC operation) that are each capable of performing a coarse search followed by a calculation depending on the results of the coarse search (e.g., operating as a TCAM). Conceptually, the coarse search portion implements a filter (e.g., via word line inputs) to reduce the calculation performed by the calculation portion (e.g., calculation via bit line inputs).

[0068] As an example of operation, the coarse search portion is similar to and used in the first example. Thus, the coarse search portion operates as a TCAM, and exemplary results are one-hot encoded. Furthermore, matches from the coarse search portion are then used to generate (calculate) values ​​for word lines of the array. At the same time, the bit lines of the computation portion are manipulated according to the computation, such as being manipulated according to each term / bit of the first vector input of the dot product. The stored information in the memory cells of the computation portion corresponds to each term / bit of the second input vector of the dot product.

[0069] As a specific example, the TCAM result corresponds to a matched category, the first vector input corresponds to a neuron value, and the second vector input corresponds to a weight to apply to the neuron value. As another specific example, bit lines of the computation portion are driven to (e.g., analog) voltages representing the first vector input (each bit line voltage corresponds to an element of the first vector). Threshold voltages of memory cells are programmed to voltages representing the second input vector (each memory cell threshold voltage corresponds to an element of the second vector). Summing (optionally scaling) the currents across the bit lines functions to accumulate individual products (bit line voltages multiplied by memory cell currents determined in part by their threshold voltages) into the dot product result of the first and second input vectors. One form of scaling is according to a power of two, such as to effectively encode a binary value. Another form of scaling is according to relative importance, such as scaling according to the significance of features. Some variations generate a single sum across all bit lines of the computation portion. Another variation generates multiple sums corresponding to different groups of bit lines in the calculation portion.

[0070] The sensing in the computational portion is multi-valued and encoded via either digital or analog techniques. For example, in analog techniques, sense amplifiers in the computational portion respond to bit line changes and generate analog outputs, which are then optionally scaled via analog techniques. The scaled analog outputs are then combined, for example, via analog summation, to generate a computation result. In the context of a specific example, the computation result corresponds to a dot product result. The computation result is optionally converted to a binary representation.

[0071] FIG. 3 illustrates an exemplary computational memory as computational memory 300 for performing a coarse search and subsequent calculations depending on the results of the coarse search.

[0072] 2, computational memory 300 includes two portions: a coarse portion 310 for performing a coarse search and a computation portion 320 for performing a calculation. Coarse portion 312 and computation portion 322 are portions of the same memory array, array 350. Word line circuitry 352 can provide the results of the coarse search to the computation.

[0073] Some elements in FIG. 3 are identical to, substantially similar to, or similar to corresponding elements in FIG. 2, and reference should be made to the corresponding elements for further description. For example, sense amplifier circuit 314, like sense amplifier circuit 214, includes sense circuitry capable of determining current and / or voltage changes at each of the sense amplifier terminals of coarse portion 312. In another example, IMS cell (coarse) 317 and key information 318 correspond to IMS cell (coarse) 217 ​​and key information 218, respectively. As a final example, bit line circuit 311, like bit line circuit 211, includes bit line circuitry capable of manipulating each of the bit line terminals according to a predetermined value. Furthermore, array 350 corresponds to array 250, coarse 310 corresponds to coarse 210, and calculation 320 generally corresponds to fine 220 (post-processing (scaling and summing) 325, which has a different function than post-processing (counting) 225, etc.). Elements in FIG. 3 correspond to elements in FIG. 2 identified by the last two digits of the element identifier. Therefore, the following description will focus on elements of FIG. 3 that differ in operation from or are not present in FIG. 2 as corresponding elements.

[0074] Computational memory 200 is intended for coarse search and then fine search. In contrast, computational memory 300 is intended for coarse search and then computation. When considering a coarse search, in some variations, coarse 310 operates identically to coarse 210. When considering computation versus fine search, computation 320 operates differently from fine 220. Bit line circuit 321 operates memory strings in computation portion 322 individually, rather than in pairs as exemplified by bit line circuit 221 (IMS cell (fine) 227) for weight 328. Bit line circuit 321 can optionally drive memory strings according to analog values. Computation portion 322 can optionally store analog values. Sense amplifier circuit 324 and post-processing (scaling and summing) 325 can optionally operate using analog values, etc.

[0075] More specifically, bit line circuit 321 can operate the bit lines independently of one another for respective voltages and / or currents, such as through conditional precharge or continuously provided techniques. The sense amplifiers of sense amplifier circuit 324 can represent more than two values, either through digital (e.g., multiple bits on respective terminals) or analog (e.g., different currents on a single terminal) techniques. Post-processing (scaling and summing) 325 can optionally scale the sense amplifier results (voltages or currents) according to one or more scale factors. For example, a respective scale factor is applied to each group of sense amplifier outputs of sense amplifier circuit 324. One form of scaling is via analog techniques. Another form of scaling is via digital techniques. Post-processing (scaling and summing) 325 can further combine the optionally scaled sense amplifier outputs, for example, via analog and / or digital summing. One or more outputs of post-processing (scaling and summing) 325 are presented as one or more results via calculation results 326. In some variations, the operations of sense amplifier circuitry 324 and post-processing (scaling and summing) 325 are combined, with the combining occurring conceptually before some or all of the sensing (e.g., via analog summing), and a reduced number of sense amplifiers are used. In some variations, the output of computation result 326 is analog, while in other variations the output is digital.

[0076] Like fine portion 222, the current and / or voltage changes in the memory strings in computation portion 322 result from the selective discharging of conditionally precharged memory strings based, for example, on the stored values ​​of the serially coupled memory devices of the memory strings and the values ​​provided to the word lines by word line circuitry 352.

[0077] Thus, the calculation result 326 includes information based on the course search parameters 319, information stored in the course portion 312, information based on the calculation parameters 329, information stored in the calculation portion 322, and the addition performed by post-processing (scaling and addition) 325.

[0078] Like word line circuit 252, word line circuit 352 can conditionally operate in two modes during respective first and second phases of operation. The first mode of operation is identical to word line circuit 252. In summary, one or more search parameters (coarse search parameters 319) are pairwise converted (as conceptually represented by IMS cells (coarse) 317) into voltages suitable for performing a coarse search function using memory strings in coarse portion 312 (as conceptually represented by key information 318). In the second mode, one or more results from operation in the first mode, coarse search results 315, are converted into voltages suitable for performing a computation function using memory strings in computation portion 322 (rather than a fine search function as in fine portion 222). For example, word line circuit 352 drives zero or more of the word lines of array 350 represented by coarse search results 315 (corresponding to an exact match) for a read (e.g., providing a voltage Vread). Word line circuitry 352 drives the remaining word lines of array 350 to pass (eg, provides a voltage Vpass).

[0079] An example of a memory cell used as a weight is shown as weight 328. In some variations, each memory cell used as a weight is implemented using a respective SONOS device and each weight value is implemented as a respective threshold voltage. In some variations, each memory cell used as a weight is implemented using SLC, MLC, TLC, QLC, or analog techniques.

[0080] An example of a row of memory cells used as a category is shown as category 327 .

[0081] In some variations and / or usage scenarios, a subportion of the calculation portion 322 is used according to each feature, and summing in post-processing (scaling and summing) 325 across the calculation portion 322 produces an overall score across the features. The overall score can be used as a classification result, for example, to rank the highest scoring instances. In some variations, the calculation 320 functions to perform a MAC operation to calculate a likelihood score between the query and a selected instance in the calculation portion 322. The selected instance is determined by the course 310 and functions to improve efficiency. Computational Memory - IMS => Access

[0082] Continuing with the third example of computational memory (an IMS operation followed by an access operation), similar to the first example, a single computational memory array has two portions (one for an IMS operation and one for an access operation) that are each capable of performing a coarse search (e.g., operating as a TCAM) followed by an access operation depending on the results of the coarse search. Conceptually, the coarse search portion implements a filter (e.g., via a word line input) to reduce the access cost performed by the access portion (e.g., to provide one or more result values).

[0083] As an example of operation, the coarse search portion is similar to and used in the first example. Thus, the coarse search portion is operated as a TCAM, and exemplary results are one-hot encoded. Furthermore, matches from the coarse search portion are then used to generate values ​​for word lines of the array (access operations). At the same time, the bit lines of the access operation portion are operated to enable reading stored values ​​from memory cells in the access operation portion as selected by the word lines. Sense amplifiers in the access operation portion detect the stored values ​​from the selected memory cells, providing, for example, a page of data.

[0084] As a specific example, the stored values ​​in the coarse search portion correspond to key values, and the (optionally masked) input key is matched against the stored values ​​in the access operation portion corresponding to each value. The coarse search portion is used to find at most one match, and only one word line is activated during the access operation. Thus, the computational memory can operate as a key-value store.

[0085] FIG. 4 illustrates an exemplary computational memory 400 for performing a coarse search followed by access operations depending on the results of the coarse search.

[0086] 2, computational memory 400 includes two portions: a coarse portion 410 for performing a coarse search and an access portion 420 for performing an access operation. The coarse portion 412 and the access portion 422 are portions of the same memory array 450. A word line circuit 452 enables the results of the coarse search to be provided to the access operation.

[0087] Some elements in Figure 4 are identical, substantially similar, or similar to corresponding elements in Figure 2, and reference should be made to the corresponding elements for further description. For example, IMS Cell (Course) 417 and Key Information 418 correspond to IMS Cell (Course) 217 ​​and Key Information 218, respectively. Furthermore, Array 450 corresponds to Array 250, Course 410 corresponds to Course 210, Access 420 generally corresponds to Fine 220 (Bit Line Circuit 421 has no input corresponding to Fine Search Parameters 229, and Post-Processing (Count) 225 has no corresponding element in Fine 220), and so on. As in Figure 3, elements in Figure 4 correspond to elements in Figure 2 identified by the last two digits of the element identifier. Therefore, the following description focuses on elements in Figure 4 that operate differently from their corresponding elements in Figure 2.

[0088] Similar to wordline circuit 252, wordline circuit 452 drives (e.g., provides voltage Vread) a single one of the wordlines of array 450 for reading (corresponding to the exact match represented in coarse search result 415), and wordline circuit 452 activates (e.g., provides voltage Vpass) the remaining wordlines of array 450 for passing.

[0089] Bit line circuitry 421 corresponds in configuration to bit line circuitry 221, but differs in that it operates the bit line terminals of access portion 422 according to predetermined values, e.g., includes a precharger for each of the bit line terminals (similar to bit line circuitry 211). The prechargers operate (in conjunction with other circuits, e.g., word line circuitry 452 and / or sense amplifier circuitry 424) to precharge the memory strings of access portion 422.

[0090] Sense amplifier circuit 424 corresponds to sense amplifier circuit 224. However, rather than providing the results to another element for further processing, the results are provided directly (e.g., in binary encoding) as access results 426. The results correspond to a selected page of data, an example of which is shown as page data 427.

[0091] Thus, the access results 426 include information based on the course search parameters 419 as well as information stored in the course portion 412 and the access portion 422 .

[0092] In some variations of the above computational memory, the word lines are continuous across two portions of the array. For example, the word lines (e.g., WL1...WL48) are continuous across the coarse portion 212 and the fine portion 222 (FIG. 2). In other examples, the word lines are continuous across the coarse portion 312 and the computation portion 322 (FIG. 3), and across the coarse portion 412 and the access portion 422 (FIG. 4). In some variations, the word lines of the two portions are driven separately. For example, the word lines are not continuous between the two portions.

[0093] In some variations of the above computational memory, the bit line circuitry and / or sense amplifier circuitry are partitioned between two portions of the array. For example, bit line circuit 211 and bit line circuit 221 are two segments of a bit line circuit spanning coarse portion 212 and fine portion 222 (FIG. 2). In another example, bit line circuit 311 and bit line circuit 321 are two segments of a bit line circuit spanning coarse portion 312 and computation portion 322 (FIG. 3), and bit line circuit 411 and bit line circuit 421 are two segments of a bit line circuit spanning coarse portion 412 and access portion 422. In a similar example, sense amplifier circuit 214 and sense amplifier circuit 224 are two segments of a sense amplifier circuit spanning coarse portion 212 and fine portion 222 (FIG. 2). In another similar example, sense amplifier circuit 314 and sense amplifier circuit 324 are two segments of the sense amplifier circuit spanning course portion 312 and calculation portion 322 (FIG. 3), and sense amplifier circuit 414 and sense amplifier circuit 424 are two segments of the sense amplifier circuit spanning course portion 412 and access portion 422. In some examples of partitioned sense amplifier circuits, sense amplifier post-processing is included in a segment of the sense amplifier circuit. For example, sense amplifier circuit 214 is included in a first segment of the sense amplifier circuit, and sense amplifier circuit 224, together with post-processing (counting) 225, is included in a second segment of the sense amplifier circuit (FIG. 2). For another example, sense amplifier circuit 314 is included in a first segment of the sense amplifier circuit, and sense amplifier circuit 324, together with post-processing (scaling and summing) 325, is included in a second segment of the sense amplifier circuit (FIG. 3).

[0094] In some variations of the above computational memories, the bit lines are precharged, for example, according to a predetermined value or according to a dynamic value, depending on whether the bit lines are being used as inputs. In other variations, the bit lines are not precharged, but are instead driven according to a predetermined or dynamic value.

[0095] In some variations of the above computational memories, each memory cell can store one or more symbols, for example, via binary or analog techniques. For example, a memory cell can store a single symbol as an analog value, such as a device threshold voltage. As a specific example, programming the threshold voltage of a SONOS cell can be used for (e.g., analog) data storage. In another example, a memory cell can store a single symbol, interpreted as, for example, a single bit of information, using SLC techniques. In other examples, a memory cell can store multiple symbols using MLC, TLC, or QLC techniques.

[0096] In some variations of the above computational memory, a page buffer (e.g., implemented as a page buffer circuit) and / or a page cache (e.g., implemented as a page cache circuit) are used to store the results. For example, fine search results 226 are associated with fine portion 222 (FIG. 2) and stored in a page buffer. In another example, calculation results 326 are associated with calculation portion 322 (FIG. 3) and stored in a page buffer, and access results 426 are associated with access portion 422 (FIG. 4) and stored in a page buffer and / or page cache. In another example, access results 426 are stored in a page cache circuit coupled to sense amplifier circuit 424. The page cache circuit can cache pages of results read from access portion 422. The pages of results correspond to information stored in page data 427, for example. Computational Memory Devices

[0097] Some elements (e.g., integrated circuits, one or more dies of a system-on-chip, and / or a packaging die) include one or more computational memories (such as computational memory 200 of FIG. 2 , computational memory 300 of FIG. 3 , and / or computational memory 400 of FIG. 4 ) along with one or more optional hardware circuit blocks for implementing memory components that can be used as standalone components and / or as components in a system. For example, the hardware circuitry enables the use of the computational memory in a computational SSD (such as computational SSD 700 of FIG. 7 and / or computational SSD 840 of FIG. 8 as configurable computational memory device 765). In another example, the optional hardware circuit blocks enable the use of the computational memory as a component of a system-on-chip.

[0098] Exemplary optional hardware circuit blocks are an I / O interface, a controller, and an analog source.

[0099] The I / O interface allows interfacing to an agent (such as a host) external to the computational memory to use the computational memory. Exemplary uses are configuring an array of the computational memory (such as configure array 501 in FIG. 5), programming an array of the computational memory (such as program array 502 in FIG. 5), instructing the computational memory to perform a first function and optionally receive a result of the first function (such as first function 503 in FIG. 5), and instructing the computational memory to perform a second function and optionally receive a result of the second function (such as second function 504 in FIG. 5).

[0100] The controller may provide overall control of the operation of and between various hardware circuit blocks of one or more computational memories. For example, the controller coordinates the operation of I / O interfaces to and from portions of a memory array of the computational memory. In another example, the controller coordinates the operation of analog sources with reference to configuration information. In another example, the controller optionally coordinates the ordering of a second function depending on a first function.

[0101] The analog sources may generate and / or provide one or more analog outputs to, for example, a memory array, bit line circuitry, sense amplifier circuitry, and / or word line circuitry of a computational memory. The analog outputs may comprise zero or more voltage and / or current sources (e.g., reference sources), such as those generated by one or more bias circuits. Computational Memory Operations

[0102] FIG. 5 shows an example flow diagram for a technique for operating computational memory, such as with respect to the computational SSD techniques shown or referenced in any of the other figures.

[0103] The flow proceeds in four actions: configure array 501, program array 502, first function 503, and second function 504. The flow is for one of three types of dedicated arrays and for arrays that are configurable according to any one or more of the three types of dedicated arrays. The flow for each type of dedicated array is described first, followed by the flow for configurable arrays.

[0104] The flow for any of the three types of specialized arrays begins with the array's program 502. Consider an array (such as array 250 in FIG. 2) specialized for a first IMS (coarse search) followed by a second IMS (fine search) responsive to the first search. The details of the flow are indicated by the actions of coarse 519 and fine 529.

[0105] The flow begins with programming the array 502 by storing values ​​in respective portions of dedicated arrays. The coarse search portion of the array is programmed with values ​​to be searched for matches using the coarse search portion of the array (program coarse array 512). The fine search portion of the array is programmed with values ​​to store and match search information provided via bit lines in the fine search portion of the array (program fine array 522).

[0106] Flow then proceeds to a first function 503. The first of the two functions (corresponding to a coarse search) is performed using a coarse search portion of the array. The word lines of the array are driven, and the bit lines of the coarse search portion of the array are manipulated and sensed (Drive WL, Manipulate BL, Sense 513). More specifically, the word lines of the array are driven according to coarse search information (e.g., key information and optionally a mask). The bit lines of the coarse search portion of the array are manipulated according to predetermined values ​​that enable the coarse search portion of the array to operate as a readable memory with respect to the word lines, and values ​​programmed into the coarse search portion of the array. The bit lines of the coarse search portion of the array are sensed to determine a match between the word lines and the values ​​programmed as a result of the first function. The results of the first function (the coarse search) are provided for use by a second function.

[0107] Flow then proceeds to a second function 504. The second of the two functions (fine search) is performed using the fine search portion of the array. The word lines of the array are driven, and the bit lines of the fine search portion of the array are manipulated, sensed, and counted (Drive WL; Manipulate BL; Sense and Count 524). More specifically, the word lines are driven according to the results of the coarse search. The bit lines of the fine search portion of the array are manipulated according to their dynamic values ​​stored in the fine search portion of the array, which serve as search parameters for the fine search portion of the array to search (in parallel). The bit lines of the fine search portion of the array are sensed to determine matches, and the matches are then counted (e.g., in one or more groups) to determine the overall best match or matches as the result of the second function. The results of the second function (fine search) are then available for use by other agents. Thus, the flow for the array dedicated to the first IMS followed by the second IMS is completed.

[0108] Next, consider an array (such as array 350 in FIG. 3) that is specific to an IMS (course search) followed by an IMC (calculation) that depends on the IMS. The flow details are shown by the actions Course 519 and Calculation 539.

[0109] For arrays dedicated to the first and second IMS searches, the flow begins with programming the arrays 502 by storing values ​​in the respective portions of the dedicated arrays. The coarse search portion of the array is programmed with values ​​to be searched for matches using the coarse search portion of the array (program coarse array 512). The computation portion of the array is programmed with values ​​to store and compute using computation parameters supplied via the bit lines of the computation portion of the array (program computation array 532).

[0110] For arrays dedicated to the first and second IMS searches, flow then proceeds to a first function 503, which performs the first function by driving the word lines and steering and sensing the bit lines of the coarse search portion of the array (Drive WL; Steering BL; Sensing 513). The results of the first function (the coarse search) are provided for use by a second function.

[0111] For arrays dedicated to the first and second IMS searches, flow then proceeds to a second function 504. The second of the two functions (computation) is performed using the computation portion of the array. The word lines of the array are driven, and the bit lines of the computation portion of the array are manipulated, sensed, and summed (Drive WL; Manipulate BL; Sense and Add 534). More specifically, the word lines of the array are driven according to the results of the coarse search. The bit lines of the computation portion of the array are manipulated according to respective dynamic values ​​provided as computation parameters that the computation portion of the array uses as computation operands (in parallel) with the stored values ​​of the computation portion of the array. The bit lines of the computation portion of the array are sensed to determine respective intermediate results (e.g., respective analog currents or voltages). The intermediate results are then combined (e.g., summed using analog techniques) to generate one or more results of the second function. The results are optionally converted to a digital representation. In some variations, sensing and summing are performed together. The results of the second function (computation) are then available for use by other agents. Thus, the flow for an IMS-specific array followed by an IMC is complete.

[0112] Next, consider an array (such as array 450 in FIG. 4) specific to an IMS (course search) followed by an access operation according to the IMS. The flow details are shown by the actions Course 519 and Access 549.

[0113] For arrays dedicated to the first and second IMS searches, the flow begins with programming the arrays 502 by storing values ​​in the respective portions of the dedicated arrays. The coarse search portion of the array is programmed with values ​​to be searched for matches using the coarse search portion of the array (program coarse array 512). The access operation portion of the array is programmed with values ​​to store that are available for reading by subsequent access operations (program access array 542).

[0114] For arrays dedicated to the first and second IMS searches, flow then proceeds to a first function 503, which performs the first function by driving the word lines and steering and sensing the bit lines of the coarse search portion of the array (Drive WL; Steering BL; Sensing 513). The results of the first function (the coarse search) are provided for use by a second function.

[0115] For arrays dedicated to the first and second IMS searches, flow then proceeds to a second function 504. The second of the two functions (the access operation) is performed using the access operation portion of the array. The word lines of the array are driven, and the bit lines of the access operation portion of the array are manipulated and sensed (Drive WL; Manipulate BL; Sense 544). More specifically, the word lines are driven according to the results of the coarse search. The bit lines of the access operation portion of the array are manipulated according to predetermined values ​​that enable the access operation portion of the array to operate as a readable memory with respect to the word lines, and values ​​programmed in the fine search portion of the array. The bit lines of the access operation portion of the array are sensed to determine respective digital results that collectively form one or more results of the second function. The results of the second function (the access operation) are then available for use by other agents. Thus, the flow for an IMS-dedicated array followed by an access operation is complete.

[0116] The configurable array flow begins with the action Configure Array 501. A configurable array (such as a configurable combination of elements from Figures 2, 3, and / or 4) is configured according to a specialized allocation for each type of operation, i.e., fine search, calculation, and access operations.

[0117] Flow then proceeds individually (optionally in parallel) for each assignment according to the configuration as indicated by configurable 550. Thus, for each assignment configured as a first IMS (coarse search) followed by a second IMS (fine search) responsive to the first IMS search, flow proceeds according to coarse 519 and fine 529. For each assignment configured as a first IMS (coarse search) followed by an IMC (calculate) responsive to the IMS search, flow proceeds according to coarse 519 and calculate 539. For each assignment configured as a first IMS (coarse search) followed by an access operation responsive to the IMS, flow proceeds according to coarse 519 and access 549. Exemplary Wordline and Bitline Based Search

[0118] Figures 6A and 6B collectively illustrate a search through information provided on a word line, and Figures 6C and 6D collectively illustrate a search through information provided on a bit line.

[0119] Referring first to Figures 6A and 6B and the search through the word lines, coarse portion 612 and IMS cell (coarse) 617 correspond to coarse portion 212 and IMS cell (coarse) 217, respectively, of Figure 2 (although Figure 6A omits some details shown in Figure 2). T1 671 and T2 672 are contiguous on BL1 693 and coupled to word lines WL1 691 and WL2 692, respectively. Figure 6B shows example threshold voltages for programming T1 671 and T2 672 and search voltages for driving WL1 691 and WL2 692, which allow matching search information to stored information.

[0120] The threshold voltages for T1 671 and T2 672 shown in FIG. 6B specify encodings that allow for matching on only zero ("0"), only one ("1"), anything ("X"), and nothing ("void"). The search voltages for WL1 691 and WL2 692 shown in FIG. 6B specify encodings that allow for searching on only zero ("0"), only one ("1"), anything / wildcard ("WC"), and nothing ("void"). As one specific example, to match on zero, T1 671 is programmed to a threshold voltage of Vt.High and T2 672 is programmed to a threshold voltage of Vt.Low. To search for zero, WL1 691 is driven to V.High2 and WL2 692 is driven to V.High1. The last row of the table in FIG. 6B shows an exemplary relationship between two threshold voltages Vt.Low and Vt.High and two search voltages V.High1 and V.High2. Specifically, the two threshold voltages (Vt.Low and Vt.High) are lower than either of the two search voltages (V.High1 and V.High2). In other words, the two search voltages are higher than either of the two threshold voltages. Additionally, Vt.Low is a voltage lower than Vt.High, and V.High1 is a voltage lower than V.High2. As a specific example, Vt.Low (the lowest voltage) is −1V, Vt.High is 3V, V.High1 is 4V, and V.High2 (the highest voltage) is 5V.

[0121] During operation, pairs of memory devices in a coarse portion of a memory array (e.g., memory devices BL1, ... BL48 in coarse portion 212 of FIG. 2) are programmed with data to search according to FIG. 6B. Programming is performed, for example, as part of program 512 of the coarse array of FIG. 5. A search is then performed according to driving pairs of word lines (e.g., WL1, WL2, ... WL47, WL48 of FIG. 2) according to FIG. 6B. The search is performed as part of drive WL; operate BL; sense 513 of FIG. 5.

[0122] 6C, 6D, and the search through bit lines, fine portion 622 and IMS cell (fine) 627 correspond to fine portion 222 and IMS cell (fine) 227, respectively, of FIG. 2 (although FIG. 6C omits some details shown in FIG. 2). T1681 and T2682 are coupled to respective bit lines BL128K-1698 and BL128K699, and share word lines. FIG. 6D shows example threshold voltages for programming T1681 and T2682, and search voltages for driving BL128K-1698 and BL128K699, which enable a match of search information to stored information.

[0123] Similar to FIG. 6B, the threshold voltages for T1 681 and T2 682 shown in FIG. 6D specify encodings to allow matching for zero only ("0"), one only ("1"), anything ("X"), and nothing ("void"). The search voltages for BL128K-1698 and BL128K699 shown in FIG. 6D specify encodings to allow searching for zero only ("0"), one only ("1"), anything / wildcard ("WC"), and nothing ("void"). As one specific example, to match for zero, T1 681 is programmed to a threshold voltage of Vt. High and T2 682 is programmed to a threshold voltage of Vt. Low. To search for zero, BL128K-1698 is driven to V. High and BL128K699 is driven to V. Low. The last row of the table in FIG. 6D shows an exemplary relationship between the threshold voltages Vt.Low and Vt.High and the search voltages V.Low and V.High. Specifically, two threshold voltages (Vt.Low and Vt.High) are mixed with respect to the voltage levels between the two search voltages (V.Low and V.High). V.Low is the lowest voltage, Vt.Low is the next highest voltage, V.High is the next highest voltage, and Vt.High is the highest voltage. As a specific example, V.Low is 0V, Vt.Low is 1V, V.High is 2V, and Vt.High is 3V.

[0124] During operation, pairs of memory devices in the fine portion of the memory array (e.g., memory devices BL49, BL50, BL128K-1, and BL128K in FIG. 2) are programmed with data to search according to FIG. 6D. Programming is performed, for example, as part of program fine array 522 in FIG. 5. A search is then performed according to FIG. 6D, with driving pairs of bit lines (e.g., BL128K-1 and BL128K in FIG. 2). The search is performed, for example, as part of drive WL; drive BL; sense and count 524 in FIG. 5.

[0125] In an example of wordline encoding (such as in FIG. 6B), the search information is a binary key value, allowing only searches for zeros and ones. As another example, the search information is a binary key value along with a binary mask value of equal length to the binary key value. Each bit in the binary mask value indicates whether the corresponding bit in the binary key value is ignored (e.g., matches anything) or matches according to the corresponding binary key value bit. As yet another example, building on the previous example, another binary mask value is further used to indicate whether the corresponding bit in the binary key value is considered invalid (e.g., matches nothing). For example, a 4-bit key value is 0b0111 and the corresponding mask value is 0b0001, resulting in a search for 0b011x, which matches against stored values ​​of 0b110 or 0b0111. Similar examples of bitline encoding (e.g., as in Figure 6D) use a search value alone, a search value in conjunction with a mask value, and / or a search value in conjunction with multiple mask values. For example, a 4-bit search (e.g., key) value might be 0b1010 and the corresponding mask value might be 0b1000, resulting in a search for 0bx010, which would result in a match against a stored value of 0b1010 or 0b0010. Computational SSDs

[0126] Computational SSD resources can be used in a variety of systems (e.g., systems using smart SSDs), such as compute servers, database servers, IMS servers, IMC servers, and AI accelerators.

[0127] FIG. 7 illustrates an exemplary computational SSD as computational SSD 700.

[0128] Computational SSD 700 includes at least one instance of a computational memory device, such as at least one of computational memory device 762, computational memory device 763, computational memory device 764, or configurable computational memory device 765. It should be noted that each instance of coarse search 710, fine search 720, calculate 730, and access 740 may be similar, substantially similar, or identical to one another, depending on the configuration.

[0129] The computational memory device 762 is intended to implement a fine search capability and includes a memory array operable in two parts to implement a coarse search 710 that provides information to a second function 752 for implementing a fine search 720. The computational memory device 762 can be used, for example, in systems (such as database servers) intended to provide large-scale search capabilities.

[0130] The computational memory device 763 includes a memory array operable as two parts to implement a course search 710 that provides information to a second function 753 for implementing calculation 730 for the purpose of implementing computational power. The computational memory device 763 can be used, for example, in a server (such as an AI system) intended to provide large-scale computational power.

[0131] The computational memory device 764 is intended to implement the access capability and includes a memory array operable as two parts to implement a course search 710 that provides information to a second function 754 to implement the access 740. The computational memory device 764 can be used in a server intended to provide key-value information, such as, for example, a key-value SSD-based system.

[0132] The configurable computational memory device 765 is intended for configurable computational SSD capabilities, such as those usable in database servers, AI systems, and / or key-value SSD-based systems, according to configuration. The configurable computational memory device 765 includes a memory array operable as two parts to implement a coarse search 710 that provides information to a configurable second function 755 to implement a configuration determined by one of fine search 720, calculation 730, and access 740.

[0133] Interface 780 interfaces the computational memory device to a host and / or bus via host / bus coupling 782.

[0134] Computational SSD 700 is an exemplary implementation of computational SSD 840 of FIG. 8, with host / bus coupling 782 functioning to couple to bus / interface 880 of FIG.

[0135] Course search 710 is exemplified by course 210 in FIG. 2, course 310 in FIG. 3, and / or course 410 in FIG.

[0136] Fine search 720 is exemplified by fine 220 in Figure 2. Compute 730 is exemplified by compute 320 in Figure 3. Access 740 is exemplified by access 420 in Figure 4.

[0137] Other compartmentalizations of elements, couplings between elements, and capabilities and / or capacities of elements shown in the figures, as well as additional elements, are contemplated according to usage requirements. Computational SSD Systems

[0138] 8 illustrates an exemplary hardware system with a computational SSD as computational SSD system 800. The system includes hardware blocks CPU 810, GPU 820, RAM 830, computational SSD 840, conventional SSD 850, HDD 860, and I / O 870 coupled by a hardware block bus / interface 880.

[0139] Computational SSD 840 includes one or more instances of computational SSD 700 of FIG.

[0140] CPU 810 comprises one or more processing units, such as any combination of hardware units capable of executing programmed instructions, such as microprocessors, signal processors, AI processors, etc. One or more of the processing units optionally include one or more internal registers (some of which are, optionally, architecturally visible), one or more cache memories, and / or one or more internal memories (such as for buffering and / or coalescing), represented by registers, caches, and internal memory 812.

[0141] GPU 820 comprises one or more processing units, such as any combination of units capable of accelerating processing for processes subject to a relatively high degree of parallelism, such as graphics processing, signal processing, and / or AI processing. Similar to the registers, cache, and internal memory 812 of CPU 810, one or more of the processing units optionally include one or more internal registers (some of which are optionally architecturally visible, represented by registers, cache, and internal memory 822), one or more cache memories, and / or one or more internal memories (such as for buffering and / or fusion).

[0142] The RAM 830 comprises one or more memory elements for storing instructions and / or data in a larger amount than the storage internal to the CPU 810 and / or GPU 820. The RAM 830 can be implemented via volatile memory elements such as, for example, DRAM and / or SRAM.

[0143] Conventional SSD 850 optionally includes one or more storage elements, such as flash-based storage elements, for storing instructions and / or data that are accessible with reduced latency compared to HDD 860.

[0144] HDD 860 optionally includes one or more storage elements, such as rotational-based magnetic and / or non-volatile optical storage elements (e.g., disks), for storing instructions and / or data in larger quantities than a conventional SSD 850 can store.

[0145] I / O 870 includes elements for interfacing any combination of CPU 810, GPU 820, RAM 830, computational SSD 840, conventional SSD 850, and / or HDD 860 with elements external to computational SSD system 800. Exemplary external elements include mass storage devices, local and wide area networks (such as the Internet), human interface components (such as a keyboard, mouse, and / or monitor), and other elements that provide capabilities to extend and / or enhance capabilities not otherwise provided by computational SSD system 800.

[0146] Bus interface 880 enables communication between elements coupled thereto (e.g., CPU 810, GPU 820, RAM 830, computational SSD 840, conventional SSD 850, HDD 860, and / or I / O 870). I / O 870 may comprise one or more serial and / or parallel communication channels, as well as optional protocol conversion and / or adaptation capabilities to facilitate communication between elements coupled thereto.

[0147] Conceptually, the various storage elements in computational SSD system 800 comprise a memory hierarchy for purposes such as reducing overall instruction and / or data access time, reducing overall cost of instruction and / or data storage, and / or reducing power consumption relative to storage capacity. For example, the registers, cache, and internal memory 812 of CPU 810 and the registers, cache, and internal memory 822 of GPU 820 collectively comprise the highest level of the memory hierarchy. The memory hierarchy further includes (from top to bottom) RAM 830, conventional SSD 850, HDD 860, and, optionally, storage accessible via I / O 870 (such as website information accessible via the Internet). In examples, higher levels of the memory hierarchy have lower latency and lower capacity than lower levels. For example, the registers, cache, and internal memory 812 and the registers, cache, and internal memory 822 have lower access latency and / or storage capacity than RAM 830. On the other hand, the RAM 830 has lower access latency and / or storage capacity than the conventional SSD 850.

[0148] In a first variation of the example, computational SSD 840 includes a level of memory hierarchy between RAM 830 and conventional SSD 850 and / or HDD 860, bridging the gap in access latency and / or storage capacity. In a second variation of the example, any one or more of registers, cache, and internal memory 812, registers, cache, and internal memory 822, RAM 830, conventional SSD 850, HDD 860, and / or storage accessible via I / O 870 are augmented with elements based on computational SSD 840 techniques to reduce access latency and / or increase storage capacity. In other examples, various combinations of SCM, NVDIMM, CXL memory, SSD, and / or DRAM-like storage are implemented using computational SSD 840 techniques. In yet another example, the computational SSD 840 can reduce the processing load (e.g., on the CPU 810 and / or GPU 820) and / or reduce traffic on the bus / interface 880 by performing processing locally.

[0149] Other compartmentalizations of elements, couplings between elements, and capabilities and / or capacities of elements shown in the figures, as well as additional elements, are contemplated according to usage requirements. More information on computational SSDs

[0150] 2, 3, and 4 show techniques that may be applied to an architecture for a computational SSD. Other techniques may also be applied according to different memory technologies, etc.

[0151] Exemplary memory technologies applicable to the memory array of the computational SSD disclosed herein include floating gate, split gate, SONOS, floating dot, DRAM, DRAM-like (e.g., 2T0C), FeFET, and any memory technology compatible with searching via word lines and bit lines. Exemplary SONOS memory technology (sometimes referred to as charge trapping memory) uses a trap-containing insulating layer (e.g., of silicon nitride) to capture and retain charge when injected from the channel. Exemplary floating dot memory technology conceptually replaces the floating gate with floating silicon nanodots or embeds floating silicon nanodots within a polysilicon gate. Exemplary 2T0C memory technology uses the parasitic capacitance of the read transistor to store charge rather than an explicit storage capacitor. Exemplary FeFET memory technology uses the permanent field polarization of a ferroelectric material embedded between the gate and source-gate conducting regions to store information. Exemplary memory structures applicable to the memory array of a computational SSD include a 2D structure (e.g., a 2D flash structure) and a 3D structure (e.g., a 3D flash structure). Exemplary array architectures applicable to the memory array of a computational SSD include a NOR / OR type array architecture and an AND / NAND type array architecture.

[0152] It is understood that the foregoing disclosure presents implementations, variations, embodiments, and examples in an intended illustrative, and not a limiting, sense. Modifications and combinations within the spirit of this disclosure and the scope of the following claims are contemplated as being discernible.

Claims

1. 1. A method for operating a memory system, comprising: first sensing a first portion of memory strings of a memory array according to (i) a first voltage driven on a word line of the memory array and (ii) a predetermined operating condition of the first portion of the memory strings; second sensing a second portion of the memory strings of the memory array according to (i) a second voltage driven on a word line of the memory array and (ii) a dynamic operating condition of the second portion of the memory strings; and providing a result of said second detecting step; the second voltage being based on a result of the first sensing step; the dynamic operating condition is selected from at least one of a fine search, a calculation, and an access operation; method.

2. The method of claim 1 , wherein the dynamic operating condition is generated by manipulating bit line circuit terminals of a second portion of the memory strings according to a dynamic value.

3. 3. The method of claim 2, wherein the second sensing step includes counting approximate matches between a value stored in a second portion of the memory string and the dynamic value.

4. 3. The method of claim 2, wherein the second sensing step includes summing according to a current in a second portion of the memory string.

5. 5. The method of claim 4, wherein the dynamic values ​​are analog values, the values ​​stored in the second portion of the memory string are analog values, and the summing is according to an analog technique.

6. 6. The method of claim 5, wherein the second sensing step includes scaling the currents in a second portion of the memory strings and then summing.

7. 7. The method of claim 1, wherein the dynamic operating condition enables matching the dynamic value to any value stored in any of the second portions of the memory strings based on a dynamic value and a mask value.

8. 7. The method of claim 1, wherein the dynamic operating condition is based on a dynamic value and a mask value and makes it impossible to match the dynamic value to any value stored in any of the second portions of the memory strings.

9. 7. The method of claim 1, wherein the result of the second sensing step indicates a multiply-accumulate operation, a first operand of the multiply-accumulate operation is a dynamic value, the dynamic operating condition is determined according to the dynamic value, and a second operand of the multiply-accumulate operation corresponds to a value to be programmed into a second portion of the memory string.

10. 7. The method of claim 1, wherein the dynamic operating condition is determined according to a dynamic value, and the result of the second sensing step indicates a search operation for the dynamic value among values ​​programmed into the second portion of the memory string.

11. a memory array including a first portion and a second portion of memory strings, where one or more of the memory strings in the first portion of memory strings and one or more of the memory strings in the second portion of memory strings each include a plurality of contiguously connected memory devices; a word line circuit having terminals coupled to respective control inputs of respective rows in which said memory strings are organized; a bit line circuit having terminals coupled to the bit line terminals of each of the memory strings; a sense amplifier circuit having a terminal coupled to a sense amplifier terminal of each of said memory strings; Equipped with the terminals of the bit line circuit coupled to the bit line terminals of the first portion of the memory strings are capable of providing identical predetermined operating conditions to the bit line terminals of the first portion of the memory strings; the terminals of the bit line circuit coupled to the bit line terminals of the second portion of the memory strings are capable of providing respective dynamic values ​​to the bit line terminals of the second portion of the memory strings; the word line circuitry is capable of selectively driving the control input in accordance with one of a first word line control value and a second word line control value, the first word line control value corresponding to a provided value and the second word line control value corresponding to a result produced by the sense amplifier circuitry based on information provided via the terminals coupled to the bit line terminals of the first portion of the memory strings; the dynamic value corresponds to a dynamic operating condition, the dynamic operating condition being selected from at least one of a fine search, a calculation, and an access operation. Memory system.

12. 12. The memory system of claim 11, further comprising: a counting circuit coupled to the sense amplifier circuit and capable of counting exact matches between values ​​stored in a second portion of the memory string and the respective dynamic values.

13. 12. The memory system of claim 11, further comprising a summing circuit coupled to the sense amplifier circuitry to enable summing according to currents in a second portion of the memory strings.

14. A memory array including a first portion and a second portion of memory strings, wherein one or more of the memory strings in the first portion of memory strings and one or more of the memory strings in the second portion of memory strings each include a plurality of contiguously connected memory devices; a word line circuit having terminals coupled to respective control inputs of respective rows in which said memory strings are organized; a bit line circuit having terminals coupled to the bit line terminals of each of the memory strings; a sense amplifier circuit having a terminal coupled to a sense amplifier terminal of each of said memory strings; Equipped with the terminals of the bit line circuit coupled to the bit line terminals of the first portion of the memory strings are capable of providing identical predetermined operating conditions to the bit line terminals of the first portion of the memory strings; the terminals of the bit line circuit coupled to the bit line terminals of the second portion of the memory strings are capable of providing respective dynamic values ​​to the bit line terminals of the second portion of the memory strings; the word line circuitry is capable of selectively driving the control input in accordance with one of a first word line control value and a second word line control value, the first word line control value corresponding to a provided value and the second word line control value corresponding to a result produced by the sense amplifier circuitry based on information provided via the terminals coupled to the bit line terminals of the first portion of the memory strings; a summing circuit coupled to the sense amplifier circuit and adapted to enable summing according to a current of a second portion of the memory string; Memory system.

15. 14. The memory system of claim 13, wherein each of the dynamic values ​​is an analog value, the values ​​stored in the second portions of the memory strings are analog values, and the summing circuitry is operable according to analog techniques.

16. 16. The memory system of claim 15, wherein the summing circuit is further capable of scaling the currents prior to summing.

17. 17. The memory system of claim 11, further comprising one or more processors capable of accessing the memory array.

18. 17. The memory system of claim 11, further comprising: a page cache circuit coupled to the sense amplifier circuit and capable of caching a resulting page read from values ​​stored in the second portion of the memory strings, the terminals of the bit line circuits coupled to the bit line terminals of the second portion of the memory strings being capable of providing identical predetermined operating conditions to the bit line terminals of the second portion of the memory strings.

19. a memory array including a first portion and a second portion of memory strings, where one or more of the memory strings in the first portion of memory strings and one or more of the memory strings in the second portion of memory strings each include a plurality of contiguously connected memory devices; a word line circuit having terminals coupled to respective control inputs of respective rows in which said memory strings are organized; a bit line circuit having terminals coupled to respective bit line terminals of the memory strings and capable of providing identical predetermined operating conditions to the bit line terminals; a sense amplifier circuit having terminals coupled to the sense amplifier terminals of each of the memory strings; the word line circuitry is capable of selectively driving the control input in accordance with one of a first word line control value and a second word line control value, the first word line control value corresponding to a provided value and the second word line control value corresponding to a result produced by the sense amplifier circuitry based on information provided via the terminals coupled to the bit line terminals of the first portion of the memory strings; the terminals of the bit line circuit coupled to the bit line terminals of the second portion of the memory strings are capable of providing dynamic values ​​to the bit line terminals of the second portion of the memory strings; the dynamic value corresponds to a dynamic operating condition, the dynamic operating condition being selected from at least one of a fine search, a calculation, and an access operation. Memory system.

20. 20. The memory system of claim 19, wherein the provided values ​​include a key and a mask, and the selective driving of the control inputs includes selectively driving the control inputs in respective pairs in accordance with a plurality of encodings determined respectively from a respective bit of the key and a corresponding respective bit of the mask, wherein (i) a first one of the plurality of encodings enables selectively matching a stored zero value in response to the provided value being zero, (ii) a second one of the plurality of encodings enables selectively matching a stored one value in response to the provided value being one, (iii) a third one of the plurality of encodings enables selectively matching a stored zero value or a stored one value in response to the provided value being zero or one, and (iv) a fourth one of the plurality of encodings disables selectively matching any stored value to the provided value.

21. A memory array including a first portion and a second portion of memory strings, wherein one or more of the memory strings in the first portion of memory strings and one or more of the memory strings in the second portion of memory strings each include a plurality of contiguously connected memory devices; a word line circuit having terminals coupled to respective control inputs of respective rows in which said memory strings are organized; a bit line circuit having terminals coupled to respective bit line terminals of the memory strings and capable of providing identical predetermined operating conditions to the bit line terminals; a sense amplifier circuit having terminals coupled to the sense amplifier terminals of each of the memory strings; the word line circuitry is capable of selectively driving the control input in accordance with one of a first word line control value and a second word line control value, the first word line control value corresponding to a provided value and the second word line control value corresponding to a result produced by the sense amplifier circuitry based on information provided via the terminals coupled to the bit line terminals of the first portion of the memory strings; the provided values ​​include a key and a mask, and the selective driving of the control inputs includes selectively driving the control inputs in respective pairs according to a plurality of encodings determined respectively from respective bits of the key and corresponding respective bits of the mask, wherein (i) a first of the plurality of encodings enables selectively matching a stored zero value in response to the provided value being zero, (ii) a second of the plurality of encodings enables selectively matching a stored one value in response to the provided value being one, (iii) a third of the plurality of encodings enables selectively matching a stored zero value or a stored one value in response to the provided value being zero or one, and (iv) a fourth of the plurality of encodings disables selectively matching any stored value to the provided value. Memory system.

22. 22. The memory system of claim 19, further comprising one or more processors capable of accessing a computational solid-state drive (SSD) including the memory array including at least one memory device.

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