Data transmission device, memory device having the same, and method of operating the same

Abstract

To provide a data transmission device that reduces power consumption and an operation method thereof.SOLUTION: A data transmission device 100 includes a transmitter 110, a first line Q0, a second line Q1, and a receiver 120. The transmitter converts received binary data into ternary data, and toggling is performed on only one of the first and second lines during each of continuous 2-bit data transmission time intervals. The receiver converts the turnary data received from the first line and the second line into binary data. Therefore, the power consumption is reduced by toggling and outputting the voltage of only one of the first line and the second line of the 2-bit data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a data transmission device, a memory device having the same, and a method of operating the same. [Background technology]

[0002] In general, semiconductor memory devices, which are widely used in high-performance electronic systems, are increasing in capacity and speed. As an example of a semiconductor memory device, a dynamic random access memory (DRAM) is a volatile memory that determines data based on a charge stored in a capacitor. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a data transmission device that reduces power consumption, a memory device having the same, and an operating method thereof. [Means for solving the problem]

[0004] The data transmission device according to the embodiment of the present invention includes a first line, a second line, and a ternary data transmission line for receiving binary data. and a receiver implemented to convert the ternary data received from the first and second lines into binary data by toggling only one of the first and second lines during each of consecutive 2-bit data transmission time intervals.

[0005] A method of transmitting data according to an embodiment of the present invention includes converting two consecutive bits of serially received binary data into ternary data, and decoding the ternary data received from a pair of signal lines into binary data, wherein the ternary data is provided to the pair of signal lines using a return-to-zero toggling operation, and the ternary data may be applied to only one of the pair of signal lines during each of a plurality of consecutive 2-bit data transmission time intervals.

[0006] A data transmission device according to one embodiment of the present invention includes a first line, a second line, a transmitter that receives binary data, converts the binary data to ternary data, and outputs the converted ternary data to the first line and the second line, and a receiver that receives the ternary data via the first line and the second line and converts the received ternary data to the binary data, and is characterized in that when the ternary data is transmitted to the first line and the second line, any one of the first line and the second line is not toggled.

[0007] A memory device according to an embodiment of the present invention may include a first transistor having a drain connected to a power supply terminal and a gate connected to a first local I / O line; a second transistor having a drain connected to a source of the first transistor and a gate connected to an inverted line of the first local I / O line; a third transistor having a drain connected to a source of the second transistor, a source connected to a ground terminal, and a gate receiving a local sense amplification activation signal; a fourth transistor having a drain connected to the source of the first transistor and a gate connected to an inverted line of a second local I / O line; a fifth transistor having a drain connected to the source of the fourth transistor, a source connected to a first global I / O line, and a gate receiving the local sense amplification activation signal; a sixth transistor having a drain connected to the source of the first transistor and a gate connected to a second local I / O line; and a seventh transistor having a drain connected to the source of the sixth transistor, a source connected to a second global I / O line, and a gate receiving the local sense amplification activation signal.

[0008] A method of operating a data transmission device according to an embodiment of the present invention includes converting binary data into ternary data using a code map in a transmitter, and transmitting the converted ternary data from the transmitter via a 2-line, wherein the code map maps the ternary data corresponding to the binary data using a state in which the 2-lines do not toggle simultaneously. Effect of the Invention

[0009] A data transmission device, a memory device having the same, and an operating method thereof according to embodiments of the present invention can reduce the number of data lines during data transmission and reduce power consumption by transmitting ternary data that is not toggled simultaneously on two lines. [Brief description of the drawings]

[0010] The following attached drawings are provided to facilitate understanding of the present embodiments and, together with the detailed description, provide the embodiments. [Figure 1] 1 is a diagram illustrating an exemplary data transmission device 100 according to an embodiment of the present invention. [Diagram 2] 13 is a diagram illustrating an example of data transmitted on two lines Q0 and Q1 in a non-toggle case according to an embodiment of the present invention. FIG. [Diagram 3] 1 is an exemplary diagram illustrating a transmitter 110 according to an embodiment of the present invention. [Figure 4] 1 is an exemplary diagram illustrating an embodiment of a receiver 120 according to an embodiment of the present invention. [Diagram 5] 5 is a diagram illustrating an example of the T-to-B decoder 124 shown in FIG. 4. [Figure 6] 10 is a diagram illustrating an example of a table related to a decoding process of a receiver 120 according to an embodiment of the present invention. [Figure 7] 4 is a flow chart illustrating an exemplary method of operation of a transmitter 110 according to an embodiment of the present invention. [Figure 8] 4 is a flow chart illustrating an exemplary method of operation of a receiver 120 according to an embodiment of the present invention. [Figure 9] 13 is a diagram illustrating a memory device according to another embodiment of the inventive concept; [Figure 10] FIG. 10 illustrates a portion of the bank array shown in FIG. 9 in greater detail. [Figure 11] 11 is a diagram illustrating an example of a bit line sense amplifier BLSA shown in FIG. [Figure 12] 12 is an exemplary diagram illustrating the local sense amplifier circuit LSA shown in FIG. 11. [Figure 13] 13 is a diagram illustrating an example of ternary data transmitted to global input / output lines GIO0 and GIO1 according to an embodiment of the present invention. [Figure 14] 2 is an exemplary diagram illustrating a transmitter 272 for global input / output line signaling according to an embodiment of the present invention. [Figure 15] 2 is an exemplary diagram illustrating a receiver 274 for global input / output line signaling in accordance with an embodiment of the present invention. [Figure 16] 13 is a diagram illustrating an example of a decoding table for global input / output lines according to an embodiment of the present invention; [Figure 17a] FIG. 2 illustrates an embodiment of a chord map according to an embodiment of the present invention. [Figure 17b] FIG. 2 illustrates an embodiment of a chord map according to an embodiment of the present invention. [Figure 17c] FIG. 2 illustrates an embodiment of a chord map according to an embodiment of the present invention. [Figure 17d] FIG. 2 illustrates an embodiment of a chord map according to an embodiment of the present invention. [Figure 18] 30 is an exemplary diagram illustrating a mobile device 3000 according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the following, the contents of the present invention will be described clearly and in detail with reference to the drawings to such an extent that a person having ordinary skill in the technical field of the present invention can easily carry out the invention.

[0012] 1 is a diagram illustrating a data transmission device 100 according to an embodiment of the present invention. Referring to FIG. 1, the data transmission device 100 may include a transmitter 110 and a receiver 120.

[0013] The transmitter (TX) 110 can be realized to receive binary data (or binary data) and transmit a ternary code (or ternary code) corresponding to the binary data via two lines Q0 and Q1. Here, the ternary code can be expressed as any one of "-1", "0", and "1".

[0014] In an embodiment, when the ternary data is "-1", the ternary data has a first level, when the ternary data is "0", the ternary data has a second level, and when the ternary data is "1", the ternary data has a third level, where the first level is lower than the second level, the third level is higher than the second level, and the second level may be the level of a reference voltage.

[0015] The transmitter 110 may include an encoder 114 that receives binary data and outputs a ternary code corresponding to the binary data using a code map. In an embodiment, the code map may be set so that the two lines Q0 and Q1 that transmit the ternary code do not transmit toggling data at the same time.

[0016] A receiver (RX) 120 can be implemented to receive the ternary code via two lines Q0, Q1 and output binary data corresponding to the ternary code. The receiver 120 may include a decoder 124 that receives the ternary code and uses the code map to output binary data that corresponds to the ternary code.

[0017] 1 may be implemented as a single integrated circuit. However, the present invention is not limited thereto. The transmitter 110 and the receiver 120 may be implemented as their own respective integrated circuits.

[0018] The data transmission device 100 according to an embodiment of the present invention can reduce the number of toggles by converting 2-bit binary data into ternary data and transmitting the converted ternary data on two lines using a code map for the non-toggle case.

[0019] 2 is a diagram illustrating an example of data transmitted to two lines Q0 and Q1 in a non-toggle case according to an embodiment of the present invention. Referring to FIG. 2, when the first line Q0 has the same level as the reference voltage VREF and the second line Q1 has a level lower than the reference voltage VREF, the 2-bit binary data can correspond to "00". Here, when the first line Q0 is the reference voltage VREF, the ternary data is "0", and when the second line Q1 has a level lower than the reference voltage VREF, the ternary data is "-1".

[0020] Also, when the first line Q0 has a level lower than the reference voltage VREF and the second line Q1 has a level equal to the reference voltage VREF, the 2-bit binary data can correspond to "10".

[0021] Also, when the first line Q0 has the same level as the reference voltage VREF and the second line Q1 has a level higher than the reference voltage VREF, the 2-bit binary data may correspond to "11." Here, when the second line Q1 has a level higher than the reference voltage VREF, the ternary data is "1."

[0022] Also, when the first line Q0 has a level higher than the reference voltage VREF and the second line Q1 has a level equal to the reference voltage VREF, the 2-bit binary data can correspond to '01'.

[0023] Meanwhile, the data transmitted to each of the two lines Q0 and Q1 may be an RZ (Return-to-Zero) signaling signal as shown in FIG. 2. That is, after transmitting 2-bit data using a ternary code, a reset section RST exists. The level of the reset section RST may be the level of a reference voltage VREF. However, the present invention is not limited thereto. The data transmitted to each of the two lines Q0 and Q1 may be an NRZ (Non-Return-to-Zero) signaling signal.

[0024] On the other hand, it should be understood that the binary data corresponding to the non-toggle ternary data on the two lines Q0 and Q1 shown in FIG. 2 is merely an embodiment.

[0025] 3 is a diagram illustrating an example of a transmitter 110 according to an embodiment of the present invention. Referring to FIG. 3, the transmitter 110 may include transistors T1 to T7 and switches SW1 and SW2. For convenience of explanation, it is assumed in FIG. 3 that the 2-bit binary data includes a first data bit D0 and a second data bit D1.

[0026] The first transistor T1 includes a drain coupled to a power supply terminal VDD and a gate receiving a first data bit D0. The second transistor T2 includes a drain coupled to a source of the first transistor T1 and a gate receiving an inverted bit D of the first data bit D0. 0 The third transistor T3 may include a drain connected to the source of the second transistor T2, a source connected to the ground terminal GND, and a gate receiving an activation signal EN. The fourth transistor T4 may include a drain connected to the source of the first transistor T1, and a gate receiving an inverted bit D1B of the second data bit D1. The fifth transistor T5 may include a drain connected to the source of the fourth transistor T4, a source connected to the first line Q0, and a gate receiving the activation signal EN. The sixth transistor T6 may include a drain connected to the source of the first transistor T1, and a gate receiving the second data bit D1. The seventh transistor T7 may include a drain connected to the source of the sixth transistor T4, a source connected to the second line Q1, and a gate receiving the activation signal EN.

[0027] The first switch SW1 may provide a precharge voltage VPRE to the first line Q0 in response to a precharge signal P_PRE, and the second switch SW2 may provide a precharge voltage VPRE to the second line Q1 in response to the precharge signal P_PRE.

[0028] However, it should be understood that the configuration of the transmitter 110 shown in FIG. 3 is merely an embodiment.

[0029] 4 is a diagram illustrating an exemplary embodiment of a receiver 120 according to an embodiment of the present invention. Referring to FIG. 4, the receiver 120 may include a first comparator 121, a second comparator 122, and a T-to-B decoder 124.

[0030] The first comparator 121 may be implemented to compare the voltage of the first line Q0 with the voltage of the second line Q1 and output a first comparison voltage F_DIFF. Here, the first comparison voltage F_DIFF may be a differential voltage. Meanwhile, the first comparator 121 may be referred to as a differential latch Q1-Q0.

[0031] The second comparator 122 may be realized to compare a common voltage (Q0+Q1) / 2 of the voltages of the first line Q0 and the second line Q1 with a reference voltage VREF and output a second comparison voltage F_CM. Here, when binary data is transmitted using a ternary code, either the voltage of the first line Q1 or the voltage of the second line Q1 may be the reference voltage VREF. Also, the second comparison voltage F_CM may be a common mode voltage. Meanwhile, the second comparator 122 may be called a common mode detector (Q0+Q1) / 2).

[0032] In addition, the first comparator 121 and the second comparator 122 can be activated in response to a clock signal CLK.

[0033] The T-to-B decoder 124 may be implemented to receive the first comparison voltage F_DIFF and the second comparison voltage F_CM, and output corresponding binary data to the first data line D0 and the second data line D1.

[0034] Fig. 5 is a diagram illustrating an example of the T-to-B decoder 124 shown in Fig. 4. Referring to Fig. 5, the T-to-B decoder 124 may include inverters INV1 to INV4 and transistors T8 to T12.

[0035] The first inverter INV1 can receive the second comparison voltage V_CM and invert the second comparison voltage V_CM. The second inverter INV2 can invert the output value of the first inverter INV1 and transmit the inverted output value to the first data line D0. The third inverter INV3 can invert the first comparison voltage F_DIFF. The fourth inverter INV4 can invert the second comparison voltage F_CM.

[0036] The eighth transistor T8 may include a drain receiving the first comparison voltage F_DIFF, a source coupled to the second data line D1, and a gate receiving the second comparison voltage F_CM. The ninth transistor T9 may include a source receiving the first comparison voltage F_DIFF, a drain coupled to the second data line D1, and a gate receiving an output value of the fourth inverter INV4. The tenth transistor T10 may include a drain receiving an output value of the third inverter INV3, a source coupled to the second data line D1, and a gate receiving an output value of the fourth inverter INV4. The eleventh transistor T11 may include a source receiving an output value of the third inverter INV3, a drain coupled to the second data line D1, and a gate receiving the second comparison voltage F_CM. The twelfth transistor T12 may include a drain coupled to the second data line D1, a source coupled to the ground terminal GND, and a gate receiving a clock CLKB that is an inverted version of the clock CLK.

[0037] In an embodiment, each of the eighth, tenth, and twelfth transistors T8, T10, and T12 may include an n-channel metal-oxide-silicon (NMOS) field effect transistor (FET).

[0038] In an embodiment, each of the ninth and eleventh transistors T9 and T11 may include a p-channel metal-oxide-silicon (PMOS) field effect transistor (FET).

[0039] 6 is a diagram illustrating an example of a table related to a decoding process of the receiver 120 according to an embodiment of the present invention. Referring to FIG 6, a bit of a first data line D0 may be a value corresponding to a second comparison voltage F_CM, and a bit of a second data line D1 may be a result of an XNOR operation on the first comparison voltage F_DIFF and the second comparison voltage F_CM.

[0040] If the code value of the first line Q0 is "1" and the code value of the second line Q1 is "0", the value of the first comparison voltage F_DIFF is "0" and the value of the second comparison voltage F_CM is "1". Therefore, the decoded binary data is "10".

[0041] If the code value of the first line Q0 is "-1" and the code value of the second line Q1 is "0", the value of the first comparison voltage F_DIFF is "1" and the value of the second comparison voltage F_CM is "0". Therefore, the decoded binary data is "01".

[0042] If the code value of the first line Q0 is "0" and the code value of the second line Q1 is "1", the value of the first comparison voltage F_DIFF is "1" and the value of the second comparison voltage F_CM is "1". Therefore, the decoded binary data is "11".

[0043] If the code value of the first line Q0 is '0' and the code value of the second line Q1 is '-1', the value of the first comparison voltage F_DIFF is '0' and the value of the second comparison voltage F_CM is '0'. Therefore, the decoded binary data is '00'.

[0044] 7 is a flowchart illustrating an exemplary operation method of the transmitter 110 according to an embodiment of the present invention. Referring to FIGs. 1 to 7, the operation of the transmitter 110 may proceed as follows.

[0045] The transmitter 110 may receive binary data. The transmitter 110 may convert the received binary data into ternary data using a code map (S110). The converted ternary data may then be transmitted via two lines Q0 and Q1 (S120). Here, the code map may be set so that no toggling data occurs on either of the two lines Q0 and Q1.

[0046] In the data transmission method according to the embodiment of the present invention, when transmitting 2-bit binary data in a situation of transmitting serial data with 2 pins or more, the data is converted into ternary data (-1, 0, 1) and transmitted to 2-line in Return to Zero (RZ), and when both lines toggle, the data can be transmitted using the remaining state except when neither line toggles. Therefore, when transmitting RZ data by pair coding 2-line, the number of toggles can be reduced to half compared to the binary RZ method.

[0047] 8 is a flowchart illustrating an example of an operation method of the receiver 120 according to an embodiment of the present invention. Referring to FIGs. 1 to 8, the operation method of the receiver 120 may proceed as follows.

[0048] The receiver 120 can receive ternary data via two lines Q0 and Q1 (S210). The receiver 120 can convert the received ternary data into binary data using a code map (S220).

[0049] Meanwhile, the data transmission method according to the embodiment of the present invention can be used for internal data transmission in a dynamic random access memory (DRAM), for example, the data transmission method according to the present invention can be applied to GIO signaling in a DRAM.

[0050] 9 is a diagram illustrating a memory device according to another embodiment of the present invention. Referring to FIG. 9, the memory device 200 may include a memory cell array 210, a row decoder 220, a column decoder 230, a sense amplifier circuit 240, an address register 250, a bank control logic 252, a refresh counter 254, a row address multiplexer 256, a column address latch 258, a control logic 260, a timing control circuit 264, an input / output gating circuit 270, an error correction circuit 280, and a data input / output buffer 282.

[0051] The memory cell array 210 may include first to eighth bank arrays 211 to 218. However, it should be understood that the number of bank arrays constituting the memory cell array 210 is not limited to this.

[0052] The row decoder 220 may include first through eighth bank row decoders 221-228 connected to the first through eighth bank arrays 211-218, respectively. The column decoder 230 may include first through eighth bank column decoders 231-238 connected to the first through eighth bank arrays 211-218, respectively. The sense amplifier circuit 240 may include first through eighth bank sense amplifiers 241-248 connected to the first through eighth bank arrays 211-218, respectively.

[0053] Meanwhile, the first through eighth bank arrays 211-218, the first through eighth bank row decoders 221-228, the first through eighth bank column decoders 231-238, and the first through eighth bank sense amplifiers 241-248 may form first through eighth banks, respectively. Each of the first through eighth bank arrays 211-218 may include a plurality of memory cells MC formed at the intersections of word lines WL and bit lines BL.

[0054] The address register 250 can receive and store an address ADDR having a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from an external memory controller. The address register 250 can provide the received bank address BANK_ADDR to a bank control logic 252, the received row address ROW_ADDR to a row address multiplexer 256, and the received column address COL_ADDR to a column address latch 258.

[0055] The bank control logic 252 may generate a bank control signal in response to a bank address BANK_ADDR. Among the first through eighth bank row decoders 221-228, a bank row decoder corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal. Among the first through eighth bank column decoders 231-238, a bank column decoder corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0056] The row address multiplexer 256 may receive the row address ROW_ADDR from the address register 250 and the refresh row address REF_ADDR from the refresh counter 254. The row address multiplexer 256 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 256 may be applied to the first through eighth bank row decoders 221-228, respectively.

[0057] Among the first through eighth bank row decoders 221-228, a bank row decoder activated by the bank control logic 252 may decode a row address RA output from the row address multiplexer 256 to activate a word line corresponding to the row address. For example, the activated bank row decoder may apply a word line driving voltage to a word line corresponding to the row address.

[0058] The column address latch 258 may receive the column address COL_ADDR from the address register 250 and temporarily store the received column address COL_ADDR. Also, the column address latch 258 may gradually increase the received column address COL_ADDR in a burst mode. The column address latch 258 may apply the temporarily stored or gradually increased column address COL_ADDR to the first through eighth bank column decoders 231-238, respectively.

[0059] Of the first through eighth bank column decoders 231-238, the bank column decoder activated by the bank control logic 252 can activate, via the input / output gating circuit 270, a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR.

[0060] Each of the input / output gating circuits of the input / output gating circuit 270 may include, together with a circuit for gating input / output data, an input data mask logic, a read data latch for storing data output from the first through eighth bank arrays 211-228, and a write driver for writing data to the first through eighth bank arrays 211-218. Also, the input / output gating circuit 270 may be realized by the data transmission device 100 and the data transmission method thereof shown in FIGS. 1 through 6.

[0061] A codeword (CW) read from one of the first through eighth bank arrays 211-218 may be sensed by a sense amplifier corresponding to one of the bank arrays and stored in a read data latch. The codeword CW stored in the read data latch may be ECC decoded by an error correction circuit 280 and then provided to a memory controller via a data input / output buffer 282. Data DQ to be written to one of the first through eighth bank arrays 210-218 may be ECC encoded by the error correction circuit 280 and then written to one of the bank arrays via a write driver.

[0062] In a write operation, the data input / output buffer 282 provides data DQ to the error correction circuit 280 based on a clock signal CLK provided from the memory controller, and in a read operation, the data input / output buffer 282 can provide data DQ provided from the error correction circuit 280 to the memory controller.

[0063] In a write operation, the error correction circuit 280 generates a parity bit based on the data bits of the data DQ provided from the data input / output buffer 282, and provides a code word CW including the data DQ and the parity bit to the input / output gating circuit 270, which can write the code word CW to the bank array.

[0064] In addition, in a read operation, the error correction circuit 280 may receive a codeword CW read from one bank array from the input / output gating circuit 270. The error correction circuit 280 may perform ECC decoding on the data DQ using a parity bit included in the read codeword CW to correct at least one error bit included in the data DQ, and provide the corrected data to the data input / output buffer 282.

[0065] The control logic circuit 260 may be implemented to control the operation of the memory device 200. For example, the control logic circuit 260 may generate control signals to cause the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 260 may include a command decoder 261 that decodes a command CMD received from a memory controller and a mode register 262 that sets an operation mode of the memory device 200.

[0066] For example, the command decoder 261 may generate operation control signals ACT, PCH, WE, and RD corresponding to the command CMD by decoding a write enable signal / WE, a row address strobe signal / RAS, a column address strobe signal / CAS, a chip select signal / CS, etc. The control logic circuit 260 may provide the operation control signals ACT, PCH, WE, and RD to the timing control circuit 264. The control signals ACT, PCH, WR, and RD may include an active signal ACT, a precharge signal PCH, a write signal WR, and a read signal RD. The timing control circuit 264 may generate a first control signal CTL1 for controlling a voltage level of a word line WL and a second control signal CTL2 for controlling a voltage level of a bit line BL in response to the operation control signals ACT, PCH, WR, and RD, and provide the first control signal CTL1 and the second control signal CTL2 to the memory cell array 210.

[0067] Figure 10 is a more detailed diagram of a portion of the bank array shown in Figure 9. Referring to Figures 9 and 10, the portion of the bank array may include a sub-array block SCB, a bit line sense amplifier region BLSA, a sub-word line driver region SWB, and a conjunction region CONJ.

[0068] The sub-array block SCB may include a plurality of word lines WL1-WL4 extending in a row direction (first direction) and a plurality of bit line pairs BL1-BL2, BLB1-BLB2 extending in a column direction (second direction). The sub-array block SCB may include memory cells MC arranged at points where the plurality of word lines WL1-WL4 and the plurality of bit line pairs BL1-BL2, BLB1-BLB2 intersect.

[0069] The sub-word line driver region SWB may include sub-word line drivers SWD for driving the word lines WL1 to WL4, respectively. The sub-word line drivers SWD may be alternately arranged on the left and right sides of the sub-array block SCB.

[0070] The bit line sense amplifier region BLSAB may include a bit line sense amplifier BLSA connected to the bit line pairs BL1-BL2, BLB1-BLB2 and a local sense amplifier circuit LSA. The bit line sense amplifier BLSA may amplify a voltage level difference sensed by the bit line pair BL, BLB and provide the amplified voltage level difference to the local I / O line pair LIO, LIOB. The local sense amplifier circuit LSA may control a connection between the local I / O line pair LIO1, LIOB1 and the global I / O line pair GIO1, GIOB1 in response to a gate enable signal GEN1 and a local control signal LCTL.

[0071] The local sense amplifier circuit LSA can control the connection between the local I / O line pair LIO2, LIOB2 and the global I / O line pair GIO2, GIOB2 in response to corresponding gate enable signals and local control signals.

[0072] In an embodiment, as shown in FIG. 8, the bit line sense amplifiers BLSA may be alternately arranged above and below the sub-array block SCB. In an embodiment, a junction region CONJ may be arranged adjacent to the bit line sense amplifier region BLSAB, the sub-word line driver region SWB, and the sub-array block SCB. A block control circuit may be arranged in the junction region CONJ. The block control circuit may provide a gate enable signal GEN1 to the local sense amplifier circuit LSA in response to an enable signal EN1 and a selection signal SEL1. The local sense amplifier circuit LSA may selectively provide or block a connection to the global input / output line pair GIO1, GIOB1 in response to the gate enable signal GEN1.

[0073] On the other hand, while FIG. 10 shows a bank array portion in a folded bit line structure, the explanation with reference to FIG. 10 can be applied substantially similarly to an open bit line structure.

[0074] Figure 11 is a diagram illustrating an example of the bit line sense amplifier BLSA shown in Figure 10. Referring to Figure 11, a bit line sense amplifier 650 may be connected to the bit lines BL and BLB of memory cells 660 and 670 included in the memory cell array. The bit line sense amplifier 650 may include an N sense amplifier 651, a P sense amplifier 652, a precharge circuit 653, column selection switches 654a and 654b, an NSA driver 655, and a PSA driver 656.

[0075] The N sense amplifier 651 can discharge the bit line having a lower potential among the bit lines BL and BLB during a sensing operation. The N sense amplifier 651 can include NMOS transistors NM1 and NM2. The gate of the NMOS transistor NM1 can be connected to the bit line BLB, the drain of the NMOS transistor NM1 can be connected to the bit line BL, and the source of the NMOS transistor NM1 can be connected to the sense enable line LAB. The gate of the NMOS transistor NM2 can be connected to the bit line BL, the drain of the NMOS transistor NM2 can be connected to the bit line BLB, and the source of the NMOS transistor NM2 can be connected to the sense enable line LAB.

[0076] The N sense amplifier 651 can discharge a low potential bit line by a ground voltage VSS provided to a sense enable line LAB. The low potential bit line can be one of the bit lines BL and BLB depending on the data stored in the memory cells 660 and 670.

[0077] The P sense amplifier 652 may charge the higher potential bit line of the bit lines BL and BLB to a power supply voltage VDD level during a sensing operation. The P sense amplifier 652 may include PMOS transistors PM1 and PM2. The gate of the PMOS transistor PM1 may be connected to the bit line BLB, the source of the PMOS transistor PM1 may be connected to the bit line BL, and the drain of the PMOS transistor PM1 may be connected to a sense enable line LA. The gate of the PMOS transistor PM2 may be connected to the bit line BL, the source of the PMOS transistor PM2 may be connected to the bit line BLB, and the drain of the PMOS transistor PM2 may be connected to the sense enable line LA.

[0078] The P sense amplifier 652 can charge the bit line having a higher potential among the bit lines BL and BLB with a power supply voltage VDD provided to a sense enable line LA. At this time, the sense enable line LA can be provided with a charging voltage VDD provided from the PSA driver 656. Therefore, the transistor PM2 having a gate connected to the bit line BL whose voltage increases due to charge sharing can be turned off.

[0079] Fig. 12 is a diagram illustrating an example of the local sense amplifier circuit LSA shown in Fig. 11. Referring to Fig. 12, the local sense amplifier circuit 700 may include a local sense amplifier 710, a local input / output line controller 720, and an activation control circuit 730.

[0080] The activation control circuit 730 may output the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 by performing an XOR operation with the gate enable signal GEN1 for each of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2. Therefore, the logic levels of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 may be maintained or inverted according to the logic level of the gate enable signal GEN1, and may be provided as the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4. The activation control circuit 730 may include first to third XOR gates 731, 732, and 733.

[0081] The local sense amplifier 710 may amplify a voltage difference between the local I / O line pair LIO1, LIOB1 in response to a second local sense enable signal PLSAEN2, and transmit data corresponding to the amplified voltage difference to the global I / O line pair GIO1, GIOB1.

[0082] The local I / O line controller 720 includes first to fourth NMOS transistors 721, 722, 723, and 724, and can control the connection between the local I / O line pair LIO1, LIOB1 and the global I / O line pair GIO1, GIOB1 in response to a third connection control signal PMUXON3 and a fourth connection control signal PMUXON4.

[0083] In an embodiment, when the first local sense enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 are at a high level and the gate enable signal GEN1 is at a high level, the second local sense enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 may each have a low level. Thus, the local sense amplifier 710 is deactivated and the local I / O line controller 720 may cut off the connection between the local I / O line pair LIO1, LIOB1 and the global I / O line pair GIO1, GIOB1.

[0084] In an embodiment, when the first local sense enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 are at a high level and the gate enable signal GEN1 is at a low level, the second local sense enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 may each have a high level. Thus, the local sense amplifier 710 is activated and the local I / O line controller 720 may provide a connection between the local I / O line pair LIO1, LIOB1 and the global I / O line pair GIO1, GIOB1.

[0085] Meanwhile, the data transmission method of the present invention is applicable to data transmitted through a global input / output line. 2-GIO can be ternary coded and represented in 2 bits. This is called a multi-level single global input / output line (multi-level single GIO).

[0086] 13 is a diagram illustrating an example of ternary data transmitted to global I / O lines GIO0 and GIO1 according to an embodiment of the present invention. Referring to FIG. 13, binary data "11" can be expressed as the first global I / O line GIO0 having a gradually increasing level and the second global I / O line GIO1 maintaining a constant level. Binary data "10" can be expressed as the first global I / O line GIO0 maintaining a constant level and the second global I / O line GIO1 having a gradually increasing level. Binary data "01" can be expressed as the first global I / O line GIO0 having a gradually decreasing level and the second global I / O line GIO1 maintaining a constant level. Binary data "00" can be expressed as the first global I / O line GIO0 maintaining a constant level and the second global I / O line GIO1 having a gradually decreasing level.

[0087] As shown in FIG. 13, a voltage difference GIO between a first global I / O line GIO0 and a second global I / O line GIO1 can be used to distinguish data.

[0088] Meanwhile, as shown in FIG. 13, either the first global I / O line GIO0 or the second global I / O line GIO1 is always non-toggled.

[0089] Fig. 14 is a diagram illustrating an example of a transmitter 272 for global input / output line signaling according to an embodiment of the present invention. Referring to Fig. 14, the transmitter 272 may be realized similarly to the transmitter 110 illustrated in Fig. 3. In Fig. 14, unlike Fig. 3, the binary data is local input / output data LIO0, LIO2, and ternary data corresponding to the local input / output data may be provided to global input / output lines GIO_0, GIO_2.

[0090] The transmitter 272 according to an embodiment of the present invention includes a first transistor T1 having a drain connected to a power supply terminal VDD and a gate connected to a first local I / O line LIO0, a second transistor T2 having a drain connected to a source of the first transistor T1 and a gate connected to an inverted line LIO0B for the first local I / O line LIO0, a third transistor T3 having a drain connected to the source of the second transistor T2, a source connected to a ground terminal GND, and a gate receiving a local sense amplification enable signal LSA_EN, a drain connected to the source of the first transistor T1, and an inverted line LIO2B for the second local I / O line LIO2. B; a fifth transistor T5 having a drain connected to the source of the fourth transistor T4, a source connected to the first global I / O line GIO_0, and a gate receiving a local sense amplification activation signal LSA_EN; a sixth transistor T2 having a drain connected to the source of the first transistor T1 and a gate connected to the second local I / O line LIO2; and a seventh transistor T7 having a drain connected to the source of the sixth transistor T6, a source connected to the second global I / O line GIO_2, and a gate receiving a local sense amplification activation signal LSA_EN.

[0091] In the embodiment, each of the first to seventh transistors T1 to T7 may include an NMOS transistor.

[0092] In an embodiment, the transmitter 272 may further include a first switch SW1 that provides a global input / output line pre-charge voltage VGIOPRE to the first global input / output line GIO_0 and a second switch SW2 that provides the global input / output line pre-charge voltage VGIOPRE to the second global input / output line GIO_2.

[0093] Figure 15 is a diagram illustrating an example of a receiver 274 for global I / O line signaling according to an embodiment of the present invention. Referring to Figure 15, the receiver may be implemented similarly to the receiver 120 illustrated in Figure 4. In Figure 15, unlike Figure 4, the receiver 274 receives ternary data from the global I / O lines GIO_0 and GIO_2, performs a comparison operation in response to an I / O sense amplifier activation signal IOSA_EN, and outputs binary data according to the result.

[0094] The receiver 274 may include a differential comparator 274-1 that compares a first voltage of the first global I / O line GIO_0 with a second voltage of the second global I / O line GIO_2 in response to an I / O sense amplification activation signal IOSA_EN, a common mode detector 274-2 that compares a common voltage of the first and second voltages with a reference voltage in response to the I / O sense amplification activation signal IOSA_EN, and a decoder 274-4 that receives a first output value IOSA_DIFF of the differential comparator 274-1 and a second output value IOSA_LVL of the common mode detector 274-2 and outputs a first bit B_LIO0, D0 and a second bit B_LIO2, D1 for the first and second local I / O lines LIO0, LIO2.

[0095] In an embodiment, the decoder 274-4 can output a first bit B_LIO0 and a second bit B_LIO2 corresponding to the second output value IOSA_LVL by performing an XNOR operation on the first output value IOSA_DIFF and the second output value IOSA_LVL.

[0096] 16 is a diagram illustrating a decoding table for global input / output lines according to an embodiment of the present invention. Referring to FIG. 16, a first data bit D 0 The second data D may be a result of an XNOR operation on the first comparison voltage F_DIFF and the second comparison voltage F_CM. 1 may be a value corresponding to the second comparison voltage F_CM.

[0097] If the code value of the first line Q0 is "1" and the code value of the second line Q1 is "0", the value of the first comparison voltage F_DIFF is "0" and the value of the second comparison voltage F_CM is "1". Therefore, the decoded binary data is "10".

[0098] If the code value of the first line Q0 is "-1" and the code value of the second line Q1 is "0", the value of the first comparison voltage F_DIFF is "1" and the value of the second comparison voltage F_CM is "0". Therefore, the decoded binary data is "01".

[0099] If the code value of the first line Q0 is "0" and the code value of the second line Q1 is "1", the value of the first comparison voltage F_DIFF is "1" and the value of the second comparison voltage F_CM is "1". Therefore, the decoded binary data is "11".

[0100] If the code value of the first line Q0 is '0' and the code value of the second line Q1 is '-1', the value of the first comparison voltage F_DIFF is '0' and the value of the second comparison voltage F_CM is '0'. Therefore, the decoded binary data is '00'.

[0101] The multi-level single-GIO according to the embodiment of the present invention can reduce the number of data transmission lines by ternary coding 2-GIO and expressing it in 2-bit. Also, one multi-level single-GIO according to the embodiment of the present invention can reduce current consumption by always non-toggle one transmission line.

[0102] Figures 17a, 17b, 17c, and 17d illustrate embodiments of code maps in accordance with embodiments of the present invention. Referring to Figures 17a, 17b, 17c, and 17d, there are 16 possible cases associated with mapping ternary data to binary data.

[0103] The first case corresponds to the code maps described in Figures 2 to 6. The ternary data transmitted on the two lines Q0 and Q1 corresponding to the binary data "11" are "0" and "1", the ternary data transmitted on the two lines Q0 and Q1 corresponding to the binary data "10" are "1" and "0", the ternary data transmitted on the two lines Q0 and Q1 corresponding to the binary data "01" are "-1" and "0", and the ternary data transmitted on the two lines Q0 and Q1 corresponding to the binary data "00" are "0" and "-1".

[0104] In the second case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "0" and "1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "0" and "-1", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "-1" and "0".

[0105] In the third case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "0" and "1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "-1" and "0", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "0" and "-1".

[0106] In the fourth case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "0" and "1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "0" and "-1", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "-1" and "0".

[0107] In the fifth case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "-1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "0" and "-1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "1" and "0", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "-1" and "0".

[0108] In the sixth case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "0" and "-1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "-1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "1" and "0", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "0" and "1".

[0109] In the seventh case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "-1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "0" and "-1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "0" and "1", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "1" and "0".

[0110] In the eighth case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "0" and "-1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "-1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "0" and "1", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "1" and "0".

[0111] In the ninth case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "-1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "0" and "1", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "0" and "-1".

[0112] In the tenth case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "-1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "0" and "1", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "0" and "-1".

[0113] In the 11th case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "-1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "0" and "-1", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "0" and "1".

[0114] In the 12th case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "-1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "1" and "0", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "0" and "-1", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "0" and "1".

[0115] In the thirteenth case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "0" and "1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "0" and "-1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "1" and "0", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "-1" and "0".

[0116] In the 14th case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "0" and "1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "0" and "-1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "-1" and "0", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "1" and "0".

[0117] In the 15th case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "0" and "-1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "0" and "1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "1" and "0", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "-1" and "0".

[0118] In the 16th case, the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "11" is "0" and "-1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "10" is "0" and "1", the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "01" is "-1" and "0", and the ternary data transmitted on each of the two lines Q0, Q1 corresponding to the binary data "00" is "1" and "0".

[0119] Furthermore, the logic circuit constituting the decoder of the receiver may include a first logic circuit that outputs the first data bit D0 and a second logic circuit that outputs the second data bit D1. Here, the first logic circuit may include an INV (inverter) operator, and the second logic circuit may include an XOR operator, an XNOR operator, or an INV operator.

[0120] On the other hand, the data reception method in each case can have the effect of improving power efficiency by a factor of two by halving current consumption when maintaining the same Signal-VREF at the receiver Rx, compared to the pseudo differential or single-ended method.

[0121] On the other hand, the memory device according to the embodiment of the present invention is applicable to mobile devices.

[0122] 18 is a diagram illustrating a mobile device 3000 according to an embodiment of the present invention. Referring to FIG. 18, the mobile device 3000 may include an application processor 3100, at least one DRAM 3200, at least one storage device 3300, at least one sensor 3300, a display device 3400, an audio device 3500, a network processor 3600, and at least one input / output device 3700. For example, the mobile device 3000 may be realized as a laptop computer, a mobile phone, a smart phone, a tablet personal computer, or a wearable computer.

[0123] The application processor 3100 may be implemented to control the overall operation of the mobile device 3000. The application processor 3100 may execute applications that provide an Internet browser, games, videos, and the like. In an embodiment, the application processor 3100 may include a single core or a multi-core. For example, the application processor 3100 may include a multi-core such as a dual-core, a quad-core, a hexa-core, and the like. In an embodiment, the application processor 3100 may further include a cache memory located internally or externally.

[0124] The application processor 3100 may include a controller 3110, an NPU (Neural Processing Unit (artificial intelligence processor)) 3120, and an interface 3130. In an embodiment, the NPU 3120 may be provided as an option.

[0125] In an embodiment, the application processor 3100 may be realized as a system-on-chip (SoC). A kernel of an operating system operated by the system-on-chip (SoC) may include an I / O scheduler and a device driver for controlling the storage device 3300. The device driver may control the access performance of the storage device 3300 by referring to the number of synchronous queues managed by the I / O scheduler, or may control a CPU mode, a DVFS level, etc. within the SoC.

[0126] The DRAM 3210 may be coupled to the controller 3110. The DRAM 3210 may store data necessary for the operation of the application processor 3100. For example, the DRAM 3210 may temporarily store an operating system (OS) and application data, or may be used as an execution space for various software codes.

[0127] The DRAMs 3210 and 3220 may be implemented to convert binary data into ternary data and transmit the data on 2-line as described in FIG. 1 through FIG. 17. The DRAM 3210 has a relatively faster latency and BW than an I / O device or a flash memory. The DRAM 3210 is initialized at the time of mobile power-on, and the OS and application data are loaded into the DRAM 3210 to be used as a temporary storage location for the OS and application data, or as an execution space for various software codes. The mobile system performs a multitasking operation to simultaneously load multiple applications, and switching between applications and execution speed can be used as a performance index of the mobile system. The DRAM 3220 may be connected to the NPU 3120. The DRAM 3220 may store data related to artificial intelligence calculations.

[0128] The storage device 3300 may be coupled to the interface 3130. In an embodiment, the interface 3130 may operate according to any one of the following communication protocols: DDR, DDR2, DDR3, DDR4, low power DDR (LPDDR), universal serial bus (USB), multimedia card (MMC), embedded MMC, peripheral component interconnection (PCI), non-volatile memory express (NVMe), peripheral component interconnect express (PCIe), serial at attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), universal storage bus (USB) attached SCSI (UAS), internet small computer system interface (iSCSI), Fiber Channel, and fiber channel over ethernet (FCoE). In an embodiment, any one of the storage devices 3000 may be included in the mobile device 3000 in an embedded form. In another embodiment, any one of the storage devices 3000 may be included in the mobile device 3000 in a removable manner.

[0129] The storage device 3300 may be implemented to store user data. For example, the storage device 3300 may store data collected from the sensor 3400, or may store network data, Augmented Reality (AR) / Virtual Reality (VR) data, and High Definition (HD) 4K content. The storage device 3300 may include at least one non-volatile memory device. For example, the storage device 3300 may include a Solid State Drive (SSD), an embedded Multimedia Card (eMMC), etc.

[0130] In an embodiment, the storage device 3300 may be implemented as a separate chip to the application processor 3100 or implemented together with the application processor 3100 in one package.

[0131] In an embodiment, the storage device 3300 may be implemented using various types of packages. For example, the storage device 3300 may be implemented using a package such as a PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), etc.

[0132] The sensor 3300 may be implemented to sense the external environment of the mobile device 3000. In an embodiment, the sensor 3300 may include an image sensor that senses an image. In this case, the sensor 3300 may transmit the generated image information to the application processor 3100. In another embodiment, the sensor 3300 may include a biosensor that senses biometric information. For example, the sensor 3300 may sense a fingerprint, an iris pattern, a blood vessel pattern, a heart rate, blood sugar, etc., and generate sensing data corresponding to the sensed information. Meanwhile, it should be understood that the sensor 3300 is not limited to an image sensor or a biosensor. The sensor 3300 of the present invention may include any sensor such as an illuminance sensor, an acoustic sensor, an acceleration sensor, etc.

[0133] The display device 3500 may be implemented to output data. For example, the display device 3500 may output image data sensed by the sensor 3300 or data calculated by the application processor 3100.

[0134] The audio device 3600 may be implemented to output audio data externally or to sense external audio.

[0135] The network processor 3700 can be implemented to communicate with external devices via wired or wireless communication.

[0136] The input / output device 3800 may be implemented to input data to the mobile device 3000 or output data from the mobile device 3000. The input / output device 3800 may include devices that provide digital input and output functions, such as a USB, storage, a digital camera, an SD card, a touch screen, a DVD, a modem, and a network adapter.

[0137] A mobile device 3000 according to an embodiment of the present invention can enable low current and low power by transmitting multi-level data such that they are not toggled simultaneously.

[0138] Meanwhile, in Fig. 1 to Fig. 18, the data transmission apparatus and method transmit the ternary code via two lines. However, the present invention is not necessarily limited to this. The data transmission apparatus and method of the present invention can also transmit the ternary code via three lines.

[0139] 1 to 18, a method of converting binary data into ternary data and transmitting the converted data is described. However, the present invention is not limited to this. The present invention can be extended to a method of converting binary data into multi-level data in addition to ternary data and transmitting the converted data.

[0140] The above-mentioned contents of the present invention are merely specific embodiments for carrying out the invention. The present invention includes not only specific and practical means itself, but also technical ideas that are abstract and conceptual ideas that can be utilized as future technologies. [Explanation of symbols]

[0141] 100 Data transmission device 110, 272 Transmitter 114 Encoder 120, 274 Receiver 121 First comparator 122 Second comparator 124 Decoder 200 Memory Device

Claims

1. Only the first and second lines; a transmitter realized to convert received 2-bit binary data into two ternary data and output each bit of the ternary data to the first and second lines as a logical value in a group consisting of "-1" corresponding to a first voltage level, "0" corresponding to a second voltage level, and "1" corresponding to a third voltage level, and configured to provide the logical value of "-1" or "1" by toggling only one of the first and second lines during each of consecutive 2-bit data transmission time periods; a receiver implemented to convert the ternary data received from the first and second lines into binary data; A data transmission device in which the toggling is realized by the transmitter simultaneously transmitting the first ternary data of the two ternary data obtained by the conversion on the first line and the second ternary data on the second line in a return-to-zero (RZ) format.

2. the first voltage level is lower than the second voltage level; 2. The data transmission device of claim 1, wherein the second voltage level is lower than the third voltage level.

3. 2. The data transmission device of claim 1, wherein the receiver is implemented to convert the four combinations of the ternary data into respective ones of the following logic state pairs: (0,0), (0,1), (1,0), and (1,1).

4. A method for transmitting data in a data transmission device, comprising: the data transmission device includes only first and second signal lines, and the method comprises: converting two consecutive bits of the sequentially received binary data into two ternary data; outputting each bit of the ternary data as a logical value from a group consisting of "-1" corresponding to a first voltage level, "0" corresponding to a second voltage level, and "1" corresponding to a third voltage level to the first and second signal lines, toggling only one of the first and second signal lines during each of successive 2-bit data transmission time periods to provide the logical value of "-1" or "1"; decoding the ternary data received from the first and second signal lines into binary data; the ternary data is provided to the first and second signal lines using a return-to-zero toggling operation; The toggling operation is realized by simultaneously transmitting a first ternary data of the two ternary data obtained by the conversion on the first signal line and a second ternary data on the second signal line in the return-to-zero manner.

5. 5. The method of claim 4, wherein during each of the 2-bit data transmission time intervals, a first one of the first and second signal lines is driven at a logic state of "+1" or "-1" and a second one of the first and second signal lines is driven at a reference logic state.

6. 6. The method of claim 4 or 5, wherein during the decoding, the four combinations of the ternary data are converted into respective ones of the following logic state pairs: (0,0), (0,1), (1,0), and (1,1).

7. the first voltage level is lower than the second voltage level; the third voltage level is greater than the second voltage level; 2. The data transmission device according to claim 1, wherein the second voltage level is a reference voltage level.

8. The transmitter includes:

2. The data transmission apparatus of claim 1, further comprising an encoder for receiving the 2-bit binary data and encoding the received 2-bit binary data into the two ternary data.

9. The transmitter includes: a first transistor having a drain coupled to a power supply and a gate for receiving a first bit of the binary data; a second transistor having a drain connected to the source of the first transistor and a gate receiving an inverse bit of the first bit; a third transistor having a drain connected to the source of the second transistor, a source connected to a ground terminal, and a gate receiving an activation signal; a fourth transistor having a drain coupled to the source of the first transistor and a gate receiving an inverse bit of the second bit of the binary data; a fifth transistor having a drain connected to the source of the fourth transistor, a source connected to the first line, and a gate receiving the activation signal; a sixth transistor having a drain coupled to the source of the first transistor and a gate receiving the second bit; a seventh transistor having a drain coupled to the source of the sixth transistor, a source coupled to the second line, and a gate receiving the activation signal.

10. The transmitter includes: a first switch responsive to a precharge signal for providing a precharge voltage to the first line; 10. The data transmission device of claim 9, further comprising a second switch responsive to the precharge signal to provide the precharge voltage to the second line.

11. The receiver includes: a first comparator responsive to a clock signal for comparing the voltage on the first line with the voltage on the second line; a second comparator responsive to the clock signal for comparing a common voltage of the first line and the second line with a reference voltage; 2. The data transmission device of claim 1, further comprising a decoder receiving the first comparison voltage of the first comparator and the second comparison voltage of the second comparator, and outputting the first bit and the second bit of the binary data.

12. 12. The data transmission device according to claim 11, wherein the decoder outputs the first bit by performing an operation on the first comparison voltage and the second comparison voltage.

13. The decoder comprises: a first inverter connected to an output terminal of the second comparator and inverting the second comparison voltage; a second inverter that inverts an output value of the first inverter and outputs the second bit; a third inverter connected to an output terminal of the first comparator and inverting the first comparison voltage; a fourth inverter connected to an output terminal of the second comparator and inverting the second comparison voltage; an eighth transistor having a drain connected to the output terminal of the first comparator, a source connected to a first data line, and a gate receiving the second comparison voltage; a ninth transistor having a source connected to the output terminal of the first comparator, a drain connected to the first data line, and a gate connected to the output terminal of the fourth inverter; a tenth transistor having a drain connected to the output terminal of the third inverter, a source connected to the first data line, and a gate connected to the output terminal of the fourth inverter; an eleventh transistor having a source connected to the output terminal of the third inverter, a drain connected to the first data line, and a gate receiving the second comparison voltage; a twelfth transistor having a drain coupled to the first data line, a source coupled to a ground terminal, and a gate receiving an inverted signal of the clock signal.

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