Semiconductor Device

Abstract

This semiconductor device is provided with at least one semiconductor element having a switching function, an electrical conduction member providing a path for a current switched by the semiconductor element and made of a first material, and a coating layer covering at least a part of the electrical conduction member and made of a second material. The second material satisfies at least one of the following three requirements: (a) has a magnetic permeability higher than that of the first material; (b) has an electrical resistivity higher than that of the first material; and (c) has a dielectric tangent greater than zero.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device including a semiconductor element. [Background technology]

[0002] Patent Document 1 discloses a conventional semiconductor device. The semiconductor device described in Patent Document 1 includes a semiconductor element, an island, leads, a plurality of bonding materials, a connection plate, and a sealing resin. In this semiconductor device, the semiconductor element is, for example, a transistor such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-204863 A Summary of the Invention [Problem to be solved by the invention]

[0004] When a semiconductor device is energized, a main circuit current that is switched by a semiconductor element flows through the islands and leads. The faster the switching speed, the more likely ringing occurs in the main circuit current. This ringing can cause electromagnetic interference noise that adversely affects the operation of surrounding equipment, for example.

[0005] In view of the above problems, an object of the present disclosure is to provide a semiconductor device capable of suppressing ringing. [Means for solving the problem]

[0006] The semiconductor device provided by the present disclosure includes at least one semiconductor element having a switching function, a conductive member made of a first material that serves as a path for a current switched by the semiconductor element, and a covering layer made of a second material that covers at least a part of the conductive member. The second material satisfies at least one of the following three requirements: (a) a magnetic permeability higher than that of the first material, (b) an electrical resistivity higher than that of the first material, and (c) a dielectric loss tangent greater than 0.

[0007] Preferably, the second material is a magnetic conductor having a higher magnetic permeability than the first material and a higher electrical resistivity than the first material.

[0008] Preferably, the second material has a dielectric loss tangent greater than zero.

[0009] Preferably, the second material has a higher magnetic permeability and a dielectric loss tangent greater than 0 than the first material.

[0010] Preferably, the second material has a higher electrical resistivity and a dielectric loss tangent greater than 0 than the first material.

[0011] Preferably, the coating layer has a thickness of 1 μm to 5 μm.

[0012] Preferably, the second material has a relative magnetic permeability of 10 or more.

[0013] Preferably, the electrical resistivity of the second material is at least twice the electrical resistivity of the first material.

[0014] Preferably, the second material has a dielectric loss tangent of 0.01 or more.

[0015] Preferably, the semiconductor device according to the present disclosure further includes a capacitor having a first end and a second end for electrical connection. The at least one semiconductor element is a plurality of semiconductor elements constituting a half bridge including at least one pair of upper and lower arms, and the plurality of semiconductor elements includes a first semiconductor element included in the upper arm and a second semiconductor element included in the lower arm. The conductive member includes a first metal layer connected to a drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to a source electrode of the second semiconductor element. The first end of the capacitor is connected to the first power lead, and the second end of the capacitor is connected to the second power lead. The covering layer includes a first portion covering the first power lead and a second portion covering the second power lead.

[0016] Preferably, the first power lead includes a portion that constitutes a path between the first semiconductor element and the capacitor, and this portion of the first power lead is not covered by the first portion.

[0017] Preferably, the second power lead includes a portion that constitutes a path between the second semiconductor element and the capacitor, and this portion of the second power lead is not covered by the second portion.

[0018] Preferably, the covering layer includes a third portion covering the first metal layer.

[0019] Preferably, the conductive member includes a second metal layer connected to the drain electrode of the second semiconductor element and a third power lead connected to the second metal layer, and the second metal layer and the third power lead are not covered by the covering layer.

[0020] Preferably, the conductive member includes an intermediate lead connected to a source electrode of the first semiconductor element and the second metal layer, and the intermediate lead is not covered by the covering layer.

[0021] Preferably, the conductive member includes a first spacer interposed between the first metal layer and the first power lead, and the covering layer includes a fourth portion covering the first spacer.

[0022] Preferably, the conductive member includes a conductor interposed between a source electrode of the second semiconductor element and the second power lead.

[0023] Preferably, the semiconductor element is any one of a SiC MOSET, a SiC IGBT, a Si MOSFET, a Si IGBT, and a GaN HEMT. Effect of the Invention

[0024] According to the present disclosure, in a semiconductor device, it is possible to suppress ringing, and it is possible to simplify the snubber circuit and improve its reliability. [Brief description of the drawings]

[0025] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment. [Diagram 2] 1 is a perspective view showing a main part of a semiconductor device according to a first embodiment; [Diagram 3] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 4] 4 is a plan view of FIG. 3 in which the sealing resin is indicated by imaginary lines. [Diagram 5] FIG. 5 is a partially enlarged plan view of a part of FIG. [Figure 6] FIG. 1 is a front view showing a semiconductor device according to a first embodiment. [Figure 7] FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment. [Figure 8] FIG. 1 is a left side view showing a semiconductor device according to a first embodiment. [Figure 9] FIG. 2 is a right side view showing the semiconductor device according to the first embodiment. [Figure 10] FIG. 5 is a cross-sectional view taken along line XX in FIG. [Figure 11] 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 4 is a cross-sectional view showing a first modified example of the semiconductor device in accordance with the first embodiment. [Figure 13] FIG. 4 is a cross-sectional view showing a second modified example of the semiconductor device in accordance with the first embodiment. [Figure 14] FIG. 11 is a perspective view showing a main part of a semiconductor device according to a second embodiment. [Figure 15] FIG. 11 is a plan view showing a semiconductor device according to a second embodiment. [Figure 16] 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15. [Figure 17] FIG. 11 is a perspective view showing a main part of a semiconductor device according to a third embodiment. [Figure 18] FIG. 13 is a plan view showing a semiconductor device according to a third embodiment. [Figure 19] 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. [Figure 20] FIG. 13 is a plan view showing a semiconductor device according to a fourth embodiment. [Figure 21] FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings.

[0027] 1 to 11 show a semiconductor device according to a first embodiment. The semiconductor device A1 of the first embodiment includes a plurality of semiconductor elements 10, a support substrate 20, a plurality of leads, a plurality of intermediate leads 40, a plurality of wire members 50, a plurality of conductive blocks 60, a sealing resin 70, a capacitor 81, and a coating layer 90. The plurality of leads include a first power lead 31, a second power lead 32, a third power lead 33, a pair of gate leads 34A, 34B, a pair of driver source leads 35A, 35B, and a plurality of dummy leads 36. The plurality of conductive blocks 60 include a plurality of first blocks 61 and a plurality of second blocks 62.

[0028] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a perspective view of FIG. 1 with the sealing resin 70 omitted. In FIG. 2, a plurality of wire members 50 are omitted. FIG. 3 is a plan view showing the semiconductor device A1. FIG. 4 is a plan view of FIG. 3 with the sealing resin 70 shown by imaginary lines (two-dot chain lines). FIG. 5 is a partially enlarged view of FIG. 4. FIG. 6 is a front view showing the semiconductor device A1. FIG. 7 is a bottom view showing the semiconductor device A1. FIG. 8 is a left side view showing the semiconductor device A1. FIG. 9 is a right side view showing the semiconductor device A1. FIG. 10 is a cross-sectional view taken along the line XX in FIG. 4. FIG. 11 is a cross-sectional view taken along the line XI-XI in FIG. 10. In FIG. 1 to FIG. 8, for ease of understanding, a plurality of discrete points are drawn on the coating layer 90.

[0029] In the following description, three mutually orthogonal directions (x direction, y direction, z direction) will be referred to as appropriate. The z direction corresponds to the thickness direction of the semiconductor device A1. The x direction corresponds to the left-right direction in the plan view of the semiconductor device A1 (see Figures 3 and 4). The y direction corresponds to the up-down direction in the plan view of the semiconductor device A1 (see Figures 3 and 4). Where necessary, one of the x directions will be referred to as the x1 direction and the other of the x directions will be referred to as the x2 direction. Similarly, one of the y directions will be referred to as the y1 direction and the other of the y directions will be referred to as the y2 direction, one of the z directions will be referred to as the z1 direction and the other of the z directions will be referred to as the z2 direction.

[0030] Each of the semiconductor elements 10 has a function of switching a main circuit current, and the specific configuration is not particularly limited. Specific examples of the semiconductor elements 10 include a SiC (silicon carbide) MOSET, a SiC IGBT, a Si MOSFET, a Si IGBT (insulated gate bipolar transistor), and a GaN (gallium nitride) HEMT (high electron mobility transistor). Each semiconductor element 10 has a rectangular shape when viewed in the z direction (also called a "planar view"), but the present disclosure is not limited thereto.

[0031] 5 and 10, each of the multiple semiconductor elements 10 has an element main surface 101 and an element back surface 102. In each semiconductor element 10, the element main surface 101 and the element back surface 102 are spaced apart in the z direction and face opposite each other. In this embodiment, the element main surface 101 faces the z2 direction, and the element back surface 102 faces the z1 direction.

[0032] Each of the plurality of semiconductor elements 10 has a principal surface electrode 11, a rear surface electrode 12, and an insulating film 13, as shown in FIGS.

[0033] The principal surface electrode 11 is provided on the element principal surface 101 as shown in FIG. 5. The principal surface electrode 11 includes a source electrode 111, a gate electrode 112, and a driver source electrode 113 as shown in FIG. 5. In this embodiment, the source electrode 111 is an electrode through which a source current flows. In this embodiment, a gate voltage for driving each semiconductor element 10 is applied to the gate electrode 112. The driver source electrode 113 is an electrode that serves as a reference potential for the gate voltage. The source electrode 111 is larger than the gate electrode 112 and the driver source electrode 113. The gate electrode 112 and the driver source electrode 113 are substantially the same size. In this embodiment, the source electrode 111 is configured as one region, but may be divided into multiple regions.

[0034] 10, the back electrode 12 is provided on the back surface 102 of the element. The back electrode 12 is formed over the entire back surface 102 of the element. In this embodiment, the back electrode 12 is an electrode through which a drain current flows, and will also be referred to as a drain electrode 12 in the following description.

[0035] As shown in FIG. 5, the insulating film 13 is provided on the element principal surface 101. The insulating film 13 has electrical insulation properties. The insulating film 13 surrounds the principal surface electrode 11 in a plan view. The insulating film 13 insulates the source electrode 111 from the gate electrode 112. The insulating film 13 is formed by laminating, for example, a SiO2 (silicon dioxide) layer, a Si3N4 (silicon nitride) layer, and a polybenzoxazole layer in this order on the element principal surface 101, with the polybenzoxazole layer being the surface layer. In the insulating film 13, a polyimide layer may be used instead of the polybenzoxazole layer. The configuration of the insulating film 13 is not limited to that described above.

[0036] The multiple semiconductor elements 10 include multiple first semiconductor elements 10A and multiple second semiconductor elements 10B. In this embodiment, the semiconductor device A1 configures a half-bridge type switching circuit. The multiple first semiconductor elements 10A configure an upper arm circuit in this switching circuit, and the multiple second semiconductor elements 10B configure a lower arm circuit in this switching circuit. As shown in FIG. 4, the semiconductor device A1 includes four first semiconductor elements 10A and four second semiconductor elements 10B. The number of semiconductor elements 10 is not limited to this configuration and can be freely set according to the performance required of the semiconductor device A1.

[0037] Each of the multiple first semiconductor elements 10A is mounted on a support substrate 20 (conductive substrate 22A) as shown in FIG. 2, FIG. 4, FIG. 5, and FIG. 10. In this embodiment, the multiple first semiconductor elements 10A are aligned in the y direction and spaced apart from one another. When each first semiconductor element 10A is mounted on the conductive substrate 22A, the element rear surface 102 faces the conductive substrate 22A. Each first semiconductor element 10A is conductively bonded to the support substrate 20 (conductive substrate 22A) via, for example, a conductive element bonding material (not shown). Examples of the element bonding material include solder, sintered silver, and silver paste.

[0038] Each of the second semiconductor elements 10B is mounted on a support substrate 20 (conductive substrate 22B) as shown in FIG. 2, FIG. 4, FIG. 5, and FIG. 10. In this embodiment, the second semiconductor elements 10B are arranged in the y direction and spaced apart from each other. When each second semiconductor element 10B is mounted on the conductive substrate 22B, the element rear surface 102 faces the conductive substrate 22B. Each second semiconductor element 10B is conductively bonded to the support substrate 20 (conductive substrate 22B) via, for example, a conductive element bonding material (not shown). In this embodiment, the first semiconductor elements 10A and the second semiconductor elements 10B overlap each other when viewed in the x direction. Alternatively, the first semiconductor elements 10A and the second semiconductor elements 10B may not overlap each other when viewed in the x direction.

[0039] The support substrate 20 is a support member that supports a plurality of semiconductor elements 10. The support substrate 20 includes an insulating substrate 21, two conductive substrates 22A and 22B, a pair of insulating layers 23A and 23B, a pair of gate layers 24A and 24B, a pair of driver source layers 25A and 25B, a first spacer 26A, and a second spacer 26B.

[0040] The insulating substrate 21 is a plate-like member having electrical insulation properties. The insulating substrate 21 supports two conductive substrates 22A and 22B. In this embodiment, the insulating substrate 21 is composed of two insulating substrates 21A and 21B, each of which is a flat plate. The configuration of the insulating substrate 21 is not limited to that described above, and may be, for example, a single flat plate instead of being divided into two insulating substrates 21A and 21B. The constituent material of each of the insulating substrates 21A and 21B is, for example, ceramics having excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride), SiN (silicon nitride), and Al2O3 (aluminum oxide).

[0041] Each of the insulating substrates 21A and 21B has a rectangular shape in a plan view. The insulating substrate 21A supports the conductive substrate 22A, and the insulating substrate 21B supports the conductive substrate 22B. The insulating substrates 21A and 21B are spaced apart from each other. In this embodiment, the insulating substrates 21A and 21B are spaced apart from each other in the x-direction and are aligned side by side, as shown in FIGS. 2, 4, and 10.

[0042] As shown in FIG. 10, the insulating substrate 21A has a main surface 211A and a back surface 212A. The main surface 211A and the back surface 212A are separated from each other in the z direction and face opposite each other. The main surface 211A faces the z2 direction, and the back surface 212A faces the z1 direction. The main surface 211A faces the conductive substrate 22A, and the back surface 212A is exposed from the sealing resin 70. Unlike the illustrated example, another conductive substrate may be bonded to the back surface 212A of the insulating substrate 21A. In this case, the back surface of the conductive substrate is exposed from the sealing resin 70.

[0043] As shown in FIG. 10, the insulating substrate 21B has a main surface 211B and a back surface 212B. The main surface 211B and the back surface 212B are spaced apart in the z direction and face opposite each other. The main surface 211B faces the z2 direction, and the back surface 212B faces the z1 direction. The main surface 211B faces the conductive substrate 22B, and the back surface 212B is exposed from the sealing resin 70. Unlike the illustrated example, another conductive substrate may be bonded to the back surface 212B of the insulating substrate 21B. In this case, the back surface of the conductive substrate is exposed from the sealing resin 70.

[0044] Each of the conductive substrates 22A and 22B is a plate-like member having electrical conductivity. In this embodiment, as shown in FIG. 10, each of the conductive substrates 22A and 22B is a composite substrate including a graphite substrate 220m and a copper film 220n formed on both sides of the graphite substrate 220m in the z direction. The material of each of the conductive substrates 22A and 22B is not limited thereto, and may be Cu or a Cu alloy. Each surface of the conductive substrates 22A and 22B may be covered with silver plating. The conductive substrates 22A and 22B, together with a plurality of leads (a first power lead 31, a second power lead 32, a third power lead 33, a pair of gate leads 34A and 34B, a pair of driver source leads 35A and 35B, and a plurality of dummy leads 36), form a conduction path to a plurality of semiconductor elements 10. The conductive substrates 22A and 22B are spaced apart from each other. As shown in FIG. 4 and FIG. 10, the conductive substrate 22A and the conductive substrate 22B are spaced apart from each other in the x direction and are arranged side by side. As shown in FIG. 4, the conductive substrates 22A and 22B are rectangular in plan view. The conductive substrates 22A and 22B have a dimension in the z direction of about 1.0 to 3.5 mm. In this embodiment, the dimension in the z direction of the graphite substrate 220m is about 0.5 to 2.5 mm, and the dimension in the z direction of each of the pair of copper films 220n is about 0.25 to 0.5 mm. These dimensions in the z direction are not limited to those described above. The copper film 220n on the upper side of the conductive substrate 22A in FIG. 10 is an example of the "first metal layer", and the copper film 220n on the upper side of the conductive substrate 22B in FIG. 10 is an example of the "second metal layer". The copper film 220n on the upper side in Fig. 10 of the conductive substrate 22A and the copper film 220n on the upper side in Fig. 10 of the conductive substrate 22B are examples of "conductive members". The material constituting the copper film 220n on the upper side in Fig. 10 of the conductive substrate 22A and the copper film 220n on the upper side in Fig. 10 of the conductive substrate 22B is an example of a "first material".

[0045] As shown in Fig. 10, the conductive substrate 22A is bonded to the insulating substrate 21A via a substrate bonding material 220A. The substrate bonding material 220A may be, for example, a conductive bonding material such as silver paste, solder, or sintered metal, or may be an insulating bonding material. As shown in Figs. 4 and 10, the conductive substrate 22A is located in the x1 direction from the conductive substrate 22B. When viewed in the x direction, the conductive substrate 22A entirely overlaps the conductive substrate 22B.

[0046] 10, the conductive substrate 22A has a main surface 221A and a back surface 222A. The main surface 221A and the back surface 222A are spaced apart in the z direction and face opposite each other. The main surface 221A faces the z2 direction, and the back surface 222A faces the z1 direction. A plurality of first semiconductor elements 10A are mounted on the main surface 221A. An insulating layer 23A is bonded to the main surface 221A.

[0047] 10, the conductive substrate 22B is bonded to the insulating substrate 21B via a substrate bonding material 220B. The substrate bonding material 220B may be, for example, a conductive bonding material such as silver paste, solder, or sintered metal, or may be an insulating bonding material.

[0048] 10, the conductive substrate 22B has a main surface 221B and a back surface 222B. The main surface 221B and the back surface 222B are spaced apart in the z direction and face opposite each other. The main surface 221B faces the z2 direction, and the back surface 222B faces the z1 direction. A plurality of second semiconductor elements 10B are mounted on the main surface 221B. An insulating layer 23B and one ends of a plurality of intermediate leads 40 are respectively joined to the main surface 221B.

[0049] The pair of insulating layers 23A, 23B has electrical insulation properties, and is made of, for example, glass epoxy resin or ceramics. As shown in FIG. 4, the pair of insulating layers 23A, 23B are each in the form of a strip extending in the y direction. As shown in FIG. 4 and FIG. 10, the insulating layer 23A is bonded to the main surface 221A of the conductive substrate 22A. The insulating layer 23A is located in the x1 direction from the multiple first semiconductor elements 10A. Alternatively, the insulating layer 23A may be disposed on the x2 direction side from the multiple first semiconductor elements 10A. As shown in FIG. 4 and FIG. 10, the insulating layer 23B is bonded to the main surface 221B of the conductive substrate 22B. The insulating layer 23B is located in the x2 direction from the multiple second semiconductor elements 10B. Alternatively, the insulating layer 23B may be disposed on the x1 direction side from the multiple second semiconductor elements 10B.

[0050] The pair of gate layers 24A, 24B are conductive and are made of, for example, Cu or a Cu alloy. As shown in FIG. 4 and other figures, the pair of gate layers 24A, 24B include a strip-shaped portion extending in the y direction and a hook-shaped portion protruding from the strip-shaped portion. The shape of the pair of gate layers 24A, 24B is not limited to that shown in FIG. 4, and may be composed of only the strip-shaped portion without the hook-shaped portion. As shown in FIG. 4 and FIG. 10, the gate layer 24A is disposed on the insulating layer 23A. The gate layer 24A is electrically connected to the gate electrode 112 of each first semiconductor element 10A via a wire member 50 (a gate wire 51 described later). The gate layer 24B is disposed on the insulating layer 23B as shown in FIG. 4 and FIG. 10. The gate layer 24B is electrically connected to the gate electrode 112 of each second semiconductor element 10B via a wire member 50 (a gate wire 51 described later).

[0051] The pair of driver source layers 25A, 25B are conductive and are made of, for example, Cu or a Cu alloy. As shown in FIG. 4 and other figures, the pair of driver source layers 25A, 25B include a strip-shaped portion extending in the y direction and a hook-shaped portion protruding from the strip-shaped portion. The shape of the pair of driver source layers 25A, 25B is not limited to that shown in FIG. 4, and may be composed of only the strip-shaped portion without the hook-shaped portion. As shown in FIG. 4 and FIG. 10, the driver source layer 25A is disposed on the insulating layer 23A together with the gate layer 24A. In a plan view, the driver source layer 25A is located next to the gate layer 24A on the insulating layer 23A and is spaced apart from the gate layer 24A. In this embodiment, the driver source layer 25A is disposed closer to the multiple first semiconductor elements 10A than the gate layer 24A in the x direction. Therefore, the driver source layer 25A is located on the x2 direction side of the gate layer 24A. The arrangement of the gate layer 24A and the driver source layer 25A in the x direction may be the opposite of the above. The driver source layer 25A is electrically connected to the driver source electrode 113 of each first semiconductor element 10A via a wire member 50 (driver source wire 52). The driver source layer 25B is arranged on the insulating layer 23B together with the gate layer 24B, as shown in FIG. 4 and FIG. 10. The driver source layer 25B is located next to the gate layer 24B on the insulating layer 23B in a plan view and is spaced apart from the gate layer 24B. In this embodiment, the driver source layer 25B is arranged closer to the multiple second semiconductor elements 10B than the gate layer 24B. Therefore, the driver source layer 25B is located on the x1 direction side of the gate layer 24B. The arrangement of the gate layer 24B and the driver source layer 25B in the x direction may be the opposite of the above. The driver source layer 25B is electrically connected to the driver source electrodes 113 of the second semiconductor elements 10B via the wire members 50 (driver source wires 52).

[0052] The first spacer 26A and the second spacer 26B are conductive, and are made of, for example, Cu or a Cu alloy. The materials of the first spacer 26A and the second spacer 26B are not limited to those described above, and may be, for example, a CuMo (Cu-Molybdenum) composite material or a CIC (Copper-Inver-Copper) composite material. The materials of the first spacer 26A and the second spacer 26B may be different from each other. The first spacer 26A and the second spacer 26B are an example of a "conductive member", and the material of the first spacer 26A and the second spacer 26B is an example of a "first material".

[0053] As shown in FIG. 10, the first spacer 26A is interposed between the conductive substrate 22A and the first power lead 31. As shown in FIG. 4, the first spacer 26A has a rectangular shape extending in the y direction in a plan view. The first spacer 26A is conductively joined to the conductive substrate 22A. The first spacer 26A is located near the edge of the conductive substrate 22A in the x1 direction in a plan view. The first spacer 26A is provided to place the first power lead 31 at substantially the same position as the second power lead 32 in the z direction. Alternatively, the first spacer 26A may be omitted and the first power lead 31 may be directly joined to the conductive substrate 22A. The shape of the first spacer 26A is not particularly limited.

[0054] As shown in FIG. 10, the second spacer 26B is interposed between the conductive substrate 22B and the third power lead 33. As shown in FIG. 4, the second spacer 26B has a rectangular shape extending in the y direction in a plan view. The second spacer 26B is conductively joined to the conductive substrate 22B. The second spacer 26B is located near the edge of the conductive substrate 22B in the x2 direction in a plan view. The second spacer 26B is provided to place the third power lead 33 at substantially the same position as the second power lead 32 in the z direction. Alternatively, the second spacer 26B may be omitted, and the third power lead 33 may be directly joined to the conductive substrate 22B. The shape of the second spacer 26B is not particularly limited.

[0055] Each of the multiple leads (first power lead 31, second power lead 32, third power lead 33, a pair of gate leads 34A, 34B, a pair of driver source leads 35A, 35B, and multiple dummy leads 36) includes a portion located inside the sealing resin 70 and a portion located outside the sealing resin 70. That is, each lead includes a portion covered by the sealing resin 70 and a portion exposed from the sealing resin 70. Each lead is used when mounting the semiconductor device A1 on a circuit board of an electronic device or the like.

[0056] The first power lead 31 and the second power lead 32 are each a metal plate. The metal plate is made of Cu or a Cu alloy. The material of the first power lead 31 and the second power lead 32 is not limited thereto, and may be, for example, aluminum. In this embodiment, the dimension of both the first power lead 31 and the second power lead 32 in the z direction is about 0.8 mm, but the present disclosure is not limited thereto. As shown in FIGS. 1 to 4 and 7, both the first power lead 31 and the second power lead 32 are located closer to the x1 direction in the semiconductor device A1. For example, a power supply voltage is applied between the first power lead 31 and the second power lead 32. The first power lead 31 is a positive electrode (P terminal), and the second power lead 32 is a negative electrode (N terminal). The first power lead 31 and the second power lead 32 are spaced apart from each other. The second power lead 32 is spaced apart from the conductive substrate 22A. The first power lead 31 and the second power lead 32 are an example of a "conductive member", and the material that constitutes the first power lead 31 and the second power lead 32 is an example of a "first material".

[0057] As shown in FIG. 4, the first power lead 31 has a pad portion 311 and a terminal portion 312.

[0058] The pad portion 311 is a portion of the first power lead 31 that is covered with the sealing resin 70. The pad portion 311 is electrically connected to the conductive substrate 22A via the first spacer 26A. The pad portion 311 is electrically connected to the first spacer 26A as shown in Figs. 2, 4 and 10. The method of electrically connecting the pad portion 311 is not limited in any way, and may be, for example, laser bonding, bonding using a conductive bonding material, or the like.

[0059] The terminal portion 312 is a portion of the first power lead 31 that is exposed from the sealing resin 70. The terminal portion 312 extends from the sealing resin 70 in the x1 direction, as shown in FIGS.

[0060] As shown in FIG. 4, the second power lead 32 has a pad portion 321 and a terminal portion 322.

[0061] The pad portion 321 is a portion of the second power lead 32 that is covered with the sealing resin 70. The pad portion 321 includes a coupling portion 321a, a plurality of extending portions 321b, and a connecting portion 321c.

[0062] The connecting portion 321a has a strip shape extending in the y direction. The connecting portion 321a connects the multiple extending portions 321b.

[0063] Each of the extensions 321b is a strip extending from the connecting portion 321a in the x2 direction. In this embodiment, each extension 321b extends in the x direction from the connecting portion 321a until it overlaps with each second semiconductor element 10B in a plan view. Each extension 321b extends from the conductive substrate 22A to the conductive substrate 22B in a plan view. A tip portion of each extension 321b overlaps with the second block 62 in a plan view. The extensions 321b are arranged in the y direction and are spaced apart from each other in a plan view. Each extension 321b is electrically connected to the source electrode 111 (source electrode) of the second semiconductor element 10B via the conductive blocks 60. As shown in FIG. 4 and FIG. 10, a tip portion of each extension 321b is electrically connected to the second block 62. The method of conductive joining is not limited in any way, and may be, for example, laser joining, joining with a conductive joining material, or the like.

[0064] The connection portion 321c is a portion that connects the coupling portion 321a and the terminal portion 322. In the present embodiment, as shown in Fig. 4, the connection portion 321c extends in the x1 direction from an edge of the coupling portion 321a that is on the y2 direction side and the x1 direction side in a plan view.

[0065] The terminal portion 322 is a portion of the second power lead 32 exposed from the sealing resin 70. As shown in FIGS. 1, 3, 4, and 7, the terminal portion 322 extends in the x1 direction from the sealing resin 70. The terminal portion 322 has a rectangular shape in plan view. As shown in FIGS. 3, 4, and 7, the terminal portion 322 is located on the y2 direction side of the terminal portion 312 of the first power lead 31 in plan view. In this embodiment, the shape of the terminal portion 322 is the same as the shape of the terminal portion 312, but the present disclosure is not limited thereto.

[0066] The third power lead 33 is a metal plate. The constituent material of the metal plate is, for example, Cu or a Cu alloy. The constituent material of the third power lead 33 is not limited to this, and may be, for example, aluminum. As shown in FIGS. 1 to 4, 6, 7, and 10, the third power lead 33 is located toward the x2 direction in the semiconductor device A1. The AC power (voltage) converted by the multiple semiconductor elements 10 is output from the third power lead 33.

[0067] As shown in FIGS. 4 and 10, the third power lead 33 includes a pad portion 331 and a terminal portion 332 .

[0068] The pad portion 331 is a portion of the third power lead 33 that is covered with the sealing resin 70. The pad portion 331 is electrically connected to the conductive substrate 22B via the second spacer 26B. The pad portion 331 is electrically connected to the second spacer 26B as shown in Figs. 2, 4 and 10. The method of electrically connecting the pad portion 331 is not limited in any way, and may be, for example, laser connecting or connecting using a conductive connecting material.

[0069] The terminal portion 332 is a portion of the third power lead 33 that is exposed from the sealing resin 70. The terminal portion 332 extends from the sealing resin 70 in the x2 direction, as shown in FIGS.

[0070] 1 to 7, the pair of gate leads 34A, 34B are located adjacent to each of the conductive substrates 22A, 22B in the y direction. A gate voltage for driving the multiple first semiconductor elements 10A is applied to the gate lead 34A. A gate voltage for driving the multiple second semiconductor elements 10B is applied to the gate lead 34B.

[0071] 5, each of the pair of gate leads 34A, 34B has a pad portion 341 and a terminal portion 342. In each of the gate leads 34A, 34B, the pad portion 341 is covered with the sealing resin 70. Each of the gate leads 34A, 34B is supported by the sealing resin 70. The terminal portion 342 is connected to the pad portion 341 and is exposed from the sealing resin 70. The terminal portion 342 is L-shaped when viewed in the x direction. In this embodiment, the terminal portion 342 protrudes from a surface (resin side surface 733) of the sealing resin 70 facing the y1 direction.

[0072] The pair of driver source leads 35A, 35B are located next to the pair of gate leads 34A, 34B in the x-direction as shown in Figs. 1 to 7. The driver source lead 35A is a lead that serves as a reference potential for the gate voltage for driving the multiple first semiconductor elements 10A. The driver source lead 35B is a lead that serves as a reference potential for the gate voltage for driving the multiple second semiconductor elements 10B.

[0073] As shown in FIG. 5, each of the pair of driver source leads 35A, 35B has a pad portion 351 and a terminal portion 352. In each of the driver source leads 35A, 35B, the pad portion 351 is covered with the sealing resin 70. Each of the driver source leads 35A, 35B is supported by the sealing resin 70. The terminal portion 352 is connected to the pad portion 351 and is exposed from the sealing resin 70. The terminal portion 352 is L-shaped when viewed in the x direction. In this embodiment, the terminal portion 352 protrudes from a surface (resin side surface 733) of the sealing resin 70 facing the y1 direction.

[0074] As shown in FIGS. 1 to 7, the multiple dummy leads 36 are located on the opposite side of the pair of driver source leads 35A, 35B with respect to the pair of gate leads 34A, 34B in the x direction. In this embodiment, the number of dummy leads 36 is four. Two of the dummy leads 36 are located on one side of the x direction (x2 direction). The remaining two dummy leads 36 are located on the other side of the x direction (x1 direction). The multiple dummy leads 36 are not limited to the configuration described above. A configuration without the multiple dummy leads 36 may be used.

[0075] 5, each of the multiple dummy leads 36 has a pad portion 361 and a terminal portion 362. In each dummy lead 36, the pad portion 361 is covered with the sealing resin 70. The multiple dummy leads 36 are supported by the sealing resin 70. The terminal portion 362 is connected to the pad portion 361 and is exposed from the sealing resin 70. The terminal portion 362 is L-shaped when viewed in the x direction. In this embodiment, the terminal portion 362 protrudes from a surface (resin side surface 733) of the sealing resin 70 facing the y1 direction.

[0076] In this embodiment, the gate leads 34A, 34B, the driver source leads 35A, 35B and the dummy leads 36 have substantially the same shape. As shown in Figs. 1 to 7, they are arranged along the x direction. In the semiconductor device A1, the leads (the first power lead 31, the second power lead 32, the third power lead 33, the pair of gate leads 34A, 34B, the pair of driver source leads 35A, 35B and the multiple dummy leads 36) are all formed from the same lead frame.

[0077] The intermediate leads 40 connect each of the first semiconductor elements 10A and the conductive substrate 22B. The material of each of the intermediate leads 40 is, for example, Cu or a Cu alloy. The material of each of the intermediate leads 40 is not limited to this, and may be a clad material such as CIC, aluminum, or the like. Each of the intermediate leads 40 is a flat connecting member. As shown in FIG. 4, each of the intermediate leads 40 has a rectangular shape extending in the x-direction in a plan view. Each of the intermediate leads 40 overlaps with each of the extension portions 321b of the second power leads 32 in a plan view. The intermediate leads 40 are an example of a "conductive member", and the material constituting the intermediate leads 40 is an example of a "first material".

[0078] As shown in FIG. 10, each intermediate lead 40 includes a first joint portion 41, a second joint portion 42, and a connecting portion 43.

[0079] 10, the first joint portion 41 is a portion joined to the first block 61. In this embodiment, the first joint portion 41 and the first block 61 are electrically connected to each other. The method of electrically connecting the first joint portion 41 and the first block 61 is not particularly limited, and may be, for example, laser connecting, connecting using a conductive connecting material, or the like.

[0080] 10, the second bonding portion 42 is a portion bonded to the conductive substrate 22B. In this embodiment, the second bonding portion 42 and the conductive substrate 22B are conductively bonded. The method of conductive bonding is not particularly limited, and may be, for example, laser bonding, bonding using a conductive bonding material, or the like.

[0081] The connecting portion 43 is a portion that connects the first joint portion 41 and the second joint portion 42. The dimension of the connecting portion 43 in the z direction is the same as that of the first joint portion 41 and the second joint portion 42. In this embodiment, the connecting portion 43 is partially bent in the z direction. The bending of the connecting portion 43 connects the first joint portion 41 and the second joint portion 42, which are located at different positions in the z direction.

[0082] Each of the plurality of wire members 50 is a wire (bonding wire). Each of the wire members 50 has electrical conductivity, and is made of, for example, aluminum, gold, or Cu. In this embodiment, the plurality of wire members 50 includes a plurality of gate wires 51, a plurality of driver source wires 52, a pair of first connecting wires 53, and a pair of second connecting wires 54, as shown in FIGS. 4 and 5.

[0083] 5, one end (first end) of each of the multiple gate wires 51 is joined to the gate electrode 112 of each semiconductor element 10, and the other end (second end) is joined to one of the pair of gate layers 24A, 24B. Among the multiple gate wires 51, there are ones that connect the gate electrode 112 and gate layer 24A of each first semiconductor element 10A to electrical continuity, and ones that connect the gate electrode 112 and gate layer 24B of each second semiconductor element 10B to electrical continuity.

[0084] 5, one end of each of the multiple driver source wires 52 is joined to the driver source electrode 113 of each semiconductor element 10, and the other end is joined to one of the pair of driver source layers 25A, 25B. The multiple driver source wires 52 include one that electrically connects the driver source electrode 113 of each first semiconductor element 10A to the driver source layer 25A, and one that electrically connects the driver source electrode 113 of each second semiconductor element 10B to the driver source layer 25B.

[0085] 5, one of a pair of first connecting wires 53 connects the gate layer 24A and the gate lead 34A, and the other connects the gate layer 24B and the gate lead 34B. One of the first connecting wires 53 has one end bonded to the gate layer 24A, and the other end bonded to the pad portion 341 of the gate lead 34A. The other first connecting wire 53 has one end bonded to the gate layer 24B, and the other end bonded to the pad portion 341 of the gate lead 34B.

[0086] 5, one of the pair of second connecting wires 54 connects the driver source layer 25A and the driver source lead 35A, and the other connects the driver source layer 25B and the driver source lead 35B. One end of one second connecting wire 54 is joined to the driver source layer 25A, and the other end is joined to the pad portion 351 of the driver source lead 35A. The other second connecting wire 54 has one end joined to the driver source layer 25B, and the other end joined to the pad portion 351 of the driver source lead 35B.

[0087] The plurality of conductive blocks 60 are conductive. Each of the plurality of conductive blocks 60 is bonded onto a corresponding one of the semiconductor elements 10. Each of the conductive blocks 60 has a dimension in the z direction of about 0.1 to 2.0 mm, but the present disclosure is not limited to this. The plurality of conductive blocks 60 includes a plurality of first blocks 61 and a plurality of second blocks 62.

[0088] Each of the multiple first blocks 61 is bonded one by one onto any one of the multiple first semiconductor elements 10A. Each of the first blocks 61 is conductively bonded to each of the first semiconductor elements 10A by solder or the like. Each of the first blocks 61 faces the element main surface 101 of each of the first semiconductor elements 10A. In this embodiment, as shown in FIG. 4, each of the first blocks 61 is a columnar body having a rectangular shape in a plan view. The shape of each of the first blocks 61 in a plan view is not limited thereto, and may be a circle, an ellipse, or a polygon. The first blocks 61 are made of, for example, Cu or a Cu alloy.

[0089] Each of the second blocks 62 is bonded one by one onto any one of the second semiconductor elements 10B. Each of the second blocks 62 is conductively bonded to each of the second semiconductor elements 10B by solder or the like. Each of the second blocks 62 faces the element main surface 101 of each of the second semiconductor elements 10B. The z-direction dimension of each of the second blocks 62 is not particularly limited, but is, for example, about 1.83 mm in this embodiment. In this embodiment, each of the second blocks 62 is a columnar body and has a rectangular shape in a plan view, as shown in FIG. 4 and FIG. 10. The plan view shape of each of the second blocks 62 is not limited thereto, and may be a circle, an ellipse, or a polygon. The second block 62 is made of, for example, Cu or a Cu alloy.

[0090] The dimension in the z direction of each first block 61 is smaller than the dimension in the z direction of each second block 62. In the present embodiment, the dimension in the z direction of each second block 62 is approximately 1.83 mm as described above, and therefore the dimension in the z direction of each first block 61 is smaller than this value. This allows each extension portion 321b of the second power lead 32 to be disposed above each intermediate lead 40.

[0091] The capacitor 81 is a chip type having a first end and a second end, the first end being placed on the pad portion 311 of the first power lead 31, and the second end being placed on the connecting portion 321a of the second power lead 32. The capacitor 81 and each of the power leads 31, 32 can be joined by, for example, a conductive joining material. By electrically connecting the capacitor 81 to the first power lead 31 and the second power lead 32, it is possible to stabilize the power supply voltage (input voltage) applied between the first power lead 31 and the second power lead 32. The capacitor 81 may be referred to as a DC link capacitor. Unlike this embodiment, a configuration without the capacitor 81 may be used.

[0092] As shown in Fig. 4 and Fig. 10, the sealing resin 70 covers the semiconductor elements 10, a part of the support substrate 20, a part of each of the leads (the first power lead 31, the second power lead 32, the third power lead 33, the pair of gate leads 34A, 34B, the pair of driver source leads 35A, 35B, and the dummy leads 36), the intermediate leads 40, the wire members 50, and the conductive blocks 60. The sealing resin 70 is made of, for example, epoxy resin. As shown in Figs. 1, 3, and 6 to 10, the sealing resin 70 has a resin main surface 71, a resin back surface 72, and a plurality of resin side surfaces 731 to 734.

[0093] As shown in FIG. 6 and FIG. 8 to FIG. 10, the resin main surface 71 and the resin back surface 72 are spaced apart in the z direction and face opposite directions to each other. The resin main surface 71 faces the z2 direction, and the resin back surface 72 faces the z1 direction. As shown in FIG. 7, the resin back surface 72 is frame-shaped in plan view surrounding the back surface 212A of the insulating substrate 21A and the back surface 212B of the insulating substrate 21B. Each of the back surfaces 212A and 212B is exposed from the resin back surface 72. As shown in FIG. 3 and FIG. 6 to FIG. 10, each of the multiple resin side surfaces 731 to 734 is connected to both the resin main surface 71 and the resin back surface 72 and is sandwiched between them in the z direction. In this embodiment, the resin side surfaces 731 and 732 are spaced apart in the x direction and face opposite directions to each other. The resin side surface 731 faces the x1 direction, and the resin side surface 732 faces the x2 direction. The resin side surfaces 733 and 734 are spaced apart in the y direction and face opposite each other. The resin side surface 733 faces the y1 direction, and the resin side surface 734 faces the y2 direction.

[0094] The covering layer 90 is a layer that covers at least a part of the "conductive member" and is made of a second material. This second material satisfies at least one of the following three requirements: (1) It has a higher magnetic permeability than the first material constituting the "conductive member". (2) It has a higher electrical resistivity than the first material. (3) It has a dielectric loss tangent that is greater than 0 (greater than the dielectric loss tangent of an ideal dielectric). In this regard, for example, the first material is Cu. In this case, examples of the second material having a higher magnetic permeability than the first material include magnetic metals such as Ni, Co, and Fe. Examples of the second material having a higher electrical resistivity than the first material include metals such as Ni, W, and Mo, conductive polymers, and transparent conductive films. Examples of the second material having a dielectric loss tangent that is greater than 0 include dielectric materials. In addition, when the magnetic permeability of the second material is made higher than that of the first material, it is preferable that the relative magnetic permeability of the second material is, for example, 10 or more. When the electrical resistivity of the second material is made higher than that of the first material, the electrical resistivity of the second material is preferably, for example, at least twice as high as that of the first material. Regarding the above requirement (3), the dielectric tangent of the second material is preferably 0.01 or more. The thickness of the coating layer 90 is not particularly limited, and is, for example, 1 μm to 5 μm. When the coating layer 90 is made of a metal, the coating layer 90 is formed by plating, such as magnetic plating.

[0095] The covering layer 90 may be a magnetic metal in which the magnetic permeability of the second material is higher than that of the first material and the electrical resistivity of the second material is higher than that of the first material. The covering layer 90 may be configured in such a way that the magnetic permeability of the second material is higher than that of the first material and the dielectric loss tangent of the second material is greater than 0. The covering layer 90 may be configured in such a way that the electrical resistivity of the second material is higher than that of the first material and the dielectric loss tangent of the second material is greater than 0. The covering layer 90 may be configured in such a way that the magnetic permeability of the second material is higher than that of the first material, the electrical resistivity of the second material is higher than that of the first material and the dielectric loss tangent of the second material is greater than 0.

[0096] As shown in Figs. 1 to 11, in this embodiment, the covering layer 90 has a first portion 91 and a second portion 92. The first portion 91 covers at least a part of the first power lead 31. In this embodiment, the first portion 91 covers the entire first power lead 31. As shown in Fig. 11, when the first power lead 31 functions as a path for a main circuit current, the entire circumference of the cross section of the first power lead 31 is covered by the first portion 91. The second portion 92 covers at least a part of the second power lead 32. In this embodiment, the second portion 92 covers the entire second power lead 32. As with the first portion 91, when the second power lead 32 functions as a path for a main circuit current, the entire circumference of the cross section of the second power lead 32 is covered by the second portion 92.

[0097] Next, the effects of the above-described semiconductor device A1 will be described.

[0098] In general, when an AC current flows through a conductor, the current density becomes higher at the surface of the conductor (this is called the skin effect). The higher the frequency of the AC current, the more pronounced the skin effect becomes. In this embodiment, the coating layer 90 is provided on a conductive member that forms a path of the main circuit current in the semiconductor device A1. More specifically, the coating layer 90 is provided in a portion where the density of the AC current becomes high due to the skin effect. When the magnetic permeability of the second material that constitutes the coating layer 90 is higher than the magnetic permeability of the first material (Cu, etc.) that constitutes the conductive member (first power lead 31, second power lead 32, etc.), the influence of the skin effect becomes more pronounced, and the AC resistance of the current path becomes high. This makes it possible to attenuate the AC current flowing through the coating layer 90 and suppress ringing. On the other hand, the skin effect is relatively unlikely to occur for low-frequency components of the current. Therefore, the coating layer 90 does not unduly attenuate the low-frequency components of the current. Furthermore, because ringing can be suppressed, the snubber circuit provided in the semiconductor device A1 can be simplified, and the reliability of the semiconductor device A1 itself can be improved.

[0099] Furthermore, even if the electrical resistivity of the second material constituting the coating layer 90 is higher than the electrical resistivity of the first material (Cu, etc.) constituting the conductive members (the first power lead 31, the second power lead 32, etc.), it is possible to attenuate the AC current flowing through the coating layer 90 and suppress ringing. As described above, the low-frequency component of the current is not unduly attenuated by the coating layer 90.

[0100] Furthermore, even when the dielectric tangent of the second material constituting the coating layer 90 is greater than 0 (greater than the dielectric tangent of an ideal dielectric), the energy of the AC current flowing through the coating layer 90 can be consumed as dielectric loss, and ringing can be suppressed.

[0101] The effects obtained by the requirements for the magnetic permeability, electrical resistivity, and dielectric loss tangent of the second material described above can be achieved independently of each other. Therefore, ringing can be more effectively suppressed not only by a configuration in which only one of the requirements for the magnetic permeability, electrical resistivity, and dielectric loss tangent of the second material is satisfied, but also by a configuration in which any two of the requirements are satisfied, or even by a configuration in which all three of the requirements are satisfied.

[0102] 12 to 21 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals.

[0103] FIG. 12 shows a first modified example of the semiconductor device A1. In the semiconductor device A11 of this modified example, the configuration of the covering layer 90 is different from that of the above-mentioned example. Taking the first portion 91, which is a part of the covering layer 90, as an example, in this modified example, in a cross section through which a main circuit current flows, the first portion 91 does not cover the entire circumference of the cross section of the first power lead 31, but covers only a part of it. More specifically, the first portion 91 covers only three sides (the upper side and two side sides) of the rectangular cross section of the first power lead 31, and does not cover the remaining side (the bottom side) (i.e., the bottom side is exposed from the first portion 91). Note that each of the three sides (the upper side and two side sides) is completely covered by the first portion 91.

[0104] FIG. 13 shows a second modified example of the semiconductor device A1. Taking the first portion 91, which is a part of the covering layer 90, as an example, in this modified example, in a cross section through which the main circuit current flows, the first portion 91 is formed over the entire circumference of the cross section of the first power lead 31, but all of the sides (the upper side, the two side sides, and the bottom side) are partially exposed from the first portion 91 (in other words, are partially covered by the first portion 91). In the example shown in the figure, the first portion 91 has a plurality of voids spaced apart from each other along the entire circumference of the rectangular cross section. The plurality of voids includes one or more voids corresponding to each side of the cross section. Such a first portion 91 (covering layer 90) can be configured, for example, to have a plurality of small holes or slits formed therein. Alternatively, the first portion 91 (covering layer 90) can be configured as a collection of a plurality of small regions spaced apart from each other.

[0105] The semiconductor devices A11 and A12 can also suppress ringing. As can be seen from these modified examples, the specific configuration of the covering layer 90 is not particularly limited. Even in the case where the covering layer 90 is configured to cover a part of the conductive member (FIGS. 12 and 13), the ringing can be suppressed depending on the position, size, etc. of the region where the covering layer 90 is provided.

[0106] 14 to 16 show a semiconductor device according to a second embodiment of the present disclosure. In a semiconductor device A2 of this embodiment, the configuration of a covering layer 90 is different from that of the covering layer 90 of the semiconductor device A1 described above.

[0107] In the second embodiment, the first portion 91 covers a portion of the first power lead 31, and the second portion 92 covers a portion of the second power lead 32. More specifically, the first portion 91 does not cover a portion of the first power lead 31 that forms a path between the first semiconductor element 10A and the capacitor 81. In other words, the first portion 91 covers the terminal portion 312 of the first power lead 31, but does not cover the pad portion 311.

[0108] Further, the second portion 92 does not cover a portion of the second power lead 32 that constitutes a path between the second semiconductor element 10B and the capacitor 81. That is, the second portion 92 covers the terminal portion 322 and the connection portion 321c of the pad portion 321 of the second power lead 32, but does not cover the coupling portion 321a and the multiple extending portions 321b.

[0109] The second embodiment can also suppress ringing. The resistance of the portion of the first power lead 31 and the second power lead 32 that constitutes the path through which only the charge / discharge current of the capacitor 81 flows is equivalent to the ESR of the capacitor 81. That is, since this path is a path through which a steep charge / discharge current flows to the capacitor 81, it is not preferable that the AC resistance is too high. In this respect, it is preferable for steep charging / discharging to the capacitor 81 to be performed by not covering a portion of the first power lead 31 and a portion of the second power lead 32 as in the above-mentioned configuration.

[0110] 17 to 19 show a semiconductor device according to a third embodiment of the present disclosure. In a semiconductor device A3 of this embodiment, the configuration of a covering layer 90 is different from the covering layer 90 of the semiconductor devices A1 and A2 described above.

[0111] In the third embodiment, the covering layer 90 includes a first portion 91, a second portion 92, a third portion 93, a fourth portion 94, a fifth portion 95, and a sixth portion 96. The first portion 91 and the second portion 92 have the same configuration as the first portion 91 and the second portion 92 in the semiconductor device A1.

[0112] The third portion 93 covers the copper film 220n of the conductive substrate 22A as the first metal layer. The fourth portion 94 covers the first spacer 26A. The fifth portion 95 covers the copper film 220n of the conductive substrate 22B as the second metal layer. The sixth portion 96 covers the intermediate leads 40. In the illustrated example, the third portion 93 covers a portion of the copper film 220n excluding the bonding surface with the graphite substrate 220m. The fifth portion 95 covers a portion of the copper film 220n excluding the bonding surface with the graphite substrate 220m.

[0113] Ringing can also be suppressed by the third embodiment. As can be seen from this embodiment, the location of the covering layer 90 can be changed as appropriate depending on the desired degree of ringing suppression and the configuration of the semiconductor device.

[0114] 20 and 21 show a semiconductor device according to a fourth embodiment of the present disclosure. In a semiconductor device A4 of this embodiment, the configurations of a first power lead 31 and a second power lead 32 are different from those of the above-described embodiments.

[0115] In the fourth embodiment, the terminal portion 312 of the first power lead 31 and the terminal portion 322 of the second power lead 32 overlap each other when viewed along the z direction. The terminal portion 312 is covered by the first portion 91, and the terminal portion 322 is covered by the second portion 92. An insulator 89 is provided between the terminal portion 312 and the terminal portion 322. The insulator 89 is for insulating the terminal portion 312 and the terminal portion 322 from each other when an expected voltage is applied between them.

[0116] In the fourth embodiment, the second material constituting the covering layer 90 is made of a material having a dielectric tangent at least greater than 0 (greater than the dielectric tangent of an ideal dielectric), for example, a dielectric tangent of 0.01 or more. When the covering layer 90 having such a configuration is adopted, the terminal portion 312 and the terminal portion 322 and the covering layer 90 and the insulator 89 interposed therebetween provide a portion having a capacitance, that is, a portion having an electrical configuration similar to that of a capacitor.

[0117] The fourth embodiment can also suppress ringing. Moreover, the capacitance formed by the terminal portion 312, the terminal portion 322, and the covering layer 90 and the insulator 89 interposed therebetween is expected to produce a synergistic effect with the capacitor 81, and can further enhance the effect of stabilizing the power supply voltage (input voltage) applied between the first power lead 31 and the second power lead 32.

[0118] The semiconductor device according to the present disclosure is not limited to the above-described embodiment and modified examples. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways.

[0119] The semiconductor device according to the present disclosure includes the embodiments described in the following appendices. Appendix 1. At least one semiconductor element having a switching function; a conductive member that serves as a path for a current switched by the semiconductor element and is made of a first material; a covering layer covering at least a portion of the conductive member and made of a second material; It is equipped with The second material meets the following three requirements: (a) having a higher magnetic permeability than the first material; (b) a higher electrical resistivity than the first material; and (c) the dielectric tangent is greater than 0; A semiconductor device that satisfies at least one of the requirements. Appendix 2. The semiconductor device according to claim 1, wherein the second material is a magnetic conductor having a higher magnetic permeability than the first material and a higher electrical resistivity than the first material. Appendix 3. 3. The semiconductor device of claim 2, wherein the second material has a dielectric tangent greater than 0. Appendix 4. The semiconductor device of claim 1, wherein the second material has a higher magnetic permeability and a dielectric tangent greater than 0 than the first material. Appendix 5. The semiconductor device of claim 1, wherein the second material has a higher electrical resistivity and a dielectric tangent greater than 0 than the first material. Appendix 6. 6. The semiconductor device according to claim 1, wherein the coating layer has a thickness of 1 μm to 5 μm. Appendix 7. The semiconductor device according to any one of claims 1 to 6, wherein the second material has a relative permeability of 10 or more. Appendix 8. The semiconductor device according to any one of claims 1 to 7, wherein the electrical resistivity of the second material is at least twice as high as the electrical resistivity of the first material. Appendix 9. The semiconductor device according to any one of claims 1 to 8, wherein the second material has a dielectric tangent of 0.01 or more. Appendix 10. a capacitor having a first end and a second end for electrical connection; the at least one semiconductor element is a plurality of semiconductor elements constituting a half bridge including at least one pair of upper and lower arms, the plurality of semiconductor elements include a first semiconductor element included in the upper arm and a second semiconductor element included in the lower arm; the conductive member includes a first metal layer connected to a drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to a source electrode of the second semiconductor element, the first end of the capacitor is connected to the first power lead and the second end of the capacitor is connected to the second power lead; 10. The semiconductor device according to claim 1, wherein the covering layer includes a first portion covering the first power lead and a second portion covering the second power lead. Appendix 11. 11. The semiconductor device of claim 10, wherein the first power lead includes a portion that forms a path between the first semiconductor element and the capacitor, and the portion of the first power lead is not covered by the first portion. Appendix 12. 12. The semiconductor device of claim 10, wherein the second power lead includes a portion that forms a path between the second semiconductor element and the capacitor, and the portion of the second power lead is not covered by the second portion. Appendix 13. 13. The semiconductor device according to claim 10, wherein the covering layer includes a third portion covering the first metal layer. Appendix 14. the conductive member includes a second metal layer connected to a drain electrode of the second semiconductor element and a third power lead connected to the second metal layer; 14. The semiconductor device according to any one of claims 10 to 13, wherein the second metal layer and the third power lead are not covered by the covering layer. Appendix 15. The semiconductor device described in Appendix 14, wherein the conductive member includes an intermediate lead connected to a source electrode of the first semiconductor element and the second metal layer, and the intermediate lead is not covered by the covering layer. Appendix 16. the conductive member includes a first spacer interposed between the first metal layer and the first power lead; 16. The semiconductor device according to claim 10, wherein the covering layer includes a fourth portion covering the first spacer. Appendix 17. 17. The semiconductor device according to claim 10, wherein the conductive member includes a conductor interposed between a source electrode of the second semiconductor element and the second power lead. Appendix 18. 18. The semiconductor device according to any one of appendix 1 to 17, wherein the semiconductor element is any one of a SiC MOSET, a SiC IGBT, a Si MOSFET, a Si IGBT, and a GaN HEMT. [Explanation of symbols]

[0120] A1, A11, A12, A2, A3, A4: Semiconductor device 10: Semiconductor elements 10A: First semiconductor element 10B: second semiconductor element 11: Main surface electrode 12: Drain electrode (rear electrode) 13: Insulating film 20: Support substrate 21, 21A, 21B: insulating substrate 22A, 22B: Conductive substrate 23A, 23B: Insulating layer 24A, 24B: Gate layer 25A, 25B: Driver source layer 26A: First spacer 31: 1st power lead 32: 2nd power lead 33: 3rd power lead 34A, 34B: Gate lead 35A, 35B: Driver source leads 36: Dummy read 40: Middle lead 41: 1st joint 42:Second joint 43: Liaison Department 50: Wire material 51: Gate wire 52: Driver source wire 53: First connecting wire 54: Second connecting wire 60: Conductive block 61: 1st block 62: Second Block 70: Sealing resin 71: Resin main surface 72: Resin back 81: Capacitor 89: Insulator 90: Covering layer 91: Part 1 92: Part 2 93: Part 3 94: Part 4 95: Part 5 96: Part 6 101: Element main surface 102: Back side of element 111: Source electrode 112: Gate electrode 113: Driver source electrode 211A, 211B: Main surface 212A, 212B: Back side 220A, 220B: Substrate bonding material 220m: Graphite substrate 220n: Copper film 221A, 221B: Main surface 222A, 222B: Back side 260A: Spacer bonding material 260B: Spacer bonding material 311, 321, 331, 341, 351, 361: Pad section 312,322,332,342,352,362:Terminal section 321a: Connection part 321b: Extension part 321c: Connection 731, 732, 733, 734: Resin side

Claims

1. At least one semiconductor element having a switching function; a conductive member that serves as a path for a current switched by the semiconductor element and is made of a first material; a covering layer covering at least a portion of the conductive member and made of a second material; Equipped with The second material has the following three requirements: (a) having a higher magnetic permeability than the first material; (b) a higher electrical resistivity than the first material; and (c) a dielectric tangent greater than 0; At least one of the following requirements is met: The second material has a dielectric tangent greater than zero.

2. 2. The semiconductor device according to claim 1, wherein the second material is a magnetic conductor having a higher magnetic permeability than the first material and a higher electrical resistivity than the first material.

3. 3. The semiconductor device according to claim 1, wherein the second material has a higher magnetic permeability and a dielectric loss tangent greater than 0 than the first material.

4. The semiconductor device according to claim 1 , wherein the second material has a higher electrical resistivity and a dielectric loss tangent greater than 0 than the first material.

5. 5. The semiconductor device according to claim 1, wherein the coating layer has a thickness of 1 μm to 5 μm.

6. 6. The semiconductor device according to claim 1, wherein the second material has a relative magnetic permeability of 10 or more.

7. 7. The semiconductor device according to claim 1, wherein the electrical resistivity of the second material is at least twice as high as the electrical resistivity of the first material.

8. 8. The semiconductor device according to claim 1, wherein the second material has a dielectric loss tangent of 0.01 or more.

9. a capacitor having a first end and a second end for electrical connection; the at least one semiconductor element is a plurality of semiconductor elements constituting a half bridge including at least one pair of upper and lower arms, the plurality of semiconductor elements include a first semiconductor element included in the upper arm and a second semiconductor element included in the lower arm, the conductive member includes a first metal layer connected to a drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to a source electrode of the second semiconductor element, the first end of the capacitor is connected to the first power lead and the second end of the capacitor is connected to the second power lead; 9. The semiconductor device according to claim 1, wherein said covering layer includes a first portion covering said first power lead and a second portion covering said second power lead.

10. 10. The semiconductor device according to claim 9, wherein the first power lead includes a portion that constitutes a path between the first semiconductor element and the capacitor, and the portion of the first power lead is not covered by the first portion.

11. 11. The semiconductor device according to claim 9, wherein the second power lead includes a portion that constitutes a path between the second semiconductor element and the capacitor, and the portion of the second power lead is not covered by the second portion.

12. At least one semiconductor element having a switching function; a conductive member that serves as a path for a current switched by the semiconductor element and is made of a first material; a covering layer covering at least a portion of the conductive member and made of a second material; Equipped with The second material has the following three requirements: (a) having a higher magnetic permeability than the first material; (b) a higher electrical resistivity than the first material; and (c) a dielectric tangent greater than 0; At least one of the following requirements is met: a capacitor having a first end and a second end for electrical connection; the at least one semiconductor element is a plurality of semiconductor elements constituting a half bridge including at least one pair of upper and lower arms, the plurality of semiconductor elements include a first semiconductor element included in the upper arm and a second semiconductor element included in the lower arm, the conductive member includes a first metal layer connected to a drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to a source electrode of the second semiconductor element, the first end of the capacitor is connected to the first power lead and the second end of the capacitor is connected to the second power lead; the covering layer includes a first portion covering the first power lead and a second portion covering the second power lead; A semiconductor device, wherein the first power lead includes a portion that forms a path between the first semiconductor element and the capacitor, and the portion of the first power lead is not covered by the first portion.

13. At least one semiconductor element having a switching function; a conductive member that serves as a path for a current switched by the semiconductor element and is made of a first material; a covering layer covering at least a portion of the conductive member and made of a second material; Equipped with The second material has the following three requirements: (a) having a higher magnetic permeability than the first material; (b) a higher electrical resistivity than the first material; and (c) a dielectric tangent greater than 0; At least one of the following requirements is met: a capacitor having a first end and a second end for electrical connection; the at least one semiconductor element is a plurality of semiconductor elements constituting a half bridge including at least one pair of upper and lower arms, the plurality of semiconductor elements include a first semiconductor element included in the upper arm and a second semiconductor element included in the lower arm, the conductive member includes a first metal layer connected to a drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to a source electrode of the second semiconductor element, the first end of the capacitor is connected to the first power lead and the second end of the capacitor is connected to the second power lead; the covering layer includes a first portion covering the first power lead and a second portion covering the second power lead; A semiconductor device, wherein the second power lead includes a portion that forms a path between the second semiconductor element and the capacitor, and the portion of the second power lead is not covered by the second portion.

14. 14. The semiconductor device according to claim 9, wherein the covering layer includes a third portion covering the first metal layer.

15. the conductive member includes a second metal layer connected to a drain electrode of the second semiconductor element and a third power lead connected to the second metal layer; 15. The semiconductor device according to claim 9, wherein said second metal layer and said third power lead are not covered by said covering layer.

16. At least one semiconductor element having a switching function; a conductive member that serves as a path for a current switched by the semiconductor element and is made of a first material; a covering layer covering at least a portion of the conductive member and made of a second material; Equipped with The second material has the following three requirements: (a) having a higher magnetic permeability than the first material; (b) a higher electrical resistivity than the first material; and (c) a dielectric tangent greater than 0; At least one of the following requirements is met: a capacitor having a first end and a second end for electrical connection; the at least one semiconductor element is a plurality of semiconductor elements constituting a half bridge including at least one pair of upper and lower arms, the plurality of semiconductor elements include a first semiconductor element included in the upper arm and a second semiconductor element included in the lower arm, the conductive member includes a first metal layer connected to a drain electrode of the first semiconductor element, a first power lead connected to the first metal layer, and a second power lead connected to a source electrode of the second semiconductor element, the first end of the capacitor is connected to the first power lead and the second end of the capacitor is connected to the second power lead; the covering layer includes a first portion covering the first power lead and a second portion covering the second power lead; the conductive member includes a second metal layer connected to a drain electrode of the second semiconductor element and a third power lead connected to the second metal layer; The second metal layer and the third power lead are not covered by the covering layer.

17. 17. The semiconductor device according to claim 15, wherein the conductive member includes an intermediate lead connected to a source electrode of the first semiconductor element and the second metal layer, the intermediate lead being not covered by the covering layer.

18. the conductive member includes a first spacer interposed between the first metal layer and the first power lead; 18. The semiconductor device according to claim 9, wherein the covering layer includes a fourth portion covering the first spacer.

19. 19. The semiconductor device according to claim 9, wherein the conductive member includes a conductor interposed between a source electrode of the second semiconductor element and the second power lead.

20. 20. The semiconductor device according to claim 1, wherein the semiconductor element is any one of a SiC MOSET, a SiC IGBT, a Si MOSFET, a Si IGBT, and a GaN HEMT.

Images