Preregulation for LDO

Abstract

The electronic device includes a voltage regulator circuit (102) having a power NFET (MNOUT) coupled between an upper supply voltage (VCC) and a pre-regulator output node (103) and a current source (CS1, MP1 with MP2) coupled in series with a diode element (107, Z1) between the upper supply voltage and a lower supply voltage (e.g., ground). The gate of the power NFET is coupled to a first node (105) between the current source and the diode element. A bypass circuit (106, 108, MPOUT) includes a power PFET (MPOUT) coupled between the upper supply voltage and the pre-regulator output node. A comparison circuit (106) is coupled to turn off the bypass circuit when the upper supply voltage is greater than a regulation threshold voltage (e.g., approximately 4V).

Description

[Technical field]

[0001] In devices such as smoke detectors, a wide input voltage range is desirable to allow for a variety of power sources. For example, a system powered using alternating current (AC) converted direct current (DC) and using a battery backup may require the device to operate from a 15V AC / DC power source and a battery that discharges down to 2V. This power source is typically connected to an integrated circuit (IC) that manages the power for the various amplifiers and drivers in the device. An IC that can operate over such a wide range of supply voltages poses many challenges to the designer. Summary of the Invention

[0002] The disclosed embodiments provide a pre-regulator circuit that regulates an upper supply voltage greater than a regulation threshold voltage, for example 4.0V, using a simple clamp diode on the gate of a pass transistor. Clamping the gate ensures that the output voltage does not damage downstream circuitry. A bypass switch allows an upper supply voltage less than the regulation threshold voltage to bypass the regulator. A comparison circuit receives the upper supply voltage and an internally generated reference voltage that is used to open and close the bypass switch. The pre-regulator circuit is simple and can scale up the input voltage of the LDO without requiring a high voltage device in the LDO.

[0003] In one aspect, an embodiment of an electronic device is disclosed, the electronic device includes a voltage regulator circuit including a power N-type field effect transistor (NFET) coupled between an upper supply voltage and a pre-regulator output node, a current source coupled in series with a diode element between the upper supply voltage and a lower supply voltage, a gate of the power NFET coupled to a first node between the current source and the diode element, a bypass circuit including a power P-type field effect transistor (PFET) coupled between the upper supply voltage and the pre-regulator output node, and a comparison circuit coupled to turn off the bypass circuit when the upper supply voltage is greater than a regulation threshold voltage.

[0004] In another aspect, an embodiment of a method of operating a pre-regulator circuit for a low drop out (LDO) regulator is disclosed, the method includes receiving an upper supply voltage having a range between a lower limit and an upper limit having a difference of at least 10 volts at an input node, determining whether the upper supply voltage is greater than a regulation threshold voltage, passing the upper supply voltage directly to a pre-regulator output node coupled to the LDO regulator if the upper supply voltage is not greater than the regulation threshold voltage, and regulating the upper supply voltage to provide a regulated output voltage at a power pre-regulator output node if the upper supply voltage is greater than the regulation threshold voltage. [Brief description of the drawings]

[0005] The embodiments of the present disclosure are illustrated by way of example, and not limitation, in the figures of the accompanying drawings, in which like reference numerals denote like elements. It should be noted that different references to "a" or "one" embodiment in the present disclosure are not necessarily to the same embodiment, and such references may mean at least one. Also, if a particular feature, structure, or characteristic is described in connection with one embodiment, it is within the knowledge of one skilled in the art to implement such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described. As used herein, the terms "couple" or "couple" shall mean an indirect or direct electrical connection, unless limited as in the case of "communicatively coupled," which may include a wireless connection. Thus, when a first device couples to a second device, the connection may be by a direct electrical connection or by an indirect electrical connection via other devices and connections.

[0006] The accompanying drawings are incorporated in and constitute a part of this specification for the purpose of illustrating one or more exemplary embodiments of the present disclosure. Various advantages and features of the present disclosure will become apparent from the following detailed description, taken in conjunction with the appended claims, and with reference to the accompanying drawings, in which:

[0007] [Figure 1]FIG. 2 is a high level block diagram of a pre-conditioner circuit in accordance with an embodiment of the present disclosure.

[0008] [Diagram 2] 1 illustrates an implementation of a pre-regulator circuit according to an embodiment of the present disclosure.

[0009] [Figure 2A] 1 illustrates an implementation of a pre-regulator circuit according to an embodiment of the present disclosure.

[0010] [Diagram 3] 1 shows the input and output voltages when the pre-regulator circuit is powered with an input voltage of 4V and loaded according to an embodiment of the present disclosure.

[0011] [Figure 4] 1 shows the input and output voltages when the pre-regulator circuit is powered with an input voltage of 15V and loaded according to an embodiment of the present disclosure.

[0012] [Diagram 5] 1 illustrates the total quiescent current of a pre-regulator circuit at low and high temperatures when operating at an input voltage of 4V according to an embodiment of the present disclosure.

[0013] [Figure 6] 1 illustrates the total quiescent current of a pre-regulator circuit at low and high temperatures when operating at an input voltage of 15V according to an embodiment of the present disclosure.

[0014] [Figure 7] 1 is a block diagram of a smoke detector utilizing a pre-regulator circuit in accordance with an embodiment of the present disclosure.

[0015] [Figure 8] 1 illustrates a method of operating a pre-regulator circuit for an LDO regulator according to an embodiment of the present disclosure.

[0016] [Figure 9A]1 shows a smoke detector operating with an LDO according to the prior art.

[0017] [Figure 9B] 1 shows a smoke detector operating with a step-down DC-DC converter according to the prior art; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Now, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following detailed description of the embodiments of the present invention, many specific details are described in order to provide a more complete understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known features are not described in detail to avoid unnecessarily complicating the description.

[0019] In a typical smoke detector, which may be powered from a battery or from a mains supply via an AC / DC converter, a wide range of input supply voltages may be used. For example, a smoke detector may be hardwired to a mains supply that is stepped down to 12 volts. When using a battery as either the mains or backup power supply, the battery may be a 9V battery, or two AA batteries may be required to provide 3V. The IC chip connected to the input power supply needs to be able to handle this wide range of supply voltages without allowing any reliability issues.

[0020] The need for devices inside the IC to handle such a wide voltage range presents a challenge, as high-voltage devices require a large area and are not suitable for high-speed, low-current applications. In particular, smoke detectors must be designed as low-power devices. To be certified by Underwriters Laboratories (UL), a global authority in product safety testing and certification, non-AC-powered smoke detectors must have a 10-year lifespan using a household 3.3V lithium battery. The circuit must also maintain high reliability even when fluctuations in the input power supply can occur.

[0021] In most practical applications, this problem is solved by providing a fixed step-down DC-DC converter or LDO that steps down a high voltage to a constant low voltage so that the internal circuitry of the IC can avoid such a wide range of input supplies and can be designed for low voltages. Figures 9A and 9B show two such prior art solutions.

[0022] In FIG. 9A, a prior art smoke detector 900A includes an LDO regulator 902 coupled to receive an AC / DC power source 904 and a battery power source 906 as alternative upper supply voltages at an input node 908. The LDO regulator 902 is also coupled to provide an internal supply voltage Vinternal at an output node 910 that is coupled to a smoke detector analog front end (AFE) 912, which may include internal circuitry, amplifiers, drivers, etc. The LDO regulator 902 includes a power P-type field effect transistor (PFET) Ma coupled between the input node 908 and an output node 910 to regulate the internal supply voltage Vinternal provided at the output node 910. A differential amplifier 914 is coupled to the input supply voltage and is capacitively coupled to the output node 910. The differential amplifier 914 has a non-inverting input coupled to receive a reference voltage Vref. The inverting input of the differential amplifier 914 is coupled to receive feedback from the output node 910 through a resistive divider 918 coupled between the output node 910 and a lower supply voltage, which may be a ground plane.

[0023] In Fig. 9B, the prior art smoke detector 900B includes a DC-DC converter 932 coupled to receive an AC / DC power source 934 and a battery power source 936 as an alternative upper supply voltage at an input node 938. The DC-DC converter 932 is also coupled to provide an internal supply voltage Vinternal at an output node 940 that is coupled to a smoke detector AFE 942, which may also include internal circuitry, amplifiers, drivers, etc. The DC-DC converter 932 includes a high-side power PFET Mhs coupled in series with a low-side power N-type field effect transistor (NFET) Mls between the input node 938 and the lower supply voltage, with a switch node SW located between the high-side power PFET Mhs and the low-side power NFET Mls. An inductor L1 is coupled between the switch node SW and an output node 940, and a capacitor Cout is coupled between the output node 940 and the lower supply voltage, which may be a ground plane. Logic circuitry 944 is coupled to a high side driver 946 that drives a high side power PFET Mh, and is also coupled to a low side driver 948 that drives a low side power NFET Mls.

[0024] An LDO regulator or DC-DC converter circuit is a dedicated circuit that requires not only amplifiers, but also high-precision reference voltages and bias currents. Such requirements lead to increased current consumption. Designing either the LDO regulator 902 or the DC-DC converter 932 to handle the required wide voltage range requires additional silicon area, more pins, and higher power consumption. In addition, converting an input supply voltage from 15V to 2V is highly inefficient if the output of the LDO regulator 902 or the DC-DC converter 932 is fixed at 2V as the lowest potential power supply. Even converting an input supply voltage from 3.6V means losing otherwise usable headroom. As will be seen below, the disclosed pre-regulation circuit addresses this latter problem by regulating the upper supply voltage as it rises above a regulation threshold voltage, while providing a bypass circuit for lower values ​​of the upper supply voltage.

[0025] 1 is a high-level block diagram of a system 100 that includes a pre-regulation circuit 102 that operates to receive a wide range of input voltages and provides an output voltage that operates within a much lower range. The pre-regulation circuit 102 does not provide as high precision at high input voltages as either the LDO regulator 902 or the DC-DC converter 932, but instead utilizes a simple circuit that provides an output voltage that is low enough to prevent damage to the internal circuitry 104, but does not starve the circuit. The LDO circuit following the pre-regulation circuit 102 does not require high voltage devices and can be designed only for low voltages.

[0026] The preregulation circuit 102 is coupled between a preregulator input node 110 providing an upper supply voltage VCC and a lower supply voltage, and is also coupled to provide a preregulator output voltage Vprereg to an internal circuit element 104 for the system 100. The internal circuit element 104 may also include, for example, an LDO, a driver, etc. When the upper supply voltage VCC is greater than a regulation threshold voltage, which is about 4V in one embodiment, a voltage regulator circuit 101 including a power NFET MNOUT operates during a regulation mode to provide a regulated output current. The voltage regulator circuit 101 also includes a current source CS1, a first capacitor C1, and a diode element 107. The power NFET MNOUT is coupled between the upper supply voltage VCC and a preregulator output node 103. A current source CS1 is coupled in series with a first capacitor C1 between an upper supply voltage VCC and a lower supply voltage, e.g., ground, and a gate of a power NFET MNOUT is coupled to a first node 105 between the current source CS1 and the first capacitor C1. A diode element 107 is coupled between the gate of the power NFET MNOUT and the lower supply voltage to regulate the preregulator output voltage Vprereg to a value equal to the voltage drop across the diode element minus the gate-to-source voltage Vgs of the power NFET MNOUT during regulation mode. In at least one embodiment, the power NFET MNOUT is a laterally diffused metal-oxide semiconductor field effect transistor (LDMOSFET).

[0027] A bypass circuit to avoid voltage regulation of the power NFET MNOUT is provided by a power PFET MPOUT, also coupled between the upper supply voltage VCC and the preregulator output node 103. The bypass circuit also includes a comparison circuit that can determine when to turn off the power PFET MPOUT, and may further include a pull-up circuit 108 to ensure that the power PFET MPOUT is turned off quickly. The comparison circuit 106 is powered by the upper supply voltage VCC and also receives an internal reference voltage Vintref. A first output of the comparison circuit 106 is coupled to the gate of the output PFET MPOUT. In at least one embodiment, a pull-up circuit 108 is coupled between the upper supply voltage VCC and the gate of the power PFET MPOUT and receives a second output of the comparison circuit 106.

[0028] The comparator circuit 106 compares the upper supply voltage VCC with an internal reference voltage Vintref and may compare either the voltage or the associated current. When the upper supply voltage VCC is equal to or less than the regulation threshold voltage, the power PFET MPOUT is turned on and passes the upper supply voltage VCC to the preregulator output node 103 with almost no voltage loss. This is achieved by making the power PFET MPOUT a large, low on-resistance transistor. When the upper supply voltage VCC is greater than the regulation threshold voltage, the power PFET MPOUT is turned off so that the preregulator output voltage Vprereg is regulated by the power NFET MNOUT. If desired, a pull-up circuit 108 may also be provided to ensure that the power PFET MPOUT is turned off completely and / or to turn off the power PFET MPOUT more quickly.

[0029] 2 illustrates a preregulator circuit 200 that may be used as an exemplary implementation of preregulator circuit 102. In preregulator circuit 200, a power NFET MNOUT, which in at least one embodiment is an LDMOSFET, is coupled between a preregulator input node 201 providing an upper supply voltage and a preregulator output node 214 to regulate the voltage in a regulation mode, as described below. Also, a power PFET MPOUT is coupled between preregulator input node 201 and preregulator output node 214 to provide a bypass circuit that bypasses regulation via power NFET MNOUT when the upper supply voltage is below a regulation threshold voltage.

[0030] Also, a first resistor R1 is coupled in series with a second resistor R2 and a first NFET MN1 between the upper supply voltage VCC and the lower supply voltage. The gate and drain of the first NFET MN1 are coupled together such that the first NFET MN1 acts as a diode. In one embodiment, the second resistor R2 is sized to have a resistance value that is 4.6 times the resistance value of the first resistor R1. A first PFET MP1 is coupled in series with a second NFET MN2 between the upper supply voltage VCC and the lower supply voltage. The gate of the second NFET MN2 is coupled together to the gate of the first NFET MN1 and to the gate and drain of the first PFET MP1. When the pre-regulator circuit 200 is turned on, a first current I1 flows through the first resistor R1, the second resistor R2, and the first NFET MN1, and a second current I2 flows through the first PFET MP1 and the second NFET MN2.

[0031] The pre-regulator circuit 200 also includes a second PFET MP2 coupled in series with a diode element comprised of a first Zener diode Z1 between the upper supply voltage VCC and the lower supply voltage, and the gate of the power NFET MNOUT is coupled to a first node 202 between the second PFET MP2 and the first Zener diode Z1 to receive the gate voltage Vz. In one embodiment, the current mirror formed by the first PFET MP1 and the second PFET MP2 forms the current source CS1 of FIG. 1. A first capacitor C1 is coupled between the gate of the power NFET MNOUT and the lower supply voltage, and a second capacitor C2 is coupled between the pre-regulator output node 214 and the lower supply voltage. A third PFET MP3 is coupled in series with the switching PFET MPSW and the third NFET MN3 between the upper supply voltage VCC and the lower supply voltage. The gate of the switching PFET MPSW is coupled to a second node 204 between the first resistor R1 and the second resistor R2 for receiving a gate voltage Vb, and the gate and drain of the third NFET MN3 are coupled together. The gate of the second PFET MP2 and the gate of the third PFET MP3 are respectively coupled to the gate of the first PFET MP1. When the upper supply voltage is greater than a Zener voltage, which is typically about 5V, a third current I3 flows through the second PFET MP2 and the first Zener diode Z1. When the switching PFET MPSW is turned on, a fourth current I4 flows through the third PFET MP3, the switching PFET MPSW, and the third NFET MN3.

[0032] Also, a fourth PFET MP4 is coupled in series with the fourth NFET MN4 between the upper supply voltage and the lower supply voltage. The gate of the fourth PFET MP4 is coupled to the gate of the first PFET MP1, and the gate of the fourth NFET is coupled to the gate of the third NFET MN3. Also, a fifth PFET MP5 is coupled in series with the fifth NFET MN5 between the upper supply voltage VCC and the lower supply voltage, and a fourth node 208 is interposed between the fifth PFET MP5 and the fifth NFET MN5. The gate of the fifth PFET MP5 is coupled to the gate of the first PFET MP1, and the gate of the fifth NFET MN5 is coupled to a third node 206 between the fourth PFET MP4 and the fourth NFET MN4 to receive a gate voltage Vpdn. A second Zener diode Z2 is coupled between the gate of the fifth NFET MN5 and the lower supply voltage.

[0033] The gate of the power PFET MPOUT is coupled to a fourth node 208 between the fifth PFET MP5 and the fifth NFET MN5 to receive the gate voltage Vg. A third Zener diode Z3 and a third resistor R3 are each coupled between the upper supply voltage and the gate of the power PFET MPOUT. When the switching transistor MPSW is turned on, a fifth current I5 flows through the fourth PFET MP4 and the fourth NFET MN4, and when the fifth NFET MN5 is turned on, a sixth current I6 flows through the fifth PFET MP5.

[0034] Also, a sixth PFET MP6 and a seventh PFET MP7 are coupled in series with the sixth NFET MN6 between the upper and lower supply voltages. The gate of the sixth PFET MP6 is coupled to the gate of the first PFET MP1, and the gate of the sixth NFET MP6 is coupled to the gate of the third NFET MN3. An eighth PFET MP8, a ninth PFET MP9, and a tenth PFET MP10 are each diode-coupled and coupled in series with the seventh NFET MN7 between the upper and lower supply voltages. The gate of the seventh NFET MN7 is coupled to the gate of the third NFET MN3, and the gate of the seventh PFET MP7 is coupled to a fifth node 210 between the tenth PFET MP10 and the seventh NFET MN7. When the sixth NFET MN6 and the seventh PFET MP7 are on, a seventh current I7 flows through the sixth PFET MP6, the seventh PFET MP7, and the sixth NFET MN6. Similarly, when the seventh NFET MN7 is on, an eighth current flows through the eighth PFET MP8, the ninth PFET MP9, the tenth PFET MP10, and the seventh NFET MN7. Finally, an eleventh PFET MP11 is coupled between the upper supply voltage and the fourth node 208, with the gate of the eleventh PFET MP11 coupled to a sixth node 212 between the sixth PFET MP6 and the seventh PFET MP7.

[0035] During operation of the pre-regulator circuit 200, the first current I1 is a function of the gate-source voltage Vgs of the first NFET MN1, the resistances of resistors R1 and R2, and the upper supply voltage VCC. As a result, in low voltage applications, the first current I1 is small, which helps meet low power requirements. The second current I2 through the eighth current I8 are also related to the first current I1 through various current mirrors, and therefore remain low when the upper supply voltage VCC is low.

[0036] As can be seen from the embodiment of the pre-regulator upper supply circuit 200, the circuit can be generally divided into four parts: a first part 222 including the first current I1 and the second current I2; a second part 224 including the third current I3, the fourth current I4, and the fifth current I5; a third part 226 including the sixth current I6 and both output circuits; and a fourth part 228 including the seventh current I7 and the eighth current I8. During low voltage operation, e.g., below 4V, only the first part 222 and the third part 226 consume power, as will be explained in more detail below. In one embodiment, a simple circuit that is active during low voltage implementation can use less than 500 nA of power. Only at higher voltages from the upper supply voltage VCC, i.e., voltages higher than the regulation threshold voltage, the second part 224 and the fourth part 228 consume power.

[0037] In one embodiment of FIG. 2, when operating below 4.0 volts, a first current I1 and a second current I2 flow through the respective circuits. The fourth PFET MP4 is on and pulls up the third node 206, turning on the fifth NFET MN5, which causes a sixth current I6 to flow. When the upper supply voltage VCC is below the regulation threshold voltage, the difference between the voltage drop across the third PFET MP3 and the voltage drop across resistor R1 is not large enough to allow the gate-source voltage Vgs of the switching PFET MPSW to conduct substantial current. This means that the current mirror of the third NFET MN3 and the fourth NFET MN4 is not turned on, and therefore the fourth current I4 does not flow.

[0038] More specifically, for switching PFET MPSW, the gate voltage Vb is equal to (VCC-I1 x R1), where R1 represents the resistance of resistor R1. The voltage across R1 required to turn on switching PFET MPSW is Vgsmpsw+Vdsatmp3, where Vgsmpsw is the gate / source voltage of switching PFET MPSW and Vdsatmp3 is the drain / source voltage at saturation of third PFET MP3. For low values ​​of VCC, the gate / source voltage of switching PFET MPSW is not high enough to turn on switching PFET MPSW. Third NFET MN3, fourth NFET MN4, sixth NFET MN6, and seventh NFET MN7 are all off, so fourth current I4, fifth current I5, seventh current I7, and eighth current I8 do not flow. While the fourth NFET MN4 is off, the fourth PFET MP4 pulls up the third node 206, turning on the fifth NFET MN5, which has a higher gate-to-source voltage than the fifth PFET MP5, so the gate voltage Vg of the fourth node 208 and the power PFET MPOUT is pulled low, turning the power PFET MPOUT fully on.

[0039] When the voltage VCC increases, the first current I1 increases, and I1×R1 increases accordingly. When I1×R1 is greater than Vgsmpsw+Vdsatmp3, the switching PFET MPSW turns on. Therefore, the values ​​of I1, R1, Vgsmpsw, and Vdsatmp3 can be used to define an adjustment threshold voltage that turns on the switching PFET MPSW, thereby causing the current I4 to flow to the third NFET MN3. The third NFET MN3 is diode-coupled and further coupled to the fourth NFET MN4, so that both the fourth current I4 and the fifth current I5 flow. The fourth NFET MN4 is designed to be a stronger transistor than the fourth PFET MP4, so that the third node 206 is pulled low. The third node 206 controls the gate voltage Vpdn for the fifth NFET MN5, which turns off the fifth NFET MN5. When the fifth NFET MN5 is turned off, the fifth PFET MP5 pulls up the gate voltage Vg for the power PFET MPOUT to the upper supply voltage VCC, turning off the power PFET MPOUT.

[0040] When the upper supply voltage VCC becomes greater than the regulation threshold voltage and the power PFET MPOUT is turned off, the source voltage of the power NFET MNOUT decreases, which turns on the power NFET MPOUT. The power NFET MNOUT may provide a preregulator output voltage Vprereg, which is the voltage of the Zener diode Z1 minus the gate / source voltage Vgs of the power NFET MNOUT. The Zener voltage is typically 5V and the gate / source voltage Vgs of the power NFET MNOUT is about 1V, so the preregulator output voltage Vprereg is regulated to about 4V via the power NFET MNOUT. As will be seen below, due to process and temperature variations, the preregulator output voltage Vprereg via the power NFET MNOUT may be as high as about 5.4V in some cases. In one embodiment, the maximum gate voltage allowed by the internal circuitry of the smoke alarm is about 6V, so the preregulator output voltage Vprereg does not need to be controlled as tightly as it would otherwise be.

[0041] When the switching transistor MPSW is fully on and acts to turn off the power PFET MPOUT, the sixth NFET MN6 and the seventh NFET MN7 are also turned on, thus activating the clamp circuit including the sixth through eleventh PFETs MP6 through MP11. The eighth PFET MP8, the ninth PFET MP9, and the tenth PFET MP10 are diode-coupled, such that the voltage at the fifth node 210 is equal to VCC-3×Vgs. The voltage at the fifth node 210 is provided to the gate of the seventh PFET MP7, which turns on the seventh PFET MP7 to provide the voltage VCC-2×Vgs at the sixth node 212, which turns on the eleventh PFET MP11. Turning on the eleventh PFET MP11 helps pull up the fourth node 208 so that the gate voltage Vg goes high, ensuring that the power PFET MPOUT is turned off quickly.

[0042] Those skilled in the art will appreciate that modifications to the circuit of FIG. 2 may be made within the spirit of the disclosed pre-regulator circuit 200. Pre-regulator circuit 200A of FIG. 2A illustrates one such modification. Pre-regulator circuit 200A is the same as pre-regulator circuit 200 except that the use of Zener diode Z1 as diode element 107 is replaced with stacked diode-connected NFETs MN8-MN12 that impose approximately the same limit on gate voltages as Zener diode Z1 on the pair, and thus pre-regulator circuit 200A provides the same benefits as pre-regulator circuit 200.

[0043] It should be noted that the voltage required for internal circuitry, such as internal circuitry 104 in FIG. 1, is extremely low. Conventional LDOs are generally designed to operate over a wide range of both input and output voltages. This is in contrast to the present application, where a wide input range and a narrow output range are required. By including two operating modes, e.g., a regulation mode when the upper supply voltage VCC is greater than the regulation threshold voltage and a bypass circuit when the upper supply voltage VCC is less than the regulation threshold voltage, any of the disclosed pre-regulators, e.g., pre-regulator circuit 102, pre-regulator circuit 200, and pre-regulator 200A, may use a simpler design to step down voltages.

[0044] Using the disclosed pre-conditioner, one or more of the following advantages may be achieved. The circuit does not require an external reference circuit or current source. Extremely low current consumption in Li-Ion battery applications at nominal temperature and process, thus enabling longer battery life in smoke detector applications. When the upper supply voltage VCC is lower than the regulation threshold voltage, the power PFET acts as a switch and transfers VCC directly to the pre-regulator output node. In Li-Ion battery applications, the voltage drop across the power PFET is negligible. When the upper supply voltage VCC is greater than the regulation threshold voltage, the preregulator output is controlled by the gate voltage Vz of the power NFET MNOUT, which is limited by the Zener voltage. The preregulator output voltage Vprereg is the gate voltage Vz minus the gate-source voltage Vgs of the power NFET MNOUT, and once the output reaches this value, the regulated output remains constant for upper supply voltages VCC as high as 15V.

[0045] FIG. 3 shows a graph 300 of simulated values ​​of the upper supply voltage VCC and the preregulator output voltage Vprereg under a 30 mA load after turning on the circuit with an upper supply voltage of 4V. The simulations vary across temperature and transistor parameters. When the circuit is turned on, the upper supply voltage VCC rises steadily until it reaches 4V in all embodiments. Different simulations take slightly different amounts of time for the preregulator output voltage Vprereg to begin to rise, but all simulations quickly achieve a steady rise to 4V for the preregulator output voltage Vprereg. When a 30mA load is applied, a small deviation in the preregulator output voltage Vprereg is observed. Removing the load returns to a steady output of 4V in all simulations. At 30mA current, the preregulator output voltage Vprereg ranges from a minimum of 3.9348V to a maximum of 3.956V, with a typical voltage of 3.95V. When the current was less than 1 μA, the preregulator output voltage Vprereg ranged from a minimum of 3.999V to a maximum of 4.0V, with a typical voltage of 3.999V.

[0046] FIG. 4 shows a graph 400 of simulated values ​​of the upper supply voltage VCC and the preregulator output voltage Vprereg, again under a 30 mA load, after turning on the circuit with an upper supply voltage of 15V. Again, the temperature and overall transistor parameters are varied. When the circuit is turned on, the upper supply voltage VCC rises steadily in all embodiments until it reaches 15V. After some small variations in the time at which the preregulator output voltage Vprereg starts to rise, the steady state of the preregulator output voltage Vprereg is shown to have a larger maximum voltage variation before and after the 30 mA load than when simply passing the upper supply voltage. When the current is 30mA, the preregulator output voltage Vprereg ranges from a minimum of 3.935V to a maximum of 3.956V, with a typical voltage of 3.945V. When the current is less than 1 μA, the preregulator output voltage Vprereg ranges from a minimum of 3.999V to a maximum of 4.0V, with a typical voltage of 3.999V.

[0047] 5 illustrates a graph 500 of the total quiescent current consumed by pre-regulator circuit 200 over process and temperature variations ranging from 0 to 85° C. at an upper supply voltage VCC of 4V. A low temperature range is shown on the left side of graph 500, where the quiescent current averaged 1.13 μA, and a high temperature range is shown on the right side of graph 500, where the quiescent current averaged 2.62 μA. A typical quiescent current is 1.66 μA.

[0048] 6 similarly illustrates a graph 600 of the total quiescent current consumed by the pre-regulator circuit 200 over process variations and temperature variations ranging from 0 to 85° C. at an upper supply voltage VCC of 15V. Again, a low temperature region is shown on the left side of the graph 600, where the quiescent current averaged 5.88 μA, and a high temperature region is shown on the right side of the graph 600, where the quiescent current averaged 9.88 μA. A typical quiescent current when the upper supply voltage VCC is 15V is 7.63 μA. Although the quiescent current at 15V is less favorable than the quiescent current at 4V, when the circuit receives 15V, the system is generally using a mains power source and the need to minimize current is not as critical as when employing battery power.

[0049] 7 is a block diagram of an electronic device that is a smoke detector 700 incorporating a pre-regulator circuit (pre-LDO) 720 according to an embodiment of the present disclosure. The smoke detector 700 includes an IC chip 701 on which a number of circuits are implemented, including a pre-regulator circuit 720, which may be implemented using the circuits shown in one of the pre-regulator circuits 102 and 200 and the method described in FIG. 8. The IC chip 701 also includes a carbon monoxide detection circuit 704, a light detection circuit 706, an optional ion detection circuit 708, and a horn driver 721. In one embodiment, the light detection circuit 706 also includes a first light emitting diode (LED) driver 712 and a second LED driver 714. The carbon monoxide detection circuit 704 is coupled to a first plurality of pins 705, the light detection circuit 706 is coupled to a second plurality of pins 707, and the horn driver 721 is coupled to a third plurality of pins 711. A multiplexer 710 coupled to a fifth pin P5 that is part of a fourth plurality of pins 713 may receive input signals from each of the carbon monoxide detection circuit 704 and the light detection circuit 706. If an optional ion detection circuit 708 is provided, the ion detection circuit 708 is coupled to a fifth plurality of pins 709 and the multiplexer 710 is also coupled to receive an input signal from the ion detection circuit 708. A horn driver 721 may be provided for driving a horn 729.

[0050] Four specific power supply pins of the IC chip 701 are shown: a first pin P1, a second pin P2, a third pin P3, and a fourth pin P4. A pre-regulator circuit 720 is coupled to the first pin P1, which is also coupled to an AC / DC converter 732. The pre-regulator circuit 720 is also coupled to a second pin P2 (coupling not specifically shown) for receiving a lower supply voltage. A DC / DC boost converter 702 is coupled to the third pin P3 for receiving power from a battery BAT via an inductor L, and is also coupled to a fourth pin P4 for providing an output voltage Vbst boosted from the battery power. The fourth pin P4 is also coupled to the first pin P1 for providing a boosted output voltage Vbst to the pre-regulator circuit 720 when dependent on the battery power. The second pin P2 is coupled to a ground plane, although no internal connections to the circuit are specifically shown.

[0051] The pre-regulator circuit 720 provides a pre-regulator output voltage Vprereg that is used to provide a gate driver supply voltage VCC for the internal circuitry on the IC chip 701. The pre-regulator output voltage Vprereg may be distributed to a microcontroller (MCU) LDO regulator 716, an internal LDO regulator 718, and a VCC voltage divider 719. The MCU LDO regulator 716 provides a supply voltage to the MCU 730 and I / O buffers (not specifically shown), the internal LDO regulator 718 provides a supply voltage to internal circuits such as the data core and analog blocks, e.g., the carbon monoxide detection circuit 704, the light detection circuit 706, and the ion detection circuit 708, and the VCC voltage divider 719 provides a supply voltage to the multiplexer 710.

[0052] In the smoke detector 700, the carbon monoxide detection circuit 704 is coupled to a carbon monoxide sensor 722 via a first plurality of pins 705, the light detection circuit 706, which may include a first LED driver 712 and a second LED driver 714, is coupled to a light sensor 724 and an LED 726 via a second plurality of pins 707, the ion detection circuit 708 is coupled to an ion sensor 728 via a fifth plurality of pins 709, and the horn driver 721 is coupled to a horn 729 via a third plurality of pins 711. The carbon monoxide sensor 722, the photo sensor 724, and the ion sensor 728 collect information required to detect smoke and carbon monoxide in the area, and the horn 729 issues a loud audible warning when smoke or carbon monoxide is detected. The IC chip 701 is also coupled to a microcontroller 730 via a fourth plurality of pins 713, providing both power and information to the microcontroller 730 and receiving instructions to control various aspects of the operation of the smoke detector 700. A fifth pin P5, which is part of a fourth plurality of pins 713, provides a path for the multiplexer 710 to provide the outputs of the carbon monoxide detection circuit 704, the light detection circuit 706, and the ion detection circuit 708 to the MCU 730.

[0053] FIG. 8 illustrates a method 800 of operating a pre-regulator circuit for an LDO regulator. The method begins with receiving (805) an upper supply voltage at a power input node having a range between a lower limit and an upper limit with a difference of at least 10 volts. In one embodiment, the lower limit is about 3.3V and the upper limit is about 15V, so that the difference is about 12V. The method determines (810) whether the upper supply voltage is greater than a regulation threshold voltage. In one embodiment, the regulation threshold voltage is about 4V. If the upper supply voltage is not greater than the regulation threshold voltage, the upper supply voltage is passed directly to a power output node coupled to provide power to the LDO regulator (815). If the upper supply voltage is greater than the regulation threshold voltage, the method adjusts the upper supply voltage and provides the regulated voltage at the power output node (820).

[0054] Applicant has disclosed an electronic device and method for expanding the input voltage of an LDO regulator without the need for a high voltage device by providing a pre-regulator circuit. The electronic device can be a circuit, an IC chip, or a system, such as a smoke detector. The pre-regulator circuit consumes very little current when a low voltage battery input is provided, making it highly suitable for battery applications and providing the maximum battery voltage to the LDO regulator. The pre-regulator circuit does not require an external bias current or reference voltage to function. The same resistor that generates the bias current can be used to switch from the PMOS pass FET to the LDMOSFET when VCC crosses the regulation threshold voltage.

[0055] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. The above detailed description should not be read as implying that any particular component, element, step, operation, or function is essential to be included in the claims. Reference to an element in the singular does not mean "only one" unless expressly stated otherwise, but means "one or more." All structural and functional equivalents to the elements of the above-described embodiments known to those skilled in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Thus, those skilled in the art will appreciate that the exemplary embodiments described herein can be practiced with various modifications and alterations within the spirit and scope of the claims appended below.

Claims

1. 1. An electronic device comprising:

1. A voltage regulator circuit comprising: a power N-type field effect transistor (NFET) coupled between an upper supply voltage and a preregulator output node, the power NFET having a gate coupled to the first node; a first P-type field effect transistor (PFET) coupled between the upper supply voltage and the first node; a diode element coupled between the first node and a lower supply voltage; the voltage regulator circuit comprising: a bypass circuit including a power P-type field effect transistor (PFET) coupled between the upper supply voltage and the preregulator output node; a comparison circuit configured to turn off the bypass circuit when the upper supply voltage is greater than an adjustment threshold voltage, a first resistor having a first terminal coupled to the upper supply voltage and a second terminal coupled to a second node; a second resistor having a first terminal coupled to the second node and a second terminal; a first NFET coupled between a second terminal of the second resistor and the lower supply voltage, the first NFET having a gate coupled to the second terminal of the second resistor; a second NFET coupled to the lower supply voltage, the second NFET having a gate coupled to the gate of the first NFET; a second PFET coupled between the upper supply voltage and the second NFET, the second PFET having a gate coupled to the second NFET and to a gate of the first PFET; the comparison circuit, 2. An electronic device comprising:

2. 2. The electronic device of claim 1, The voltage regulator circuit comprises: a first capacitor coupled between the gate of the power NFET and the lower supply voltage; a second capacitor coupled between the source of the power NFET and the lower supply voltage; The electronic device further comprises:

3. 2. The electronic device of claim 1, The electronic device, wherein the diode element includes a first Zener diode.

4. 4. The electronic device of claim 3, The comparison circuit, a third PFET coupled to the upper supply voltage, the third PFET having a gate coupled to the gate of the first PFET; a switching PFET coupled in series with the third PFET, the switching PFET having a gate coupled to the second node; a third NFET coupled between the switching PFET and the lower supply voltage, the third NFET having a gate coupled to the switching PFET; a fourth PFET coupled between the upper supply voltage and a third node, the fourth PFET having a gate coupled to the gate of the first PFET; a fourth NFET coupled between the third node and the lower supply voltage, the fourth NFET having a gate coupled to a gate of the third NFET; a fifth PFET coupled between the upper supply voltage and a fourth node coupled to the gate of the power PFET, the fifth PFET having a gate coupled to the gate of the first PFET; a fifth NFET coupled between the fourth node and the lower supply voltage, the fifth NFET having a gate coupled to the third node; a second Zener diode coupled between the gate of the fifth NFET and the lower supply voltage; a third Zener diode coupled between the upper supply voltage and the gate of the power PFET; a third resistor coupled between the upper supply voltage and the gate of the power PFET; The electronic device further comprises:

5. 2. The electronic device of claim 1, The electronic device further comprising a pull-up circuit coupled between the upper supply voltage and a gate of the power PFET, the pull-up circuit coupled to be controlled by the comparison circuit.

6. 6. The electronic device of claim 5, The pull-up circuit is a sixth PFET coupled between the upper supply voltage and a sixth node, the sixth PFET having a gate coupled to a gate of the first PFET; a seventh PFET coupled to the sixth node, the seventh PFET having a gate; a sixth NFET coupled between the seventh PFET and the lower supply voltage, the sixth NFET having a gate coupled to a gate of the third NFET; an eighth PFET coupled to the upper supply voltage, the eighth PFET having a gate and a drain coupled together; a ninth PFET coupled to the drain of the eighth PFET, the ninth PFET having a gate and a drain coupled together; a tenth PFET coupled between the drain of the ninth PFET and a fifth node, the tenth PFET having a gate and a drain coupled together, the gate of the tenth PFET being coupled to the gate of the seventh PFET; a seventh NFET coupled between the drain of the tenth PFET and the lower supply voltage, the seventh NFET having a gate coupled to the gate of the third NFET; an eleventh PFET coupled between the upper supply voltage and the sixth node, the eleventh PFET having a gate coupled to the sixth node; 2. An electronic device comprising:

7. 2. The electronic device of claim 1, The electronic device, wherein the voltage regulator circuit, the bypass circuit and the comparison circuit are fabricated on an integrated circuit (IC) chip.

8. 8. The electronic device of claim 7, The electronic device further comprising an LDO regulator configured to provide power to at least one circuit, the LDO regulator being fabricated on the IC chip.

9. 9. The electronic device of claim 8, The IC chip is a first pin coupled to the AC / DC converter; a second pin coupled to the ground plane; a third pin coupled to the battery; a fourth pin for providing a boosted output voltage from the battery; 2. An electronic device comprising:

10. 10. The electronic device of claim 9, A carbon monoxide detection circuit; A photodetection circuit; Horn driver and a multiplexer coupled to receive outputs from the carbon monoxide detection circuit and the optical detection circuit; Further comprising: the IC chip further comprising a first plurality of pins coupled to the carbon monoxide detection circuit, a second plurality of pins coupled to the photo detection circuit, a third plurality of pins coupled to the horn driver, and a fifth pin coupled to the multiplexer, the fifth pin communicating the output.

11. 11. The electronic device of claim 10, a smoke detector including a carbon monoxide sensor coupled to the first plurality of pins, a light sensor coupled to the second plurality of pins, a horn coupled to the third plurality of pins, and a microcontroller; The electronic device, wherein the IC chip includes a fourth plurality of pins coupled to the microcontroller, the fourth plurality of pins including the fifth pin.

12. 11. The electronic device of claim 10, further comprising an ion detection circuit; The electronic device, wherein the IC chip further comprises a fifth plurality of pins coupled to the ion detection circuitry, and the multiplexer is further coupled to receive an output from the ion detection circuitry.

13. 13. The electronic device of claim 12, The electronic device further comprising a smoke detector, the smoke detector including an ion sensor coupled to the fifth plurality of pins.

14. 1. A method of operating a pre-regulator circuit for a low drop out (LDO) regulator, comprising: receiving an upper supply voltage having a range between a lower limit and an upper limit having a difference of at least 10 volts at a preregulator input node; determining whether the upper supply voltage is greater than an adjustment threshold voltage using a comparison circuit; passing the upper supply voltage directly to a pre-regulator output node coupled to the LDO regulator if the upper supply voltage is not greater than the regulation threshold voltage; adjusting the upper supply voltage when the upper supply voltage is greater than the adjustment threshold voltage to provide a regulated output voltage at the pre-regulator output node; Including, The comparison circuit, a first resistor having a first terminal coupled to the upper supply voltage and a second terminal; a second resistor having a first terminal coupled to the second terminal of the first resistor and a second terminal; a first N-type field effect transistor (NFET) coupled between the second terminal of the second resistor and a lower supply voltage, the first NFET having a gate coupled to the second terminal of the second resistor; a second NFET coupled to the lower supply voltage, the second NFET having a gate coupled to the gate of the first NFET; a first P-type field effect transistor (PFET) coupled between the upper supply voltage and the second NFET, the first PFET having a gate coupled to the second NFET; A method comprising:

15. 15. The method of claim 14, The method, wherein adjusting the upper supply voltage includes limiting a gate voltage of a power NFET with a diode element.

16. 16. The method of claim 15, The method further comprising using an N-type LDMOSFET as the power NFET.

17. 15. The method of claim 14, The method of claim 1, wherein the lower limit is about 2 volts and the upper limit is about 15 volts.

18. 20. The method of claim 17, The method, wherein the adjustment threshold voltage is about 4V.

19. 15. The method of claim 14, The method of claim 1, wherein the regulated output voltage is constant for input voltages greater than the regulation threshold voltage.

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