Photoelectric conversion device and electronic device

Abstract

To provide a photoelectric conversion device and an electronic device, in which conversion accuracy of a delta-sigma analog-to-digital converter can be improved.SOLUTION: A photoelectric converter includes: a plurality of pixel units in each of which a plurality of pixels each including a photoelectric conversion element is arranged in a matrix; and a plurality of signal processors each of which is configured to process a pixel signal output from the pixel unit. The signal processor includes a ΔΣ AD converter 450 configured to convert the pixel signal into a digital signal. The ΔΣ AD converter 450 includes: a subtracter 45 which includes a first input terminal to which the pixel signal is input and a second input terminal to which a subtraction signal is input; an integrator 40 configured to receive output from the subtracter 45; a comparator 41 configured to compare output from the integrator 40 with a predetermined voltage; a decimation filter 43 configured to generate the digital signal on the basis of a comparison result output from the comparator; a delay unit 46 configured to delay output from the comparator; a buffer unit 411 configured to buffer output from the delay unit; and a D / A converter 44 configured to convert output from the buffer unit into an analog signal to generate the subtraction signal.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and an electronic device. [Background technology]

[0002] Patent Document 1 discloses a solid-state imaging device that uses a delta-sigma (ΔΣ) type analog-to-digital (AD) converter in its analog-to-digital conversion section. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 Summary of the Invention [Problem to be solved by the invention]

[0004] In the ΔΣ AD converter shown in Patent Document 1, the operation of a digital-to-analog (DA) converter is controlled by a signal output from a quantizer (comparator). The signal for controlling the DA converter may be delayed due to parasitic resistance and parasitic capacitance of the wiring pattern from the comparator to the DA converter. If the amount of signal delay changes due to manufacturing variations or environmental changes such as temperature, conversion errors may occur in each ΔΣ AD converter, and the operation of the ΔΣ AD converter may vary between columns, resulting in a decrease in the accuracy of AD conversion.

[0005] An object of the present invention is to provide a technique that is advantageous for improving the conversion accuracy of a delta-sigma analog-to-digital converter. [Means for solving the problem]

[0006] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device including a pixel section in which a plurality of pixels each including a photoelectric conversion element are arranged in a matrix, and a signal processing section that processes a pixel signal output from the pixel section via a vertical signal line, wherein the signal processing section includes a ΔΣ AD converter that converts the pixel signal into a digital signal, and the ΔΣ AD converter includes a subtractor having a first input to which the pixel signal is input and a second input to which a subtraction signal is input, an integrator that receives the output of the subtractor, a comparator that compares the output of the integrator with a predetermined voltage, a decimation filter that generates the digital signal based on the comparison result output from the comparator, a delay section that delays the output of the comparator, a buffer section that buffers the output of the delay section, and a DA converter that converts the output of the buffer section into an analog signal and generates the subtraction signal. Effect of the Invention

[0007] According to the present invention, it is possible to provide a technique that is advantageous for improving image quality in a photoelectric conversion device using a delta-sigma type analog-to-digital converter. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an outline of the configuration of a photoelectric conversion device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device in FIG. [Diagram 3] 2 is a diagram showing an example of the configuration of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1; [Figure 4] 2 is a diagram showing an example of the configuration of a buffer unit of a ΔΣ AD converter in the photoelectric conversion device of FIG. 1; [Diagram 5] 2 is a diagram showing an example of the configuration of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1; [Figure 6] 2 is a diagram showing an example of the configuration of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1; [Figure 7] 2 is a diagram showing an example of the configuration of a buffer unit of a ΔΣ AD converter in the photoelectric conversion device of FIG. 1; [Figure 8]2 is a diagram showing an example of the configuration of a ΔΣ AD converter of the photoelectric conversion device of FIG. 1; [Figure 9] 2 is a diagram showing an example of the configuration of a DA converter of a ΔΣ AD converter in the photoelectric conversion device of FIG. 1; [Figure 10] 2 is a diagram showing an example of the configuration of a buffer unit of a ΔΣ AD converter in the photoelectric conversion device of FIG. 1; [Figure 11] 2 is a diagram showing an example of the configuration of a current-voltage conversion circuit of the photoelectric conversion device of FIG. 1; [Figure 12] FIG. 1 is a diagram showing an example of the configuration of a camera incorporating a photoelectric conversion device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0010] A photoelectric conversion device according to an embodiment of the present disclosure will be described with reference to Figs. 1 to 12. Fig. 1 is a block diagram showing an example of a configuration of a photoelectric conversion device 100 according to this embodiment. The photoelectric conversion device 100 includes a pixel unit 10 and a signal processing unit 600 that processes pixel signals output from the pixel unit 10 via a vertical signal line 12. The signal processing unit 600 includes a current source unit 200, a sample and hold unit 300, an analog-to-digital (AD) conversion unit 400, a digital signal processing unit 500, and an output unit 800. The photoelectric conversion device 100 may be a so-called CMOS image sensor.

[0011] A plurality of pixels 11, each including a photoelectric conversion element, are arranged in a matrix in the pixel section 10. Here, the row direction refers to the left-right direction in Fig. 1, and the column direction refers to the up-down direction in Fig. 1. The pixels 11 generate signal charges according to incident light.

[0012] In the pixel section 10, vertical signal lines 12 are arranged in the column direction corresponding to pixel columns in which the pixels 11 are arranged. The vertical signal lines 12 may be arranged such that one vertical signal line corresponds to one pixel column, or a plurality of vertical signal lines may be arranged for one pixel column. The vertical signal lines 12 transfer pixel signals corresponding to signal charges generated by photoelectric conversion elements of the pixels 11 from the pixels 11 to the sample hold section 300.

[0013] The current source sections 200 are arranged corresponding to the respective vertical signal lines 12. The current source sections 200 supply bias currents via the vertical signal lines 12 to the pixels 11 selected to read out pixel signals.

[0014] The sample and hold unit 300 samples and holds signals generated by the photoelectric conversion elements of the respective pixels 11 from the pixel unit 10 via the vertical signal line 12. For example, in the sample and hold unit 300, two sample and hold circuits may be connected to one vertical signal line 12: a sample and hold circuit that samples a signal when the photoelectric conversion element is reset, and a sample and hold circuit that samples a signal when the photoelectric conversion element performs a photoelectric conversion operation.

[0015] The AD conversion unit 400 performs analog-to-digital conversion on the pixel signal input from the sample-and-hold unit 300 via a signal line 401. In the AD conversion unit, a delta-sigma (ΔΣ) analog-to-digital converter (hereinafter sometimes referred to as a ΔΣ AD converter) that converts an analog pixel signal into a digital signal is connected to each vertical signal line 12. The ΔΣ AD converter will be described later.

[0016] The digital signal processing unit 500 processes the digital signal output from the AD conversion unit 400 via a signal line 501. For example, correction processing, complementation processing, etc. may be performed on the digital signal output from the AD conversion unit 400. The output unit 800 outputs the signal processed by the digital signal processing unit 500 from the photoelectric conversion device 100 to the outside.

[0017] FIG. 2 is a circuit diagram showing a configuration example of a pixel 11. The pixel 11 includes a photoelectric conversion element 13, a transfer transistor 14, a reset transistor 15, an amplification transistor 16, and a selection transistor 17. The photoelectric conversion element 13 can be, for example, a photodiode. One of the main electrodes of the photoelectric conversion element 13 is connected to a ground potential GND, and the photoelectric conversion element 13 photoelectrically converts received light into a signal charge (for example, photoelectrons) having an amount of charge corresponding to the amount of light, and accumulates the signal charge. The other of the main electrodes of the photoelectric conversion element 13 is electrically connected to the gate electrode of the amplification transistor 16 via the transfer transistor 14. The node FD to which the gate electrode of the amplification transistor 16 is electrically connected functions as a floating diffusion. The node FD functioning as a floating diffusion is a charge-voltage conversion unit that converts the signal charge generated by the photoelectric conversion element 13 into a signal voltage.

[0018] A transfer signal PTX is supplied to the gate electrode of the transfer transistor 14. When the transfer transistor 14 becomes conductive in response to the transfer signal PTX, a signal charge that is photoelectrically converted by the photoelectric conversion element 13 and accumulated in the photoelectric conversion element 13 is transferred to a node FD that functions as a floating diffusion.

[0019] The reset transistor 15 is connected between a power supply potential VDD and a node FD. Here, when a transistor is expressed as being connected between A and B, it means that one of the main electrodes of the transistor is connected to A, and the other of the main electrodes is connected to B. In addition, the gate electrode of the transistor is not connected to A or B.

[0020] A reset signal PRES is supplied to the gate electrode of the reset transistor 15. When the reset transistor 15 becomes conductive in response to the reset signal PRES, the potential of the node FD (floating diffusion) is reset to the power supply potential VDD, and the charge accumulated in the floating diffusion is swept away.

[0021] The amplification transistor 16 is connected between a power supply potential VDD and the selection transistor 17, and the gate electrode of the amplification transistor 16 is connected to a node FD. The amplification transistor 16 serves as an input section of a source follower that reads out a signal obtained by photoelectric conversion of the photoelectric conversion element 13. That is, the other of the main electrodes of the amplification transistor 16 is connected to the vertical signal line 12 via the selection transistor 17. The amplification transistor 16 and the above-mentioned current source section 200 connected to the vertical signal line 12 constitute a source follower that converts the voltage of the node FD into the potential of the vertical signal line 12.

[0022] The selection transistor 17 is connected between the amplification transistor 16 and the vertical signal line 12. A selection signal PSEL is supplied to a gate electrode of the selection transistor 17. When the selection transistor 17 becomes conductive in response to the selection signal PSEL, the pixel 11 is put into a selected state, and a signal output from the amplification transistor 16 is transmitted to the vertical signal line 12.

[0023] The circuit configuration of the pixel 11 is not limited to the configuration shown in FIG. 2. For example, the selection transistor 17 may be connected between the power supply potential VDD and the amplification transistor 16. In addition, in the configuration shown in FIG. 2, the pixel 11 has a so-called four-transistor (4Tr.) type configuration including the transfer transistor 14, the reset transistor 15, the amplification transistor 16, and the selection transistor 17, but is not limited to this. For example, the pixel 11 may have a 3Tr. type configuration in which the selection transistor 17 is omitted and the amplification transistor 16 also functions as the selection transistor. In addition, a 5Tr. type or more configuration in which the number of transistors is increased according to the specifications required for the photoelectric conversion device 100 may be used for the pixel 11.

[0024] Next, a ΔΣAD converter 450 that is disposed in the AD conversion unit 400 and converts a pixel signal into a digital signal will be described with reference to FIG. 3(a). The ΔΣAD converter 450 includes a subtractor 45, an integrator 40, a comparator 41 (which may also be called a quantizer), a digital-to-analog (DA) converter 44, and a decimation filter 43. The subtractor 45 has an input (+) to which a pixel signal is input from the sample-and-hold unit 300 via a signal line 401, and an input (-) to which a subtraction signal is input. The integrator 40 receives the output of the subtractor 45, integrates it, and outputs the integrated value to the comparator 41 via a signal line 405. The comparator 41 compares the output of the integrator 40 with a predetermined voltage. When the output of the comparison result signal of the comparator 41 is 1 bit, the predetermined voltage may be one type. When the output of the comparator 41 is 2 bits or more, the comparator 41 outputs a comparison result obtained by comparing a plurality of types of voltages with the output of the integrator 40. The decimation filter 43 generates a digital signal based on the comparison result output from the comparator 41 via the signal line 42, and outputs it to the digital signal processing unit 500 via the signal line 501. The DA converter 44 converts the output of the comparator 41 via the vertical signal line 12 into an analog signal, and generates a subtraction signal to be output to the input (-) of the subtractor 45. The subtractor 45 feeds back a previously sampled data value to the pixel signal by taking the difference between the pixel signal supplied to the input (+) and the subtraction signal supplied to the input (-), thereby reducing quantization noise. In FIG. 3(a), the signal line 20 may be at the ground potential GND.

[0025] In order to feed back the subtraction signal output from the comparator 41 to the pixel signal input to the subtractor 45, in the configuration shown in FIG. 3(a), the ΔΣ AD converter 450 is provided with a delay unit 46 that delays the comparison result signal output from the comparator 41. Meanwhile, the integrator 40 and the comparator 41 may also cause delays with respect to the signal input to the ΔΣ AD converter 450. In addition, delays may also occur due to parasitic loads such as the signal lines 405 and 42 in the ΔΣ AD converter 450. For this reason, the delay unit 46 can be said to represent delay components in the circuits and signal lines in the ΔΣ AD converter 450. Therefore, there may be cases where no element is provided in the ΔΣ AD converter 450 as the delay unit 46.

[0026] The DA converter 44 is controlled by the output (comparison result) of the comparator 41. As described above, the output of the comparator 41 for controlling the DA converter 44 may be delayed due to parasitic resistance and parasitic capacitance of the wiring pattern of the signal line 42 from the comparator 41 to the DA converter 44. For example, when the signal line 42 has a layout extending in one direction like a column circuit, the influence of the parasitic load of the signal line 42 becomes large, and the signal is delayed. In addition, the amount of this delay may change due to manufacturing variations of the photoelectric conversion device 100 and environmental changes such as temperature. Variations and changes in the amount of delay cause conversion errors in the ΔΣAD converter 450 and variations in operation between the ΔΣAD converters 450 arranged corresponding to each vertical signal line 12. As a result, the image quality of the image obtained by the photoelectric conversion device 100 may be deteriorated.

[0027] Therefore, in this embodiment, a buffer unit 411 that buffers the signal output from the comparator 41 and input to the DA converter 44 via the signal line 42 is provided between the comparator 41 and the DA converter 44. Control of the DA converter 44 affects the accuracy of AD conversion by the ΔΣAD converter 450. For this reason, the driving force of the DA converter 44 for the output of the comparator 41 is improved, and an appropriate delay amount is added, thereby reducing the influence of the variation in the delay amount caused by a parasitic load, etc., and suppressing deterioration of the accuracy of the AD conversion. In addition, the variation in the delay amount between columns corresponding to each vertical signal line 12 can also be reduced by providing the buffer unit 411, and the variation in the AD conversion between columns can be reduced.

[0028] The buffer unit 411 may include an amplifier 423 configured by a two-stage inverter circuit 420 or the like, as shown in FIG. 4(a), for example. The buffer unit 411 buffers the output of the comparator 41, whereby the output of the comparator 41 (the output of the delay unit 46) is amplified, and waveform shaping, impedance conversion, and the like are performed, thereby improving the accuracy of the AD conversion. In addition, for example, the buffer unit 411 may include a level shifter 424 as shown in FIG. 4(b), and the output of the comparator 41 may be level-converted. When there is a mismatch between the output of the comparator 41 (for example, a power supply voltage) and the control voltage of the DA converter 44, the signal is boosted or lowered in the buffer unit 411, so that the DA converter 44 can be operated appropriately. The circuit configurations of the amplifier 423 and the level shifter 424 are not limited to those shown in FIG. 4(a) and FIG. 4(b), and circuits of appropriate configurations may be used.

[0029] FIG. 3(a) shows a case where a voltage signal is input as a pixel signal via a signal line 401. On the other hand, FIG. 3(b) shows a case where a current signal is input as a pixel signal to the ΔΣAD converter 450. When a current signal is supplied as a pixel signal to the ΔΣAD converter 450 via the signal line 401, the signal output from the pixel 11 is a voltage signal as described above, so that the signal processing unit 600 needs to convert the pixel signal from a voltage signal to a current signal. Therefore, the signal processing unit 600 further includes a conversion circuit that converts the pixel signal from a voltage signal to a current signal. For example, the sample hold unit 300 may be configured to include a conversion circuit so that the signal output from the sample hold unit 300 becomes a current signal. Also, for example, as shown in FIG. 3(b), a conversion circuit 47 that converts a voltage signal to a current signal may be disposed between the sample hold unit 300 and the ΔΣAD converter 450. With this configuration, the pixel signal converted into a current signal is input to the subtractor 45. As described above, the delay unit 46 represents the delay component in the circuits and signal lines within the ΔΣ AD converter 450, and since there may be cases where no element is arranged as the delay unit 46, the delay unit 46 is not shown in Figures 3(b) and onwards.

[0030] 3(c) is a more specific configuration example of the ΔΣAD converter 450 to which the pixel signal converted into a current signal is input. A capacitive element 402 is arranged as the above-mentioned integrator 40. Also, a DA converter 403 is arranged as the above-mentioned DA converter 44. The capacitive element 402 is connected in parallel with the DA converter 403. In the configuration shown in FIG. 3(c), the DA converter 403 may include a current source for supplying a current to a signal line 405. Also, a change in the amount of current (for example, a change between supplying and not supplying a current) that the DA converter 403 supplies to the signal line 405 in response to the output (comparison result) of the comparator 41 corresponds to the operation of the above-mentioned subtractor 45.

[0031] The ΔΣAD converter disposed in the AD conversion unit 400 is not limited to a configuration that performs first-order ΔΣ modulation, such as the ΔΣAD converter 450 shown in FIG. 3(a) to FIG. 3(c). As shown in FIG. 5(a), a ΔΣAD converter 451 that performs second-order ΔΣ modulation may be disposed in the AD conversion unit 400. The subtractor 45 shown in FIG. 3(a) is set as the subtractor 45a, the integrator 40 as the integrator 40a, and the DA converter 44 as the DA converter 44a. In this case, the ΔΣAD converter 451 further includes an integrator 40b, a subtractor 45b, and a DA converter 44b. The integrator 40b is connected between the integrator 40a and the comparator 41. The subtractor 45b has an input (+) that receives the output of the integrator 40a and an input (-) that receives a subtraction signal from the DA converter 44b. The subtractor 45b outputs the subtraction result to the integrator 40b. As the buffer unit 411, a buffer unit 411a is disposed between the comparator 41 and the DA converter 44a, and a buffer unit 411b is disposed between the comparator 41 and the DA converter 44b. The DA converter 44b converts the output of the buffer unit 411b into an analog signal and generates a subtraction signal to be supplied to the subtractor 45b.

[0032] The buffer units 411a and 411b, like the configuration shown in FIG. 3(a), play a role of impedance conversion to relay the comparison result output by the comparator 41. This can reduce the rounding of the waveform of the signal indicating the comparison result. In addition, by adding a delay amount, the influence of the variation in the delay amount is reduced, and deterioration of the accuracy of the AD conversion is suppressed. The buffer units 411a and 411b may include an amplifier 423 as shown in FIG. 4(a), for example. The accuracy of the AD conversion is further improved by the ΔΣ AD converter 451 performing second-order ΔΣ modulation. In addition, a ΔΣ AD converter having a configuration performing higher-order ΔΣ modulation such as third order or higher may be arranged in the AD conversion unit 400.

[0033] As shown in FIG. 5(a), two buffer units 411a and 411b may be arranged as the buffer unit, but the present invention is not limited thereto. For example, only the buffer unit 411b may be arranged in the ΔΣAD converter 451. Even in this case, the output of the comparator 41 supplied to the DA converter 44a and the DA converter 44b can be buffered. Also, for example, only the buffer unit 411a may be arranged in the ΔΣAD converter 451. The distance from the output end of the comparator 41 to the input end of the DA converter 44a is longer than the distance from the output end of the comparator 41 to the input end of the DA converter 44b, and the influence of the parasitic load of the signal line 42 may become greater. The buffer unit 411a is arranged only between the output unit of the comparator 41 and the input unit of the DA converter 44a, and the buffered signal is supplied to the DA converter 44a, and no buffer unit is provided between the output unit of the comparator 41 and the input unit of the DA converter 44b. This reduces the difference in the influence of parasitic loads between the output terminal of comparator 41 and the input terminal of DA converter 44a and the output terminal of comparator 41 and the input terminal of DA converter 44b, thereby improving the accuracy of AD conversion.

[0034] FIG. 5(b) is a diagram showing a configuration example of performing second-order ΔΣ modulation when a pixel signal converted into a current signal is input to a ΔΣAD converter 451. Two sets of a capacitive element 402 and a DA converter 403 are arranged. The capacitive element 402a functions as the integrator 40a in FIG. 5(a), and the DA converter 403a functions as the subtractor 45a and the DA converter 44a in FIG. 5(a). Similarly, the capacitive element 402b functions as the integrator 40b in FIG. 5(a), and the DA converter 403b functions as the subtractor 45b and the DA converter 44b in FIG. 5(a). The capacitive element 402b is connected in parallel with the DA converter 403b. A current-voltage conversion circuit 48 is arranged between the two sets. For example, a Gm amplifier as shown in FIG. 11 may be used for the current-voltage conversion circuit 48. The conversion circuit 47 for supplying a current signal to the ΔΣAD converter 451 and the current-voltage conversion circuit 48 may be conversion circuits having the same configuration, or may be circuits having different configurations. Appropriate circuits may be used depending on the specifications of the conversion circuit 47 and the current-voltage conversion circuit 48.

[0035] Next, a modified example of the ΔΣ AD converter 451 shown in Fig. 5(b) will be described with reference to Fig. 6, Fig. 7(a), and Fig. 7(b). In the ΔΣ AD converter 451 shown in Fig. 5(b), the output of the buffer unit 411b is supplied to the buffer unit 411a and the DA converter 403b via a common signal line 480. On the other hand, in the ΔΣ AD converter 452 shown in Fig. 6, the output of the buffer unit 411b is supplied to the buffer unit 411a via the signal line 480, and is supplied to the DA converter 403b via a signal line 482 separate from the signal line 480.

[0036] Fig. 7(a) shows a configuration example of the buffer unit 411a, and Fig. 7(b) shows a configuration example of the buffer unit 411b. As shown in Fig. 7(a) and Fig. 7(b), the buffer units 411a and 411b include a phase adjuster 421. This allows the buffer units 411a and 411b to adjust the phase of the output of the comparator 41.

[0037] The phase adjustment may be performed on both the signal supplied to the DA converter 403a and the signal supplied to the DA converter 403b, or on one of the signals supplied to the DA converter 403a or the DA converter 403b. The combination for performing the phase adjustment can be switched by appropriately selecting the conductive or non-conductive state of each of the switches S0 to S3 shown in FIG. 7(a) and FIG. 7(b). At this time, the phase relationship between the phase of the output of the comparator 41 that controls the DA converter 403a and the phase of the output of the comparator 41 that controls the DA converter 403b may be controlled so as to always be the same. For example, the phase of the signal supplied to the DA converter 403a on the upstream side with respect to the input of the pixel signal through the signal line 481 may be ahead of the phase of the signal supplied to the DA converter 403b through the signal line 482. However, this is not limited to this, and the phase of the signal supplied to the DA converter 403a may be behind the phase of the signal supplied to the DA converter 403b. The phase relationship can be appropriately set so as to improve the accuracy of AD conversion and suppress variations between columns corresponding to the respective vertical signal lines 12.

[0038] For example, the phase of the output signal of the comparator 41 supplied to the DA converter 403b may be ahead of that of the DA converter 403a, but the amount of parasitic load may change due to an environmental change or the like, and the phase supplied to the DA converter 403a may become ahead during operation. If the phase (timing) of the signal output from the comparator 41 supplied to each of the DA converters 403a and 403b changes in this way, there is a high possibility that the results of the AD conversion will vary. Therefore, by providing the buffer units 411a and 411b with a phase adjustment function, the accuracy of the AD conversion can be improved.

[0039] 3(a) to 3(c), in the ΔΣ AD converter 450 performing first-order ΔΣ modulation, the buffer unit 411 may also perform phase adjustment on the output of the comparator 41. By adjusting the phase so that an appropriate delay amount is provided for the signal output from the comparator 41 and supplied to the DA converters 44 and 403, the accuracy of the AD conversion can be improved.

[0040] Also, for example, the buffer units 411a and 411b may be provided with an amplifier 423 using an inverter circuit 420 or a level shifter 424, similar to the buffer unit 411 shown in FIG. 4(a) described above. By appropriately combining the amplifier 423, the level shifter 424, and the phase adjuster 421, the buffer units 411a and 411b can appropriately combine and perform amplification, level conversion, and phase adjustment on the output of the comparator 41. In this case, the buffer units 411a and 411b may have multiple paths that can be switched by a switch or the like, and may buffer the signal output from the comparator 41 by combining one or more of amplification, level conversion, and phase adjustment. In this case, different buffer processes may be performed in the buffer units 411a and 411b.

[0041] Next, a modified example of the ΔΣAD converter 451 shown in FIG. 5(b) will be described with reference to FIG. 8, FIG. 9(a), FIG. 9(b), FIG. 10(a), and FIG. 10(b). FIG. 8 is a diagram showing a configuration example of a ΔΣAD converter 453 that performs AD conversion on a pixel signal converted into a current signal. In response to an increase in the dynamic range of the photoelectric conversion device 100, the pixel signal supplied via the signal line 401 may have a wide dynamic range. In order to perform AD conversion on a pixel signal having a wide dynamic range without impairing the signal range, in this embodiment, an analog switch is used as a switch that supplies a current from a current source arranged in the DA converters 403a and 403b to the signal lines 405a and 405b.

[0042] 9(a) and 9(b) are diagrams showing configuration examples of the DA converters 403a and 403b. As shown in FIG. 9(a) and FIG. 9(b), the DA converters 403a and 403b include a current source 472 and an analog switch 471 (CMOS analog switch) for controlling the supply of current from the current source 472 to the signal lines 405a and 405b.

[0043] 10(a) and 10(b) are diagrams showing configuration examples of buffer units 411a and 411b for supplying the signal output by the comparator 41 to the DA converters 403a and 403b. The buffer units 411a and 411b generate a non-inverted signal and an inverted signal according to the comparison result output by the comparator 41 by buffering the output of the comparator 41 in order to operate the analog switch 471 shown in FIG. 9(a) and FIG. 9(b). The analog switch 471 operates according to the non-inverted signal and the inverted signal. More specifically, the buffer units 411a and 411b include an inverter circuit 420 and a non-inverted amplifier circuit 422. In response to the comparison result signal output by the comparator 41 input via the signal line 42, the buffer unit 411a generates a non-inverted signal to be output to the signal line 481 via the inverter circuit 420 and an inverted signal to be output to the signal line 483 via the inverter circuit 420 and the non-inverted amplifier circuit 422. As shown in Fig. 8, a non-inverted signal is supplied from the buffer unit 411a to the DA converter 403a via a signal line 481, and an inverted signal is supplied from the buffer unit 411a to the DA converter 403a via a signal line 481. Similarly, in response to a comparison result signal input via a signal line 42, a non-inverted signal is generated in the buffer unit 411b to be output to a signal line 480 via the inverter circuit 420, and an inverted signal is generated to be output to a signal line 482 via the inverter circuit 420 and the non-inverting amplifier circuit 422. As shown in Fig. 8, a non-inverted signal is supplied from the buffer unit 411b to the DA converter 403b via a signal line 480, and an inverted signal is supplied from the buffer unit 411b to the DA converter 403b via a signal line 480.

[0044] The buffer units 411a and 411b generate normal and inverted signals with the same phase from the comparison result signal, which is one control signal output from the comparator 41, and supply them to the DA converters 403a and 403b. This allows the analog switches 471 arranged in the DA converters 403a and 403b to be appropriately controlled. The buffer units 411a and 411b and the DA converters 403a and 403b have such a configuration, so that even if the pixel signal has a wide dynamic range, it is possible to perform an appropriate conversion operation without impairing the signal range. This makes it possible to suppress deterioration of the accuracy of the AD conversion and suppress variations in the AD conversion between columns.

[0045] 10(a) and 10(b), the above-mentioned level shifter 424 may be provided to perform level conversion processing. This is because the operating voltage of the comparator 41 may differ from the operating voltage of the signal lines 405a and 405b generated by the capacitive elements 402a and 402b functioning as the integrator 40. Furthermore, a phase adjuster 421 may be provided in the buffer units 411a and 411b to adjust the phase in the same manner as described above.

[0046] An application example of the photoelectric conversion device 100 according to the above embodiment will be described below. Fig. 12 is a schematic diagram of an electronic device EQP equipped with the photoelectric conversion device 100. Fig. 12 shows a camera as an example of the electronic device EQP. Here, the concept of a camera includes not only a device whose main purpose is to take pictures, but also a device that has a supplementary photography function (for example, a personal computer or a mobile terminal such as a smartphone).

[0047] The photoelectric conversion device 100 may be a semiconductor chip having a stacked structure in which a pixel unit 10 is provided. As shown in FIG. 12, the photoelectric conversion device 100 is accommodated in a semiconductor package PKG. The package PKG may include a base on which the photoelectric conversion device 100 is fixed, a cover such as glass facing the photoelectric conversion device 100, and a conductive connection member such as a bonding wire or bump that connects a terminal provided on the base to a terminal provided on the photoelectric conversion device 100. The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, and a memory device MMRY.

[0048] The optical system OPT forms an image on the pixel unit 10 of the photoelectric conversion device 100, and may be, for example, a lens, a shutter, or a mirror. The control device CTRL controls the operation of the photoelectric conversion device 100, and may be, for example, a semiconductor device such as an ASIC. The processing device PRCS processes the signal output from the photoelectric conversion device 100, and may be, for example, a semiconductor device such as a CPU or an ASIC. The display device DSPL may be an EL display device or a liquid crystal display device that displays image data obtained by the photoelectric conversion device 100. The memory device MMRY is a magnetic device or a semiconductor device that stores image data obtained by the photoelectric conversion device 100. The memory device MMRY may be a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. The mechanical device MCHN in the camera can drive parts of the optical system OPT for zooming, focusing, and shutter operation. In the device EQP, the image data output from the photoelectric conversion device 100 is displayed on the display device DSPL, or transmitted to the outside by a communication device (not shown) included in the device EQP. For this reason, the device EQP may include a memory device MMRY and a processing device PRCS as shown in FIG.

[0049] A camera incorporating the photoelectric conversion device 100 can be used as a surveillance camera, or an on-board camera mounted on transportation equipment such as automobiles, railroad cars, ships, aircraft, or industrial robots. In addition, a camera incorporating the photoelectric conversion device 100 can be used not only in transportation equipment but also in a wide range of equipment that uses object recognition, such as an intelligent transport system (ITS).

[0050] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0051] 10: pixel section, 11: pixel, 12: vertical signal line, 40: integrator, 41: comparator, 43: decimation filter, 44: DA converter, 45: subtractor, 100: photoelectric conversion device, 411: buffer section, 450 to 453: ΔΣ AD converter, 600: signal processing section

Claims

1. a pixel section in which a plurality of pixels, each of which includes a photoelectric conversion element, are arranged in a matrix; a signal processing unit that processes pixel signals output from the pixel unit via vertical signal lines, the signal processing unit includes a ΔΣ AD converter that converts the pixel signal into a digital signal; The ΔΣ AD converter is a photoelectric conversion device characterized in that it includes a subtractor having a first input to which the pixel signal is input and a second input to which a subtraction signal is input, an integrator that receives the output of the subtractor, a comparator that compares the output of the integrator with a predetermined voltage, a decimation filter that generates the digital signal based on the comparison result output from the comparator, a delay unit that delays the output of the comparator, a buffer unit that buffers the output of the delay unit, and a DA converter that converts the output of the buffer unit into an analog signal and generates the subtraction signal.

2. The signal processing unit further includes a conversion circuit that converts the pixel signal from a voltage signal to a current signal, 2. The photoelectric conversion device according to claim 1, wherein the pixel signal converted into a current signal is input to the subtractor.

3. a pixel section in which a plurality of pixels, each of which includes a photoelectric conversion element, are arranged in a matrix; a signal processing unit that processes pixel signals output from the pixel unit via vertical signal lines, the signal processing unit includes a conversion circuit that converts the pixel signal from a voltage signal to a current signal, and a ΔΣ AD converter that converts the pixel signal converted into the current signal by the conversion circuit into a digital signal; The ΔΣ AD converter is a photoelectric conversion device characterized in that it includes a subtractor having a first input to which the pixel signal is input and a second input to which a subtraction signal is input, an integrator that receives the output of the subtractor, a comparator that compares the output of the integrator with a predetermined voltage, a decimation filter that generates the digital signal based on the comparison result output from the comparator, a buffer unit that buffers the output of the comparator, and a DA converter that converts the output of the buffer unit into an analog signal and generates the subtraction signal.

4. 4. The photoelectric conversion device according to claim 2, wherein the integrator includes a capacitive element connected in parallel with the DA converter.

5. 5. The photoelectric conversion device according to claim 2, wherein the DA converter includes a current source.

6. the buffer unit generates a non-inverted signal and an inverted signal of the comparison result by buffering the comparison result; 6. The photoelectric conversion device according to claim 2, wherein the DA converter includes an analog switch that operates in response to the non-inverted signal and the inverted signal.

7. 7. The photoelectric conversion device according to claim 1, wherein the buffer section includes an amplifier.

8. 8. The photoelectric conversion device according to claim 1, wherein the buffer section includes a phase adjuster.

9. 9. The photoelectric conversion device according to claim 1, wherein the buffer section includes a level shifter.

10. The subtractor is a first subtractor, the integrator is a first integrator, the DA converter is a first DA converter, and the subtraction signal is a first subtraction signal, The photoelectric conversion device described in any one of claims 1 to 9, characterized in that the ΔΣ AD converter further includes a second integrator connected between the first integrator and the comparator, a second subtractor having a third input for receiving the output of the first integrator and a fourth input for receiving a second subtraction signal, and outputting the subtraction result to the second integrator, and a second DA converter for converting the output of the buffer unit into an analog signal and generating the second subtraction signal.

11. 11. The photoelectric conversion device according to claim 10, wherein the buffer unit adjusts the phase of the comparison result by buffering the comparison result, and supplies the comparison result of different phases to the first DA converter and the second DA converter.

12. 12. The photoelectric conversion device according to claim 11, wherein the buffer section adjusts a phase so that the comparison result supplied to the first DA converter leads in phase with the comparison result supplied to the second DA converter.

13. 13. The photoelectric conversion device according to claim 10, wherein the second integrator includes a conversion unit that converts the output of the second subtractor from a voltage signal to a current signal, and a capacitive element connected in parallel with the second DA converter.

14. 14. The photoelectric conversion device according to claim 13, wherein the second DA converter includes a current source.

15. A photoelectric conversion device according to any one of claims 1 to 14, A control device for controlling an operation of the photoelectric conversion device; An electronic device comprising:

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