Amplification circuit that enables accurate measurement of minute electrical signals

Abstract

The amplifier circuit is configured with a resistor divider (R ) including n resistor elements, two main nodes defined across the resistor elements, two readout nodes (d , d ), and a resistor node (q) defined between adjacent resistor elements. REF ), and an input current source (I REF ), including the resistor divider (R REF ) is the feedback signal (S FB ) and includes two arrays of addressable switch elements that can be controlled to open or close by a second node (b). The amplifier circuit includes a differential pair of transistors (T1, T2), the source terminals of each of the transistors (T1, T2) are connected to a second node (b), the gate terminals of the transistors (T1, T2) are connected to input signals (v1, v2), the drain terminals of the transistors (T1, T2) are connected to current sources (I1, I2), and the bulk terminals of the transistors (T1, T2) are connected to readout nodes (d1, d2). The amplifier circuit functions as a differential amplifier, where the bulk terminals are connected to a feedback signal (S FB ) determined by the resistor divider (R REF ) affects the thresholds of the transistors (T1, T2) respectively so as to add or subtract the differential signal derived from the read nodes (d1, d2).

Description

[Technical Field]

[0001] The present invention relates to an amplifier circuit and method for providing accurate measurement of small electrical signals introduced or generated by sensors or sensor elements, including, for example, passive infrared (PIR) sensors and thermopile sensors. [Background technology]

[0002] Most sensors and transducers that convert physical quantities and parameters into electrical signals generate signals that are small and require sensitive equipment to detect. Often, such signals are associated with high output impedance from the sensors and transducers, charge buildup on the sensors themselves, noisy environments, and other situational challenges, requiring additional care in mediating and detecting these signals.

[0003] One example is the field of thermal detection, where thermopile or pyroceramic elements are used in applications such as passive infrared (PIR) detection, which often require measuring small voltages and currents from the sensors, preferably in a differential manner, to ensure accurate readouts. It is also desirable that the reading of these small voltage and / or current signals not affect the normal operation of the sensing element. Converting these signals to digital representations allows greater flexibility in processing them for decision making and other purposes. When this conversion occurs early in the signal chain, environmental factors (e.g., RF coupling, power supply fluctuations, etc.) are less likely to affect signal fidelity and accuracy.

[0004] Requirements for such a measuring device or equipment may include: · The ability to operate in a differential manner, and also in a single-ended manner if required, for example if the sensor does not have a differential output; Ability to operate with input voltages above and below 0V (symmetrical and asymmetrical); Low noise contribution to ensure maximum signal-to-noise ratio (S / N ratio) since the measurement device is usually located early in the signal chain (where it can affect everything downstream); Low power operation to enable use in battery-operated devices and ensure optimal use of energy; · A high dynamic range that ensures accurate detection over a wide range of signals that may be generated by the sensor; · Ability to convert analog signals to digital signals for further processing as early as possible in the signal chain; High linearity; Sufficient bandwidth to ensure accurate tracking of changes in the input signal generated by the sensor; a robust implementation that makes it possible to implement such a measuring device or measuring equipment in electronic devices of different nature, including a discrete implementation, an integrated circuit using CMOS or bipolar technology, or any other implementation that is considered suitable for a given application.

[0005] Prior art document DE102013014810B4 ​​describes a differential amplifier stage that meets several of the above requirements. This publication discloses a digitally controlled series resistor array used to drive a constant reference current through either branch of a differential amplifier in response to a feedback signal generated as part of a sigma-delta analog-to-digital converter (ADC). This feedback signal is essential for establishing the functionality of the differential engine used as part of the sigma-delta converter architecture. One drawback of this approach is that the resistor connected between the sources of the two transistors limits the final noise performance, especially if the resistor value is very high due to the requirement for low current consumption. Summary of the Invention

[0006] The present invention provides an amplifier circuit comprising: n resistor elements (r n ) including a resistor divider (R REF ): The resistive divider (R REF ) is the resistor divider (R REF ) including two principal nodes defined at either end of the first principal node (a) and the second principal node (b); The resistive divider (R REF ) also includes two readout nodes (d1, d2), namely a first readout node (d1) and a second readout node (d2); The resistive divider (R REF ) includes a resistive node (q) defined between adjacent resistive elements; Input current source (I REF ) is connected or connectable to the first main node (a); The resistive divider (R REF ) includes two arrays of addressable switch elements, a first array of switch elements being provided between each resistance node (q) of the resistive element and the first read node (d1), and a second array of switch elements being provided between each resistance node (q) of the resistive element and the second read node (d2); The state of the switch element is determined by a feedback signal (S FB ) and the resistive element thus acts as a selectable voltage tap for the readout nodes (d1, d2); A differential pair of transistors (T1, T2) comprising a first transistor (T1) having at least four terminals and a second transistor (T2) having at least four terminals: a first terminal of each of the transistors (T1, T2) is connected to the second node (b); The second terminals of the transistors (T1, T2) are connected to respective input signals (v1, v2); The third terminals of the transistors (T1, T2) are connected to respective current sources (I1, I2) and output a differential output signal (vOUT ) is generated between the third terminals of the transistors (T1, T2); The fourth terminals of the transistors (T1, T2) are connected to respective readout nodes (d1, d2); The amplifier circuit is configured to perform the function of a differential amplifier, in which the transistors (T1, T2) form a differential amplifier with the respective input signals (v1, v2) at the second terminals of the transistors (T1, T2); The fourth terminal receives the feedback signal (S FB ) determined by the resistor divider (R REF ) based on the voltage signal generated by the operation of the resistor divider (R REF ) affects the thresholds of the transistors (T1, T2) respectively so as to add or subtract the differential signal obtained from the read nodes (d1, d2).

[0007] The input signals (V1, V2) may come from an external source, which may be a sensor.

[0008] The transistors (T1, T2) may be MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The transistors (T1, T2) may be n-type MOSFETs or p-type MOSFETs.

[0009] The terminals of the transistors (T1, T2) may be as follows: 1st terminal = source terminal; Second terminal = gate terminal; third terminal = drain terminal; and / or 4th terminal = bulk terminal.

[0010] The readout nodes (d1, d2) may be considered as differential nodes. In other words, the signal at the readout nodes (d1, d2) is a differential signal (S FB ) may be a differential representation of

[0011] The amplifier circuit may be configured to perform the function of an integrator. A differential pair is formed by the transistors (T1, T2), the current sources (I1, I2), and the nodal parasitic capacitance and nodal parasitic resistance present at the nodes connected to the third terminals of each transistor (T1, T2), and the operation of the amplifier circuit as a differential difference amplifier with respect to differential signals (v1, v2) and (d1, d2) is achieved by providing a differential output (v OUT ) may perform the function of an integrator to exhibit integrated output characteristics. An additional capacitor may be added to the node connected to the third terminal of each of the transistors (T1, T2) to modify the integrator operation.

[0012] The amplifier circuit may use a fourth terminal (e.g., bulk terminal) of each transistor (T1, T2) to form a "second gate," i.e., another terminal that affects the threshold voltage of each transistor. In other words, the feedback signal (S FB ) may be applied directly to the transistors (T1, T2), effectively forming a differential difference amplifier for direct application to a sigma-delta converter. FB ) may be a digital signal that controls the state (e.g., open or closed) of a switch element, so that the feedback signal (S FB ) can be easily controlled. FB Depending on the content and format of the readout nodes (d1, d2), the voltage signals at the readout nodes (d1, d2) may be correlated or may be independently controlled. In one exemplary application, the voltage signals at the readout nodes (d1, d2) may be varied in opposite directions as part of the intended operation of the amplifier circuit.

[0013] The amplifier circuit may be configured to receive the following input signals (v1, v2) from the sensors, respectively: A differential signal, if the sensor provides a differential output signal; If the sensor only provides a single-ended output, a variable input signal and a fixed or grounded input signal.

[0014] Each input signal (v1, v2) is a (relatively) negative input signal (v IN ) and a positive input signal (v IP ) can be used. IN ) may be connected to the gate terminal of the first transistor (T1), and a positive input signal (v IP ) may be connected to the gate terminal of the second transistor (T2).

[0015] In other words, the resistor divider (R REF ) are the individual resistor elements (r n ) and a switch element, and the switch element may be formed by a resistor divider (R REF ) to provide two programmable voltage taps at the readout nodes (d1, d2) that addressably access nodes within the resistor divider (R REF When a current flows through each resistor element (r n ), the feedback signal (S FB ) is determined by the readout nodes (d1, d2) depending on the particular state (open or closed) of the switch element. REF Therefore, the feedback signal (S FB ) through the appropriately applied readout nodes (d1, d2) via a resistive voltage divider (R REF ) can be selected.

[0016] The amplifier circuit may form part of a Sigma-Delta ADC (Analog-to-Digital Converter). With this in mind, the transistors (T1, T2) may be configured to function as or form part of a summing node. REF) may be configured to function as, or form part of, a DAC (Digital to Analog Converter) used to provide a feedback signal to the differential pair required for the operation of the Sigma-Delta ADC. The current sources (I1, I2), together with supporting circuitry, may be configured to function as, or form part of, an integrator. The Sigma-Delta ADC may be viewed as a measurement device of which the amplifier circuitry described above forms a part. The output of the ADC is fed to feedback logic to provide a R REF S operates taps d1 and d2 FB which may generate an analog signal that is applied to the bulk of transistors T1 and T2, and which allows the subtraction or addition of a feedback signal from the original ADC output.

[0017] The sigma-delta ADC may include a comparator, the inputs of which are connected to the differential output signal (V OUT ) may be connected to

[0018] The sigma-delta ADC may include ADC (analog-to-digital converter) logic, such as decimation, whose input may be connected to the output of the comparator.

[0019] The sigma-delta ADC may include feedback logic. The feedback logic may be connected to the output of the ADC logic. The feedback logic may provide a feedback signal (S FB ) The output of the ADC may be log2(n) bits.

[0020] The present invention provides a method of operating an amplifier circuit, the method comprising: n resistor elements (r n ) including a resistor divider (R REF ) steps to provide: The resistive divider (R REF ) is the resistor divider (RREF ) including two principal nodes defined at either end of the first principal node (a) and the second principal node (b); The resistive divider (R REF ) also includes two readout nodes (d1, d2), namely a first readout node (d1) and a second readout node (d2); The resistive divider (R REF ) includes a resistive node (q) defined between adjacent resistive elements; Input current source (I REF ) is connected or connectable to the first main node (a); The resistive divider (R REF ) includes two arrays of addressable switch elements, the first array of switch elements being connected to the resistor elements (r n ) and the first read node (d1), and a second array of switch elements is provided between each resistor node (q) of the resistor element (r n ) between each resistor node (q) and the second read node (d2); The state of the switch element is determined by a feedback signal (S FB ) and the opening and closing of the resistor element (r n ) serves as a selectable voltage tap for said readout nodes (d1, d2); Providing a differential pair of transistors (T1, T2) comprising a first transistor (T1) having at least four terminals and a second transistor (T2) having at least four terminals: a first terminal of each of the transistors (T1, T2) is connected to the second node (b); The second terminals of the transistors (T1, T2) are connected to respective input signals (v1, v2); The third terminals of the transistors (T1, T2) are connected to respective current sources (I1, I2) and output a differential output signal (v OUT ) is generated between the third terminals of the transistors (T1, T2); The fourth terminals of the transistors (T1, T2) are connected to respective readout nodes (d1, d2); a step of performing, by means of said amplifier circuit, the function of a difference amplifier, in which said transistors (T1, T2) form a differential amplifier with respective input signals (v1, v2) at the second terminals of said transistors (T1, T2): The fourth terminal of the transistor (T1, T2) supplies the feedback signal (S FB ) determined by the resistor divider (R REF ) based on the voltage signal generated by the operation of the resistor divider (R REF affecting the transconductance of each of said transistors (T1, T2) so as to add or subtract the differential signal obtained from said read nodes (d1, d2) of said transistors (T1, T2).

[0021] The invention will now be further explained, by way of example only, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0022] [Figure 1] 1 shows a circuit diagram of an amplifier circuit according to the present invention; [Figure 2] 2 shows a circuit diagram of the resistor divider of the amplifier circuit of FIG. 1. [Figure 3] 2 shows a circuit diagram illustrating the amplifier circuit of FIG. 1 in more detail. [Figure 4] Figure 1 shows a schematic diagram of a sigma-delta ADC, of ​​which the amplifier circuitry may form a part. [Figure 5] 5 shows a circuit and schematic diagram of a first embodiment illustrating the sigma-delta ADC of FIG. 4 in more detail. [Figure 6] 5 shows a circuit and schematic diagram of a second embodiment showing the sigma-delta ADC of FIG. 4 in more detail. [Figure 7] 3 shows a circuit diagram of an alternative resistive divider to that of FIG. 2; [Figure 8] 3 shows a circuit diagram of an alternative resistive divider to that of FIG. 2; [Figure 9]3 shows a circuit diagram of an alternative resistive divider to that of FIG. 2; DETAILED DESCRIPTION OF THE INVENTION

[0023] 1 illustrates a circuit diagram of an amplifier circuit 100 in accordance with the present invention. The amplifier circuit 100 includes a resistor divider (R REF ) and this resistor divider (R REF ) is shown in more detail in Figures 2 and 7 to 9. The resistor divider (R REF ) is the resistor divider (R REF ) and includes two main nodes defined across a resistor divider (R REF ) also includes two readout nodes (d1, d2), namely a first readout node (d1) and a second readout node (d2). In this exemplary configuration, the readout nodes (d1, d2) are differential and may therefore be considered as differential nodes (d1, d2).

[0024] Input current source (I REF ) is connected or connectable to the first main node (a). REF ) is constant or nearly constant and can be thought of as a bias current source.

[0025] Resistor divider (R REF ) is the resistance of the adjacent resistor elements (r1...r n ) and a resistor node (represented by reference character (q) in FIGS. 7-9) defined between the resistor divider (R REF ) are two arrays of addressable switch elements (S a1 , S a2 ), a first array of switch elements (S a1 ) is a resistor element (r1...r n ) and the first read node (d1), and a second array of switch elements (S a2 ) is a resistor element (r1...r n) and the second read node (d2). a1 , S a2 ) each state is determined by the feedback signal (S FB ) are individually controlled to open and close, and therefore the resistance elements (r1...r n ) serves as a selectable voltage tap that references the readout nodes (d1, d2).

[0026] The amplifier circuit 100 comprises a differential pair of transistors (T1, T2) consisting of a first transistor (T1) and a second transistor (T2). In this example, the transistors (T1, T2) are MOSFETs, each having four terminals as typically expected in modern CMOS processes. The amplifier circuit 100 has the terminals of the transistors (T1, T2) connected as follows: The first terminal (in this exemplary configuration, the source terminal) of each of the transistors (T1, T2) is connected to the second node (b); The second terminals (gate terminals in this exemplary configuration) of the transistors (T1, T2) are connected to respective input signals (v1, v2); The third terminals (drain terminals in this exemplary configuration) of the transistors (T1, T2) are connected to respective current sources (I1, I2); The fourth terminals (bulk terminals in this exemplary configuration) of the transistors (T1, T2) are connected to respective readout nodes (d1, d2).

[0027] Therefore, between the drain terminals of the transistors (T1 and T2), there is a voltage v OUT +, v OUT - a differential output signal (v OUT ) is generated. The amplifier circuit 100 is configured to perform the function of a differential amplifier, with the transistors (T1, T2) forming a differential amplifier with respective input signals (V1, V2) at their gate terminals. The bulk terminals are connected to the feedback signal (S FB ) determined by the resistor divider (R REF) based on the voltage signal generated by the operation of the resistor divider (R REF ) affects the threshold voltages of the transistors (T1, T2) respectively so as to add or subtract the differential signal obtained from the read nodes (d1, d2).

[0028] Resistor divider (R REF ) is shown in more detail in FIG. 2 (variations thereof are shown in FIGS. 7 to 9). The individual resistive elements (r1...r n ) may or may not be of similar size. n-1 ) is the resistance of the adjacent resistors (r1...r n ) and main nodes a and b are provided at both ends of the resistor. In this example, there are 2*n switch elements, each of which is defined as: (1) resistor node (q1...q n-1 ) and the second main node b, and (2) between the read nodes (d1, d2). Figure 7 shows an example where there are 2*(n+1) switch elements. Figure 8 shows an example where a switch element is connected to the main node a (instead of the main node b), and Figure 9 shows an example where the resistor nodes (q1...q n-1 ) and not connected to the main nodes a and b.

[0029] Regardless of the exact configuration, the switch element is driven by a feedback signal (S FB ), the read nodes (d1, d2) are connected to the selected individual resistor elements (r1...r n ) from which the two signals at the readout nodes (d1, d2) are derived. REF ), a voltage is divided across the array of individual resistive elements, resulting in a feedback signal (S FB ) are connected to the resistor divider (R REF ) can be accessed as a discrete division of the total voltage applied to the

[0030] The input signals (V1, V2) may come from sensors, and V IN and V IP and connected to the gate terminals of each of the transistors (T1, T2). If the sensor provides a differential output signal, the signal will be differential. If the sensor only provides a single-ended output, one of the inputs will be grounded or connected to a fixed potential. The signal V IN and V IP may each be positive or negative with respect to a common reference, or one or both may be connected to such a reference.

[0031] Referring to Figure 3, circuit 200 performs the functions of a differential amplifier and an integrator, both of which are required for the operation of a sigma-delta analog-to-digital converter. One aspect of the invention is to use a differential amplifier to convert the output signal (v OUT ) to the feedback signal (S FB ) is subtracted.

[0032] In prior art circuits where the bulk connection is connected to a constant potential, V IN =V IP In this case, the tail current I REF will be split evenly between branches 1 and 2. V IN and V IP Any imbalance between I1 and I2 will change the transistor transconductance, causing more tail current to flow in one branch. The transistor output impedance at the drain node is finite, the impedance associated with current sources I1 and I2, and therefore the resulting v OUT is an amplified imbalance between the inputs.

[0033] However, in the present invention, the bulk terminal of each transistor (T1, T2) is used to form a "second gate", i.e., another terminal acting on the transconductance of each transistor (T1, T2). The bulk terminals of each transistor (T1, T2) are connected so that the bulk terminal of the first transistor (T1) is connected to a signal from the readout node (d1) and the bulk terminal of transistor (T2) is connected to a signal from the readout node (d2).

[0034] Thus, feedback can be applied directly to the differential pair of transistors (T1, T2), effectively forming a differential difference amplifier for direct application to sigma-delta converters. FB ) is typically a digital signal that controls the state of a switch element, as shown in Figure 2, so the feedback signal (S FB ) can be easily controlled. FB ), the signals at the readout nodes (d1, d2) may be correlated or may be independently controlled. In a typical application, the signals at the readout nodes (d1, d2) will change in opposite directions as part of the intended operation of the amplifier circuits 100, 200.

[0035] The current sources I1, I2, together with their parasitic resistance and capacitance, provide both the integration function and gain at the drains of the transistors (T1, T2). An additional capacitance 210 may be added to the drain terminals to modify and improve the integration function.

[0036] Because the amplifier circuits 100 and 200 are intended for use as part of a sigma-delta analog-to-digital converter, it may be necessary to interpret the individual functions of the circuits in this context. Figure 4 shows a typical architecture, or functional block diagram, of a single-bit or multi-bit sigma-delta ADC 250. A summing node (40) is required to subtract a feedback signal from the DAC. The error signal is processed by an integrator (41) and sent to a comparator (42) for decision. A digital circuit (ADC logic) (43) uses the comparator's output signal to form a digital representation of the input signal. This representation is fed back to the summing node via a digital-to-analog converter (44) and subtracted from the current input signal. This approach is generally well known to those skilled in the art.

[0037] In this context, the amplifier circuit 100, 200 may uniquely and effectively combine the functions of a summing node 40, an integrator 41, and a DAC converter 44. The subtraction function at the summing node 40 is performed using a differential pair of transistors T1, T2, utilizing the techniques described above. FB ) is derived from the ADC output, while the DAC function (44) generates a feedback signal (S FB ) into a resistor divider (R REF ), thereby generating a bulk voltage used by the differential pair of transistors T1, T2. Integration by the integrator 41 occurs at the drain terminals of the differential pair of transistors T1, T2.

[0038] FIG. 5 shows a sigma-delta ADC 300 including an amplifier circuit 200. The differential pair of transistors (T1, T2) are PMOS transistors that receive a differential input signal (V IN -V IP ) and a signal from the differential read node (d1, d2) generated by the DAC function (54), thereby subtracting feedback from the input signal through the operation of the differential pair (50).OUT ) represents the integration of the difference signal due to the nodal characteristic of the integrator (50), which is passed to the comparator (52) and fed to the ADC logic (53) which converts the output signal of the 1-bit comparator into a multi-bit signal. The ADC output is fed to the resistor divider (R REF ) is applied with an appropriate feedback signal (S FB ), which generates signals at readout nodes (d1, d2) to close the feedback loop.

[0039] In this example shown in Figure 5, the operation is fully differential, so the signals at the read nodes (d1, d2) move symmetrically in opposite directions. That is, as d1 increases, d2 decreases in the same proportion. If the implementation is a multi-bit implementation, there will be a relationship between the ADC output and the number of elements in the reference resistor, as shown in Figure 6.

[0040] In another version of the measurement device, the circuit may have NMOS transistors of opposite polarity forming a differential pair, in which case the current source (I REF ) and reference resistor (R REF The polarity and position of the ) are adapted accordingly to provide the same functionality to the circuit. In fact, any field-effect transistor whose bulk or body terminal can serve as a second input to control the transconductance can be used.

[0041] 6 shows another version of the sigma-delta ADC 400 in which the amplifier circuit 200 may receive a single-ended input, where one input is grounded, for example, and a signal is applied to the other input. Either input may be grounded, and the other input may receive a positive or negative input signal.

[0042] The sigma-delta ADC 300, 400 may be considered a measurement circuit or a measurement device. The amplifier circuit 100, 200 and / or the sigma-delta ADC 300, 400 may be an integrated circuit or part of an integrated circuit.

[0043] The illustrated invention provides an approach for measuring physical parameters such as temperature, radiation, and thermal signatures from signals generated by sensors that sense such parameters. While complying with the requirements for measurement devices as described above, a novel approach is used to generate a differential function between a feedback signal, usually in digital form, and a differential (but potentially single-ended) input signal from the sensor, which must be subtracted from the input signal as part of a sigma-delta analog-to-digital converter. Power consumption is also minimized because the reference current is also used as the operating current for the differential amplifier.

[0044] The devices are generally applicable to many applications, but are primarily intended for implementation in integrated semiconductor circuits and devices. The devices can be fabricated using cost-effective, industry-standard manufacturing processes such as silicon-based complementary metal-oxide-semiconductor (CMOS). The devices are used in sensor applications where measurement and discretization of input signals over a relatively wide dynamic range are required, for example, in readout circuits for passive infrared (PIR) sensors, thermopiles, and other sensors.

[0045] Some or all of the requirements listed in the "Background Art" section can be achieved by configuring the amplifier circuit 100, 200, or the measurement device 300, 400 including the amplifier circuit 100, 200, as described above. Furthermore, the novel amplifier circuit 100, 200 or measurement device 300, 400 disclosed herein can achieve distinct advantages over the prior art, such as lower noise operation and more flexibility in controlling the feedback signal.

Claims

1. An amplifier circuit, The amplifier circuit comprises: n resistor elements (r 1 to r n ) including a resistor divider (R REF ): The resistive divider (R REF ) is the resistor divider (R REF a first principal node (a) and a second principal node (b) defined at opposite ends of a The resistive divider (R REF ) is the first read node (d 1 ) and a second read node (d 2 ) also included; The resistive divider (R REF ) includes a resistive node (q) defined between adjacent resistive elements; Input current source (I REF ) is connected to the first main node (a); The resistive divider (R REF ) includes two arrays of switch elements that can be individually addressed or controlled, the first array of switch elements being connected to the resistor divider (R REF ) and the first read node (d 1 ), and a second array of switch elements is provided between the resistor divider (R REF ) and the second read node (d 2 ) and The state of the first array of switch elements and the state of the second array of switch elements are determined by a feedback signal (S FB ) is controlled to open or close, and the first read node (d 1 ) is obtained depending on the state of the first array of switch elements, and the voltage at the second read node (d 2 ) voltage is obtained in response to the state of the second array of switch elements; a first transistor (T) having at least four terminals; 1 ) and a second transistor (T 2 ) and a differential pair of transistors, including: The first transistor (T 1 ) and the second transistor (T 2 ) has its source terminal connected to said second main node (b); The first transistor (T 1 ) and the second transistor (T 2 ) gate terminals are connected to each input signal (v 1 , v 2 ) is connected to; The first transistor (T 1 ) and the second transistor (T 2 ) drain terminal of each current source (I 1 , I 2 ), and a differential output signal (v OUT ) is the first transistor (T 1 ) and the second transistor (T 2 ) between the drain terminals of The first transistor (T 1 ) bulk terminal is connected to the first read node (d 1 ), and the second transistor (T 2 ) bulk terminal is connected to the second read node (d 2 ) is connected to; The amplifier circuit includes the first transistor (T 1 ) and the second transistor (T 2 ) is the first transistor (T 1 ) and the second transistor (T 2 ) at the gate terminal of each of the input signals (v 1 , v 2 ) forming a differential amplifier; The first transistor (T 1 ) and the bulk terminal of the second transistor (T 2 ) is connected to the bulk terminal of the feedback signal (S FB ) determined by the resistive divider (R REF ) based on the voltage signal generated by the operation of the resistor divider (R REF ) the first read node (d 1 ) and the second read node (d 2 ) to add or subtract a differential signal obtained from the first transistor (T 1 ) and the second transistor (T 2 ) threshold, an amplifier circuit.

2. The first transistor (T 1 ) and the second transistor (T 2 ) is connected to a sensor, and each of the input signals (v 1 , v 2 2. The amplifier circuit of claim 1, wherein:

3. The first transistor (T 1 ) and the second transistor (T 2 2. The amplifier circuit according to claim 1, wherein the first transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET).

4. The first read node (d 1 ) and the second read node (d 2 ) is a differential node, and the first read node (d 1 ) and the second read node (d 2 ) is the feedback signal (S FB 2. The amplifier circuit according to claim 1, wherein the differential expression of

5. The amplifier circuit includes the first transistor (T 1 a first capacitor connected to the drain terminal of the second transistor (T 2 2. The amplifier circuit of claim 1, further comprising: a second capacitor connected to the drain terminal of said first capacitor;

6. Each of the input signals (v 1 , v 2 )of, as a differential signal, or As variable and fixed or grounded input signals, 10. The amplifier circuit of claim 1, configured for receiving.

7. 10. An amplifier circuit as claimed in claim 1, which is an integrated circuit or forms part of an integrated circuit.

8. 2. A sigma-delta analog-to-digital converter comprising the amplifier circuit of claim 1.

9. a summing node, and the first transistor (T 1 ) and the second transistor (T 2 9. A sigma-delta analog-to-digital converter as claimed in claim 8, wherein a first input terminal is arranged to function as the summing node or to form part of the summing node.

10. DAC (Digital-to-Analog Converter), and the resistor divider (R REF 9. A sigma-delta analog-to-digital converter as claimed in claim 8, wherein a first input signal is connected to said first input signal and a second input signal is connected to said second input signal.

11. an integrator, and each of the current sources (I 1 , I 2 9. A sigma-delta analog-to-digital converter as claimed in claim 8, wherein a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage, a sixth stage, a sixth stage, a seventh ...

12. a comparator, and an input of the comparator is connected to the differential output signal (v OUT 9. The sigma-delta analog-to-digital converter according to claim 8, wherein the input terminals are connected to the input terminals.

13. 13. The sigma-delta analog-to-digital converter of claim 12, further comprising an ADC (analog-to-digital converter) logic, the input of said ADC logic being connected to the output of said comparator.

14. connected to the output of the ADC logic, and the feedback signal (S FB 14. The sigma-delta analog-to-digital converter of claim 13, further comprising feedback logic configured to generate a

15. 9. A sigma-delta analog-to-digital converter as claimed in claim 8, which is an integrated circuit or forms part of an integrated circuit.

16. 1. A method of operating an amplifier circuit, comprising: n resistor elements (r 1 to r n ) including a resistor divider (R REF ) steps to provide: The resistive divider (R REF ) is the resistor divider (R REF a first principal node (a) and a second principal node (b) defined at opposite ends of a The resistive divider (R REF ) is the first read node (d 1 ) and a second read node (d 2 ) also included; The resistive divider (R REF ) includes a resistive node (q) defined between adjacent resistive elements; Input current source (I REF ) is connected to the first main node (a); The resistive divider (R REF ) includes two arrays of switch elements that can be individually addressed or controlled, the first array of switch elements being connected to the resistor divider (R REF ) and the first read node (d 1 ), and a second array of switch elements is provided between the resistor divider (R REF ) and the second read node (d 2 ) and The state of the first array of switch elements and the state of the second array of switch elements are determined by a feedback signal (S FB ) is controlled to open or close, and the first read node (d 1 ) is obtained depending on the state of the first array of switch elements, and the voltage at the second read node (d 2 ) voltage is obtained in response to the state of the second array of switch elements; a first transistor (T) having at least four terminals; 1 ) and a second transistor (T 2 ) and a transistor (T 1 , T 2 ) providing a differential pair: The first transistor (T 1 ) and the second transistor (T 2 ) has its source terminal connected to said second main node (b); The first transistor (T 1 ) and the second transistor (T 2 ) gate terminals are connected to each input signal (v 1 , v 2 ) is connected to; The first transistor (T 1 ) and the second transistor (T 2 ) drain terminal of each current source (I 1 , I 2 ), and a differential output signal (v OUT ) is the first transistor (T 1 ) and the second transistor (T 2 ) between the drain terminals of The first transistor (T 1 ) bulk terminal is connected to the first read node (d 1 ), and the second transistor (T 2 ) bulk terminal is connected to the second read node (d 2 ) is connected to; The first transistor (T 1 ) and the second transistor (T 2 ) is the first transistor (T 1 ) and the second transistor (T 2 ) at the gate terminal of each of the input signals (v 1 , v 2 providing a differential amplifier, the differential amplifier having a The first transistor (T 1 ) and the second transistor (T 2 ) by the bulk terminal of the feedback signal (S FB ) determined by the resistive divider (R REF ) based on the voltage signal generated by the operation of the resistor divider (R REF ) the first read node (d 1 ) and the second read node (d 2 ) to add or subtract a differential signal obtained from the first transistor (T 1 ) and the second transistor (T 2 ) affecting the transconductance of the

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