Integrated circuit device with receiver chain peak detector - Patents.com

Abstract

An integrated circuit device (100) is provided. In some examples, the integrated circuit device includes an amplifier stage (106) that receives an input signal (102A) and a control signal (110) and provides an amplified signal (102B) in response. A main path (116, 120, 122) is coupled to the amplifier stage to receive the amplified signal and provide a first feedback signal (124) corresponding to the signal strength of a data-bearing portion of the input signal. A control path (126, 128, 134) also receives the amplified signal and provides a second feedback signal (136) corresponding to the signal strength of the data-bearing portion and an interference component. A gain control circuit (108) is coupled to the main path and to the control path to receive the first and second feedback signals (124, 136) and provide a control signal in response to the feedback signals. In some such examples, the control path and the main path include separate mixer stages (116, 126) having different performance characteristics.

Description

[Technical field]

[0001] A receiver of a communication device, such as a wireless transceiver, may include a set of signal processing stages arranged in a receiver chain. These stages may include one or more amplifier stages. To improve reception of weak signals, the combined gain of the amplifier stages may be relatively high. However, applying a large gain to a strong signal may saturate the amplified signal, causing distortion (e.g., clipping) of the amplified signal, which may make it more difficult to extract data from the signal. In extreme cases, data may be lost entirely. Therefore, some receivers use automatic gain control (AGC) adjustments to dynamically control the gain based on signal strength.

[0002] In many applications, the receiver receives interference along with the data-bearing portion of the signal. Later stages can filter out the interference, but stages before the filter stage can be affected by the interference component of the signal. When the signal is amplified, both the interference and the data-bearing portion can contribute to saturation of the amplified signal. Summary of the Invention

[0003] In some examples, an integrated circuit is provided that includes a receiver chain for a wireless receiver. The receiver chain includes an amplifier stage, a mixer stage, a filter stage, and / or other suitable stages. The characteristics of these stages, including the gain, may be controlled by an automatic gain control (AGC) circuit that receives signal strength feedback from the various stages and adjusts the characteristics of the stages accordingly. Various stages of the receiver chain may filter interference and may preserve data-bearing portions of the signal, so that feedback from these stages may not measure interference components. Because interference may contribute to signal saturation, especially in stages of the receiver chain prior to the filter stage, the receiver chain may include a separate control path running in parallel that preserves the interference for use in AGC decisions.

[0004] In some examples, an integrated circuit device includes an amplifier stage that receives an input signal and a control signal and provides an amplified signal in response to the input signal and the control signal. A main path is coupled to the amplifier stage, the main path receiving the amplified signal and providing a first feedback signal corresponding to a signal strength of a data-bearing portion of the input signal. A control path is coupled to the amplifier stage, the control path receiving the amplified signal and providing a second feedback signal corresponding to the signal strength of the data-bearing portion and an interference component of the input signal. A gain control circuit is coupled to the main path and the control path, the gain control circuit receiving the first feedback signal and the second feedback signal and providing a control signal in response to the first feedback signal and the second feedback signal.

[0005] In some examples, an integrated circuit includes an amplifier having a first input, a control input, and an output. A first path is coupled to the amplifier, the first path including an output and a first mixer stage coupled to the output of the amplifier. A second path is coupled to the amplifier, the second path including an output and a second mixer stage coupled to the output of the amplifier. The integrated circuit also includes a control circuit having a first input coupled to the output of the first mixer stage, a second input coupled to the output of the second mixer stage, and an output coupled to the control input of the amplifier.

[0006] In some examples, a method includes receiving an input signal and amplifying the input signal according to a gain control signal to generate an amplified signal. A first baseband conversion is performed on the amplified signal to generate a first intermediate frequency signal, and a first feedback signal is determined based on the first intermediate frequency signal corresponding to a signal strength of a data-bearing portion of the input signal. A second baseband conversion is performed on the amplified signal to generate a second intermediate frequency signal, and a second feedback signal is determined based on the signal strength of the data-bearing portion and the second intermediate frequency signal corresponding to an interference component of the input signal. The gain control signal is modified based on the first feedback signal and the second feedback signal.

[0007] The features of the present invention will be understood from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 2 is a circuit diagram of a receiver chain in accordance with certain aspects of the present disclosure. [Figure 1B] FIG. 2 is a circuit diagram of a receiver chain in accordance with certain aspects of the present disclosure.

[0009] [Diagram 2] 1 is a circuit diagram of a mixer stage in accordance with certain aspects of the present disclosure.

[0010] [Diagram 3] FIG. 2 is a circuit diagram of a peak detector in accordance with certain aspects of the present disclosure.

[0011] [Figure 4] 1 is a flowchart of a method for performing gain control in a receiver chain, in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Specific examples are described in detail below with reference to the accompanying drawings. These examples are not limiting, and unless otherwise specified, these features are not required for any particular example. Also, a first device that is coupled (electrically, physically, or otherwise) to a second device may be directly coupled without an intervening device, or may be indirectly coupled through one or more intervening devices.

[0013] An example receiver includes a receiver chain having multiple analog and digital stages that process a received signal to extract data from the signal. These stages may include one or more amplifier stages that amplify the received signal. The maximum combined gain of the receiver chain may be relatively high (e.g., about 60 dB in some examples) so that data may be extracted from weak signals. However, applying maximum gain to strong signals may saturate the amplified signal, resulting in clipping and other types of distortion. Thus, the example receiver includes an automatic gain control (AGC) circuit that adjusts the operation of one or more stages in the receiver chain to reduce gain when the signal is relatively strong and increase gain when the signal is relatively weak.

[0014] In some examples, the AGC circuit receives a first feedback signal corresponding to the signal strength from an analog-to-digital converter (ADC) of the receiver chain. The first feedback signal may correspond primarily to the strength of the data-bearing portion of the signal, since the receiver chain may have filtered out interference from the signal before it reaches the ADC. However, both the interference and the data-bearing portion in the signal may contribute to signal saturation. Thus, the example AGC also receives a second feedback signal corresponding to the signal strength of both the data-bearing portion and the interference. This second feedback signal may be provided by a parallel control path in the receiver chain, including stages such as a baseband downconversion mixer, a peak detector, and / or an ADC. The stages of the control path may be specifically configured to store and even amplify the interference.

[0015] By considering the interference as well as the data-bearing portion of the signal, the AGC can increase the gain more aggressively in low and medium interference conditions. In some such instances, the receiver can use amplification to detect received signals that have 40 dB less power than a comparable design.

[0016] In some examples, the control path includes a baseband downconversion mixer with a wide bandwidth to preserve interference that also amplifies the signal being downconverted to increase the sensitivity of the signal to interference components. In some such examples, the baseband downconversion mixer provides this amplification without inductors, which tend to have a large layout footprint. The baseband downconversion mixer allows peak detection of the signal to be performed in the intermediate frequency domain (e.g., the baseband domain) rather than the radio frequency domain, which may allow for simpler peak detector circuits since the frequencies are lower and the range of frequencies of interest is smaller in the intermediate frequency domain. In these and other examples, the receiver exhibits higher signal sensitivity with the same or reduced power and area despite the addition of a control path stage.

[0017] Of course, these advantages are merely examples, and no advantage is required for any particular embodiment.

[0018] Examples of integrated circuit devices having receiver chains are described below with reference to the figures, in which: FIG 1A is a circuit diagram of a receiver chain 100 of a receiver in accordance with certain aspects of the present description.

[0019] The receiver chain 100 may be part of a wireless transceiver and may receive the input signal 102A via an antenna 104. In further embodiments, the receiver chain 100 is part of a wired transceiver (e.g., an optical transceiver, an Ethernet transceiver) and receives the input signal 102A via a receiver element such as a photodiode or via a direct electrical connection with a transmitter.

[0020] The input signal 102A may be a differential or single-ended signal and may include a data-bearing portion occurring at one or more specified frequencies or frequency ranges. The input signal 102A may also include interference components at other frequencies. These interference components may include data-bearing emissions intended for other receivers and / or general background noise. Interference components close in frequency to the data-bearing portion may be referred to as interferers or blockers.

[0021] The receiver chain 100 may include two parallel signal paths of the receiver chain: a main receiver path 112 and a control path 114. The main receiver path 112 may process the received signal to extract data from the data-bearing portion, which may include filtering by one or more stages to remove interference and extract the data-bearing portion. In response, the control path 114 may store at least a portion of the interference for use in setting gains and / or other operating parameters of stages in the main receiver path 112.

[0022] The main receiver path 112 is described first. The main receiver path 112 includes an amplifier stage 106 coupled to an antenna 104. An input signal 102A, including a data-bearing portion and any interference, is received by an input of the amplifier stage 106. The amplifier stage 106 may include any suitable amplifier circuit, and in some examples, the amplifier stage 106 includes a low noise amplifier (LNA) or similar amplifier. The amplifier stage 106 amplifies the input signal 102A according to a set of operating parameters (e.g., gain value, frequency response curve, and / or other operating parameters) provided by an AGC circuit 108 via a set of AGC control signals 110 at a control input of the amplifier stage 106. The amplifier stage 106 provides the amplified input signal 102A as an amplified signal 102B. The amplifier stage 106 may be configured to remove a portion of the interference from the input signal 102A via filtering or control of the amplifier's frequency response curve. However, significant interference may be present in the amplified signal 102B, especially at frequencies near the frequencies of the data-bearing portions of the signal.

[0023] The amplifier stage 106 may provide the amplified signal 102B to the remainder of the main receiver path 112 as well as the control path 114. In the main receiver path 112, a first mixer stage 116 coupled to the amplifier stage 106 receives the radio frequency amplified signal 102B and converts it to a first intermediate frequency signal 102C. The first mixer stage 116 may include a baseband downconversion mixer that mixes the radio frequency amplified signal 102B with a fixed amplitude signal (e.g., a square wave signal, a sine wave signal, etc.) at a carrier frequency generated by a local oscillator (LO) 118. The first mixer stage 116 may also include a baseband filter (e.g., a low pass filter) coupled to the downconversion mixer to remove aliases from the output signal of the downconversion mixer to generate the first intermediate frequency signal 102C. Operating parameters of the first mixer stage 116 , such as gain, frequency response curve, and / or other parameters, may be controlled by an AGC control signal 110 of the AGC circuit 108 , which is received at a control input of the mixer stage 116 .

[0024] The downmixing and filtering of the first mixer stage 116 may remove some of the interference from the first intermediate frequency signal 102C, and to the extent any interference remains, the main receiver path 112 may include one or more filter stages 120 coupled to the first mixer stage 116, which receive the first intermediate frequency signal 102C from the first mixer stage 116 and generate a filtered signal 102D. The operating parameters of the filter stage 120, including its frequency response curve, may be controlled by an AGC control signal 110 of the AGC circuit 108, which is received at a control input of the filter stage 120.

[0025] The main receiver path 112 includes a first analog-to-digital converter (ADC) stage 122 coupled to the filter stage 120 to receive the filtered signal 102D from the filter stage 120. The first ADC stage 122 may convert the voltage of the filtered signal 102D to a digital representation of the filtered signal 102D to generate a digital output signal 102E. The digital output 102E may be provided to the remainder of the receiver for further signal processing, including extracting the data encoded in the digital output 102E.

[0026] The ADC stage 122 may also provide a first feedback signal 124 to an input of the AGC circuit 108. The first feedback signal 124 corresponds to the signal strength of the filtered signal 102D and / or the digital output signal 102E, and thus the signal strength of the data-bearing portion of the received input signal 102A. In some examples, the first feedback signal 124 corresponds to a peak value of the data-bearing portion of the input signal 102A within a period of time. In some examples, the first feedback signal 124 corresponds to an average of the data-bearing portion of the input signal 102A over a period of time. In further examples, the first feedback signal 124 includes other representations of signal strength.

[0027] The AGC circuit 108 uses the first feedback signal 124 to provide operating parameters via the AGC control signal 110 to various stages of the main receiver path 112, such as, for example, the amplifier stage 106, the first mixer stage 116, and the filter stage 120. For example, the AGC circuit 108 may increase the gain of these stages when the first feedback signal 124 indicates that the signal strength is low and may decrease the gain of these stages when the first feedback signal 124 indicates that the signal strength is high.

[0028] Elements of the main receiver path 112, such as the filter stage 120, may remove most or all of the interference from the filtered signal 102D before it reaches the first ADC stage 122. Thus, the first feedback signal 124, which is based on the filtered signal 102D, may represent a primarily data-bearing portion of the input signal 102A without interference. The control path 114 may be configured to process the received signal (e.g., the amplified signal 102B) in a manner that preserves at least a portion of the interference so that the AGC circuit 108 may also take the interference component into account.

[0029] In some examples, the control path 114 includes a second mixer stage 126 coupled to the amplifier stage 106 in parallel with the first mixer stage 116. Similar to the first mixer stage 116, the second mixer stage 126 receives the amplified signal 102B, and the second mixer stage 126 may include a baseband downconversion mixer that mixes the radio frequency amplified signal 102B with a signal at a carrier frequency generated by the LO 118. The second mixer stage 126 may also include a baseband filter (e.g., a low pass filter) coupled to the downconversion mixer that filters an output signal of the downconversion mixer to generate the second intermediate frequency signal 102F.

[0030] In contrast to the first mixer stage 116, the filters and / or downconversion mixers of the second mixer stage 126 may be configured to have a wider bandwidth such that no or reduced interference components are present in the second intermediate frequency signal 102F, which is not present in the signal 102C. In some examples, the second mixer stage 126 has a bandwidth of about 300 MHz. The second mixer stage 126 may also have a larger amplification than the first mixer stage 116 to increase sensitivity to interference components. In some such examples, the second mixer stage 126 has a gain of about 16 dB, although any suitable gain may be used. In some examples, such as those described in later figures, the second mixer stage 126 achieves this gain without the use of inductors that may otherwise consume a significant amount of circuit area.

[0031] The control path 114 further includes a peak detector 128 coupled to the second mixer stage 126 to receive the second intermediate frequency signal 102F. The peak detector 128 may generate a peak signal 102G having a voltage representative of a peak voltage of the second intermediate frequency signal 102F over a window of time. In one example, the peak detector 128 includes a diode 130 having an input coupled to receive the signal 102F and an output coupled to generate the signal 102G, and a capacitor 132 coupled between the output of the diode 130 and ground. Further examples of the peak detector 128 are described in more detail below.

[0032] By placing the peak detector 128 after the second mixer stage 126, the structure of the peak detector 128 may be simplified due to the baseband conversion. In some examples, the relevant frequencies are lower in the intermediate frequency domain, so the high frequency response of the peak detector 128 becomes less relevant, and the complexity and sensitivity of the peak detector 128 may be reduced. Similarly, in some examples, the range of relevant frequencies is smaller in the intermediate frequency domain, so the complexity and sensitivity of the peak detector 128 may be further reduced. Also, the peak detector 128 may benefit from the amplification provided by the second mixer stage 126 and / or the amplifier stage 106, which may amplify the interference and enable detection, even if the sensitivity of the peak detector 128 is reduced.

[0033] A second ADC stage 134 is coupled to the peak detector 128 and receives the peak signal 102G. The second ADC stage 134 detects a threshold voltage V Thres The second feedback signal 136 generates a second feedback signal 136 having a digital value representing the voltage of the peak signal 102G relative to the data-bearing portion of the input signal 102A. In this manner, the second feedback signal 136 has a voltage proportional to the strength of the data-bearing portion and the interference component of the input signal 102A. Similar to the first feedback signal 124, the second feedback signal 136 may correspond to a peak measurement, an average measurement, and / or any other suitable measurement of signal strength.

[0034] The AGC circuit 108 is coupled to the second ADC stage 134 and receives a second feedback signal 136 from the second ADC stage 134. Thus, the AGC circuit 108 takes into account both the first feedback signal 124 and the second feedback signal 136 when determining operating parameters (e.g., gain settings, frequency response, and / or other operating parameters) of the stages (e.g., amplifier stage 106, first mixer stage 116, filter stage 120, etc.) of the main receiver path 112 provided via the AGC control signal 110.

[0035] In one example, the AGC circuit 108 increases the gain of the stages of the main receiver path 112 when the first feedback signal 124 indicates that the signal strength of the data-bearing portion of the input signal 102A is low, and decreases the gain when the first feedback signal 124 indicates that the signal strength of the data-bearing portion is high. The example AGC circuit 108 limits the maximum gain of the stages of the main receiver path 112 based on the second feedback signal 136 to ensure that the signal strength of the combined interference and data-bearing portion represented by the second feedback signal 136 does not cause signal saturation. In particular, instead of using a conservative interference guard band, the AGC circuit 108 may apply more gain to low or medium noise signals than would otherwise be possible because the amount of interference is determined and taken into account. This more amplification may enable the receiver chain 100 to successfully extract data from weaker signals.

[0036] 1B, which is a circuit diagram of a receiver chain 150 of a receiver in accordance with certain aspects of the present description. In many aspects, the receiver chain 150 is substantially similar to the receiver chain 100. For example, the receiver chain 150 includes a main receiver path 112 that includes an amplifier stage 106, a first mixer stage 116, a filter stage 120, and a first ADC stage 122 similar to those of FIG. 1A. The receiver chain 150 also includes an AGC circuit 108 substantially similar to those of FIG. 1A.

[0037] In contrast, the control path 152 of the receiver chain 150 receives the input signal 102A directly from the antenna 104 rather than receiving the amplified signal 102B. The operation of the control path 152 is otherwise similar. The control path 152 includes a second mixer stage 154 coupled to the antenna 104 and receiving the input signal 102A. Similar to the second mixer stage 126, the second mixer stage 154 may include a baseband downconversion mixer that mixes the radio frequency input signal 102A with a signal at a carrier frequency generated by the LO 118. The second mixer stage 154 may also include a baseband filter (e.g., a low pass filter) coupled to the downconversion mixer that filters an output signal of the downconversion mixer to generate the second intermediate frequency signal 102F.

[0038] The filter and / or downmixer of the second mixer stage 154 may be configured to have a wider bandwidth than the first mixer stage 116, such that interference components that are not present or are reduced in the signal 102C are present in the second intermediate frequency signal 102F.

[0039] The control path 114 further includes a peak detector 128 (including a diode 130 and a capacitor 132) and a second ADC stage 134 that generates a second feedback signal 136, substantially as described above.

[0040] An example of a mixer stage suitable for use in the second mixer stage 126 and / or 154 of the control path 114 is described with respect to Figure 2. In that regard, Figure 2 is a circuit diagram of a mixer stage 200 in accordance with certain aspects of the present description.

[0041] The mixer stage 200 mixes an input signal (e.g., the amplified signal 102B) into a signal V inP 202 and V inM 204 as a differential pair. inP 202 is coupled to the gate of a first transistor 206, and a signal V inM 204 is coupled to the gate of a second transistor 208 .

[0042] Mixer stage 200 also receives signals LO 210 and The third transistor 214 is configured to receive a signal (e.g., a square wave signal, a sine wave signal, etc.) at a carrier frequency from the LO 118 as a differential pair of JPEG0007649780000001.jpg35212. The signal 210 is coupled to the gate of the third transistor 214. JPEG0007649780000002.jpg35212 is coupled to the gate of the fourth transistor 216 and to the gate of the fifth transistor 218. Signal LO 210 is also coupled to the gate of the sixth transistor 220.

[0043] A source of the first transistor 206 is coupled to the ground node, and a drain of the first transistor 206 is coupled to the sources of the third transistor 214 and the fourth transistor 216. Similarly, a source of the second transistor 208 is coupled to the ground node, and a drain of the second transistor 208 is coupled to the sources of the fifth transistor 218 and the sixth transistor 220.

[0044] Mixer stage 200 receives signal V outP 222 and V outM 224 as a differential pair. outM The node 224 is coupled to the drains of the third transistor 214 and the fifth transistor 218, and a first resistor 226 is coupled to the drains of the voltage source V outM Node 224. outP The node 222 is coupled to the drains of the fourth transistor 216 and the sixth transistor 220, and a second resistor 228 is coupled to the drains of the voltage source V outP Node 222.

[0045] In some examples, the mixer stage 200 includes current helper transistors 230 and 232 coupled in parallel with the first resistor 226 and the second resistor 228, respectively. In such examples, the sources of the first current helper transistor 230 and the second current helper transistor 232 are coupled to a voltage source and the gates of the first current helper transistor 230 and the second current helper transistor 232 are coupled to a bias voltage V Bias 231. The drain of the first current helper transistor 230 is coupled to V outM A drain of a second current helper transistor 232 is coupled to node 224 and connected to V outP is coupled to node 222.

[0046] Mixer stage 200 is only one example of a suitable circuit for second mixer stages 126 and 154, and other suitable circuits are contemplated and provided.

[0047] An example of a peak detector 300 suitable for use in peak detector 128 of control path 114 is described with reference to Figure 3. In that regard, Figure 3 is a circuit diagram of peak detector 300 in accordance with certain aspects of the present description.

[0048] In some examples, the peak detector 300 is configured to operate with a differential signal pair, where the first signal of the differential signal pair (V oP 304), and a main peak detector subunit 302 for generating a second signal of the differential signal pair (V oM and a replicate peak detector subunit 306 for generating a replicate peak detector subunit 308).

[0049] The main peak detector subunit 302 converts an input signal (e.g., the second intermediate frequency signal 102F) into a signal V outP 310 and V outM 312 as a differential pair. outP 310 is coupled to the gate of a first transistor 314 and supplies a signal V outM312 is coupled to the gate of a second transistor 316. The drains of the first transistor 314 and the second transistor 316 are coupled to a voltage source, and the sources of the first transistor 314 and the second transistor 316 are coupled to a first node 318.

[0050] The main peak detector subunit 302 includes a first current source 320 and a first capacitor 322 coupled in parallel between the first node 318 and a ground node. oP A first resistor 324 is coupled between a node associated with 304. oP A second capacitor 326 is coupled between node 304 and a ground node.

[0051] The replica peak detector subunit 306 is similar to the main peak detector subunit 302 and can be used to correct for DC offsets. The main peak detector subunit 302 detects a common-mode voltage V Bias 328. The drains of the third transistor 330 and the fourth transistor 332 are coupled to a voltage source, and the sources of the third transistor 330 and the fourth transistor 332 are coupled to a second node 334.

[0052] The replica peak detector subunit 306 includes a second current source 336 and a third capacitor 338 coupled in parallel between the second node 334 and a ground node. oMえ A second resistor 340 is coupled between the node associated with 308. oM A fourth capacitor 342 is coupled between the node associated with 308 and a ground node.

[0053] Peak detector 300 is only one example of a suitable circuit for peak detector 128, and other suitable circuits are contemplated and provided.

[0054] The operation of the receiver is further described with reference to Figures 1A and 4. Figure 4 is a flow chart of a method 400 for performing gain control in a receiver chain, in accordance with certain aspects of the present description. Method 400 is suitable for implementation by receiver chain 100 of Figures 1A-3 or other suitable integrated circuits. The processes of method 400 may be performed in an order other than that described, and processes may be performed simultaneously in parallel. Also, in some examples of the present description, processes of method 400 may be omitted or substituted.

[0055] Referring to block 402, the receiver chain 100 receives an input signal 102A. The input signal 102A may be received via an antenna 104, a photodiode, another receiver element, a direct electrical connection, and / or any other suitable receiving mechanism.

[0056] Referring to block 404, the amplifier stage 106 of the receiver chain 100 receives the input signal 102A, amplifies the input signal 102A according to a set of operating parameters, and provides it as an amplified signal 102B.

[0057] Referring to block 406, the first mixer stage 116 of the receiver chain 100 receives the amplified signal 102B and performs a baseband conversion to convert the amplified signal 102B to a first intermediate frequency signal 102C. Parameters of the baseband conversion, such as gain and / or frequency response, may be determined by a set of operating parameters.

[0058] Referring to block 408, the filter stage 120 of the receiver chain 100 filters the first intermediate frequency signal 102C to remove interference while preserving a data-bearing portion of the signal, which is provided as filtered signal 102D. The frequency response and / or other operating parameters of the filter stage 120 may be determined by a set of operating parameters.

[0059] Referring to block 410, the first ADC stage 122 of the receiver chain 100 receives the filtered signal 102D and digitizes the signal to generate a digital output signal 102E. Referring to block 412, the first ADC stage 122 also provides a first feedback signal 124 to the AGC circuit 108. The first feedback signal 124 corresponds to the signal strength of the data-bearing portion of the received input signal 102A.

[0060] Referring to block 414, the second mixer stage 126 of the receiver chain 100 also receives the amplified signal 102B and performs a baseband conversion to convert the amplified signal 102B to a second intermediate frequency signal 102F. Additionally or alternatively, the second mixer stage receives the input signal 102A directly and performs a baseband conversion to convert the input signal 102A to a second intermediate frequency signal 102F. In either example, in contrast to the conversion of block 406 and / or the filtering of block 408, the conversion of block 414 may be configured to preserve interference in the second intermediate frequency signal 102F. Thus, the second intermediate frequency signal 102F may include interference components that are removed by the conversion of block 406 or the filtering of block 408. For example, the baseband conversion of block 414 may be performed using a mixer stage having a larger bandwidth than that used in block 406. In some examples, the baseband conversion of block 414 includes applying gain to the amplified signal 102B to increase the strength of interference in the second intermediate frequency signal 102F.

[0061] Referring to block 416, the peak detector 128 receives the second intermediate frequency signal 102F and provides a peak signal 102G having a voltage corresponding to a peak of the second intermediate frequency signal 102F.

[0062] Referring to block 418, a second ADC stage 134 of the receiver chain 100 receives the peak signal 102G and digitizes the signal to generate a second feedback signal 136. The second feedback signal 136 corresponds to the signal strength of both the data-bearing portion of the received input signal 102A and one or more interference components of the received input signal 102A.

[0063] Referring to block 420, the AGC circuit 108 modifies a set of operating parameters of the receiver chain 100 based on the first feedback signal 124 and the second feedback signal 136. In some examples, this includes the AGC circuit 108 increasing the gain of the receiver chain 100 up to a maximum gain determined based on the second feedback signal 136 to avoid signal saturation when the first feedback signal 124 indicates the signal strength of the data-bearing portion of the received input signal 102A.

[0064] The receiver chain 100 or other integrated circuit devices may implement the processes of the method 400 using any combination of dedicated hardware and instructions stored on a non-transitory medium. Thus, an element of the receiver chain 100, such as the AGC circuit 108, may include a processing resource coupled to a non-transitory computer-readable medium. The processing resource may include one or more microcontrollers, ASICs, CPUs, GPUs, and / or other processing resources configured to execute instructions stored on the medium. Examples of suitable non-transitory computer-readable media include one or more flash memory devices, battery-backed RAM, SSDs, HDDs, optical media, and / or other memory devices suitable for storing instructions for the processing resources.

[0065] This description provides many exemplary embodiments, to which modifications can be made, and such modifications are clearly within the scope of this description, and the application of these teachings to other environments, applications, and / or purposes is consistent with and contemplated by this description.

Claims

1. 1. An integrated circuit comprising: an amplifier having a first input, a control input, and an output; a first path having an output, the first path including a first mixer having an input coupled to the output of the amplifier, a control input, and an output; a second path having an output, the second path including a second mixer having an input coupled to the output of the amplifier; a control circuit having a first input coupled to an output of the first path, a second input coupled to an output of the second path, and a control output coupled to a control input of the amplifier and a control input of the first mixer, receiving at said second input a first signal representative of an interference component and a data component of a received signal; receiving at the first input a second signal representative of the data component without the interference component; providing a control signal to the control output based on the first signal and the second signal. The control circuit is configured as follows: Including, an integrated circuit, the bandwidth of the first mixer reducing the interference component and the bandwidth of the second mixer passing the interference component;

2. 2. The integrated circuit of claim 1, The first pathway comprises: a filter having an input coupled to the output of the first mixer, a control input coupled to the control output, and an output; an analog-to-digital converter (ADC) having an input coupled to an output of the filter and an output coupled to a first input of the control circuit; The integrated circuit further comprises:

3. 2. The integrated circuit of claim 1, The second pathway comprises: a peak detector having an input coupled to the output of the second mixer and an output; an analog-to-digital converter (ADC) having an input coupled to an output of the peak detector and an output coupled to a second input of the control circuit; 4. An integrated circuit comprising:

4. 4. An integrated circuit according to claim 3, The peak detector comprises: a diode having an anode coupled to the output of the second mixer and a cathode; a capacitor having a first terminal coupled to the cathode and a second terminal coupled to a ground terminal; 4. An integrated circuit comprising:

5. 5. An integrated circuit according to claim 4, an output of the second mixer being a differential output including a first mixer output and a second mixer output.

6. 2. The integrated circuit of claim 1, The second mixer input is coupled to an output of the amplifier.

7. 2. The integrated circuit of claim 1, an input of the second mixer coupled to a first input of the amplifier;

8. 2. The integrated circuit of claim 1, The integrated circuit further includes an antenna coupled to the first input of the amplifier.

9. 2. The integrated circuit of claim 1, The integrated circuit, wherein the bandwidth of the second mixer is greater than the bandwidth of the first mixer.

10. 2. The integrated circuit of claim 1, The integrated circuit, wherein the control circuit is further configured to limit a maximum gain of the first path based on the first signal.

11. 2. The integrated circuit of claim 1, The integrated circuit, wherein the control circuit includes an automatic gain control (AGC) circuit.

12. 1. An integrated circuit comprising: an amplifier having a first input, a control input, and an output; a first path having an output, the first path including a first mixer having an input coupled to the output of the amplifier; a second path having an output, a second mixer having an input coupled to the output of the amplifier and an output; a peak detector having an input coupled to an output of the second mixer and an output, a first transistor having a first control terminal coupled to the second mixer, a first current terminal, and a second current terminal; a second transistor having a second control terminal coupled to the second mixer, a third current terminal, and a fourth current terminal; the peak detector, an analog-to-digital converter (ADC) having an input coupled to the output of the peak detector and an output; the second path comprising: a control circuit having a first input coupled to an output of the first path, a second input coupled to an output of the second path and to an output of the ADC, and a control output coupled to a control input of the amplifier, receiving at said second input a first signal representative of an interference component and a data component of a received signal; receiving at the first input a second signal representative of the data component without the interference component; providing a control signal to the control output based on the first and second signals; The control circuit is configured as follows:

4. An integrated circuit comprising:

13. 13. An integrated circuit according to claim 12, comprising: the first current terminal and the third current terminal are coupled to a voltage source terminal; The peak detector comprises: a first current source coupled to the second current terminal and to the fourth current terminal; a first capacitor having a first terminal coupled to a second current terminal and to the fourth current terminal; a first resistor having a first terminal coupled to the first terminal of the first capacitor; a second capacitor having a first terminal coupled to the second terminal of the first resistor and to an input of the ADC; The integrated circuit further comprises:

14. 14. An integrated circuit according to claim 13, comprising: The peak detector comprises: a third transistor having a third control terminal coupled to the common mode voltage terminal, a fifth current terminal, and a sixth current terminal; a fourth transistor having a fourth control terminal coupled to the common mode voltage terminal, a seventh current terminal, and an eighth current terminal; The integrated circuit further comprises:

15. 15. An integrated circuit according to claim 14, comprising: the fifth current terminal and the seventh current terminal are coupled to the voltage source terminal; The peak detector comprises: a second current source coupled to a sixth current terminal and to the eighth current terminal; a third capacitor having a first terminal coupled to a sixth current terminal and to the eighth current terminal; a second resistor having a first terminal coupled to the first terminal of the third capacitor; a fourth capacitor having a first terminal coupled to the second terminal of the second resistor and to an input of the ADC; The integrated circuit further comprises:

16. 13. An integrated circuit according to claim 12, comprising: an integrated circuit, the bandwidth of the first mixer reducing the interference component and the bandwidth of the second mixer passing the interference component;

17. 13. An integrated circuit according to claim 12, comprising: The integrated circuit, wherein the control circuit includes an automatic gain control (AGC) circuit.

18. 13. An integrated circuit according to claim 12, comprising: The integrated circuit wherein the output of the second mixer is a differential output.

19. A circuit element comprising: an amplifier having a first input, a first control input, and an output; A first pathway, a first mixer having a first input coupled to an output of the amplifier, a second control input, and an output; a filter having a first input coupled to an output of the first mixer, a third control input, and an output; a first digital-to-analog converter (ADC) having an input coupled to an output of the filter and an output; the first path including A second pathway, a second mixer having an input coupled to the first input of the amplifier and an output; a peak detector having an input coupled to an output of the second mixer and an output, a first transistor having a first control terminal coupled to the second mixer, a first current terminal, and a second current terminal; a second transistor having a second control terminal coupled to the second mixer, a third current terminal coupled to the first current terminal, and a fourth current terminal coupled to the second current terminal; a current source having a first terminal coupled to the second and fourth current terminals and a second terminal; a first capacitor having a first terminal coupled to the second and fourth current terminals and a second terminal coupled to the second terminal of the current source; a resistor having a first terminal coupled to the second and fourth current terminals and a second terminal; a second capacitor having a first terminal and a second terminal coupled to the second terminal of the current source and to the second terminal of the first capacitor; the peak detector, a second ADC having an input coupled to the output of the peak detector, to the second terminal of the resistor and to the first terminal of the second capacitor, and an output; the second path comprising: a control circuit having a first input coupled to an output of the first ADC, a second input coupled to an output of the second ADC, and a control output coupled to the first, second and third control inputs, receiving a first signal at the first input; receiving a second signal at the second input; providing a control signal to the control output based on the first and second signals; The control circuit is configured as follows: A circuit element comprising:

20. 20. A circuit element according to claim 19, comprising: A circuit element, wherein the second signal represents an interference component and a data component of a received signal, and the first signal represents the data component without the interference component.

21. 21. A circuit element according to claim 20, comprising: A circuit element, wherein a bandwidth of the first mixer reduces the interference component and a bandwidth of the second mixer passes the interference component.

Images