Semiconductor device, semiconductor device manufacturing method and manufacturing apparatus, and electronic device

Abstract

This semiconductor device comprises: a semiconductor substrate that has a main substrate, a base semiconductor section positioned above the main substrate, and a hole passing through the main substrate in the thickness direction thereof; a compound semiconductor section positioned above the base semiconductor section; a first light-reflecting section positioned above the compound semiconductor section; and a second light-reflecting section that is arranged in the hole and overlaps with the first light-reflecting section below the first light-reflecting section.

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices and the like. [Background technology]

[0002] Patent Document 1 discloses a surface-emitting semiconductor laser device in which a DBR (Distributed Bragg Reflector) layer and a light-emitting layer are provided on a GaN substrate. The structure in which a DBR is provided on a GaN substrate has a problem with heat dissipation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent No. 6555260 Summary of the Invention

[0004] The semiconductor device according to the present disclosure comprises a semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate and including a hole penetrating the main substrate in a thickness direction, a compound semiconductor portion located above the base semiconductor portion, a first light reflecting portion located above the compound semiconductor portion, and a second light reflecting portion disposed in the hole and overlapping with the first light reflecting portion below the first light reflecting portion. [Brief description of the drawings]

[0005] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 2] 4 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the embodiment. [Diagram 3] 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment of the present invention. [Figure 4] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 5]1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 6] 4 is another cross-sectional view showing the configuration of the semiconductor device in accordance with the first embodiment. FIG. [Figure 7] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Figure 8] 1 is a partially enlarged cross-sectional view showing the configuration of a semiconductor device according to a first embodiment. [Figure 9] 4 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] 1A to 1C are cross-sectional views showing steps of an example of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 11] 4 is a cross-sectional view showing an example of lateral growth of a base semiconductor portion. FIG. [Figure 12] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 13] 4 is a plan view showing another configuration of the semiconductor device of the first embodiment. FIG. [Figure 14] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 15] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 16] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 17] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 18] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 19] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 20] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 21] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 22] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 23]4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 24] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Diagram 25] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 26] 4 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. [Figure 27] FIG. 11 is a cross-sectional view taken along the X direction of a semiconductor device according to a second embodiment. [Figure 28] FIG. 11 is a cross-sectional view taken along the Y direction of the semiconductor device according to the second embodiment. [Figure 29] 28 is a flowchart showing an example of a method for manufacturing the semiconductor device of FIG. 27. [Diagram 30] 11 is a cross-sectional view showing another configuration of the semiconductor device according to the second embodiment. [Diagram 31] 31 is a flowchart showing an example of a method for manufacturing the semiconductor device of FIG. 30. [Diagram 32] 31A to 31C are cross-sectional views showing steps in an example of a method for manufacturing the semiconductor device of FIG. 30. [Diagram 33] FIG. 11 is a schematic diagram illustrating a configuration of an electronic device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] [Semiconductor Devices] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment. As shown in FIG. 1, the semiconductor device 30 according to this embodiment includes (i) a semiconductor substrate 15 having a main substrate 1, a mask pattern 6 located above the main substrate 1, and a base semiconductor portion 8 located above the mask pattern 6, and including a hole H penetrating the main substrate 1, (ii) a compound semiconductor portion 9 located above the base semiconductor portion 8, (iii) a first light reflecting portion 10 located above the compound semiconductor portion 9, and (iv) a second light reflecting portion 11 disposed in the hole H and overlapping the first light reflecting portion 10 below the first light reflecting portion 10. The second light reflecting portion 11 overlaps the first light reflecting portion 10 in a plan view. A first electrode E1 can be provided above the compound semiconductor portion 9. The mask pattern 6 includes an opening K and a mask portion 5. The mask pattern 6 may be a mask layer 6, the base semiconductor portion 8 may be a base semiconductor layer 8, and the compound semiconductor portion 9 may be a compound semiconductor layer 9. The semiconductor substrate 15 may include a main substrate 1 (e.g., a bulk crystal substrate) and a semiconductor portion (semiconductor layer), and the main substrate 1 may be a semiconductor or a non-semiconductor. For ease of explanation, the direction from the main substrate 1 toward the base semiconductor portion 8 is referred to as the "upward direction" (which may therefore differ from the vertical upward direction or the upward direction in the drawing).

[0007] Semiconductor substrate 15 includes a hole H that penetrates main substrate 1 in the thickness direction (Z direction, up-down direction) and overlaps with base semiconductor portion 8 and compound semiconductor portion 9 in a plan view. Two components overlapping in a plan view means that at least a portion of one component overlaps with the other component when viewed in the normal direction of main substrate 1 (including perspective viewing).

[0008] The first light reflecting portion 10 and the first electrode E1 may overlap in a plan view. At least a part of the second light reflecting portion 11 may be formed in the hole H. Furthermore, the second light reflecting portion 11, the base semiconductor portion 8, the compound semiconductor portion 9, the first electrode E1, and the first light reflecting portion 10 may overlap each other in a plan view. In the semiconductor device 30, the light generated in the compound semiconductor portion 9 may undergo laser oscillation by traveling back and forth between the first and second light reflecting portions 10 and 11, and may be emitted as laser light from the second light reflecting portion 11, for example. In the semiconductor device 30, the second light reflecting portion 11 is provided in the hole H of the main substrate 1, so that the heat dissipation is improved and the reliability of the semiconductor device 30 is enhanced.

[0009] In the semiconductor device 30, even if the main substrate 1 and the base semiconductor portion 8 have different lattice constants, threading dislocations (defects) in the base semiconductor portion 8 and the compound semiconductor portion 9 on the mask portion 5 are reduced. This increases the light emission efficiency of the compound semiconductor portion 9 (for example, the ratio of the amount of light to the amount of charge injected from the first electrode E1). This is because threading dislocations are dislocations (defects) that extend from the base semiconductor portion 8 to the compound semiconductor portion 9, and they impede charge transfer and cause heat generation.

[0010] The base semiconductor portion 8 and the compound semiconductor portion 9 include, for example, a nitride semiconductor. The nitride semiconductor is, for example, Al x Ga y In z N (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor portion 8 may be a doped type (e.g., n-type containing a donor) or a non-doped type. The base semiconductor portion 8 and the compound semiconductor portion 9 may be nitride semiconductor layers.

[0011] The base semiconductor portion 8 including a nitride semiconductor can be formed by an ELO (Epitaxial Lateral Overgrowth) method, but other methods may be used as long as they can achieve low defects. In the ELO method, for example, a heterogeneous substrate having a lattice constant different from that of the base semiconductor portion 8 is used as the main substrate 1, an inorganic compound film is used as the mask portion 5, and the upper surface of the base portion 4 is exposed in the opening portion K, so that the base semiconductor portion 8 can be grown laterally (in the Y direction) on the mask portion 5.

[0012] Hereinafter, the main substrate 1 and the base portion 4 may be collectively referred to as the base substrate, and the main substrate 1, the base portion 4, and the mask pattern 6 may be collectively referred to as the template substrate 7. In addition, the semiconductor layer (semiconductor portion) formed by the ELO method may be referred to as the ELO semiconductor layer.

[0013] [Semiconductor device manufacturing] Fig. 2 is a flow chart showing an example of a method for manufacturing a semiconductor device according to this embodiment. In the method for manufacturing a semiconductor device shown in Fig. 2, after a step of preparing a template substrate (substrate for ELO growth) 7, a step of forming a base semiconductor portion 8 using the ELO method, a step of forming a compound semiconductor portion 9, a step of forming a first light reflecting portion 10, and a step of forming a second light reflecting portion 11 are performed.

[0014] Fig. 3 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment. The semiconductor device manufacturing apparatus 70 in Fig. 3 includes a film forming unit 72 that forms a base semiconductor portion 8, a compound semiconductor portion 9, a first light reflecting portion 10, and a second light reflecting portion 11 on a template substrate 7, a processing unit 73 that performs etching on the main substrate 1 from its rear surface 1U, and a control unit 74 that controls the film forming unit 72 and the processing unit 73.

[0015] The film forming unit 72 may include an MOCVD (Metal Organic Chemical Vapor Deposition) device, and the control unit 74 may include a processor and a memory. The control unit 74 may be configured to control the film forming unit 72 and the processing unit 73 by executing a program stored in, for example, an internal memory, a communication device capable of communication, or an accessible network. The above-mentioned program and a recording medium on which the above-mentioned program is stored are also included in this embodiment.

[0016] [Semiconductor Devices] 4 is a cross-sectional view showing another configuration of the semiconductor device according to this embodiment. As shown in Fig. 4, the semiconductor device 30 may include a circuit board CB located on the opposite side of the main substrate 1 and electrically connected to the first electrode E1.

[0017] Example 1 (Overall composition) FIG. 5 is a cross-sectional view of the semiconductor device according to the first embodiment along the X direction. FIG. 6 is a cross-sectional view of the semiconductor device according to the first embodiment along the Y direction. FIG. 7 is a plan view of the semiconductor device according to the first embodiment. As shown in FIG. 5, FIG. 6, and FIG. 7, the semiconductor device 30 according to the first embodiment includes: (i) a main substrate 1, an underlayer 4 located on the main substrate 1, a mask pattern 6 located on the underlayer 4 and including a mask portion 5 and an opening K, and a base semiconductor portion 8 located on the mask pattern 6, a semiconductor substrate 15 including a hole H penetrating the main substrate 1, (ii) a compound semiconductor portion 9 located on the base semiconductor portion 8, (iii) an insulating film KF located on the compound semiconductor portion 9, (iv) a first electrode E1 and a second electrode E2, (v) a first light reflecting portion 10 located on the first electrode E1, and (vi) a second light reflecting portion 11 provided in the hole H. The base semiconductor portion 8 and the compound semiconductor portion 9 include a nitride semiconductor (for example, a GaN-based semiconductor). For example, the X direction is the <11-20> direction of the base semiconductor portion 8, the Y direction is the <1-100> direction of the base semiconductor portion 8, and the Z direction is the <11-20> direction of the base semiconductor portion 8. <0001> It is a direction.

[0018] The main substrate 1 is a heterogeneous substrate having a different lattice constant from that of the base semiconductor portion 8. The main substrate 1 may be a light-shielding substrate, for example, a silicon substrate. The semiconductor substrate 15 includes a hole H that penetrates between the lower surface and the upper surface of the main substrate 1 and overlaps with the compound semiconductor portion 9 in a planar view. The hole H may have a tapered shape that tapers toward the base semiconductor portion 8. The second light reflecting portion 11 provided in the hole H may overlap with the first light reflecting portion 10 in a planar view. The second light reflecting portion 11 may be in contact with at least the bottom (bottom surface) of the hole H, or may be in contact with a sidewall of the hole H.

[0019] The hole H has an opening KR, which is an emission surface of the laser light, on the rear surface (lower surface) 1U of the main substrate 1. The shape of the opening KR is rectangular, rhombic, hexagonal, circular, elliptical, etc., but is not limited thereto. In the first embodiment, at least a part of the bottom of the hole H is included in the base portion 4. As shown in FIG. 5, the entire bottom of the hole H may be located within the base portion 4.

[0020] The first electrode E1 is an anode provided on the compound semiconductor portion 9. The compound semiconductor portion 9 is provided on the base semiconductor portion 8, but the compound semiconductor portion 9 is not located above a portion of the base semiconductor portion 8, and the second electrode E2, which is a cathode, can be provided so as to be in contact with this portion of the base semiconductor portion 8. The first electrode E1 may be optically transparent.

[0021] The semiconductor device 30 is configured with one or more surface-emitting semiconductor laser elements 20 (VCSEL elements: a vertical cavity surface emitting laser element) including a base semiconductor portion 8, a compound semiconductor portion 9, an insulating film KF, first and second electrodes E1·E2, and first and second light reflecting portions 10·11. Specifically, light generated in the compound semiconductor portion 9 by a current between the first and second electrodes E1·E2 is lased by stimulated emission and feedback between the first and second light reflecting portions 10·11, and is emitted as laser light from the second light reflecting portion 11, for example. In the semiconductor device 30, the second light reflecting portion 11 is provided in the hole H of the main substrate 1, so that heat dissipation is improved and reliability is increased. The second light reflecting portion 11 may be in contact with a hollow portion VD in the hole H. The main substrate 1 maintains the rigidity of the semiconductor device. The second light reflecting portion 11 may extend to the back surface of the main substrate 1.

[0022] An insulating film KF is provided between the peripheral edge of the first electrode E1 and the compound semiconductor portion 9. The insulating film KF narrows the current path between the first and second electrodes E1 and E2 on the anode side, thereby improving the light emission efficiency (described later).

[0023] The base semiconductor portion 8 may be made of an n-type semiconductor (e.g., silicon-doped gallium nitride). The base semiconductor portion 8 may be made of a first portion HD located on the opening K, a second portion HD located on the mask portion 5, and a third portion HD having a threading dislocation density of 5×10 6 / cm 2 The compound semiconductor portion 9 includes a second portion (low defect portion) SD described below, and the second portion SD overlaps with the compound semiconductor portion 9 in a planar view. The portion of the compound semiconductor portion 9 that overlaps with the second portion SD in a planar view inherits the low dislocation properties (low defect properties), and therefore the light emission efficiency of this portion can be improved.

[0024] In the first embodiment, the first and second electrodes E1 and E2 are aligned in the Y direction. The first electrode E1 may be a transparent electrode containing, for example, ITO (Indium Tin Oxide), and the second electrode E2 may be a light-reflecting electrode. The compound semiconductor portion 9 may contain a GaN-based semiconductor, and the first electrode E1 may contain gallium oxide.

[0025] The semiconductor device 30 includes a first pad P1 in contact with an upper surface of the first electrode E1, and a second pad P2 in contact with an upper surface of the second electrode E2. In a plan view, at least a portion of the first pad P1 does not overlap with the hole H. This reduces the effect of pressure on the first pad P1 on the compound semiconductor portion 9 and the base semiconductor portion 8. Note that in FIG. 7, the first pad P1 and the second pad P2, which will be described later, are omitted from the illustration in order to clearly show the positions of the various members on the compound semiconductor portion 9.

[0026] In a plan view, at least a part of the second pad P2 does not overlap with the hole H. This reduces the effect of pressure on the second pad P2 (for example, pressure when bonding to the circuit board CB) on the compound semiconductor portion 9 and the base semiconductor portion 8. In addition, in a plan view, at least a part of the first pad P1 does not overlap with the hole H. This reduces the effect of pressure on the first pad P1 on the compound semiconductor portion 9 and the base semiconductor portion 8. The first pad P1 may be in contact with the upper surface of the first light reflecting portion 10. The first pad P1 has a higher thermal conductivity than the first light reflecting portion 10, and therefore improves heat dissipation.

[0027] In the semiconductor device 30, the upper surface levels (height positions) of the first and second pads P1 and P2 are aligned, and the upper surfaces of the first and second pads P1 and P2 are positioned higher than the upper surface of the first light reflecting portion 10. This makes it easy to mount the semiconductor device 30 on a circuit board CB (see FIG. 4).

[0028] An insulating film DF may be provided between the peripheral edge of the second electrode E2 and the base semiconductor portion 8. The insulating film DF prevents the second electrode E2 from contacting the compound semiconductor portion 9 and electrically isolates them. The second electrode E2 may have a recess EH, and the recess EH may be filled with an insulator DH. The insulator DH can flatten the upper surface of the second pad P2.

[0029] The semiconductor device 30 includes a first partition portion QF overlapping with an opening K of the mask pattern 6 in a planar view, a second partition portion QS overlapping with a mask portion 5 of the mask pattern 6 in a planar view, and a third partition portion QT dividing the compound semiconductor portion 9 in the Y direction. The first partition portion QF, the second partition portion QS, and the third partition portion QT may be light reflective. The first partition portion QF and the second partition portion QS extend in the Y direction, and the third partition portion QT extends in the X direction.

[0030] 8 is a partial enlarged view of the semiconductor device 30 shown in FIG. 6. As shown in FIG. 8, the compound semiconductor portion 9 includes, in order from the bottom, an n-type semiconductor layer 34 as a first-type semiconductor layer, an active layer 35, and a p-type semiconductor layer 36 as a second-type semiconductor layer. The active layer 35 may have, for example, an MQW (Multi-Quantum Well) structure and include an InGaN layer and a GaN layer. The n-type semiconductor layer 34 includes, for example, at least one of an n-GaN layer and an n-AlGaN layer. The p-type semiconductor layer 36 includes, for example, at least one of a p-GaN layer and a p-AlGaN layer. The first electrode E1, which is an anode, is disposed so as to be in contact with the p-type semiconductor portion 36.

[0031] An aperture portion AP (current confinement portion) is formed in the insulating film KF formed on the p-type semiconductor layer 36, and the p-type semiconductor layer 36 exposed in the aperture portion AP comes into contact with the first electrode E1. The insulating film KF may be made of SiOx, SiNx, AlOx, or the like.

[0032] In the first embodiment, the aperture portion AP overlaps with the first light reflecting portion 10, the compound semiconductor portion 9, the second portion SD (low defect portion) of the base semiconductor portion 8, and the second light reflecting portion 11 in a plan view. That is, a current path (particularly a current confinement portion) from the first electrode E1 to the base semiconductor portion 8 is formed in the base semiconductor portion 8 and the low defect portion of the compound semiconductor portion 9. This improves the light emission efficiency of the active layer 35. The area of ​​the bottom surface of the hole H in which the second light reflecting portion 11 is formed may be made larger than the area of ​​the aperture portion AP.

[0033] Incidentally, by providing the insulating film DF, the second electrode E2 and the compound semiconductor portion 9 are not in direct contact with each other, and in particular, the second electrode E2 and the p-type semiconductor portion 36 are not in direct contact with each other. This reduces the possibility that holes injected from the first electrode E1 to the p-type semiconductor portion 36 will move to the second electrode E2 without passing through the active layer 35.

[0034] A part of the compound semiconductor portion 9 may be recessed by etching or the like to expose the base semiconductor portion 8, and the second electrode E2 may be provided so as to contact the base semiconductor portion 8. Alternatively, a part of the compound semiconductor portion 9 may be recessed by etching or the like to expose, for example, the n-type semiconductor layer 34 in the compound semiconductor portion 9, and the second electrode E2 may be provided so as to contact the n-type semiconductor layer 34.

[0035] The first light reflecting portion 10 is, for example, a reflecting mirror (for example, a Distributed Bragg Reflector) in which low refraction portions 31 and high refraction portions 32 are alternately stacked as shown in FIG. 8. The low refraction portion 31 may be a first refraction portion, and the high refraction portion 32 may be a second refraction portion having a higher optical refractive index than the first refraction portion. The low refraction portion 31 includes, for example, SiO2 or the like. The high refraction portion 32 is a layer including a material having a higher refractive index than the low refraction portion 31, and includes, for example, Ta2O5, HfO2, ZrO2, TiO2, Al2O3, Nb2O5, ZnO, AlN, SiN, or MgO or the like. Light incident on the interface between the high refraction portion 32 and the low refraction portion 31 at an angle equal to or greater than the critical angle is totally reflected at this interface, and therefore, a high optical reflectance is realized in the first light reflecting portion 10. The second light reflecting portion 11 can have the same structure as the first light reflecting portion 10 (DBR).

[0036] Here, the first light reflecting portion 10 may have a reflectance of approximately 100%, for example, about 99%, for the emission wavelength of the active layer 35, and the second light reflecting portion 11 may have a reflectance lower than that of the first light reflecting portion 10, for example, about 98%. In this case, the light traveling back and forth between the first light reflecting portion 10 and the second light reflecting portion 11 is emitted as laser light from the opening KR of the main substrate 1. Since the first partition portion QF and the second partition portion QS have light reflectivity, the light utilization efficiency is improved.

[0037] The laser light is not limited to being emitted from the second light reflecting portion 11 side (hole H). It may be emitted from the first light reflecting portion 10 side, or may be emitted from each of the first and second light reflecting portions 10 and 11.

[0038] (Manufacturing method) FIG. 9 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. As shown in FIG. 9 and FIG. 10, in the method for manufacturing a semiconductor device, after the step of preparing a template substrate 7, a base semiconductor portion 8 is formed using an ELO method. Next, a step of forming a compound semiconductor portion 9 is performed, and then a step of forming an insulating film DF and first and second electrodes E1 and E2 is performed. Then, a step of forming a first light reflecting portion 10 is performed, and then a step of forming a first and second pads P1 and P2 is performed. Then, a step of etching the main substrate 1 from its rear surface 1U to form a hole H is performed. Then, a step of forming a second light reflecting portion 11 in the hole H is performed. Note that after performing ELO film formation using the mask pattern 6, for example, before forming the first and second electrodes E1 and E2, the mask portion 5 may be removed by wet etching or the like.

[0039] (Main board) The main substrate 1 may be a heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor. Examples of heterogeneous substrates include a single crystal silicon (Si) substrate, a sapphire (Al2O3) substrate, and a silicon carbide (SiC) substrate. The surface orientation of the main substrate 1 may be, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, or the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any main substrate and surface orientation may be used as long as the base semiconductor portion 8 can be grown by the ELO method. A Si substrate or a SiC substrate may be used from the viewpoint of being more thermally conductive than a GaN bulk substrate.

[0040] (Base part) As the base portion 4, a buffer portion (buffer layer) 2 and a seed portion 3 can be provided in this order from the main substrate 1 side. The buffer portion 2 has a function of, for example, reducing the melting of the main substrate 1 and the seed portion 3 due to direct contact with each other. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed portion 3, the two (the main substrate and the seed portion) melt together, and thus, for example, melting is reduced by providing the buffer portion 2 including at least one of an AlN layer and a SiC (silicon carbide) layer. The AlN layer, which is an example of the buffer portion 2, can be formed to a thickness of about 10 nm to about 5 μm (for example, 150 nm) using, for example, an MOCVD apparatus. The buffer portion 2 may have at least one of the effects of increasing the crystallinity of the seed portion 3, reducing the internal stress of the base semiconductor portion 8 (reducing the warpage of the semiconductor device 30), and increasing the heat dissipation. When a main substrate 1 that does not melt with the seed portion 3 is used, a configuration without providing the buffer portion 2 is also possible. From the viewpoint of excellent thermal conductivity, a SiC layer may be used for the seed portion 3 or the buffer portion 2. The seed portion 3 is not limited to a configuration in which it overlaps the entire mask portion 5 as shown in Fig. 5. Since it is sufficient that the seed portion 3 is exposed from the opening K of the mask 6, the seed portion 3 may be formed locally so as not to overlap at least a part of the mask portion 5.

[0041] At least one of the buffer portion 2 (for example, aluminum nitride) and the seed portion 3 (for example, GaN-based semiconductor) can be deposited using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.).

[0042] (Mask pattern) The opening K of the mask pattern 6 functions as a growth initiation hole that exposes the seed portion 3 and initiates the growth of the base semiconductor portion 8, and the mask portion 5 of the mask pattern 6 functions as a selective growth mask that causes the base semiconductor portion 8 to grow laterally. The mask pattern 6 may be removed after the base semiconductor portion 8 is formed (ELO film formation). The opening K is a portion where the mask portion 5 is not present, and the opening K does not have to be surrounded by the mask portion 5.

[0043] The mask portion 5 is, for example, a silicon oxide film (SiO x ), titanium nitride film (TiN, etc.), silicon nitride film (SiN x A single layer film including any one of a silicon oxynitride film (SiON) and a metal film having a high melting point (for example, 1000° C. or higher), or a laminated film including at least two of these can be used.

[0044] For example, a silicon oxide film having a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed on the entire surface of the base portion 4 by sputtering, and a resist is applied to the entire surface of the silicon oxide film. The resist is then patterned by photolithography to form a resist having a plurality of stripe-shaped openings. Parts of the silicon oxide film are then removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings K, and the resist is removed by organic cleaning to form the mask pattern 6.

[0045] The openings K have an elongated shape (slit shape) and are periodically arranged in the a-axis direction (X direction) of the base semiconductor portion 8. The width of the openings K can be about 0.1 μm to 20 μm. As the width of each opening becomes smaller, the number of threading dislocations propagating from each opening to the base semiconductor portion 8 decreases. Also, the low defect portion SD can be made larger.

[0046] A silicon oxide film may decompose and evaporate in small amounts during the formation of the base semiconductor portion 8 and become incorporated into the base semiconductor portion 8, but a silicon nitride film and a silicon oxynitride film have the advantage of being less susceptible to decomposition and evaporation at high temperatures.

[0047] Therefore, the mask portion 5 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order on the base portion 4, or may be a laminated film in which a silicon nitride film and a silicon oxide film are formed in this order on the base portion 4, or may be a laminated film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on the base portion 4.

[0048] Pinholes and other abnormalities in the mask portion 5 can be eliminated by performing organic cleaning after film formation, and then re-introducing the mask into the film formation device to form a film of the same type. A good quality mask pattern 6 can also be formed by using a general silicon oxide film (single layer) and using such a film re-formation method.

[0049] (Specific example of template substrate) The main substrate 1 is a silicon substrate having a (111) surface, and the buffer portion 2 of the base portion 4 is an AlN layer (for example, 30 nm). 0.6 Ga 0.4 A graded layer was formed in which an N layer (eg, 300 nm) and a GaN layer (eg, 1 to 2 μm) as a second layer were formed in this order.

[0050] A laminated body in which a silicon oxide film (SiO2) and a silicon nitride film (SiN) are formed in this order is used for the mask portion 5. The silicon oxide film has a thickness of, for example, 0.3 μm, and the silicon nitride film has a thickness of, for example, 70 nm. The silicon oxide film and the silicon nitride film are each formed by a plasma chemical vapor deposition (CVD) method.

[0051] (Base semiconductor part) In Example 1, the base semiconductor portion (ELO semiconductor layer) 8 was a GaN layer, and an MOCVD apparatus was used to perform ELO deposition of gallium nitride (GaN) on the above-mentioned template substrate 7. As an example of the ELO deposition conditions, the following can be adopted: substrate temperature: 1120° C., growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH3: 15 slm, V / III=6000 (ratio of the supply amount of group V raw material to the supply amount of group III raw material).

[0052] In this case, the base semiconductor portion 8 is selectively grown (vertical growth) on the seed portion 3 (e.g., a GaN layer) exposed in the opening portion K, and then grows laterally on the mask portion 5. Then, before the base semiconductor portions 8 growing laterally on both sides of the mask portion 5 meet, the lateral growth is stopped.

[0053] The width Wm of the mask portion 5 was 50 μm, the width of the opening K was 5 μm, the lateral width of the base semiconductor portion 8 was 53 μm, the width (size in the X direction) of the low defect portion SD was 24 μm, and the layer thickness of the base semiconductor portion 8 was 5 μm. The aspect ratio of the base semiconductor portion 8 was 53 μm / 5 μm=10.6, which is an extremely high aspect ratio.

[0054] In the formation of the base semiconductor portion 8 in Example 1, the lateral film formation rate is increased. The method for increasing the lateral film formation rate is as follows. First, a vertically grown layer growing in the Z direction (c-axis direction) is formed on the seed portion 3 exposed from the opening K, and then a laterally grown layer growing in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertically grown layer to 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less, the thickness of the laterally grown layer can be kept low and the lateral film formation rate can be increased.

[0055] Fig. 11 is a cross-sectional view showing an example of lateral growth of the base semiconductor portion 8. As shown in Fig. 11, an initial growth layer SL is formed on the seed portion 3, and then the base semiconductor portion 8 can be grown laterally from the initial growth layer SL. The initial growth layer SL serves as a starting point for the lateral growth of the base semiconductor portion 8. By appropriately controlling the ELO film formation conditions, it is possible to control the base semiconductor portion 8 to grow in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0056] Here, deposition of the initial growth layer SL may be stopped just before the edge of the initial growth layer SL rises onto the upper surface of the mask portion 5 (at the stage where it is in contact with the upper end of the side surface of the mask portion 5) or just after it rises onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions may be switched from the c-axis direction deposition conditions to the a-axis direction deposition conditions). In this way, lateral deposition is performed from a state in which the initial growth layer SL slightly protrudes from the mask portion 5, so that consumption of material in the growth of the base semiconductor portion 8 in the thickness direction can be reduced, and the base semiconductor portion 8 can be grown laterally at high speed. The initial growth layer SL may be formed to a thickness of, for example, 2.0 μm or more and 3.0 μm or less.

[0057] In the first embodiment, the lateral growth of the base semiconductor portions 8 growing laterally from both sides of the mask portion 5 is stopped before they meet, but this is not limiting. The lateral growth of the base semiconductor portions 8 growing laterally from both sides of the mask portion 5 may be stopped after they meet (see FIG. 18). In this case, since there will be many dislocations (crystal defects) at the meeting portion, the aperture portion AP of the semiconductor laser element 20 is configured not to overlap with the meeting portion in a plan view.

[0058] When the base semiconductor portion 8 is formed using the ELO method, a template substrate 7 including the main substrate 1 and the mask pattern 6 on the main substrate 1 may be used. The template substrate 7 may have a growth-inhibiting region (e.g., a region that inhibits crystal growth in the Z direction) corresponding to the mask portion 5, and a seed region corresponding to the opening K. For example, the growth-inhibiting region and the seed region may be formed on the main substrate 1, and the base semiconductor portion 8 may be formed on the growth-inhibiting region and the seed region using the ELO method.

[0059] (Compound semiconductor part and electrodes) The base semiconductor portion 8 and the compound semiconductor portion 9 may be formed continuously in the same apparatus (for example, an MOCVD apparatus), or the substrate may be removed from the apparatus once after the base semiconductor portion 8 is formed, and the compound semiconductor portion 9 may be formed after the surface of the base semiconductor portion 8 is polished. In this case, the compound semiconductor portion 9 may be formed after an n-type GaN-based semiconductor layer (for example, with a thickness of about 0.1 μm to about 3 μm) is formed on the base semiconductor portion 8 to serve as a buffer during regrowth. In addition to the MOCVD apparatus, a sputtering apparatus, a remote plasma CVD apparatus (RPCVD), a PSD (Pulse Sputter Deposition) apparatus, etc. may be used to form the compound semiconductor portion 9. In the remote plasma CVD apparatus and the PSD apparatus, hydrogen is not used as a carrier gas, so that a low-resistance p-type GaN-based semiconductor portion can be formed.

[0060] The MQW structure of the active layer 35 may be, for example, a 5-6 period structure of InGaN / GaN. The In composition varies depending on the target emission wavelength, and may be about 15-20% In concentration for blue (near 450 nm) and about 30% In concentration for green (near 530 nm). If necessary, an electron blocking layer (for example, an AlGaN layer) may be formed on the active layer 35. In addition, in order to reduce resistance, the surface (about 10 nm) of the p-type semiconductor layer 36 may be a highly doped p-type layer.

[0061] Fig. 12 is a cross-sectional view showing another configuration of the semiconductor device of Example 1. In Fig. 8, an aperture portion AP is provided in the insulating film KF, but this is not limited thereto. As shown in Fig. 12, a ring-shaped high resistance portion HR (a region with a low p-type doping concentration) may be provided in the p-type semiconductor layer 36, and the inside of the high resistance portion HR may be configured as an aperture portion AP (current confinement portion) (a configuration in which the high resistance portion HR surrounds the aperture portion AP). The high resistance portion HR may be formed by increasing the resistance of a portion of the p-type semiconductor layer 36 by ion implantation or the like.

[0062] The first electrode E1 is made of a transparent conductive material having optical transparency, such as indium tin oxide (including crystalline ITO, amorphous ITO, and Sn-doped In2O3), indium zinc oxide (IZO), IFO (F-doped In2O3), tin oxide (including SnO2, Sb-doped SnO2, and F-doped SnO2), and zinc oxide (including ZnO, Al-doped ZnO, and B-doped ZnO).

[0063] The first electrode E1 may include at least one of Ga (gallium) oxide, Ti (titanium) oxide, Nb (niobium) oxide, and Ni (nickel) oxide as a base layer. The aperture diameter of the first electrode E1 (the diameter of the current injection region in contact with the p-type semiconductor portion) may be, for example, 2 μm or more and 100 μm or less.

[0064] The first pad P1 in contact with the first electrode E1 may have a single-layer structure or a multi-layer structure containing at least one of Au, Ag, Pd, Pt, Ni, Ti, V, W, Cr, Al, Cu, Zn, Sn, and In. For the multi-layer structure, for example, with the left side as the lower layer, a configuration such as Ti layer / Au layer, Ti layer / Al layer, Ti layer / Al layer / Au layer, Ti layer / Pt layer / Au layer, Ni layer / Au layer, Ni layer / Au layer / Pt layer, Ni layer / Pt layer, Pd layer / Pt layer, Ag layer / Pd layer, etc. can be adopted.

[0065] (singularization) Fig. 13 is a plan view showing another configuration of the semiconductor device of Example 1. As shown in Fig. 13, the semiconductor device 30 of Fig. 7 may be diced into individual semiconductor devices 30, each of which includes one semiconductor laser element 20. It may also be diced into individual semiconductor devices 30, each of which includes multiple semiconductor laser elements 20.

[0066] (Modification) Fig. 14 is a cross-sectional view showing another configuration of the semiconductor device in accordance with the embodiment 1. As shown in Fig. 14, the semiconductor device 30 includes a circuit board CB disposed on the opposite side of the main substrate 1 and electrically connected to the first and second pads P1 and P2. The circuit board CB may be configured to drive the semiconductor laser element 20.

[0067] The opening KR of the main substrate 1 may be formed after bonding the semiconductor device 30 and the circuit substrate CB. When a Si substrate is used for the main substrate 1, the thickness of a typical Si substrate is about 300 μm to about 2.0 mm. Since it is not easy to form a through hole in a thick Si substrate, after bonding the circuit substrate CB to the opposite side of the Si substrate, the Si substrate (main substrate 1) may be thinned (for example, to a thickness of 300 μm or less) by a method such as wet etching, dry etching, polishing, or CMP, and then a through hole having the opening KR may be formed. When manufacturing a semiconductor laser element such as a VCSEL, the depth of the hole H and the size of the opening KR can be set so that the emitted laser light is not blocked by the hole wall of the main substrate 1.

[0068] 15 and 16 are cross-sectional views showing another configuration of the semiconductor device according to the first embodiment. In the semiconductor device 30 of FIG. 15, a hole H penetrates the base portion 4, and the bottom of the hole H is included in (in contact with) the mask portion 5. This makes it possible to suppress the propagation of light to the base portion 4. In the semiconductor device 30 of FIG. 16, a hole H penetrates the base portion 4 and the mask portion 5. This makes it possible to suppress the propagation of light to the base portion 4 and the mask portion 5.

[0069] 16, by forming the bottom of the hole H in the base semiconductor portion 8, the cavity length is shortened and the light scattering at the mask portion 5 and the semiconductor interface is reduced, so that the internal loss αi is reduced. This makes it possible to improve the light emission efficiency.

[0070] 17 and 18 are cross-sectional views showing another configuration of the semiconductor device according to the first embodiment. As shown in FIG. 17, a configuration in which the first partition portion QF and the second partition portion QS are not provided is also possible. In FIG. 5, FIG. 17, and the like, a plurality of base semiconductor portions 8 and a plurality of compound semiconductor portions 9 are formed, but this is not limiting. As shown in FIG. 18, a configuration in which the base semiconductor portions 8 grown on the mask portion 5 from adjacent openings K meet and are integrated may also be used.

[0071] Fig. 19 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. In Fig. 5, Fig. 17, etc., the first and second electrodes E1 and E2 are aligned in the Y direction (the <1-100> direction of the base semiconductor portion), but this is not limiting. As shown in Fig. 19, the first and second electrodes E1 and E2 can also be formed aligned in the X direction (the <1-100> direction of the base semiconductor portion).

[0072] Fig. 20 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1. As shown in Fig. 20, a phosphor EK (wavelength converter) may be disposed in the hole H, and the second light reflecting portion 11 may be located closer to the bottom side of the hole H than the phosphor EK. In this way, light having a wavelength (for example, in the visible light range) different from that of the light generated in the active layer 35 can be emitted from the opening KR.

[0073] Fig. 21 is a cross-sectional view showing another configuration of the semiconductor device according to Example 1. As shown in Fig. 21, the second light reflecting portion 11 may be configured to contact the lower surface 1U (non-hole portion) of the main substrate 1. This can simplify the process.

[0074] 22 and 23 are cross-sectional views showing another configuration of the semiconductor device according to the first embodiment. As shown in FIG. 22, the base portion 4 may be provided locally so as to overlap with the opening K, rather than entirely. In this way, the stress from the base portion 4 can be reduced. In this case, as shown in FIG. 23, the mask pattern 6 may be a substrate processing film SK (for example, silicon oxide, which is a thermally oxidized film of silicon or silicon carbide) obtained by processing the surface of the main substrate 1 (for example, Si or SiC).

[0075] 24 and 25 are cross-sectional views showing another configuration of the semiconductor device according to the first embodiment. Although an underlayer 4 is provided in FIG. 5 and the like, the present invention is not limited to this. As shown in FIG. 24, by using a GaN substrate (bulk crystal), a 6H—SiC substrate (bulk crystal), or the like for the main substrate 1, it is possible to grow the base semiconductor portion 8 on the main substrate 1 without providing the underlayer 4. In this case as well, the bottom of the hole H can be formed inside the base semiconductor portion 8, as shown in FIG. 25.

[0076] Fig. 26 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. As shown in Fig. 26, the semiconductor device according to the first embodiment can also be configured without the mask pattern 6 by removing the mask portion 5 after the base semiconductor portion 8 is formed. In this case, the lower surface of the base semiconductor portion 8 contacts the hollow portion TU. Note that a light-transmitting material different from the growth selection mask may be disposed in the hollow portion TU. For example, a light-transmitting material may be filled between the seed portion 3 or the main substrate 1 and the base semiconductor portion 8.

[0077] Example 2 FIG. 27 is a cross-sectional view of the semiconductor device according to the second embodiment taken along the X direction. FIG. 28 is a cross-sectional view of the semiconductor device according to the second embodiment taken along the Y direction. As shown in FIGS. 27 and 28, the semiconductor device 30 according to the second embodiment includes a seed portion 3, a mask pattern 6 located above the seed portion 3 and including a mask portion 5 and an opening K, a base semiconductor portion 8 located above the mask pattern 6, a compound semiconductor portion 9 located above the base semiconductor portion 8, an insulating film KF located on the compound semiconductor portion 9, a first electrode E1 and a second electrode E2, a first light reflecting portion 10 located on the first electrode E1, and a second light reflecting portion 11 provided below the base portion 4 and overlapping with the first light reflecting portion 10 in a plan view. A buffer portion 2 is provided between the main substrate 1 and the seed portion 3, and the base portion 4 includes the buffer portion 2 and the seed portion 3. The buffer portion 2 may be a buffer layer, and the seed portion 3 may be a seed layer. The buffer portion 2 may have a function of suppressing a melting phenomenon caused by contact between the main substrate 1 and the seed portion 3. The base portion 4 may be formed of the seed portion 3 without providing the buffer portion 2. The seed portion 3 may be provided locally (for example, in a ridge shape extending in the Y direction) so as to overlap with the opening portion K, rather than entirely.

[0078] The first electrode E1 is an anode provided on the compound semiconductor portion 9. The compound semiconductor portion 9 is provided on the base semiconductor portion 8, but the compound semiconductor portion 9 is not formed above a part of the base semiconductor portion 8, and the second electrode E2, which is a cathode, is provided so as to be in contact with this part of the base semiconductor portion 8. The first electrode E1 is optically transparent.

[0079] The semiconductor device 30 includes a vertical cavity surface emitting laser element (VCSEL) 20 including a base semiconductor portion 8, a compound semiconductor portion 9, an insulating film KF, first and second electrodes E1 and E2, and first and second light reflecting portions 10 and 11. ) is configured. Specifically, light generated in the compound semiconductor portion 9 by a current between the first and second electrodes E1 and E2 undergoes laser oscillation due to stimulated emission and feedback between the first and second light reflecting portions 10 and 11, and is emitted as laser light, for example, from the second light reflecting portion 11. In the semiconductor device 30, the second light reflecting portion 11 is in contact with the external space GK below, which improves heat dissipation and increases reliability.

[0080] An insulating film KF is provided between the peripheral edge of the first electrode E1 and the compound semiconductor portion 9. The insulating film KF narrows the current path between the first and second electrodes E1 and E2 on the anode side, thereby improving the light emission efficiency.

[0081] The base semiconductor portion 8 may be made of an n-type semiconductor (e.g., silicon-doped gallium nitride). The base semiconductor portion 8 may be made of a first portion HD located on the opening K, a second portion HD located on the mask portion 5, and a third portion HD having a threading dislocation density of 5×10 6 / cm 2 The compound semiconductor portion 9 includes a second portion (low defect portion) SD described below, and the second portion SD overlaps with the compound semiconductor portion 9 in a planar view. The portion of the compound semiconductor portion 9 that overlaps with the second portion SD in a planar view inherits the low dislocation properties (low defect properties), and therefore the light emission efficiency of this portion can be improved.

[0082] FIG. 29 is a flow chart showing an example of a method for manufacturing the semiconductor device of FIG. 27. In the method for manufacturing the semiconductor device of FIG. 29, after the step of preparing the template substrate 7, the base semiconductor portion 8 is formed by using the ELO method. Next, the step of forming the compound semiconductor portion 9 is performed, and then the step of forming the insulating film DF (current confinement layer) and the first and second electrodes E1 and E2 is performed. Then, the step of forming the first light reflecting portion 10 is performed, and then the step of forming the first and second pads P1 and P2 is performed. Then, the step of removing the main substrate 1 by wet etching or dry etching, polishing, CMP (Chemical machinery polish), etc., and the step of forming the second light reflecting portion 11 (on the base portion 4) on the opposite side to the side where the first light reflecting portion 10 is located with respect to the mask pattern 6 are performed. Before removing the main substrate 1, it may be bonded to a circuit board CB. In this way, the mechanical strength of the thinned semiconductor device 30 can be maintained.

[0083] Fig. 30 is a cross-sectional view showing another configuration of the semiconductor device in accordance with the second embodiment. As shown in Fig. 30, the semiconductor device 30 includes a support substrate SK located above the compound semiconductor portion 9. The support substrate SK is disposed on the opposite side of the mask pattern 6 from the side where the first light reflecting portion 11 is located, and is electrically connected to the first and second pads P1 and P2. The support substrate SK may be a circuit substrate that drives the semiconductor laser element 20.

[0084] FIG. 31 is a flow chart showing an example of a method for manufacturing the semiconductor device of FIG. 30. FIG. 32 is a cross-sectional view showing the steps of the method for manufacturing the semiconductor device of FIG. 30. In the method for manufacturing the semiconductor device of FIG. 30, after the step of preparing the template substrate 7, the base semiconductor portion 8 is formed by using the ELO method. Next, the step of forming the compound semiconductor portion 9 is performed, followed by the steps of forming the insulating film DF (current confinement layer), the first and second electrodes E1 and E2, the step of forming the first light reflecting portion 10, and the step of forming the first and second pads P1 and P2. Thereafter, the steps of bonding the support substrate SK to the first and second pads P1 and P2 and holding the base semiconductor portion 8 and the compound semiconductor portion 9 on the support substrate SK, removing the main substrate 1 by wet etching or dry etching, and forming the second light reflecting portion 11 (on the base portion 4) on the opposite side of the side where the support substrate SK is located with respect to the mask pattern 6 are performed.

[0085] Example 3 The base semiconductor portion 8 in the first and second embodiments may be made of GaN, but is not limited thereto. The base semiconductor portion 8 may be made of InGaN, which is a GaN-based semiconductor. The lateral deposition of InGaN is performed at a low temperature, for example, below 1000° C. This is because at high temperatures, the vapor pressure of indium increases and indium is not effectively incorporated into the film. The low deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the base semiconductor portion 8. In addition, InGaN has the effect of being less reactive with the mask portion 5 (silicon oxide film, silicon nitride film, etc.) than GaN. When indium is incorporated into the base semiconductor portion 8 at an In composition level of 1% or more, the reactivity with the mask portion 5 is further reduced, which is desirable. Triethylgallium (TEG) may be used as the gallium source gas.

[0086] Example 4 Fig. 33 is a schematic diagram showing the configuration of an electronic device according to Example 4. The electronic device 40 in Fig. 33 includes the semiconductor device 30 of Examples 1 to 3 and a control unit 80 including a processor that controls the semiconductor device 30. Examples of the electronic device 40 include a communication device, an optical device, a display device, a lighting device, a sensor device, an information processing device, a medical device, and an electric vehicle (EV).

[0087] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-mentioned embodiments. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and the embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure. [Explanation of symbols]

[0088] 1 Main Board 2 Buffer section 3 Seed Section 4 Base 5 Mask section 6 Mask Pattern 8 Base Semiconductor Section 9. Compound Semiconductor Department 10 1st light reflection section 11 Second light reflection section 15 Semiconductor Substrates 20 Semiconductor laser element 30 Semiconductor Devices K opening E1 1st electrode E2 2nd electrode H Hall CB Circuit Board SK support board

Claims

1. a semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate and including a hole penetrating the main substrate in a thickness direction; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion disposed in the hole and overlapping the first light reflecting portion below the first light reflecting portion; The second light reflecting portion is in contact with a hollow portion within the hole.

2. A semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate, the semiconductor substrate including a hole penetrating the main substrate in a thickness direction; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion disposed in the hole and overlapping the first light reflecting portion below the first light reflecting portion; at least one of a mask pattern including a mask portion and an opening and a base portion is disposed between the main substrate and the base semiconductor portion; a bottom surface of the hole is included in the base portion or the mask portion, A semiconductor device, wherein the base semiconductor portion does not include a bottom surface of the hole.

3. The semiconductor device according to claim 1 , wherein at least a portion of the second light reflecting portion is in contact with an inner surface of the main substrate.

4. The semiconductor device according to claim 1 , wherein the second light reflecting portion is positioned from a bottom surface of the hole to an inner surface of the main substrate.

5. The semiconductor device according to claim 1 , further comprising a first electrode located above the compound semiconductor portion and overlapping with the first light reflecting portion in a plan view.

6. The semiconductor device of claim 5 including a second electrode located above the base semiconductor portion.

7. The semiconductor device of claim 6 , wherein the first and second electrodes are aligned in a <1-100> direction or a <11-20> direction of the base semiconductor portion.

8. 3 . The semiconductor device according to claim 1 , wherein the base semiconductor portion includes a first portion and a second portion that overlaps with the second light reflecting portion in the thickness direction and has a threading dislocation density that is ⅕ or less than that of the first portion.

9. The semiconductor device according to claim 8 , wherein the second portion overlaps with the first light reflecting portion and the second light reflecting portion in a plan view.

10. an insulating film in contact with an upper surface of the compound semiconductor portion; The semiconductor device according to claim 9 , wherein the insulating film includes an aperture portion overlapping the first light reflecting portion, the second portion, and the second light reflecting portion in a plan view.

11. A semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate, the semiconductor substrate including a hole penetrating the main substrate in a thickness direction; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion disposed in the hole and overlapping the first light reflecting portion below the first light reflecting portion; a first electrode located above the compound semiconductor portion and overlapping with the first light reflecting portion in a plan view; a second electrode located above the base semiconductor portion, the base semiconductor portion includes a first portion and a second portion that overlaps with the second light reflecting portion in a thickness direction and has a threading dislocation density that is ⅕ or less than that of the first portion; A semiconductor device, wherein, in a plan view, the first electrode and the second electrode do not overlap with the first portion.

12. 12. The semiconductor device according to claim 1, wherein at least one of the first light reflecting portion and the second light reflecting portion is a reflecting mirror in which one or more low refractive portions and one or more high refractive portions are alternately stacked.

13. a mask pattern located above the main substrate and including a mask portion and an opening portion; The semiconductor device according to claim 1 , wherein the base semiconductor portion is disposed across the mask portion from the opening.

14. The semiconductor device according to claim 13 , wherein the semiconductor substrate includes an underlay portion between the main substrate and the mask pattern.

15. The semiconductor device according to claim 14 , wherein the base portion includes a seed portion that overlaps an opening of the mask pattern in a plan view.

16. The semiconductor device according to claim 14 , wherein at least a portion of a bottom of the hole is included in the underlying portion or the mask portion.

17. The semiconductor device of claim 13 , wherein the holes extend through the mask portion.

18. The semiconductor device of claim 1 , 2 or 11 , wherein the main substrate is a silicon substrate or a silicon carbide substrate.

19. The threading dislocation density of the second portion is 5×10 ６ / cm ２ 9. The semiconductor device of claim 8, wherein:

20. The semiconductor device according to claim 1 , wherein the compound semiconductor portion includes a first type semiconductor layer, an active layer, and a second type semiconductor layer in this order.

21. 12. The semiconductor device according to claim 1, comprising at least one surface-emitting semiconductor laser element including the base semiconductor portion, the compound semiconductor portion, and the first and second optical reflectors.

22. A semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate, the semiconductor substrate including a hole penetrating the main substrate in a thickness direction; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion disposed in the hole and overlapping the first light reflecting portion below the first light reflecting portion; a mask pattern located above the main substrate and including a mask portion and an opening; a base portion located between the main substrate and the mask pattern, The underlying portion is locally provided so as to overlap an opening of the mask pattern.

23. The semiconductor device according to claim 22 , wherein the mask portion is a thermal oxide film of the main substrate.

24. 10. The semiconductor device according to claim 9, wherein the compound semiconductor portion includes an aperture portion overlapping with the first light reflecting portion, the second portion, and the second light reflecting portion in a planar view, and a high resistance portion surrounding the aperture portion and having a current resistance higher than that of the aperture portion.

25. The semiconductor device according to claim 10 , wherein an area of ​​a bottom surface of the hole is larger than an area of ​​the aperture portion.

26. The semiconductor device according to claim 1 , wherein the second light reflecting portion is in contact with a bottom and a sidewall of the hole.

27. ​​A semiconductor device as described in claim 2, wherein a base portion located above the main substrate and a mask pattern located above the base portion are arranged between the main substrate and the base semiconductor portion.

28. A phosphor is disposed in the hole, The semiconductor device according to claim 1 , wherein the second light reflecting portion is located closer to a bottom of the hole than the phosphor.

29. A semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate, the semiconductor substrate including a hole penetrating the main substrate in a thickness direction; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion disposed in the hole and overlapping the first light reflecting portion below the first light reflecting portion; The second light reflecting portion is in contact with a lower surface of the main substrate.

30. The semiconductor device of claim 6 , wherein the second electrode contacts the base semiconductor portion.

31. A semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate, the semiconductor substrate including a hole penetrating the main substrate in a thickness direction; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion disposed in the hole and overlapping the first light reflecting portion below the first light reflecting portion; a first electrode located above the compound semiconductor portion and overlapping with the first light reflecting portion in a plan view; a second electrode located above the base semiconductor portion, the second electrode is in contact with the base semiconductor portion, The second electrode has a recess, the recess being filled with an insulator.

32. The semiconductor device of claim 6 comprising a first pad in contact with the first electrode and a second pad in contact with the second electrode.

33. 33. The semiconductor device of claim 32, wherein the top surfaces of the first and second pads are flush.

34. 34. The semiconductor device of claim 33, wherein the upper surface levels of the first and second pads are higher than the upper surface level of the first light reflecting portion.

35. The semiconductor device of claim 32 , wherein at least a portion of the second pad does not overlap the hole in a plan view.

36. The semiconductor device of claim 32 , wherein at least a portion of the first pad does not overlap the hole in a plan view.

37. The semiconductor device of claim 32 , wherein the first pad contacts an upper surface of the first light reflecting portion.

38. The semiconductor device according to claim 10 , further comprising a light-transmitting first electrode between the compound semiconductor portion and the first light reflecting portion.

39. the first electrode is in contact with an upper surface of the insulating film; The semiconductor device of claim 38 , wherein the first electrode and the compound semiconductor portion are in contact at the aperture portion.

40. 40. The semiconductor device of claim 38, wherein the compound semiconductor portion comprises a GaN-based semiconductor and the first electrode comprises gallium oxide.

41. The semiconductor device according to claim 1 , wherein the reflectance of the second light reflecting portion is smaller than the reflectance of the first light reflecting portion.

42. The semiconductor device according to claim 12 , wherein each of the low refractive portion and the high refractive portion is made of a dielectric material.

43. A semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate, the semiconductor substrate including a hole penetrating the main substrate in a thickness direction; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion disposed in the hole and overlapping the first light reflecting portion below the first light reflecting portion; a mask pattern located above the main substrate and including a mask portion and an opening; a first partition portion having light reflectivity and overlapping with an opening of the mask pattern in a plan view.

44. A semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate, the semiconductor substrate including a hole penetrating the main substrate in a thickness direction; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion disposed in the hole and overlapping the first light reflecting portion below the first light reflecting portion; a mask pattern located above the main substrate and including a mask portion and an opening; a second partition portion having light reflectivity and overlapping a center of the mask portion in a plan view.

45. 45. The semiconductor device of claim 1, 2, 11, 22, 29, 31, 43, or 44, wherein the main substrate has a higher thermal conductivity than a bulk GaN substrate.

46. A semiconductor substrate having a main substrate and a base semiconductor portion located above the main substrate, the semiconductor substrate including a hole penetrating the main substrate in a thickness direction; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion disposed in the hole and overlapping the first light reflecting portion below the first light reflecting portion; a mask pattern located above the main substrate and including a mask portion and an opening; a base portion located between the main substrate and the mask pattern, The underlying portion has a thermal conductivity greater than that of the base semiconductor portion.

47. 47. The semiconductor device of claim 46, wherein the underlayer comprises silicon carbide.

48. The semiconductor device according to claim 13 , wherein the hole has a tapered shape that narrows toward the mask pattern side.

49. The semiconductor device of claim 6 , wherein the first electrode is an anode and the second electrode is a cathode.

50. The semiconductor device of claim 5 , further comprising a circuit board in electrical communication with the first electrode.

51. 13. An electronic device comprising the semiconductor device according to claim 1 , 2 , 11 , 22 , 29 , 31 , 43 , 44 , or 46 .

52. forming a base semiconductor portion on a template substrate including a main substrate and a mask pattern by using an ELO method; forming a compound semiconductor portion above the base semiconductor portion; forming a first light reflecting portion above the compound semiconductor portion; forming a hole penetrating the main substrate in a thickness direction and overlapping with the first light reflecting portion in a plan view; forming a second light reflecting portion in the hole; A method for manufacturing a semiconductor device, wherein the second light reflecting portion is in contact with a hollow portion within the hole.

53. An apparatus for manufacturing a semiconductor device, which performs each step according to claim 52.

54. A seed portion; a mask pattern located above the seed portion and having a mask portion and an opening; a base semiconductor portion located above the mask pattern; a compound semiconductor portion located above the base semiconductor portion; a first light reflecting portion located above the compound semiconductor portion; a second light reflecting portion located below the seed portion and overlapping the first light reflecting portion below the first light reflecting portion.

55. 55. The semiconductor device of claim 54, further comprising a support substrate located above the first light reflecting portion.

56. forming a base semiconductor portion on a template substrate including a main substrate and a mask pattern by using an ELO method; forming a compound semiconductor portion above the base semiconductor portion; forming a first light reflecting portion above the compound semiconductor portion; removing the main substrate; forming a second light reflecting portion on the opposite side to the side on which the first light reflecting portion is located, using the mask pattern as a reference.

57. 57. The method of claim 56, further comprising holding the template substrate, the base semiconductor portion and the compound semiconductor portion on a support substrate before removing the main substrate.

Images