Semiconductor memory device and control method thereof

Abstract

A semiconductor memory device and a control method thereof capable of shortening the time required for impedance calibration processing when a plurality of memory dies are connected to an external resistor are provided. [Solution] The semiconductor memory device includes a plurality of memory dies 10 connected to a common external resistor R via a calibration pad ZQPAD, and a control unit 20 that performs pull-down calibration on one or more second memory dies 10b different from the first memory die 10a among the plurality of memory dies 10 while performing pull-up calibration on a first memory die 10a among the plurality of memory dies 10, and controls the first memory die 10a to be subjected to pull-down calibration while performing pull-up calibration on the second memory die 10b.

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device and a control method thereof. [Background technology]

[0002] In conventional semiconductor memory devices, there are known devices that perform impedance calibration such as ZQ calibration in order to match the impedance of a transmission line with the output impedance of an output circuit (for example, Patent Document 1). In addition, there are also known conventional semiconductor memory devices that are configured to share a ZQ terminal and an external resistor among multiple memory dies in order to reduce manufacturing costs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-123987 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, when performing ZQ calibration in a conventional semiconductor memory device, a pull-up calibration is first performed to optimize the pull-up code, and then the pull-down calibration is performed using the pull-up code to optimize the pull-down code. As a result, when performing ZQ calibration in a semiconductor memory device in which a ZQ terminal and an external resistor are shared by multiple memory dies, as shown in Fig. 1, it is necessary to shift the start timing of impedance calibration between each memory die, so there is a risk that the processing time of impedance calibration will be extended as the number of memory dies increases. For example, in the example shown in Fig. 1, if the number of memory dies is N (N is an integer equal to or greater than 2) and the processing time of each of the pull-up calibration and the pull-down calibration is t (t>0), the processing time of impedance calibration in the semiconductor memory device is expressed as (N+1)t.

[0005] The present invention has been made in consideration of the above-mentioned problems, and aims to provide a semiconductor memory device and a control method thereof that are capable of shortening the processing time for impedance calibration when multiple memory dies are connected to an external resistor. [Means for solving the problem]

[0006] In order to solve the above problem, the present invention provides a semiconductor memory device comprising: a plurality of memory dies connected to a common external resistor via a calibration pad; and a control unit that performs pull-down calibration on one or more second memory dies different from the first memory die among the plurality of memory dies while performing pull-up calibration on a first memory die among the plurality of memory dies, and controls to perform pull-down calibration on the first memory die while performing pull-up calibration on the second memory die.

[0007] According to this invention, it is possible to simultaneously perform pull-up calibration on a first memory die and pull-down calibration on a second memory die, and to simultaneously perform pull-down calibration on the first memory die and pull-up calibration on the second memory die. This makes it possible to shorten the processing time for impedance calibration in a semiconductor memory device, as compared to, for example, a case in which the start timing of impedance calibration is shifted between each memory die.

[0008] The present invention also provides a control method for a semiconductor memory device, the semiconductor memory device having a plurality of memory dies connected to a common external resistor via a calibration pad, and a control unit of the semiconductor memory device executes a control step of performing pull-down calibration on one or more second memory dies different from the first memory die among the plurality of memory dies while performing pull-up calibration on a first memory die among the plurality of memory dies, and performing pull-down calibration on the first memory die while performing pull-up calibration on the second memory die. Effect of the Invention

[0009] According to the semiconductor memory device and the control method thereof of the present invention, when a plurality of memory dies are connected to an external resistor, the time required for impedance calibration processing can be reduced. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of a sequence of an impedance calibration process in a conventional semiconductor memory device. [Diagram 2] 1 is a diagram showing an example of the configuration of a semiconductor memory device according to an embodiment of the present invention; [Diagram 3] 11 is a diagram illustrating an example of an operation of the semiconductor memory device when pull-up calibration is performed on the first memory die. FIG. [Figure 4] 11 is a diagram illustrating an example of an operation of a semiconductor memory device when pull-down calibration is performed on a first memory die. FIG. [Diagram 5] 1 is a diagram showing an example of a sequence of an impedance calibration process in a semiconductor memory device according to an embodiment; [Figure 6] 11 is a diagram showing an example of a sequence of an impedance calibration process in a semiconductor memory device according to a modified example. [Figure 7] 11 is a diagram showing an example of a sequence of an impedance calibration process in a semiconductor memory device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] FIG. 2 is a diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 2, the semiconductor memory device includes a plurality of (two in the example shown in FIG. 2) memory dies 10, and each memory die 10 is provided with a control unit 20. Here, an external resistor R shared by the plurality of memory dies 10 is connected to the calibration pad ZQPAD of each of the plurality of memory dies 10. The external resistor R may have a resistance value that satisfies the requirements of the output circuit of the semiconductor memory device. In addition, each of the plurality of memory dies 10 is provided with other pads PAD different from the calibration pad ZQPAD, and the other pads PAD of each memory die 10 are connected to each other. Note that FIG. 2 shows a case where each memory die 10 is provided with two pads ZQPAD,PAD, but each memory die 10 may be provided with, for example, three or more pads. Also, FIG. 2 shows a case where all pads of each memory die 10 are connected to pads of other memory dies 10, but at least one pad of all pads of each memory die 10 may not be connected to pads of other memory dies 10.

[0012] In this embodiment, the semiconductor memory device is described as a dynamic random access memory (DRAM) as an example, but the semiconductor memory device may be another type of semiconductor memory device (e.g., a static random access memory (SRAM), a flash memory, etc.).

[0013] In addition, in this embodiment, in order to simplify the description, detailed descriptions of other circuits (eg, a power supply circuit, a command decoder, an address decoder, a clock generator, etc.) well known in semiconductor memory devices such as DRAMs will be omitted.

[0014] Each memory die 10 includes a pull-up calibration unit 11, a pull-down calibration unit 12, a generation unit 13, a switch unit 14, and a control unit 20.

[0015] The pull-up calibration unit 11 includes a first transistor M1 and is configured to generate a first voltage based on a first control signal (pull-up code) code_p and a resistance value of an external resistor R. In this embodiment, the first transistor M1 is a P-type field effect transistor (MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)) as an example, but the first transistor M1 may be, for example, an N-type MOSFET or another transistor. In this case, the source terminal (first terminal of the first transistor) of the first transistor M1 is connected to an operating voltage VDD, the drain terminal (second terminal of the first transistor) of the first transistor M1 is connected to the external resistor R via a calibration pad ZQPAD, and the first control signal code_p is input to the gate terminal (control terminal of the first transistor).

[0016] The pull-down calibration unit 12 includes a second transistor M2 and a third transistor M3, and is configured to generate a second voltage based on a first control signal (pull-up code) code_p and a second control signal (pull-down code) code_n. In this embodiment, the second transistor M2 is a P-type MOSFET, and the third transistor M3 is an N-type MOSFET. However, the second transistor M2 may be, for example, an N-type MOSFET or other transistor, and the third transistor M3 may be, for example, a P-type MOSFET or other transistor. In this case, the source terminal (first terminal of the second transistor) of the second transistor M2 is connected to the operating voltage VDD, the drain terminal (second terminal of the second transistor) of the second transistor M2 is connected to the drain terminal (first terminal of the third transistor) of the third transistor M3, and the first control signal code_p is input to the gate terminal (control terminal of the second transistor). In addition, the source terminal (second terminal of the third transistor) of the third transistor M3 is connected to the ground voltage GND, and the second control signal code_n is input to the gate terminal (control terminal of the third transistor).

[0017] The pull-up calibration section 11 and the pull-down calibration section 12 may have the same voltage-current characteristics as the output circuit of the semiconductor memory device.

[0018] In addition, the first transistor M1 and the second transistor M2 provided in each memory die 10 may have the same size (e.g., the same channel width and channel length) and the same layout. That is, the first transistor M1 and the second transistor M2 provided in each memory die 10 may have the same resistance characteristics.

[0019] The generation unit 13 includes a comparator 13a and an arithmetic circuit 13b, and is configured to generate a first control signal code_p based on a first comparison result obtained by comparing a first voltage with a reference voltage when pull-up calibration is performed on the corresponding memory die, and to generate a second control signal code_n based on a second comparison result obtained by comparing the first voltage with a second voltage when pull-down calibration is performed on the corresponding memory die.

[0020] One terminal (positive terminal) of the comparator 13a is connected to the drain terminal (second terminal of the first transistor) of the first transistor M1, and the other terminal (negative terminal) of the comparator 13a is connected to the switch unit 14.

[0021] The arithmetic circuit 13b is connected to the output terminal of the comparator 13a and receives the comparison result from the comparator 13a. The arithmetic circuit 13b generates a first control signal code_p or a second control signal code_n based on the received comparison result. The arithmetic circuit 13b may be configured to generate either the first control signal code_p or the second control signal code_n based on the control of the control unit 20.

[0022] The switch unit 14 includes a first switch connected to a reference voltage and a second switch connected to a node between the drain terminal of the second transistor M2 (the second terminal of the second transistor) and the drain terminal of the third transistor M3 (the first terminal of the third transistor), and is configured such that only one of the first switch and the second switch is controlled to be on. For example, when the first switch is controlled to be on, the reference voltage is input to the other terminal of the comparator 13a, and when the second switch is controlled to be on, the voltage of the node between the drain terminal of the second transistor M2 (the second terminal of the second transistor) and the drain terminal of the third transistor M3 (the first terminal of the third transistor) is input to the other terminal of the comparator 13a. Note that the on / off control of the first switch and the second switch may be performed by the control unit 20. In addition, in this embodiment, a case where the value of the reference voltage is half the voltage value of the operating voltage VDD is described as an example, but the value of the reference voltage may be set to an arbitrary value.

[0023] The control unit 20 performs control so that while performing pull-up calibration on a first memory die 10a among the multiple memory dies 10, pull-down calibration is performed on one or more second memory dies 10b different from the first memory die 10a among the multiple memory dies 10, and while performing pull-up calibration on the second memory die 10b, pull-down calibration is performed on the first memory die 10a. Note that the control unit 20 may be configured with a dedicated hardware device or logic circuit.

[0024] Furthermore, when performing pull-up calibration on the first memory die 10a, the control unit 20 may control the pull-up calibration unit 11 of the first memory die 10a to operate and the pull-down calibration unit 12 of the second memory die 10b to operate, thereby performing pull-down calibration on the second memory die 10b using the first control signal code_p generated in the first memory die 10a. This makes it possible to perform pull-down calibration on the second memory die 10b using the first control signal code_p generated in the first memory die 10a while pull-up calibration is being performed on the first memory die 10a.

[0025] Furthermore, when performing pull-down calibration on the first memory die 10a, the control unit 20 may control the pull-down calibration unit 12 of the first memory die 10a to operate and the pull-up calibration unit 11 of the second memory die 10b to operate, thereby performing pull-down calibration on the first memory die 10a using the first control signal code_p generated in the second memory die 10b. This makes it possible to perform pull-down calibration on the first memory die 10a using the first control signal code_p generated in the second memory die 10b while pull-up calibration is being performed on the second memory die 10b.

[0026] Furthermore, when pull-up calibration is performed on the first memory die 10a, the control unit 20 may control the first transistor M1 of the first memory die 10a to operate and the first transistor M1 of the second memory die 10b to stop operating. This makes it possible to send only the current flowing through the first transistor M1 of the first memory die 10a to the external resistor R via the calibration pad ZQPAD when pull-up calibration is performed on the first memory die 10a, as will be described later.

[0027] Furthermore, when pull-up calibration is performed on the first memory die 10a, the control unit 20 may perform control to stop the operation of the third transistor M3 of the first memory die 10a and also stop the operation of the second transistor M2 of the second memory die 10b. This makes it possible to send a current flowing through the second transistor M2 of the first memory die 10a to the third transistor M3 of the second memory die 10b when pull-up calibration is performed on the first memory die 10a, as will be described later.

[0028] Furthermore, when pull-down calibration is performed on the first memory die 10a, the control unit 20 may control the operation of the second transistor M2 of the first memory die 10a to be stopped and the operation of the third transistor M3 of the second memory die 10b to be stopped. This makes it possible to send a current flowing through the second transistor M2 of the second memory die 10b to the third transistor M3 of the first memory die 10a when pull-down calibration is performed on the first memory die 10a, as described below.

[0029] In addition, the control unit 20 of each memory die 10 may be configured to determine, at a predetermined timing, which operation, pull-up calibration or pull-down calibration, to perform on the corresponding memory die 10 by using information stored in a non-volatile storage device, such as an OTPROM (One Time Programmable ROM) such as a fuse ROM (Read Only Memory) or a non-volatile memory.

[0030] Next, an example of the operation of the semiconductor memory device according to this embodiment will be described with reference to Figures 3 and 4. Here, Figure 3 shows an example of the operation of the semiconductor memory device when pull-up calibration is performed on the first memory die 10a, and Figure 4 shows an example of the operation of the semiconductor memory device when pull-down calibration is performed on the first memory die 10a.

[0031] First, the case of Fig. 3 will be described. For example, when a ZQ calibration command is input to the semiconductor memory device, the control unit 20 of the first memory die 10a performs pull-up calibration on the first memory die 10a based on a clock signal CLK input from the outside or generated within the semiconductor memory device, and the control unit 20 of the second memory die 10b performs pull-down calibration on the second memory die 10b. Here, the control unit 20 of the first memory die 10a stops the operation of the third transistor M3 of the first memory die 10a, and the control unit 20 of the second memory die 10b stops the operation of the first transistor M1 and the second transistor M2 of the second memory die 10b.

[0032] In this case, the current flowing through the first transistor M1 of the first memory die 10a flows to the external resistor R via the calibration pad ZQPAD of the first memory die 10a as shown by the dashed arrow in the figure. Also, the current flowing through the second transistor M2 of the first memory die 10a flows to the third transistor M3 of the second memory die 10b via the other pads PAD of the first memory die 10a and the second memory die 10b as shown by the dashed arrow in the figure. In this case, the control unit 20 of the first memory die 10a may control to turn off a switch (not shown) connected to the third transistor M3 of the first memory die 10a, and the control unit 20 of the second memory die 10b may control to turn off switches (not shown) connected to each of the first transistor M1 and the second transistor M2 of the second memory die 10b to cut off the current supply to these transistors, thereby stopping the operation of these transistors.

[0033] Furthermore, the control unit 20 of the first memory die 10a controls the first switch of the switch unit 14 of the first memory die 10a to be on. As a result, a reference voltage (here, the value of the reference voltage is shown as VDD / 2) is input to the other terminal of the comparator 13a of the generation unit 13 of the first memory die 10a. Furthermore, the control unit 20 of the second memory die 10b controls the second switch of the switch unit 14 of the second memory die 10b to be on. As a result, a voltage (second voltage) of a node between the drain terminal of the second transistor M2 (second terminal of the second transistor) and the drain terminal of the third transistor M3 (first terminal of the third transistor) of the second memory die 10b is input to the other terminal of the comparator 13a of the generation unit 13 of the second memory die 10b.

[0034] Moreover, the first voltage generated by the pull-up calibration unit 11 of the first memory die 10a is input to one terminal of the comparator 13a of the generation unit 13 of the first memory die 10a. Here, the value of the first voltage is expressed as Rzq / (Rzq+Rp0), for example, where the resistance value of the external resistor R is Rzq and the resistance value of the first transistor M1 is Rp0. Furthermore, the comparator 13a of the generation unit 13 of the first memory die 10a compares the first voltage with a reference voltage to generate a comparison result. Furthermore, when the arithmetic circuit 13b of the generation unit 13 of the first memory die 10a receives the comparison result, it performs, for example, a binary search based on the comparison result to generate a first control signal code_p for adjusting the first voltage (i.e., the resistance value of the first transistor M1 of the first memory die 10a) so that the value of the voltage on the calibration pad ZQPAD becomes equal to the reference voltage. Then, the generated first control signal code_p is input to the first transistor M1 and the second transistor M2 of the first memory die 10a.

[0035] In this manner, pull-up calibration is performed in the first memory die 10a.

[0036] On the other hand, the above-mentioned first voltage (here, the value of the first voltage is shown as Rzq / (Rzq+Rp0)) is input to one terminal of the comparator 13a of the generation unit 13 of the second memory die 10b. The second voltage generated by the pull-down calibration unit 12 of the second memory die 10b is input to the other terminal of the comparator 13a of the generation unit 13 of the second memory die 10b. Here, the value of the second voltage is expressed as Rn1 / (Rn1+Rp0), for example, when the resistance value of the second transistor M2 of the first memory die 10a is Rp0 and the resistance value of the third transistor M3 of the second memory die 10b is Rn1. Furthermore, the comparator 13a of the generation unit 13 of the second memory die 10b compares the first voltage with the second voltage to generate a comparison result. As described above, if it is assumed that the resistance values ​​(=Rp0) of the first transistor M1 and the second transistor M2 of the first memory die 10a are equal, the comparator 13a compares the resistance value Rzq of the external resistor R with the resistance value Rn1 of the third transistor M3.

[0037] Furthermore, when the arithmetic circuit 13b of the generation unit 13 of the second memory die 10b receives the comparison result, the arithmetic circuit 13b performs, for example, a binary search based on the comparison result to generate a second control signal code_n for adjusting the second voltage (i.e., the resistance value of the third transistor M3 of the second memory die 10b) so that the first voltage and the second voltage are equal. Then, the generated second control signal code_n is input to the third transistor M3 of the second memory die 10b. Considering that the resistance value of the second transistor M2 of the first memory die 10a is controlled by the first control signal code_p generated in the first memory die 10a, the pull-down calibration is performed in the second memory die 10b using the first control signal code_p generated in the first memory die 10a.

[0038] In this manner, at the same time that pull-up calibration is performed in the first memory die 10a, pull-down calibration is performed in the second memory die 10b using the first control signal code_p generated in the first memory die 10a.

[0039] Next, the case of Fig. 4 will be described. For example, when the pull-up calibration for the first memory die 10a and the pull-down calibration for the second memory die 10b are completed, the control unit 20 of the first memory die 10a performs pull-down calibration for the first memory die 10a, and the control unit 20 of the second memory die 10b performs pull-up calibration for the second memory die 10b. Here, the control unit 20 of the first memory die 10a stops the operation of the first transistor M1 and the second transistor M2 of the first memory die 10a, and the control unit 20 of the second memory die 10b stops the operation of the third transistor M3 of the second memory die 10b.

[0040] In this case, the current flowing through the first transistor M1 of the second memory die 10b flows to the external resistor R via the calibration pad ZQPAD of the second memory die 10b as shown by the dashed arrow in the figure. Also, the current flowing through the second transistor M2 of the second memory die 10b flows to the third transistor M3 of the first memory die 10a via the other pads PAD of the second memory die 10b and the first memory die 10a as shown by the dashed arrow in the figure.

[0041] Moreover, the control unit 20 of the second memory die 10b controls the first switch of the switch unit 14 of the second memory die 10b to be on. As a result, a reference voltage (here, the value of the reference voltage is shown as VDD / 2) is input to the other terminal of the comparator 13a of the generation unit 13 of the second memory die 10b. Furthermore, the control unit 20 of the first memory die 10a controls the second switch of the switch unit 14 of the first memory die 10a to be on. As a result, a voltage (second voltage) of a node between the drain terminal of the second transistor M2 (second terminal of the second transistor) and the drain terminal of the third transistor M3 (first terminal of the third transistor) of the first memory die 10a is input to the other terminal of the comparator 13a of the generation unit 13 of the first memory die 10a.

[0042] Moreover, the first voltage generated by the pull-up calibration unit 11 of the second memory die 10b is input to one terminal of the comparator 13a of the generation unit 13 of the second memory die 10b. Here, the value of the first voltage is expressed as Rzq / (Rzq+Rp1), for example, where Rzq is the resistance value of the external resistor R and Rp1 is the resistance value of the first transistor M1. Furthermore, the comparator 13a of the generation unit 13 of the second memory die 10b compares the first voltage with a reference voltage to generate a comparison result. Furthermore, upon receiving the comparison result, the arithmetic circuit 13b of the generation unit 13 of the second memory die 10b performs, for example, a binary search based on the comparison result to generate a first control signal code_p for adjusting the first voltage (i.e., the resistance value of the first transistor M1 of the second memory die 10b) so that the value of the voltage on the calibration pad ZQPAD becomes equal to the reference voltage. Then, the generated first control signal code_p is input to the first transistor M1 and the second transistor M2 of the second memory die 10b.

[0043] In this manner, the pull-up calibration is performed in the second memory die 10b.

[0044] On the other hand, the above-mentioned first voltage (here, the value of the first voltage is shown as Rzq / (Rzq+Rp1)) is input to one terminal of the comparator 13a of the generation unit 13 of the first memory die 10a. In addition, the second voltage generated by the pull-down calibration unit 12 of the first memory die 10a is input to the other terminal of the comparator 13a of the generation unit 13 of the first memory die 10a. Here, the value of the second voltage is expressed as Rn0 / (Rn0+Rp1), for example, when the resistance value of the second transistor M2 of the second memory die 10b is Rp1 and the resistance value of the third transistor M3 of the first memory die 10a is Rn0. Furthermore, the comparator 13a of the generation unit 13 of the first memory die 10a compares the first voltage with the second voltage to generate a comparison result.

[0045] Furthermore, when the arithmetic circuit 13b of the generation unit 13 of the first memory die 10a receives the comparison result, the arithmetic circuit 13b performs, for example, a binary search based on the comparison result to generate a second control signal code_n for adjusting the second voltage (i.e., the resistance value of the third transistor M3 of the first memory die 10a) so that the first voltage and the second voltage are equal. Then, the generated second control signal code_n is input to the third transistor M3 of the first memory die 10a. Considering that the resistance value of the second transistor M2 of the second memory die 10b is controlled by the first control signal code_p generated in the second memory die 10b, the first memory die 10a performs pull-down calibration using the first control signal code_p generated in the second memory die 10b.

[0046] In this manner, at the same time that pull-up calibration is performed in the second memory die 10b, pull-down calibration is performed in the first memory die 10a using the first control signal code_p generated in the second memory die 10b.

[0047] As described above, by performing pull-up calibration on the first memory die 10a while performing pull-down calibration on the second memory die 10b, and performing pull-down calibration on the first memory die 10a while performing pull-up calibration on the second memory die 10b, the processing time for impedance calibration in the semiconductor memory device can be reduced to 2t (from 3t, which is the processing time in the conventional example shown in FIG. 1), as shown in FIG. 5.

[0048] As described above, according to the semiconductor memory device and the control method thereof of this embodiment, it is possible to simultaneously perform pull-up calibration in the first memory die 10a and pull-down calibration in the second memory die 10b, and to simultaneously perform pull-down calibration in the first memory die 10a and pull-up calibration in the second memory die 10b. Therefore, for example, compared to the case where the start timing of impedance calibration is shifted between each memory die, the processing time of impedance calibration in the semiconductor memory device can be shortened.

[0049] The above-described embodiments are described for the purpose of facilitating understanding of the present invention, and are not described for the purpose of limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0050] For example, in the above-mentioned embodiment, the case where the number of the second memory die 10b is one has been described as an example, but the present invention is not limited to this case. For example, the number of the second memory die 10b may be two or more. In this case, while the pull-up calibration is performed on the first memory die 10a, the pull-down calibration may be performed on each of the plurality of second memory dies 10b, and while the pull-up calibration is performed on each of the plurality of second memory dies 10b, the pull-down calibration may be performed on the first memory die 10a. In this case, the resistance characteristics of each of the transistors M1, M2, and M3 of the plurality of second memory dies 10b may be configured to be equal among the plurality of second memory dies 10b. In this case, as in the above-mentioned embodiment, the processing time of the impedance calibration in the semiconductor memory device can be shortened.

[0051] In addition, in the case where a set of memory dies sharing an external resistor R is provided for each different external resistor R, the control unit 20 may perform control so as to perform pull-down calibration on each second memory die 10b of the set of memory dies while performing pull-up calibration on each first memory die 10a of the set of memory dies, and to perform pull-down calibration on each first memory die 10a of the set of memory dies while performing pull-up calibration on each second memory die 10b of the set of memory dies.

[0052] For example, as shown in FIG. 6, in the case where the first memory die and the second memory die share a first external resistor and the third memory die and the fourth memory die share a second external resistor, while the control unit 20 of the first memory die and the third memory die performs a pull-up calibration on the corresponding memory die (i.e., the first memory die and the third memory die), the control unit 20 of the second memory die and the fourth memory die performs a pull-down calibration on the corresponding memory die (i.e., the second memory die and the fourth memory die), and while the control unit 20 of the second memory die and the fourth memory die performs a pull-up calibration on the corresponding memory die (the second memory die and the fourth memory die), the control unit 20 of the first memory die and the third memory die performs a pull-down calibration on the corresponding memory die (the first memory die and the third memory die). In this case, as in the above-mentioned embodiment, the processing time of the impedance calibration in the semiconductor storage device can be shortened. Note that the number of memory dies constituting a set of memory dies may be three or more.

[0053] Furthermore, the control unit 20 may perform control so that while performing pull-up calibration on the i-th (i is an integer greater than or equal to 1 and less than or equal to N-2) memory die among the N (N is an integer greater than or equal to 3) memory die, pull-down calibration is performed on the i+1th memory die while performing pull-up calibration on the i+1st memory die, and pull-down calibration is performed on the 1st memory die while performing pull-up calibration on the Nth memory die.

[0054] 7, in the case of N=4, the control unit 20 of the first memory die performs pull-up calibration on the first memory die while the control unit 20 of the second memory die performs pull-down calibration on the second memory die, the control unit 20 of the third memory die performs pull-down calibration on the third memory die while the control unit 20 of the second memory die performs pull-up calibration on the second memory die, the control unit 20 of the fourth memory die performs pull-down calibration on the fourth memory die while the control unit 20 of the third memory die performs pull-up calibration on the third memory die, and the control unit 20 of the first memory die performs pull-down calibration on the first memory die while the control unit 20 of the fourth memory die performs pull-up calibration on the fourth memory die. In this case, as in the above-mentioned embodiment, the processing time of the impedance calibration in the semiconductor memory device can be shortened.

[0055] In the above embodiment, the case where the control unit 20 is provided in each memory die 10 has been described as an example, but the present invention is not limited to this case. For example, a single control unit 20 configured to control which operation of pull-up calibration or pull-down calibration is to be performed in each memory die 10 may be provided.

[0056] The configurations of the above-described embodiments are merely examples, and may be modified as appropriate, or various other configurations may be adopted. [Explanation of symbols]

[0057] 10…Memory die 10a…1st memory die 10b…Second memory die 11...Pull-up calibration section 12...Pulldown calibration section 13...Generation section 20...Control section code_p...first control signal code_n...Second control signal GND: Ground voltage M1: First transistor M2: Second transistor M3: Third transistor PAD: Other pads R…External resistance VDD: Operating voltage ZQPAD...calibration pad

Claims

1. a plurality of memory dies connected to a common external resistor via a calibration pad; a control unit that performs control so that pull-down calibration is performed on one or more second memory dies different from the first memory die among the plurality of memory dies while a pull-up calibration is performed on a first memory die among the plurality of memory dies, and so that pull-down calibration is performed on the first memory die while a pull-up calibration is performed on the second memory die. Semiconductor memory device.

2. Each of the plurality of memory dies comprises: a pull-up calibration unit that generates a first voltage based on a first control signal and a resistance value of the external resistor; a pull-down calibration unit that generates a second voltage based on the first control signal and the second control signal; a generation unit that generates the first control signal based on a first comparison result obtained by comparing the first voltage with a reference voltage when pull-up calibration is performed, and generates the second control signal based on a second comparison result obtained by comparing the first voltage with the second voltage when pull-down calibration is performed.

2. The semiconductor memory device according to claim 1.

3. The control unit is when performing pull-up calibration on the first memory die, the pull-up calibration unit of the first memory die is operated and the pull-down calibration unit of the second memory die is operated, thereby performing pull-down calibration on the second memory die using the first control signal generated in the first memory die; 3. The semiconductor memory device according to claim 2.

4. The control unit is when performing pull-down calibration on the first memory die, the pull-down calibration unit of the first memory die is operated and the pull-up calibration unit of the second memory die is operated, thereby performing pull-down calibration on the first memory die using the first control signal generated in the second memory die; 3. The semiconductor memory device according to claim 2.

5. The pull-up calibration unit includes: a first transistor including a first terminal connected to an operating voltage, a second terminal connected to the calibration pad, and a control terminal to which the first control signal is input, the first transistor adjusting a resistance value based on the first control signal; 3. The semiconductor memory device according to claim 2.

6. The control unit is When performing pull-up calibration on the first memory die, control is performed so that the first transistor of the first memory die is operated and the first transistor of the second memory die is stopped.

6. The semiconductor memory device according to claim 5.

7. the first transistor is a P-type transistor; 6. The semiconductor memory device according to claim 5.

8. The pull-down calibration unit a second transistor including a first terminal connected to an operating voltage and a control terminal to which the first control signal is input, the second transistor adjusting a resistance value based on the first control signal; a third transistor including a first terminal connected to a ground voltage, a second terminal connected to the second terminal of the second transistor, and a control terminal to which the second control signal is input, the third transistor adjusting a resistance value based on the second control signal; The second transistor is a P-type transistor and the third transistor is an N-type transistor.

3. The semiconductor memory device according to claim 2.

9. The control unit is control the third transistor of the first memory die to stop operation and the second transistor of the second memory die to stop operation when performing pull-up calibration on the first memory die; 9. The semiconductor memory device according to claim 8.

10. The control unit is When performing pull-down calibration on the first memory die, control is performed to stop operation of the second transistor of the first memory die and to stop operation of the third transistor of the second memory die.

9. The semiconductor memory device according to claim 8.

11. a second terminal of the second transistor is connected to another pad different from the calibration pad; the other pads of each of the plurality of memory dies are connected to each other; 9. The semiconductor memory device according to claim 8.

12. When a set of memory dies sharing an external resistor is provided for each different external resistor, The control unit is performing a pull-down calibration on each of the second memory die in the set of memory dies while performing a pull-up calibration on each of the first memory die in the set of memory dies, and performing a pull-down calibration on each of the first memory die in the set of memory dies while performing a pull-up calibration on each of the second memory die in the set of memory dies; 2. The semiconductor memory device according to claim 1.

13. The control unit is performing pull-down calibration on the (i+1)th memory die while performing pull-up calibration on the i-th (i is an integer between 1 and N-2) memory die among N (N is an integer between 3 and 5); performing pull-down calibration on the (i+1)th memory die while performing pull-up calibration on the (i+1)th memory die; and performing pull-down calibration on the (i+2)th memory die while performing pull-up calibration on the (N)th memory die; 2. The semiconductor memory device according to claim 1.

14. A method for controlling a semiconductor memory device, comprising: The semiconductor memory device includes: a plurality of memory dies connected to a common external resistor via a calibration pad; a control unit of the semiconductor memory device, performing a control step of performing a pull-down calibration on one or more second memory dies different from the first memory die among the plurality of memory dies while performing a pull-up calibration on a first memory die among the plurality of memory dies, and performing a pull-down calibration on the first memory die while performing a pull-up calibration on the second memory die; A method for controlling a semiconductor memory device.

Images