Clock-synchronized dynamic semiconductor memory device

Abstract

We propose an optimal operating method for memory cells that store data by the amount of electricity stored in the floating body, which satisfies the operating specifications of current SDRAM. In a clock-synchronized dynamic semiconductor memory device using memory cells that store two logical values ​​by the amount of electricity stored in the floating body, the two logical values ​​are written to the memory cells separately, not simultaneously, triggered by different commands or different timing. One of the two logical values ​​is written to the memory cell triggered by a command to release the selected state of the memory cell or by the timing to release the selection state.

Description

[Technical Field]

[0001] The present invention relates to a clock-synchronized dynamic semiconductor memory device (hereinafter referred to as SDRAM) that conforms to the specifications of a double data rate (hereinafter referred to as DDR) clock-synchronized dynamic semiconductor memory device and a low power double data rate (hereinafter referred to as LPDDR) clock-synchronized dynamic semiconductor memory device, and uses memory cells that accumulate electric charges in floating bodies and distinguish the data to be stored depending on the amount of electricity stored. [Background technology]

[0002] Dynamic semiconductor memory devices (hereinafter referred to as DRAM) are widely used as memory devices, and in recent years they have become clock-synchronized to speed up data input / output.

[0003] Current DRAM memory cells consist of one metal-oxide-semiconductor field-effect transistor (MOS transistor) and one capacitor. However, as memory cell density and capacity increase, the area occupied by the memory cell is shrinking. To fulfill its function as a memory cell, the capacitance of the capacitor must be maintained constant despite the shrinking area, or the rate at which the capacitance of the capacitor decreases must be smaller than the rate at which the area occupied by the memory cell decreases. To achieve this, memory cells are being structured in three dimensions, i.e., the MOS transistor is located on the surface of a silicon substrate, and the capacitor is arranged in a cylindrical structure above the silicon substrate. Furthermore, the aspect ratio of these capacitors is increasing. In other words, the length of the cylindrical capacitor is increasing compared to its diameter, while the diameter of the cylindrical capacitor is decreasing. Because the diameter of a capacitor's cylinder is determined by the thickness of the two capacitor electrodes and the thickness of the insulating film between the electrodes, reducing the diameter of the capacitor's cylinder increases the difficulty of manufacturing techniques such as capacitor processing and insulating film formation, and approaches physical limits.

[0004] For this reason, it has been proposed to increase capacity by arranging memory cells consisting of one MOS transistor and one capacitor parallel to the semiconductor substrate and then stacking them (Patent Document 1, Patent Document 2). Although this would require fewer manufacturing steps than stacking memory cells with a structure in which the current cylindrical capacitor extends perpendicular to the semiconductor substrate, it is clear that the manufacturing process would become more complicated.

[0005] For the above reasons, memory cells consisting of a single MOS transistor without a capacitor, which is a major factor in complicating the manufacturing process, have been proposed (see Patent Document 3, Patent Document 4, and Non-Patent Documents 1 to 5). In a memory cell consisting of a single MOS transistor and a single capacitor, logical data "1" or "0" is stored by the charge stored in the capacitor. In contrast, in a memory cell consisting of a single MOS transistor, logical data "1" or "0" is stored by the charge stored in the floating body. For example, as shown in FIG. 90, by passing a current between the source and drain of an N-channel MOS transistor, electrons and holes are generated in the channel by impact ionization, and the holes are retained in the floating body for data storage, thereby writing logical data "1." As shown in FIG. 92(A), logical data "0" is written by removing the holes from the floating body. As shown in the band diagram in Figure 92(B), the PN junction formed by the floating body and the source or drain is forward biased to remove holes from the floating body. In Figures 92(A) and 92(B), both the PN junction formed by the floating body and the source or drain are forward biased, but only one of them can be forward biased. Incidentally, when writing "0", there are cases where an excess of electrons is injected compared to the thermally stable state.

[0006] The potential of the floating body changes depending on the amount of electricity in the floating body, that is, the threshold changes as the bias state of the back gate of the MOS transistor changes, so when an N-channel MOS transistor is used, there is a difference in threshold between the "1" write state in which holes are accumulated in the floating body and the "0" write state in which holes are removed from the floating body, as shown in Figure 89. Therefore, when the gate potential is constant, the current flowing from the drain to the source differs between the "1" write state and the "0" write state, and the difference in the amount of current allows the data written to the memory cell to be distinguished.

[0007] A write method different from the impact ionization phenomenon has been proposed. Non-Patent Document 5 proposes a method for writing logical memory data "1" using not the impact ionization phenomenon but the BTBT (Band-to-Band Tunneling) phenomenon (sometimes called the GIDL (Gate Induced Drain Leakage) phenomenon) to accumulate holes in the floating body for data storage. That is, when an N-channel MOS transistor is used as shown in FIG. 91(A), a bias condition is set so that the majority carriers in the floating body are accumulated on the gate side, and a voltage is applied to the drain so that the PN junction formed by the drain and floating body is reverse biased. As shown in FIGS. 91(B) and 91(C), a high electric field between the drain and floating body causes electrons in the valence band of the floating body to flow away to the conduction band of the drain, resulting in the accumulation of holes in the floating body. In Non-Patent Document 5, too, when writing logical memory data "0", a PN junction formed by the floating body and the drain is forward biased to discharge a group of holes from within the floating body.

[0008] Under the bias conditions shown in TABLE III of Non-Patent Document 5, not only the drain voltage applied to the bit line but also the gate voltage applied to the word line differs between "0" write and "1" write. In other words, when writing "0", the PN junction formed by the floating body and drain is in a forward bias state, whereas when writing "1", the PN junction is in a reverse bias state, and the floating body potential is controlled by using the capacitive coupling between the floating body and gate, and the gate potential must be changed due to the withstand voltage of the transistors in the peripheral circuits that drive the memory cell. When using an N-channel MOS transistor, a higher gate potential is used for writing "0" than for writing "1", and a lower gate potential is used for writing "1".

[0009] In general, to achieve high integration and density in semiconductor memory devices, multiple memory cells are arranged on a plane (memory cell array) as shown in Figures 2 and 30. Driver circuits are provided at the edges of the plane, and memory cells at the intersections of word line drivers, which are selected and driven by row addresses, and bit lines, which are selected and driven by column addresses, are selected for reading or writing. Current large-capacity semiconductor memory devices simultaneously read and write data from and to multiple memory cells. Because the difference in read and write times between a CPU (central processing unit) and a semiconductor memory device has dramatically increased, the number of memory cells simultaneously read and written is on the rise. Since data is typically reflected on bit lines, multiple bit lines are selected in the same number as the number of cells to be operated during operation, while only one word line is selected. Furthermore, data in cells simultaneously written to do not generally match. Therefore, the voltages of both the bit lines and word lines differ depending on the write data, meaning that "0" and "1" writes cannot be performed simultaneously; they must be performed at different times. In a typical semiconductor memory device, writing to multiple memory cells results in a mixture of data "0" and data "1." Therefore, when writing to multiple memory cells on the same word line, it is necessary to set the word line potential for writing "0," write "0," and then set the word line potential for writing "1."

[0010] While the above problem could be avoided by allowing only one memory cell to be selected per memory cell array, this would require operating as many memory cell arrays as there are memory cells to be simultaneously written, which would increase power consumption.Furthermore, it would require disposing as many memory cell arrays and bit line driver circuits and word line driver circuits at the ends of the memory cell arrays as there are memory cells to be simultaneously written, which would increase the chip area and increase costs.

[0011] In the memory cells shown in Non-Patent Document 1 and Patent Document 3, the word line voltage is the same when writing a "1" and a "0," but it is the purge operation that actually removes holes from the floating body. The subsequent "0" write simply prevents holes from accumulating in the floating body. Therefore, a purge operation is required before the write operation, which is not specified in the current specifications for SDRAMs that use memory cells consisting of one MOS transistor and one capacitor.

[0012] In Non-Patent Document 4, the same word line potential is set for both "1" and "0" writes. When writing "0," the PN junction is forward biased by the potentials of the floating body and bit line, discharging holes from the floating body to the bit line. Raising the word line potential raises the potential of the floating body, where holes are accumulated through capacitive coupling. However, once a channel is formed, the floating body potential does not rise in response to the word line potential. Therefore, raising the word line potential to match the "1" write condition simply increases the current from the source line to the bit line, resulting in increased power consumption and placing an excessive burden on the bit line negative voltage generation circuit. In other words, it is more effective from a chip size perspective to lower the word line potential when writing "0" than when writing "1," thereby suppressing the drive current and minimizing the increase in the area of ​​the bit line negative voltage generation circuit.

[0013] In other words, in a memory cell that stores electric charge in the floating body and distinguishes the data to be stored based on the amount of electricity, if there are multiple memory cells connected to the same word line in the memory cell array that are to be written with "1" and "0," it is not possible to write "1" and "0" simultaneously at the optimal potential settings for each.

[0014] In order to write "1" and "0" at the optimal potential settings, it is possible to write "0" and "1" separately in a single write cycle using a write command issued to the SDRAM from an external device by resetting the voltages on the word line and bit line. However, the specifications for current SDRAM, which uses a memory cell consisting of one MOS transistor and one capacitor, are determined to match the operation when using a memory cell consisting of one MOS transistor and one capacitor, so they are not designed to write "0" and write "1" at different times. This is because, in the case of a memory cell consisting of one MOS transistor and one capacitor, the MOS transistor connected to the word line only acts as a switch, so there is no need to change the voltage in the first place. Therefore, the write time is only enough to apply a voltage pulse to the word line once, so there is no time to pulse the word line twice, separately to write "0" and "1".

[0015] As described above, there is a problem in that no method has been presented for satisfying the current SDRAM specifications with a memory cell that does not have a capacitor, accumulates charge in a floating body, and distinguishes the data to be stored based on the amount of charge, using an optimal operating method for the memory cell. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] US2020 / 0227416 A1 [License 2] US2020 / 0043941 A1 [License 3] US5448513 [License 4] US7280399 B2 [Patent Document 5] US7855920 B2 [License 6] US6548848 B2 [License 7] Patent No. 4354663 [License 8] Patent No. 7057032 [License 9] US6493267 B2 [License 10] Patent No. 3643385 [License 11] US5734286 [Non-licensed literature]

[0017] [Non-licensed Document 1] Hsing-jen Wann and Chenming Hu: "A Capacitorless DRAM Cell on SOI Substrate," IEEE International Electron Device Meeting Technical Digest, pp.635-638 (1993) [Non-licensed Document 2] PC Fazan, S. Okhonin, M. Nagoga and JM Sallese: “A Simple1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs,” Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, pp.99-102 (2002)

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

[0018] The problem was that no optimal operating method had been proposed for memory cells that store electric charge in the floating body and distinguish the data to be stored based on the amount of electricity stored, which is compatible with current SDRAM operating specifications. [Means for solving the problem]

[0019] In order to solve the above problems, a first invention of the present application is a clock synchronous semiconductor memory device having a memory cell array on a semiconductor substrate, in which memory cells are arranged in rows and columns in two directions perpendicular to each other in a plan view, a data register for temporarily storing data between the memory cell array and an input / output terminal of the clock synchronous semiconductor memory device; Furthermore, the clock synchronous semiconductor memory device has an instruction set which is a collection of instructions (commands) for operating the clock synchronous semiconductor memory device, The instruction set is an active command to select the memory cell; a precharge command for deselecting the memory cell; a write command for inputting data from the input / output terminal; a plurality of auto-precharge commands for releasing the selected state of the memory cell regardless of the precharge command; In response to the write command, data input from the input / output terminal of the clock synchronous semiconductor memory device is written into the data register; After receiving the precharge command or any one of the plurality of commands with auto-precharge, the data stored in the data register is written to the memory cell selected by the active command while the selected state of the memory cell is released. It is characterized by:

[0020] A second aspect of the present invention is the above-mentioned first aspect, wherein the instruction set is: a read command for outputting data from the input / output terminal, a write command with auto precharge for inputting data from the input / output terminal and releasing the selected state of the memory cell after the data input is completed, and a read command with auto precharge for outputting data from the input / output terminal and releasing the selected state of the memory cell after the data output is started, wherein the data input from the input / output terminal is written to the data register by the write command, After receiving the precharge command, or after a first time has elapsed since receiving the read command with auto-precharge, or after a second time different from the first time has elapsed since receiving the write command with auto-precharge, an operation of writing the data stored in the data register to the memory cell selected by the active command is started. It is characterized by:

[0021] The third invention of the present application is characterized in that, in the above-mentioned first invention, the data register is arranged adjacent to the memory cell array, and the number of the data registers is the same as the number of memory cells selected by the active command.

[0022] The fourth invention of the present application is characterized in that, in the above-mentioned first invention, the data register is arranged adjacent to the memory cell array, and the number of the data registers is the same as the number of memory cells selected by the active command in the memory cell array arranged adjacent to the data register.

[0023] A fifth invention of the present application is characterized in that, in the first invention, the memory cell has a structure having a MOS field effect transistor in which at least a part of a floating body serving as a storage node becomes a current path.

[0024] The sixth invention of the present application is characterized in that, in the first invention described above, the data that can be stored in the memory cells is binary in terms of logical level, and after the data stored in the selected memory cells is written to the data register by the active command, a write operation of data of one of the binary logic levels is performed on all of the selected memory cells.

[0025] The seventh invention of the present application is characterized in that, in the above-mentioned first invention, the data that can be stored in the memory cells has two logical levels, and the data stored in the data register is written to the memory cells selected by the active command by a signal different from the control signal that writes data of one of the two logical levels to all of the selected memory cells.

[0026] The eighth invention of the present application is characterized in that, in the sixth invention described above, the operation of inputting data via the input / output terminal or the operation of outputting data via the input / output terminal and the operation of writing data of one of the two logic values ​​to all the selected memory cells are performed independently and in parallel.

[0027] The ninth invention of the present application is characterized in that, in the sixth invention described above, by receiving the write command or the write command with auto-precharge, a write operation of data of one of the binary logics is performed on all of the selected memory cells.

[0028] The tenth invention of the present application is characterized in that, in the above-mentioned ninth invention, only when either the write command or the write command with auto-precharge is received first after receiving the active command, the write command or the write command with auto-precharge performs a write operation of data of one of the two logic values ​​to all of the selected memory cells.

[0029] The 11th invention of the present application is characterized in that, in the above-mentioned 9th invention, even if the read command or the read command with auto-precharge is received, a write operation of data of one of the binary logics is performed on all of the selected memory cells.

[0030] The 12th invention of the present application is characterized in that, in the above-mentioned 11th invention, the write operation of data of one of the two logic values ​​is performed on all the selected memory cells only when any one of the write command, the write command with auto precharge, the read command, or the read command with auto precharge is received first after receiving the active command.

[0031] The 13th invention of the present application is characterized in that, in the above-mentioned first invention, one end of the memory cell is connected to a bit line and the other end is connected to a source line, the data stored in the memory cell is determined by the amount of current flowing between the bit line and the source line, and the extension direction of the bit line and the extension direction of the source line are arranged parallel to each other.

[0032] The 14th invention of the present application is characterized in that, in the above-mentioned 13th invention, the bit line connected to one end of one of the memory cells and the source line connected to the other end thereof are in different wiring layers, and all of the bit lines in the memory cell array are the same wiring, and all of the source lines are in the same wiring layer.

[0033] The 15th invention of the present application is characterized in that, in the above-mentioned 13th invention, the bit line connected to one end of one of the memory cells and the source line connected to the other end thereof are in different wiring layers, and the bit lines formed in different wiring layers exist within the memory cell array.

[0034] The 16th invention of the present application is characterized in that, in the above-mentioned 13th invention, the bit line connected to one end of one of the memory cells and the source line connected to the other end thereof are in different wiring layers, and the source lines formed in different wiring layers exist within the memory cell array. [Brief explanation of the drawings]

[0035] [Figure 1] This is a block diagram of SDRAM that complies with the DDR4 standard. [Figure 2] 2 is a diagram illustrating an example of a cell array block of the SDRAM shown in FIG. 1. [Figure 3] 1 is a state transition diagram of an SDRAM, showing an excerpt of a portion related to the present invention. [Figure 4] 4 is a state transition diagram of a memory cell and a data register in an SDRAM according to the first embodiment, corresponding to the state transition diagram of FIG. 3. FIG. [Figure 5] 3A and 3B are diagrams illustrating selected main operation waveforms of the SDRAM according to the first embodiment. [Figure 6] 3A and 3B are diagrams illustrating selected main operation waveforms of the SDRAM according to the first embodiment. [Figure 7] 10 is a diagram showing selected main operation waveforms of the SDRAM according to the first, second and third embodiments. FIG. [Figure 8] 10 is a diagram showing selected main operation waveforms of the SDRAM according to the first, second and third embodiments. FIG. [Figure 9] 10 is a diagram showing selected main operation waveforms of the SDRAM according to the first, second and third embodiments. FIG. [Figure 10] 10 is a diagram showing selected main operation waveforms of the SDRAM according to the first, second and third embodiments. FIG. [Figure 11] 10 is a diagram showing selected main operation waveforms of the SDRAM according to the first, second and third embodiments. FIG. [Figure 12] 10 is a diagram showing selected main operation waveforms of the SDRAM according to the first, second and third embodiments. FIG. [Figure 13] 3A and 3B are diagrams illustrating selected main operation waveforms of the SDRAM according to the first embodiment. [Figure 14] 3A and 3B are diagrams illustrating selected main operation waveforms of the SDRAM according to the first embodiment. [Figure 15] 3A and 3B are diagrams illustrating selected main operation waveforms of the SDRAM according to the first embodiment. [Figure 16] 3A and 3B are diagrams illustrating selected main operation waveforms of the SDRAM according to the first embodiment. [Figure 17]10A and 10B are diagrams illustrating selected main operation waveforms of the SDRAM according to the first and second embodiments. [Figure 18] 4 is a state transition diagram of a memory cell and a data register in an SDRAM according to a second embodiment, corresponding to the state transition diagram of FIG. 3. FIG. [Figure 19] FIG. 4 is a state transition diagram of a memory cell and a data register in an SDRAM according to a third embodiment, corresponding to the state transition diagram of FIG. [Figure 20] 10A and 10B are diagrams illustrating selected main operation waveforms of the SDRAM according to the second and third embodiments. [Figure 21] 10A and 10B are diagrams illustrating selected main operation waveforms of the SDRAM according to the second and third embodiments. [Figure 22] 10A and 10B are diagrams illustrating selected main operation waveforms of the SDRAM according to the second and third embodiments. [Figure 23] 10A and 10B are diagrams illustrating selected main operation waveforms of the SDRAM according to the second and third embodiments. [Figure 24] 10A and 10B are diagrams illustrating selected main operation waveforms of the SDRAM according to the second and third embodiments. [Figure 25] 10A and 10B are diagrams illustrating selected main operation waveforms of the SDRAM according to the second and third embodiments. [Figure 26] 10A and 10B are diagrams illustrating selected main operation waveforms of an SDRAM according to a third embodiment. [Figure 27] 10 is a table showing, by symbols, an example of voltages applied to each wiring of a cell array of an SDRAM according to the present invention. [Figure 28(A)] 10 is a table showing an example of voltages applied to each wiring of a cell array of an SDRAM according to the present invention. [Figure 28(B)] 10 is a table showing another example of voltages applied to each wiring of a cell array of an SDRAM according to the present invention. [Figure 29(A)] FIG. 1 is a circuit diagram of a memory cell configured with one transistor and having no capacitor, which can be used in the SDRAM according to the present invention. [Figure 29(B)] FIG. 29(A) is shown as a block diagram. [Figure 29(C)]FIG. 29(B) is a diagram showing the physical structure of FIG. 29(A). [Figure 30] FIG. 2 is a block diagram of a sub-cell array of an SDRAM according to the present invention. [Figure 31] 2 is a diagram showing an example of a circuit relating to control of a sub-cell array of an SDRAM according to the first and second embodiments. [Figure 32] 2 is a diagram showing an example of a circuit related to generation of an address signal for selecting a memory cell in a sub-cell array of an SDRAM according to the present invention. [Figure 33] 1 is a diagram showing an example of a circuit for generating an address signal related to selection of a sub-cell array of an SDRAM according to the present invention. [Figure 34] This is an example of a circuit for driving MOS transistors for connecting the circuit block consisting of a BL (bit line) sense amplifier, a BL (bit line) driver, and a data register shown in Figure 42 to the bit line (BL), and MOS transistors for connecting the SL (source line) driver shown in Figure 43 to the source line (SL). [Figure 35] 2 is a diagram showing an example of a control circuit related to a read operation of a memory cell of an SDRAM according to the present invention. [Figure 36] 4 is an example of a control circuit related to an erase operation of a memory cell of the SDRAM according to the first embodiment. [Figure 37] 3 is a diagram showing an example of a control circuit related to a write operation of a memory cell of an SDRAM according to the first and second embodiments. [Figure 38] 3 is a diagram showing an example of a global WL (word line) driver and a row decoder circuit shown in FIG. 2. FIG. [Figure 39] FIG. 76 is a diagram showing an example of a local WL (word line) driver circuit shown in FIG. 2, FIG. 30, or FIG. [Figure 40(A)] FIG. 40 is a diagram showing an example of a driver circuit including a sub-row decoder and a potential switching circuit for driving the local WL (word line) driver circuit shown in FIG. 39. [Figure 40(B)]FIG. 40 is a diagram showing an example of a driver circuit including a sub-row decoder and a potential switching circuit for driving the local WL (word line) driver circuit shown in FIG. 39. [Figure 41] FIG. 40 shows an example of a driver circuit that includes a potential switching circuit that drives the local WL (word line) driver circuit shown in FIG. 39, separate from the circuits shown in FIGS. 40(A) and 40(B). [Figure 42] FIG. 76 is a diagram showing an example of circuits of a BL (bit line) sense amplifier, a BL (bit line) driver, and a data register shown in FIG. 2, FIG. 30, or FIG. [Figure 43] FIG. 76 is a diagram showing an example of an SL (source line) driver circuit shown in FIG. 2, FIG. 30, or FIG. [Figure 44(A)] 1 is a diagram showing an example of a delay circuit utilizing the RC delay of an SDRAM according to the present invention. [Figure 44(B)] FIG. 45 is an operational waveform diagram of the delay circuit utilizing the RC delay of the SDRAM according to the present invention shown in FIG. 44(A). [Figure 45] 44(A) shows an example of a circuit for generating a gate voltage for controlling the delay time in the delay circuit utilizing the RC delay of the SDRAM according to the present invention shown in FIG. 44(A). [Figure 46(A)] 1 is a diagram showing an example of a delay circuit using a counter of an SDRAM according to the present invention. [Figure 46(B)] FIG. 46(B) is an operational waveform diagram of a delay circuit using a counter of the SDRAM according to the present invention shown in FIG. 46(A). [Figure 47] 1 is an example of a circuit that generates a potential for driving memory cells of an SDRAM according to the present invention from a VPP power supply supplied from an external device. [Figure 48] 1 is an example of a circuit that generates a potential for driving memory cells of an SDRAM according to the present invention from a VDD power supply supplied from an external device. [Figure 49] 1 is an example of a circuit that generates a potential for driving memory cells of the SDRAM according to the present invention from a VBB power supply generated within the SDRAM. [Figure 50] This is an example of a circuit that generates a potential (VCBL in FIG. 42) for limiting the potential of the bit line during a read operation of the SDRAM according to the present invention from the VDD power supply supplied from an external device. [Figure 51] 44(A), 45, 47, 48, 49, and 50. FIG. 44(A), 45, 47, 48, 49, and 50 show an example of a reference potential generating circuit using a bandgap reference circuit. [Figure 52] This is an example of a reference potential generating circuit that uses a bandgap reference circuit and is used in the circuits of Figures 44(A), 45, 47, 48, 49, and 50, and is capable of generating a reference voltage that has stronger temperature dependency than Figure 51. [Figure 53(A)] 1 is a diagram showing an example of a VBB power supply generation circuit generated within an SDRAM according to the present invention. [Figure 53(B)] FIG. 54 is a waveform diagram of an operating signal for driving the circuit of FIG. 53(A). [Figure 54(A)] This is a block diagram used in FIG. 53(A). [Figure 54(B)] FIG. 54(B) is a specific circuit diagram of the block diagram shown in FIG. 54(A). [Figure 55-1] FIG. 10 is an operational waveform diagram when an active command and a precharge command are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 55-2] FIG. 10 is an operational waveform diagram when an active command and a precharge command are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 55-3] FIG. 10 is an operational waveform diagram when an active command and a precharge command are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 55-4] FIG. 10 is an operational waveform diagram when an active command and a precharge command are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 56-1] 10 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the first embodiment. FIG. [Figure 56-2] 10 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the first embodiment. FIG. [Figure 56-3] 10 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the first embodiment. FIG. [Figure 56-4] 10 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the first embodiment. FIG. [Figure 57-1] 10 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the first embodiment. FIG. [Figure 57-2] 10 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the first embodiment. FIG. [Figure 57-3] 10 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the first embodiment. FIG. [Figure 57-4] 10 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the first embodiment. FIG. [Figure 58-1] FIG. 10 is an operational waveform diagram when an active command, a write command, and a precharge command are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 58-2] FIG. 10 is an operational waveform diagram when an active command, a write command, and a precharge command are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 58-3] FIG. 10 is an operational waveform diagram when an active command, a write command, and a precharge command are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 58-4]FIG. 10 is an operational waveform diagram when an active command, a write command, and a precharge command are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 59-1] FIG. 10 is an operational waveform diagram when an active command and a write command with auto-precharge are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 59-2] FIG. 10 is an operational waveform diagram when an active command and a write command with auto-precharge are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 59-3] FIG. 10 is an operational waveform diagram when an active command and a write command with auto-precharge are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 59-4] FIG. 10 is an operational waveform diagram when an active command and a write command with auto-precharge are input in sequence to the SDRAMs according to the first and second embodiments. [Figure 60] 10 is an example of a circuit relating to control of a sub-cell array of an SDRAM according to a second embodiment. [Figure 61] 10 is an example of a control circuit related to an erase operation of a memory cell of an SDRAM according to a second embodiment. [Figure 62] 10 is an example of a control circuit related to a write operation of a memory cell of an SDRAM according to a second embodiment. [Figure 63-1] FIG. 11 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the second embodiment. [Figure 63-2] FIG. 11 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the second embodiment. [Figure 63-3] FIG. 11 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the second embodiment. [Figure 63-4]FIG. 11 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the second embodiment. [Figure 64-1] FIG. 11 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the second embodiment. [Figure 64-2] FIG. 11 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the second embodiment. [Figure 64-3] FIG. 11 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the second embodiment. [Figure 64-4] FIG. 11 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the second embodiment. [Figure 65] 10 is an example of a circuit relating to control of a sub-cell array of an SDRAM according to a third embodiment. [Figure 66] 10 is an example of a control circuit related to an erase operation of a memory cell of an SDRAM according to a third embodiment. [Figure 67] 10 is an example of a control circuit related to a write operation of a memory cell of an SDRAM according to a third embodiment. [Figure 68-1] FIG. 11 is an operational waveform diagram when an active command and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 68-2] FIG. 11 is an operational waveform diagram when an active command and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 68-3] FIG. 11 is an operational waveform diagram when an active command and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 68-4] FIG. 11 is an operational waveform diagram when an active command and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 69-1]FIG. 11 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 69-2] FIG. 11 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 69-3] FIG. 11 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 69-4] FIG. 11 is an operational waveform diagram when an active command, a read command, and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 70-1] FIG. 11 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the third embodiment. [Figure 70-2] FIG. 11 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the third embodiment. [Figure 70-3] FIG. 11 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the third embodiment. [Figure 70-4] FIG. 11 is an operational waveform diagram when an active command and a read command with auto-precharge are input in sequence to the SDRAM according to the third embodiment. [Figure 71-1] FIG. 11 is an operational waveform diagram when an active command, a write command, and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 71-2] FIG. 11 is an operational waveform diagram when an active command, a write command, and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 71-3] FIG. 11 is an operational waveform diagram when an active command, a write command, and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 71-4] FIG. 11 is an operational waveform diagram when an active command, a write command, and a precharge command are input in sequence to the SDRAM according to the third embodiment. [Figure 72-1] FIG. 11 is an operational waveform diagram when an active command and a write command with auto-precharge are input in sequence to the SDRAM according to the third embodiment. [Figure 72-2] FIG. 11 is an operational waveform diagram when an active command and a write command with auto-precharge are input in sequence to the SDRAM according to the third embodiment. [Figure 72-3] FIG. 11 is an operational waveform diagram when an active command and a write command with auto-precharge are input in sequence to the SDRAM according to the third embodiment. [Figure 72-4] FIG. 11 is an operational waveform diagram when an active command and a write command with auto-precharge are input in sequence to the SDRAM according to the third embodiment. [Figure 73(A)] 30 of the SDRAM according to the fourth embodiment, a plan view of 8×4 memory cells each having the structure and wiring layers shown in FIGS. 29(A) and 29(C). [Figure 73(B)] This is a diagram in which the wiring layers relating to the bit lines (BL) and source lines (SL) are removed from FIG. 73(A). [Fig. 73(C)] FIG. 73(B) is an equivalent circuit diagram of FIG. 73(A). [Figure 74(A)] FIG. 73(B) is a diagram showing the second metal wiring layer extracted from the plan view shown in FIG. 73(A). [Figure 74(B)] 73(A) is a diagram in which the contact holes between the second metal wiring layer and the semiconductor are extracted from the plan view shown in FIG. 73(A). [Fig. 74(C)] 73(A) is a diagram showing the first metal wiring layer extracted from the plan view shown in FIG. 73(A). [Fig. 74(D)] FIG. 73(B) is a diagram in which the contact holes between the first metal wiring layer and the semiconductor are extracted from the plan view shown in FIG. 73(A). [Figure 74(E)] This is a diagram in which the gate conductive layer is extracted from the plan view shown in FIG. 73(A). [Fig. 74(F)] This is a diagram showing a semiconductor region used as a memory cell from the plan view shown in FIG. 73(A). [Figure 75(A)] This is a cross-sectional view taken along the line AA' of the plan view shown in FIG. 73(A). [Figure 75(B)] 73(A) is a cross-sectional view taken along the line BB' of the plan view shown in FIG. 73(A). [Fig. 75(C)] 73(A) is a cross-sectional view taken along the line CC' of the plan view shown in FIG. 73(A). [Fig. 75(D)] FIG. 73(B) is a cross-sectional view taken along the line DD' of the plan view shown in FIG. 73(A). [Figure 75(E)] FIG. 73(B) is a cross-sectional view taken along the line EE' of the plan view shown in FIG. 73(A). [Fig. 75(F)] FIG. 73(B) is a cross-sectional view taken along the line FF' of the plan view shown in FIG. 73(A). [Figure 75(G)] This is a cross-sectional view taken along the line GG' of the plan view shown in FIG. 73(A). [Figure 76] FIG. 10 is a block diagram of a sub-cell array of an SDRAM according to a fifth embodiment. [Figure 77(A)] 76 of the SDRAM according to the fifth embodiment, a plan view of 8×4 memory cells each having the structure and wiring layers shown in FIGS. 29(A) and 29(C). [Figure 77(B)] This is a diagram in which the wiring layers relating to the bit lines (BL) and source lines (SL) are removed from FIG. 77(A). [Fig. 77(C)] FIG. 77(B) is an equivalent circuit diagram of FIG. [Figure 78(A)] FIG. 77(B) is a diagram showing the second metal wiring layer extracted from the plan view shown in FIG. 77(A). [Figure 78(B)] FIG. 77(B) is a diagram showing contact holes between the second metal wiring layer and the semiconductor extracted from the plan view shown in FIG. 77(A). [Fig. 78(C)] FIG. 77(B) is a diagram showing the first metal wiring layer extracted from the plan view shown in FIG. 77(A). [Figure 78(D)] FIG. 77(B) is a diagram showing contact holes between the first metal wiring layer and the semiconductor extracted from the plan view shown in FIG. 77(A). [Figure 78(E)]This is a diagram in which the gate conductive layer is extracted from the plan view shown in FIG. 77(A). [Figure 78(F)] This is a diagram showing a semiconductor region used as a memory cell from the plan view shown in FIG. 77(A). [Figure 79(A)] This is a cross-sectional view taken along the line AA' of the plan view shown in FIG. 77(A). [Fig. 79(B)] FIG. 77(B) is a cross-sectional view taken along the line BB' of the plan view shown in FIG. 77(A). [Fig. 79(C)] This is a cross-sectional view taken along the line CC' of the plan view shown in Figure 77(A). [Fig. 79(D)] This is a cross-sectional view taken along the line DD' of the plan view shown in FIG. 77(A). [Figure 79(E)] FIG. 77(B) is a cross-sectional view taken along the line EE' of the plan view shown in FIG. 77(A). [Figure 80(A)] FIG. 1 is a circuit diagram of a memory cell that does not have a capacitor as a storage element and is configured with one data storage transistor and one selection transistor, which can be used in an SDRAM according to the present invention. [Figure 80(B)] FIG. 80(A) is shown as a block diagram. [Figure 80(C)] FIG. 80(B) is a diagram showing an example of the physical structure of FIG. 80(A). [Figure 81] This is a block diagram of a sub-cell array of an SDRAM according to the present invention, which uses memory cells consisting of one data storage transistor and one selection transistor, without a capacitor as a memory element, as shown in Figures 80(A), 80(B), and 80(C). [Figure 82] This is a table showing an example of voltages applied to each wiring of the cell array of an SDRAM according to the present invention when a memory cell consisting of one data storage transistor and a selection transistor is used, without having a capacitor as a memory element as shown in Figures 80(A), 80(B), and 80(C). [Figure 83(A)] FIG. 1 is a circuit diagram of a memory cell configured with two transistors and not having a capacitor as a storage element, which can be used in the SDRAM according to the present invention. [Fig. 83(B)]FIG. 83(A) is shown as a block diagram. [Fig. 83(C)] FIG. 83(B) is a diagram showing an example of the physical structure of FIG. 83(A). [Figure 84] FIG. 83(A), FIG. 83(B), and FIG. 83(C) are block diagrams of a sub-cell array of an SDRAM according to the present invention, in which memory cells each consisting of two transistors and not having a capacitor as a memory element are used. [Figure 85] This is a table showing an example of voltages applied to each wiring of the cell array of the SDRAM of the present invention when using a memory cell consisting of two transistors and not having a capacitor as a memory element, as shown in Figures 83(A), 83(B), and 83(C). [Figure 86(A)] FIG. 1 is a circuit diagram of a memory cell that does not have a capacitor as a storage element and has a structure in which the floating body of a storage node is sandwiched between two gates, and that can be used in an SDRAM according to the present invention. [Figure 86(B)] FIG. 86(A) is shown as a block diagram. [Fig. 86(C)] This is a diagram showing the physical structure of Figure 86(A). [Figure 87] This is a block diagram of a sub-cell array of an SDRAM according to the present invention, which uses memory cells having a structure in which the floating body of a storage node is sandwiched between two gates, without having a capacitor as a storage element, as shown in Figures 86(A), 86(B), and 86(C). [Figure 88] This is a table showing an example of voltages applied to each wiring of the cell array of an SDRAM according to the present invention when using a memory cell having a structure in which the floating body of the memory node is sandwiched between two gates, without having a capacitor as a memory element, as shown in Figures 86(A), 86(B), and 86(C). [Figure 89] This is the current drive characteristic of a memory cell consisting of a single transistor without a capacitor, which stores electric charges in the floating body and distinguishes the data stored based on the amount of electricity, when it is holding data "0" and when it is holding data "1". [Figure 90] This is a diagram showing an overview of a method in which charges are stored in the floating body and the data to be stored is distinguished based on the amount of electricity stored, using impact ionization to store holes in the floating body in a memory cell consisting of a single transistor without a capacitor. [Figure 91(A)] This is a diagram showing an overview of a method for storing holes in a floating body by utilizing the BTBT (Band to Band Tunneling) phenomenon (sometimes called the GIDL (Gate Induced Drain Leakage) phenomenon) in a memory cell consisting of a single transistor without a capacitor, which stores charges in the floating body and distinguishes the data to be stored based on the amount of electricity stored. [Figure 91(B)] This is a schematic diagram of the energy band of the A-A' plane in Figure 89(A) when the BTBT (Band to Band Tunneling) phenomenon is occurring, and a schematic diagram of the state of electrons and holes. [Fig. 91(C)] This is a schematic diagram of the energy band of the A-A' plane in Figure 89(A) when the BTBT (Band to Band Tunneling) phenomenon is occurring, and a schematic diagram of the state of electrons and holes. [Figure 92(A)] This is a diagram showing an overview of a method for accumulating charges in the floating body and differentiating the stored data based on the amount of electricity in a memory cell composed of a single transistor without a capacitor, in which holes are released from the floating body. [Figure 92(B)] This is an energy band diagram (schematic diagram) and the state of holes when holes are being emitted from the floating body (schematic diagram). [Figure 93] 4 is a state transition diagram of a memory cell and a data register in a current SDRAM using a memory cell consisting of one MOS transistor and one capacitor, which corresponds to the state transition diagram of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0036] In order to solve the above problems, the SDRAM of the present invention accumulates electric charges in the floating body, and writes "0" and "1" to memory cells that distinguish the data to be stored by the amount of electricity, rather than simultaneously using a write command in accordance with the operating specifications of the DDR-SDRAM.Instead, data from the selected memory cell(s) is first read out to a data register(s) by accepting an active command in accordance with the operating specifications of the DDR-SDRAM, and then data of one logical value is written to the memory cell(s) of the selected bank, and data of the other logical value is written to the memory cell(s) before the selected memory cell(s) is deselected by a command in accordance with the operating specifications of the DDR-SDRAM, and therefore writing to the memory cell(s) is not performed for each write command.

[0037] This invention relates to writing to memory cells and not to input / output of semiconductor memory devices, so it is not applicable to DDR-SDRAM of each generation, DDR, DDR2, DDR3, DDR4, DDR5, or future generation DDR-SDRAM. LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR4X, LPDDR5, LPDDR5X generations of LPDDR or future generations of LPDDR-SDRAM and It is compatible with GDDR (Graphics Double Data Rate) SDRAM of the GDDR, GDDR3, GDDR4, GDDR5, GDDR5X, GDDR6, and GDDR6X generations, as well as future generations of GDDR-SDRAM, but is not compatible with Single Data Rate (SDR) SDRAM, which has different specifications for writing to memory cells. Furthermore, the gate insulating film of a MOS transistor is not limited to a silicon oxide film, but may be an insulating film other than a silicon oxide film, or a laminated film of a silicon insulating film and an insulating film other than a silicon insulating film. Therefore, the gate insulating film of the MOS transistor constituting the memory cell and circuit of the SDRAM according to the present invention is not limited to a silicon oxide film, but may be an insulating film other than a silicon oxide film, or a laminated film of a silicon insulating film and an insulating film other than a silicon insulating film.

[0038] (First embodiment) An SDRAM (which is an example of the "clock synchronous semiconductor memory device" in the claims) according to an embodiment of the present invention will be described below with reference to the drawings. Figure 1 shows a block diagram of an SDRAM that complies with the DDR4 specification. Therefore, if ACT_n exists, but there is no ACT_n, as in DDR3 or DDR5, it is generated internally in the SDRAM by combining command signals input from the address signal lines. That is, the address receiver shown as 112 in FIG. 1 and the address decoder shown as 117 in FIG. 1 determine the logical value of the address signal input from an external device to the SDRAM, and the command receiver and command decoder shown as 111 in FIG. 1 interpret this as a command and output it. Incidentally, signals whose names end with _n are negative logic signals, which logically represent a "1" when they are at a relatively low potential, including negative potential, and signals whose names end with _t are positive logic signals, which logically represent a "1" when they are at a relatively high potential.

[0039] 2 is a diagram showing an example of four cell array blocks, designated 101 in FIG. 1, in an SDRAM designated 100 in FIG. 1. In an SDRAM using memory cells (an example of a "memory cell" in the claims) according to this embodiment, which store electric charges in floating bodies and distinguish stored data based on the amount of electric charge, the cell array blocks can be operated independently, similar to SDRAMs using memory cells each consisting of one transistor and one capacitor. Also, similar to SDRAMs using memory cells each consisting of one transistor and one capacitor, the memory cells are divided into multiple banks across the cell array blocks.

[0040] As shown in FIG. 2, in the SDRAM according to this embodiment, which uses memory cells that store electric charges in the floating body and distinguish the data to be stored depending on the amount of electricity stored, the cell array block is divided into multiple sub-cell arrays (shown as 103 in FIG. 2) in the same way as in the current SDRAM that uses memory cells consisting of one transistor and one capacitor. Like current SDRAMs that use memory cells consisting of one transistor and one capacitor, the SDRAM of this embodiment synchronizes with an active command (an example of an "active command" in the claims, hereinafter referred to as an ACT command) and interprets an address signal input from an external device using a row decoder shown as 130 in Figure 2, thereby selecting one global word line from multiple global word lines (WL) (shown as 140 in Figure 2) and driving it by a corresponding global word line (WL) driver present in 130 in Figure 2. Similar to current SDRAMs that use memory cells consisting of one transistor and one capacitor, the global word line (WL) drives a local word line (WL) driver associated with each sub-cell array, and each word line (WL) of the sub-cell array is driven by the local word line (WL) driver as shown by 134 in Figure 2.

[0041] As shown in FIG. 2, a sub-cell array includes the same number of BL sense amplifiers (groups) as the number of bit lines (BL) (groups) for discriminating data from memory cells (groups) connectable to bit lines (BL) (groups) connected to memory cells (groups) connected to a single word line (WL), the same number of data registers (groups, an example of a "data register" in the claims) as the number of BL sense amplifiers (groups) for storing data from the memory cells (groups) discriminated by the BL sense amplifiers (groups), and the same number of BL driver circuits (groups) as the number of data registers connectable to the bit lines (BL) (groups) connected to the memory cells (groups) connected to a single word line (WL). The sub-cell array also includes source lines (SL) connected to the memory cells (groups) connected to a single word line (WL) and SL driver circuits connectable to the source lines (SL). In the fourth and fifth embodiments described below, the sub-cell array includes the same number of SL driver circuits connectable individually to the source lines (groups) connected to the memory cells (groups) connected to a single word line (WL). In 133 of FIG. 2, the BL driver circuit and the SL driver circuit are collectively referred to as a BL / SL driver. The BL sense amplifier(s), data register(s), and BL / SL driver(s) are selectively used for memory cell(s) of two sub-cell arrays that sandwich the BL sense amplifier(s), data register(s), and BL / SL driver(s). In other words, depending on the input address, the BL sense amplifier(s), data register(s), and BL / SL driver(s) are connected to the bit line(s) and source line(s) of the memory cell(s) of one of the sub-cell arrays.

[0042] In synchronization with a read command (hereinafter referred to as an RD command), a read command with auto-precharge (an example of a "command with auto-precharge" in the claims, hereinafter referred to as an RDA command), a write command (an example of a "write command" in the claims, hereinafter referred to as a WR command), or a write command with auto-precharge (an example of a "command with auto-precharge" in the claims, hereinafter referred to as a WRA command), a column decoder interprets an address signal input from an external device and outputs a selection signal for selecting one or more data registers from a plurality of data registers, an IO driver circuit writes data input from the external device to the selected data register, an IO sense amplifier circuit sense-amplifies the data signal from the selected data register to output it to the external device, and an IO MUX (131 in FIG. 2) is provided for connecting the selected data register and the IO driver circuit or the IO sense amplifier circuit in accordance with the output of the column decoder.

[0043] 3 is a diagram of the state transitions of current SDRAMs, showing the portion related to this embodiment. Although the details of the DDR-SDRAM specifications differ between generations, the operation shown in FIG. 3 is applied to each generation of DDR, and the SDRAM according to the present invention also realizes the state transitions shown in FIG. The circle indicates the state of the SDRAM, with solid arrows indicating state transitions based on the command indicated by the abbreviation attached to the arrow, and dashed arrows indicating state transitions regardless of command. The command abbreviations are explained in the table in the figure.

[0044] In response to an active command (an example of an "active command" in the claims, hereinafter referred to as an ACT command), the idle state indicated by 030 in the state transition diagram of Figure 3 changes to the activated state indicated by 031 in the state transition diagram of Figure 3, and the memory cell(s) specified by the address signal input in synchronization with the ACT command change to the active state indicated by 032 in the state transition diagram of Figure 3, where reading or writing can be performed. Unless the memory cell(s) are put into the active state, reading or writing operations cannot be performed on the memory cell(s). When a read command (hereinafter referred to as an RD command), a read command with auto-precharge (hereinafter referred to as an RDA command), a write command (hereinafter referred to as a WR command), a write command with auto-precharge (hereinafter referred to as a WRA command), or a precharge command (an example of a "precharge command" in the claims, hereinafter referred to as a PRE command) is received from the active state indicated by 032 in the state transition diagram of Figure 3, the state transitions to a read state indicated by 033 in the state transition diagram of Figure 3, a read state indicated by 035 in the state transition diagram of Figure 3, a write state indicated by 034 in the state transition diagram of Figure 3, a write state indicated by 036 in the state transition diagram of Figure 3, or a precharge state indicated by 037 in the state transition diagram of Figure 3, respectively.

[0045] When the RD command is received and the read state indicated by 033 in the state transition diagram of Figure 3 is entered, data is read from the memory cell(s) selected by the address signal input in synchronization with the RD command to an external device. When an RDA command, a WR command, a WRA command, or a PRE command is received from the read state indicated by 033 in the state transition diagram of FIG. 3, the state transitions to the read state indicated by 035 in the state transition diagram of FIG. 3, the write state indicated by 034 in the state transition diagram of FIG. 3, the write state indicated by 036 in the state transition diagram of FIG. 3, or the precharge state indicated by 037 in the state transition diagram of FIG. 3, respectively. Also, from the read state indicated by 033 in the state transition diagram of FIG. 3, it is possible to transition to the read state indicated by 033 in the state transition diagram of FIG. 3 by receiving an RD command again. If no command is input, the state returns to the active state indicated by 032 in the state transition diagram of FIG.

[0046] When the RDA command is received and the read state indicated by 035 in the state transition diagram of Figure 3 is entered, the SDRAM reads data from the memory cell(s) selected by the address signal input in synchronization with the RDA command to an external device. After a predetermined time has elapsed since the RDA command was accepted, the state transitions to the precharge state indicated by 037 in the state transition diagram of FIG. 3, even if the PRE command is not input. Since the active state is no longer present, the RD and WR commands cannot be issued after issuing the RDA command.

[0047] When the WR command is received and the write state shown as 034 in the state transition diagram of Figure 3 is reached, data is written from an external device to the SDRAM into the memory cell(s) selected by the address signal input in synchronization with the WR command. When an RD command, an RDA command, a WRA command, or a PRE command is received from the write state indicated by 034 in the state transition diagram of FIG. 3, the state transitions to the read state indicated by 033 in the state transition diagram of FIG. 3, the read state indicated by 035 in the state transition diagram of FIG. 3, the write state indicated by 036 in the state transition diagram of FIG. 3, or the precharge state indicated by 037 in the state transition diagram of FIG. 3, respectively. Also, from the write state indicated by 034 in the state transition diagram of FIG. 3, it is possible to transition to the write state indicated by 034 in the state transition diagram of FIG. 3 by receiving a WR command again. If no command is input, the state returns to the active state indicated by 032 in the state transition diagram of FIG.

[0048] When the WRA command is received and the write state shown as 036 in the state transition diagram of Figure 3 is entered, an external device writes data to the SDRAM into the memory cell(s) selected by the address signal input in synchronization with the WRA command. After a predetermined time has elapsed since the WRA command was accepted, the state transitions to the precharge state indicated by 037 in the state transition diagram of FIG. 3, even if the PRE command is not input. Since the device is no longer in the active state, the RD and WR commands cannot be issued after issuing the WRA command.

[0049] In the current SDRAM specifications, the device transitions to the precharge state shown as 037 in the state transition diagram in Figure 3 when a predetermined time has passed since the RDA command was received, or when a predetermined time has passed since the WRA command was received. Alternatively, upon receiving a PRE command, the device transitions from the active state indicated by 032 in the state transition diagram of FIG. 3, the read state indicated by 033 in the state transition diagram of FIG. 3, or the write state indicated by 034 in the state transition diagram of FIG. 3 to the precharge state indicated by 037 in the state transition diagram of FIG. 3. After the transition to the precharge state, a predetermined time elapses, and then the state transitions to the idle state indicated by 030 in the state transition diagram of FIG.

[0050] SDRAM also includes low-power consumption LPDDR-SDRAM, which differs in that it has a DLL (Delay Locked Loop; a circuit that amplifies a clock signal input from outside the device and synchronizes the clock signal used within the device using a delay circuit), but the operation shown in Figure 3, which relates to this embodiment, also applies to LPDDR-SDRAM. Furthermore, while the detailed operating specifications of GDDR-SDRAM for graphics applications differ from those of DDR-SDRAM and LPDDR-SDRAM, the basic operation of the DRAM shown in Figure 3 is also applicable.

[0051] As a comparison to clarify the purpose and differences of the present invention, Figure 93 shows a state transition diagram of one memory cell (group) and one data register (group) in a current SDRAM that uses a memory cell composed of one MOS transistor and one capacitor, which operates in response to an address signal input in synchronization with the ACT command. Shown inside the circles are the states of the memory cell(s) and data register(s) that are specified and operated by the address signal input in sync with the ACT command, shown in tabular format. Cell denotes the memory cell(s) specified by the address signal input in sync with the ACT command, and DR denotes the data register(s) specified by the address signal input in sync with the CT command. Hold indicates a state in which the held data is maintained, write indicates a write state, and read indicates a read state. Precharge indicates that the data held in the data register state is invalid. A solid arrow indicates a state transition upon receiving a command associated with the arrow, while a dashed arrow indicates a state transition without a command.

[0052] Figure 93 is a state transition diagram for certain memory cells and data registers specified by an address signal input in synchronization with an ACT command, so even if the SDRAM receives an ACT command and enters an activated state, no state transition occurs for memory cells and data registers that are not specified by the address input in synchronization with the ACT command. As a result of a previously received command, they will remain in either the idle state indicated by 010 in the state transition diagram of Figure 93 or the active state indicated by 012 in the state transition diagram of Figure 93.

[0053] Starting from the idle state, the memory cells are holding the data previously written to them, and the data registers are maintaining their precharged state due to the operations performed before entering the idle state. Thus, in the idle state, designated 010 in the state transition diagram of Figure 93, cell in the table is hold, and DR in the table is also hold.

[0054] When a current SDRAM using a memory cell consisting of one MOS transistor and one capacitor receives an ACT command, it enters an activated state, receives an address signal input simultaneously with the ACT command, reads data from the memory cell(s) selected by the received address signal, and stores the read data in the data register(s) specified by the received address signal. Therefore, in the activated state shown as 011 in the state transition diagram of Figure 93, cell in the table is read and DR in the table is write.

[0055] When data is read from the memory cell(s) specified by the address signal and stored in the data register(s) specified by the address signal, the SDRAM transitions to the active state, and the memory cell(s) and data register(s) maintain the data they hold. Therefore, in the active state shown as 012 in the state transition diagram of Figure 93, cell in the table is hold, and DR in the table is also hold. When an RD command, an RDA command, a WR command, a WRA command, or a PRE command is received from the active state indicated by 012 in the state transition diagram of FIG. 93, the state transitions to the read state indicated by 013 in the state transition diagram of FIG. 93, the read state indicated by 015 in the state transition diagram of FIG. 93, the write state indicated by 014 in the state transition diagram of FIG. 93, the write state indicated by 016 in the state transition diagram of FIG. 93, or the precharge state indicated by 017 in the state transition diagram of FIG. 93, respectively.

[0056] When the SDRAM receives the RD command, it transitions to the read state indicated by 013 in the state transition diagram of FIG. In the case of current SDRAMs that use memory cells consisting of one MOS transistor and one capacitor, when the RD command is received, the memory cells (groups) selected by the address signal received at the same time as the ACT command do not operate and retain their data. Of the data registers specified by the address signal received simultaneously with the ACT command, data is read from the data registers specified by the address signal received simultaneously with the RD command to a device external to the SDRAM. On the other hand, the data register(s) that are specified by the address signal received simultaneously with the ACT command but are not specified by the address signal received simultaneously with the RD command are in a state of holding data. Therefore, in the read state shown as 013 in the state transition diagram of FIG. 93, cell in the table is hold, and DR in the table is read and hold.

[0057] Furthermore, the SDRAM can receive the RD command again, and data is read from the data register(s) specified by the address signal received at the same time as the ACT command to a device external to the SDRAM, from the data register(s) specified by the address signal received at the same time as the RD command. In the state transition diagram of Figure 93, the SDRAM remains in the read state indicated by 013. If no command is input from the read state indicated by 013 in the state transition diagram of FIG. 93, after a predetermined time according to the current SDRAM specifications has elapsed, the state transitions to the active state indicated by 012 in the state transition diagram of FIG. 93. Furthermore, when an RDA command, a WR command, a WRA command, or a PRE command is received from the read state indicated by 013 in the state transition diagram of FIG. 93, the state transitions to the read state indicated by 015 in the state transition diagram of FIG. 93, the write state indicated by 014 in the state transition diagram of FIG. 93, the write state indicated by 016 in the state transition diagram of FIG. 93, or the precharge state indicated by 017 in the state transition diagram of FIG. 93, respectively.

[0058] When the SDRAM receives the RDA command, it transitions to the read state indicated by 015 in the state transition diagram of FIG. The memory cells designated by the address signal received simultaneously with the ACT command do not operate and are in a state of retaining data. Of the data registers specified by the address signal received simultaneously with the ACT command, data is read from the data registers specified by the address signal received simultaneously with the RDA command to a device external to the SDRAM. On the other hand, the data register(s) that are specified by the address signal received simultaneously with the ACT command but are not specified by the address signal received simultaneously with the RDA command are in a state of holding data. Therefore, in the read state shown as 015 in the state transition diagram of FIG. 93, cell in the table is hold, and DR in the table is read and hold. After a predetermined time has elapsed, the state transitions to the precharge state indicated by 017 in the state transition diagram of FIG.

[0059] When the SDRAM receives a WR command, it transitions to the write state indicated by 014 in the state transition diagram of FIG. Of the memory cells and data registers specified by the address signal received simultaneously with the ACT command, data is written from a device external to the SDRAM to the memory cells and data registers specified by the address signal received simultaneously with the WR command. On the other hand, the memory cell(s) and data register(s) that are specified by the address signal received simultaneously with the ACT command but are not specified by the address signal received simultaneously with the WR command are in a state of holding data. Therefore, in the write state shown as 014 in the state transition diagram of FIG. 93, cell in the table is write and hold, and DR in the table is also write and hold.

[0060] Furthermore, the SDRAM can receive a WR command again, and data is written from an external device to the memory cell(s) and data register(s) specified by the address signal received at the same time as the ACT command, among the memory cell(s) and data register(s) specified by the address signal received at the same time as the WR command. In the state transition diagram of Figure 93, the SDRAM remains in the write state indicated by 014. If no command is input from the write state indicated by 014 in the state transition diagram of FIG. 93, the state transitions to the active state indicated by 012 in the state transition diagram of FIG. 93 after a predetermined time period according to the current SDRAM specifications has elapsed. When the RD command, RDA command, WRA command, or PRE command is received from the write state indicated by 014 in the state transition diagram of Figure 93, the state transitions to the read state indicated by 013 in the state transition diagram of Figure 93, the read state indicated by 015 in the state transition diagram of Figure 93, the write state indicated by 016 in the state transition diagram of Figure 93, or the precharge state indicated by 017 in the state transition diagram of Figure 93, respectively.

[0061] When the SDRAM receives the WRA command, it transitions to the write state indicated by 016 in the state transition diagram of FIG. Of the memory cells and data registers specified by the address signal received simultaneously with the ACT command, data is written from a device external to the SDRAM to the memory cells and data registers specified by the address signal received simultaneously with the WRA command. On the other hand, the memory cells (group) and data registers (group) that are specified by the address signal received simultaneously with the ACT command but are not specified by the address signal received simultaneously with the WRA command are in a state of holding data. Therefore, in the write state shown as 016 in the state transition diagram of FIG. 93, cell in the table is write and hold, and DR in the table is also write and hold. After a predetermined time has elapsed, the state transitions to the precharge state indicated by 017 in the state transition diagram of FIG.

[0062] In the current SDRAM specifications, when a predetermined time has passed since the RDA command was received, or when a predetermined time has passed since the WRA command was received, the SDRAM transitions to the precharge state shown as 017 in the state transition diagram of Figure 93. Alternatively, upon receiving a PRE command, the active state indicated by 012 in the state transition diagram of FIG. 93, the read state indicated by 013 in the state transition diagram of FIG. 93, or the write state indicated by 014 in the state transition diagram of FIG. 93 transitions to the precharge state indicated by 017 in the state transition diagram of FIG. 93. In the case of current SDRAMs that use memory cells consisting of one MOS transistor and one capacitor, no operation is performed on the memory cells (group) specified by the address signal received at the same time as the ACT command, and the data is maintained, and the data registers (group) that also serve as the BL sense amplifiers (group) are precharged. Therefore, in the precharge state shown as 017 in the state transition diagram of FIG. 93, cell in the table is hold, and DR in the table is precharge.

[0063] After a further predetermined time has elapsed, the state transitions to the idle state indicated by 010 in the state transition diagram of Figure 93. No operation is performed on the memory cell(s) or data register(s) specified by the address signal received at the same time as the ACT command. Therefore, in the idle state indicated by 010 in the state transition diagram of Figure 93, both cell in the table and DR in the table are hold.

[0064] Comparing the state transition diagram of Figure 3 with the state transition diagram of Figure 93, the only difference is that when a read command is received, the data is not actually read from the memory cell, but rather the data that was previously read from the memory cell by the startup operation is read from the data register and the read operation is performed.

[0065] The SDRAM according to the first embodiment of the present invention performs the same state transitions as the current SDRAM shown in Figure 3, but stores charges in the floating body and distinguishes the data to be stored by the amount of electricity. This is because the memory cell(s) are configured with one transistor and do not have a capacitor, and the memory cell(s) are configured with potentials appropriate for writing "0" and "1", so the cells to be written with "0" and "1" connected to the same word line are not written with "0" and "1" simultaneously. The specific operation is described below.

[0066] In essence, writing one of the binary data bits is executed after receiving a WR command or a WRA command from an external device to all memory cells connected to a word line selected by an address signal input in synchronization with an ACT command from an external device. For the sake of convenience in the following explanation, what is executed here is essentially writing "0" data, and is described as erasing. There is no problem if the logical data is written as "1" instead of "0."

[0067] From the viewpoint of power consumption, it is desirable not to execute the erase operation every time a WR command is issued, and it is also desirable not to execute the erase operation again with a WRA command after a WR command has been issued. Furthermore, in consideration of the subsequent operation sequence, it is desirable to execute the erase operation only once when the first WR command or WRA command is issued. In the following operation explanation, it is assumed that the erase operation is executed only when the first WR command or WRA command is issued.

[0068] Writing of other data, different from the data written in the erase operation, to the memory cell(s) is performed after receiving a PRE command after receiving a WR command from an external device (the RD and WR commands may be received any number of times between the WR and PRE commands). Alternatively, if a WR command is received even once before inputting an RDA command (the RD and WR commands may be received any number of times between the WR and RDA commands), it is performed a predetermined time after receiving the RDA command. Alternatively, it is performed after receiving a WRA command from an external device, a predetermined time after completing data input from the external device. If the erase operation is performed to write a substantial "0" as logical data, then what is performed here is a "1" data write. If the erase operation is performed to write a substantial "1" as logical data, then the write at this point is a "0" as logical data.

[0069] A voltage is applied to write "1" to the memory cell(s) to be written with "1", but since the memory cell(s) to be written with "0" have already been erased, the write at this point simply involves applying a voltage that does not destroy the "0" state of the memory cell(s) to be written with "0", and no voltage for writing "0" is applied to the memory cells to be written with "0".

[0070] When a WR command or WRA command is received, memory cells that were not the target of writing are erased and their data becomes "0", but by receiving the ACT command, which is always input before a WR command or WRA command, the data of the memory cells that will be erased is read out in advance, written to the data register(s), and stored therein. Therefore, in addition to the data written to the data register(s) by the WR command or WRA command as the target of writing, "1" is written to the memory cells that stored "1" before erasure and were not the target of writing by the WR command or WRA command based on the data stored in the data register(s), so the data does not change.

[0071] When the SDRAM of the first embodiment receives a WR command, it does not perform a write operation to the memory cell specified by the address signal received at the same time as the WR command. However, since the data is written to the data register specified by the address signal received at the same time as the WR command, there is no problem with the read data even if the data of the memory cell specified by the address signal received at the same time as the WR command is read from the data register using a subsequent RD command.

[0072] The SDRAM according to the first embodiment does not perform a write operation after a read operation if it has not received a WR command between the time it receives an ACT command and the time it receives an RDA command.The SDRAM according to the first embodiment does not perform a write operation after a read operation if it has not received a WR command between the time it receives an ACT command and the time it receives a PRE command.

[0073] Based on the above, a state transition diagram focusing on the memory cells and data registers of the SDRAM according to the first embodiment of the present invention is shown in FIG. As with the state transition diagram shown in Figure 93, what is shown inside the circle is the state of the SDRAM to which the memory cell(s) and data register(s) transition in response to the command, as specified by the address signal input in synchronization with the ACT command, and what is shown in tabular form is the actual state of the memory cell(s) (written as cell) and data register(s) (written as DR) specified by the address signal input in synchronization with the ACT command. "Hold" indicates a state in which the held data is maintained, "Write" indicates a write state, "Erase" indicates an erase state, and "Read" indicates a read state. "Reset" indicates that the data held as the state of the data register is invalid. As with the state transition diagram shown in FIG. 93, solid arrows indicate a state transition upon receiving a command associated with the arrow, while dashed arrows indicate a state transition regardless of a command. Similar to the state transition diagram shown in Figure 93, the state transition diagram shown in Figure 4 is a state transition diagram of certain memory cell(s) and data register(s) specified by an address signal input in synchronization with an ACT command, so even if the SDRAM receives an ACT command and enters an activated state, no state transition occurs for memory cell(s) and data register(s) not specified by the address input in synchronization with the ACT command. As a result of a previously received command, the state will remain idle as shown at 040 in the state transition diagram of Figure 4, active as shown at 042 in the state transition diagram of Figure 4, or active as shown at 047 in the state transition diagram of Figure 4.

[0074] We start from the idle state shown as 040 in the state transition diagram of Figure 4. The memory cells are holding the data previously written to them, and the data registers are maintaining the precharged or reset state that was set by the operation performed before the idle state. The cell in the table stands for hold, and the DR in the table stands for hold. Even if the idle state occurs after power-on, in the case of memory cells that use the amount of electricity stored in the floating body as data according to this embodiment, the floating body is likely to be in a discharged state, and the data in the discharged state of the floating body is retained. After power-on, the data register(s) are also in a precharged state or a reset state, as determined by the sequence specified in the SDRAM specifications.

[0075] When the SDRAM according to the first embodiment of the present invention receives an ACT command, it enters the startup state shown at 041 in the state transition diagram of Figure 4, receives an address signal input simultaneously with the ACT command, reads data from the memory cell(s) selected by the received address signal, and stores the data in the data register(s) specified by the received address signal. Therefore, in the startup state shown at 041 in the state transition diagram of Figure 4, cell in the table indicates read, and DR in the table indicates write.

[0076] When data is read from the memory cell(s) specified by the address signal and stored in the data register(s) specified by the address signal, the SDRAM transitions to the active state shown at 042 in the state transition diagram of Figure 4. Therefore, in the active state shown at 042 in the state transition diagram of Figure 4, cell in the table is hold and DR in the table is hold. When an RD command, an RDA command, a WR command, a WRA command, or a PRE command is received from the active state indicated by 042 in the state transition diagram of FIG. 4, the state transitions to the read state indicated by 043 in the state transition diagram of FIG. 4, the read state indicated by 044 in the state transition diagram of FIG. 4, the write state indicated by 046 in the state transition diagram of FIG. 4, the write state indicated by 050 in the state transition diagram of FIG. 4, or the precharge state indicated by 045 in the state transition diagram of FIG. 4, respectively.

[0077] When the SDRAM according to the first embodiment of the present invention receives an RD command from the active state indicated by 042 in the state transition diagram of FIG. 4, it transitions to the read state indicated by 043 in the state transition diagram of FIG. In the SDRAM according to the first embodiment, upon receiving the RD command, the memory cells selected by the address signal received simultaneously with the ACT command do not operate and are in a state of holding data. Data is read from the data register(s) specified by the address signal received simultaneously with the RD command to a device external to the SDRAM. Meanwhile, the data register(s) specified by the address signal received simultaneously with the ACT command but not specified by the address signal received simultaneously with the RD command are in a state of holding data. Therefore, in the read state shown as 043 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is read and hold.

[0078] Furthermore, the SDRAM according to the first embodiment of the present invention can receive the RD command again, and data is read out to a device external to the SDRAM according to the first embodiment from the data register(s) specified by the address signal received at the same time as the ACT command, among the data register(s) specified by the address signal received at the same time as the RD command. In the state transition diagram of Figure 4, the SDRAM remains in the read state indicated by 043. If no command is input from the read state indicated by 043 in the state transition diagram of Figure 4, after a predetermined time according to the current SDRAM specifications has elapsed, the state transitions to the active state indicated by 042 in the state transition diagram of Figure 4. Furthermore, when an RDA command, a WR command, a WRA command, or a PRE command is received from the read state indicated by 043 in the state transition diagram of FIG. 4, the state transitions to the read state indicated by 044 in the state transition diagram of FIG. 4, the write state indicated by 046 in the state transition diagram of FIG. 4, the write state indicated by 050 in the state transition diagram of FIG. 4, or the precharge state indicated by 045 in the state transition diagram of FIG. 4, respectively.

[0079] When the SDRAM according to the first embodiment of the present invention receives an RDA command from the active state indicated by 042 in the state transition diagram of FIG. 4 or the read state indicated by 043 in the state transition diagram of FIG. 4, it transitions to the read state indicated by 044 in the state transition diagram of FIG. 4. In the SDRAM according to the first embodiment, upon receiving the RDA command, the memory cells selected by the address signal received simultaneously with the ACT command do not operate and are in a state of holding data. Data is read from the data register(s) specified by the address signal received simultaneously with the RDA command to a device external to the SDRAM. Meanwhile, the data register(s) specified by the address signal received simultaneously with the ACT command but not specified by the address signal received simultaneously with the RDA command are in a state of holding data. Therefore, in the read state shown as 044 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is read and hold. After a predetermined time has elapsed, the state transitions to the precharge state indicated by 045 in the state transition diagram of FIG.

[0080] When the SDRAM according to the first embodiment of the present invention receives a PRE command from the active state indicated by 042 in the state transition diagram of FIG. 4 or the read state indicated by 043 in the state transition diagram of FIG. 4, or when a predetermined time has elapsed from the read state indicated by 044 in the state transition diagram of FIG. 4, it transitions to the precharge state indicated by 045 in the state transition diagram of FIG. 4. In the SDRAM according to the first embodiment of the present invention, the memory cells are not operating and are in a state of retaining data. Assuming that the circuit shown in Figure 42 is used as the data register, the data register is reset. Therefore, in the precharge state shown as 045 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is reset.

[0081] When the SDRAM according to the first embodiment of the present invention receives a WR command from either the active state indicated by 042 in the state transition diagram of FIG. 4 or the read state indicated by 043 in the state transition diagram of FIG. 4, it transitions to the write state indicated by 046 in the state transition diagram of FIG. 4. In the SDRAM according to the first embodiment, upon receiving a WR command, memory cells selected by an address signal received simultaneously with the ACT command are erased. Data is written from a device external to the SDRAM to data registers specified by an address signal received simultaneously with the WR command. Meanwhile, data registers specified by an address signal received simultaneously with the ACT command but not specified by an address signal received simultaneously with the WR command retain data. Therefore, in the write state shown as 046 in the state transition diagram of FIG. 4, cell in the table is erase, and DR in the table is write and hold. The memory cell(s) selected by the address signal received at the same time as the ACT command are erased, but if writing of data from an external device to the data register(s) specified by the address signal received at the same time as the WR command has not been completed, the state transitions to the write state shown as 049 in the state transition diagram of Figure 4. When the memory cell(s) selected by the address signal received simultaneously with the ACT command have been erased and data has been written from an external device to the data register(s) specified by the address signal received simultaneously with the WR command, the SDRAM transitions to the active state indicated by 047 in the state transition diagram of Figure 4.

[0082] The memory cell(s) selected by the address signal received at the same time as the ACT command are erased, and data is written from a device external to the SDRAM to the data register(s) specified by the address signal received at the same time as the WR command, and then the SDRAM transitions to the active state indicated by 047 in the state transition diagram of Figure 4. The data register(s) specified by the address signal received simultaneously with the WR command are in a state where they hold the written data after the data has been written. On the other hand, the memory cell(s) selected by the address signal received simultaneously with the ACT command and the data register(s) not specified by the address signal received simultaneously with the WR command are in a state where they do not operate and hold the data. Therefore, in the active state shown as 047 in the state transition diagram of FIG. 4, the cell in the table is hold, and the DR in the table is also hold. When an RD command, an RDA command, a WR command, a WRA command, or a PRE command is received from the active state indicated by 047 in the state transition diagram of FIG. 4, the state transitions to the read state indicated by 048 in the state transition diagram of FIG. 4, the read state indicated by 051 in the state transition diagram of FIG. 4, the write state indicated by 049 in the state transition diagram of FIG. 4, the write state indicated by 052 in the state transition diagram of FIG. 4, or the precharge state indicated by 053 in the state transition diagram of FIG. 4, respectively.

[0083] When the SDRAM according to the first embodiment of the present invention receives a WRA command from either the active state indicated by 042 in the state transition diagram of FIG. 4 or the read state indicated by 043 in the state transition diagram of FIG. 4, it transitions to the write state indicated by 050 in the state transition diagram of FIG. 4. In the SDRAM according to the first embodiment, upon receiving the WRA command, the memory cells selected by the address signal received simultaneously with the ACT command are erased and are in a state of retaining the data. Data is written from a device external to the SDRAM to the data registers specified by the address signal received simultaneously with the WRA command. Meanwhile, the data registers specified by the address signal received simultaneously with the ACT command but not specified by the address signal received simultaneously with the WRA command are in a state of retaining the data. Therefore, in the write state shown as 050 in the state transition diagram of FIG. 4, cell in the table is erase, and DR in the table is write and hold. The memory cell(s) selected by the address signal received at the same time as the ACT command are erased, but if writing of data from an external device to the data register(s) specified by the address signal received at the same time as the WRA command has not been completed, the SDRAM transitions to the write state indicated by 052 in the state transition diagram of Figure 4. When erasure of the memory cell(s) selected by the address signal received simultaneously with the ACT command is completed and writing of data from an external device to the data register(s) specified by the address signal received simultaneously with the WRA command is completed, the SDRAM transitions to the precharge state indicated by 053 in the state transition diagram of Figure 4.

[0084] When the SDRAM according to the first embodiment of the present invention receives an RD command from either the active state indicated by 047 in the state transition diagram of FIG. 4 or the write state indicated by 049 in the state transition diagram of FIG. 4, it transitions to the read state indicated by 048 in the state transition diagram of FIG. 4. In the SDRAM according to the first embodiment, upon receiving the RD command, the memory cells selected by the address signal received simultaneously with the ACT command do not operate and are in a state of holding data. Data is read from the data register(s) specified by the address signal received simultaneously with the RD command to a device external to the SDRAM. Meanwhile, the data register(s) specified by the address signal received simultaneously with the ACT command but not specified by the address signal received simultaneously with the RD command are in a state of holding data. Therefore, in the read state shown as 048 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is read and hold.

[0085] Furthermore, the SDRAM according to the first embodiment of the present invention can receive the RD command again, and data is read out to a device external to the SDRAM according to the first embodiment from the data register(s) specified by the address signal received at the same time as the RD command, among the data register(s) specified by the address signal received at the same time as the ACT command. In the state transition diagram of Figure 4, the SDRAM remains in the read state indicated by 048. If no command is input from the read state indicated by 048 in the state transition diagram of Figure 4, after a predetermined time has elapsed according to the current SDRAM specifications, the state transitions to the active state indicated by 047 in the state transition diagram of Figure 4. Furthermore, when an RDA command, a WR command, a WRA command, or a PRE command is received from the read state indicated by 048 in the state transition diagram of FIG. 4, the state transitions to the read state indicated by 051 in the state transition diagram of FIG. 4, the write state indicated by 049 in the state transition diagram of FIG. 4, the write state indicated by 052 in the state transition diagram of FIG. 4, or the precharge state indicated by 053 in the state transition diagram of FIG. 4, respectively.

[0086] When the SDRAM according to the first embodiment of the present invention receives an RDA command from either the active state indicated by 047 in the state transition diagram of FIG. 4 or the read state indicated by 048 in the state transition diagram of FIG. 4, it transitions to the read state indicated by 051 in the state transition diagram of FIG. 4. In the SDRAM according to the first embodiment, upon receiving the RDA command, the memory cells selected by the address signal received simultaneously with the ACT command do not operate and are in a state of holding data. Data is read from the data register(s) specified by the address signal received simultaneously with the RDA command to a device external to the SDRAM. Meanwhile, the data register(s) specified by the address signal received simultaneously with the ACT command but not specified by the address signal received simultaneously with the RDA command are in a state of holding data. Therefore, in the read state shown as 051 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is read and hold. After a predetermined time has elapsed, the state transitions to the precharge state indicated by 053 in the state transition diagram of FIG.

[0087] When the SDRAM according to the first embodiment of the present invention receives a WR command from either the active state indicated by 047 in the state transition diagram of FIG. 4 or the read state indicated by 048 in the state transition diagram of FIG. 4, it transitions to the write state indicated by 049 in the state transition diagram of FIG. 4. In the SDRAM according to the first embodiment, the memory cells selected by the address signal received simultaneously with the ACT command have already been erased, and therefore are not operated and are in a state of holding data. Data is written from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WR command. Meanwhile, the data register(s) specified by the address signal received simultaneously with the ACT command but not specified by the address signal received simultaneously with the WR command are in a state of holding data. Therefore, in the write state shown as 049 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is write and hold.

[0088] The SDRAM of the first embodiment is capable of accepting the WR command again, and data is written from a device external to the SDRAM to the data register(s) specified by the address signal newly received at the same time as the WR command, among the memory cells(s) and data register(s) specified by the address signal received at the same time as the ACT command. In the state transition diagram of FIG. 4, the state will remain in the write state indicated as 049. If no command is input from the write state indicated by 049 in the state transition diagram of Figure 4, after a predetermined time has elapsed according to the current SDRAM specifications, the state transitions to the active state indicated by 047 in the state transition diagram of Figure 4. When an RD command, an RDA command, a WRA command, or a PRE command is received from the write state indicated by 049 in the state transition diagram of FIG. 4, the state transitions to the read state indicated by 048 in the state transition diagram of FIG. 4, the read state indicated by 051 in the state transition diagram of FIG. 4, the write state indicated by 052 in the state transition diagram of FIG. 4, or the precharge state indicated by 053 in the state transition diagram of FIG. 4, respectively.

[0089] When the SDRAM according to the first embodiment of the present invention receives a WRA command from the active state indicated by 047 in the state transition diagram of Fig. 4, the read state indicated by 048 in the state transition diagram of Fig. 4, or the write state indicated by 049 in the state transition diagram of Fig. 4, it enters the write state indicated by 052 in the state transition diagram of Fig. 4. Alternatively, it may transition from the write state indicated by 050 in the state transition diagram of Fig. 4 by an automatic sequence. In the SDRAM according to the first embodiment, the memory cells selected by the address signal received simultaneously with the ACT command have already been erased, and therefore do not operate and are in a state of holding data. Data is written from a device external to the SDRAM to the data register(s) specified by the address signal received simultaneously with the WRA command. Meanwhile, the data register(s) specified by the address signal received simultaneously with the ACT command but not specified by the address signal received simultaneously with the WRA command are in a state of holding data. Therefore, in the write state shown as 050 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is write and hold. When data has been written from an external device to the SDRAM into the data register(s) specified by the address signal received at the same time as the WRA command, the SDRAM transitions to the precharge state indicated by 053 in the state transition diagram of Figure 4.

[0090] In the case of the SDRAM according to the first embodiment, when a predetermined time has elapsed since the RDA command was received, or when a predetermined time has elapsed since the WRA command was received, the SDRAM transitions to the precharge state indicated by 053 in the state transition diagram of FIG. 4. Alternatively, by receiving a PRE command, the device transitions from the active state indicated by 047 in the state transition diagram of FIG. 4, the read state indicated by 048 in the state transition diagram of FIG. 4, or the write state indicated by 049 in the state transition diagram of FIG. 4 to the precharge state indicated by 053 in the state transition diagram of FIG. 4. The memory cell(s) specified by the address signal received simultaneously with the ACT command are written according to the data in the data register(s) specified by the address signal received simultaneously with the ACT command. Therefore, in the precharge state shown as 053 in the state transition diagram of FIG. 4, cell in the table is write and DR in the table is read.

[0091] The SDRAM according to the first embodiment of the present invention transitions from the precharge state indicated by 053 in the state transition diagram of FIG. 4 to the precharge state indicated by 045 in the state transition diagram of FIG. 4 by an automatic sequence. In the SDRAM according to the first embodiment of the present invention, the memory cells are not operating and are in a state of retaining data. Assuming that the circuit shown in Figure 42 is used as the data register, the data register is reset. Therefore, in the precharge state shown as 045 in the state transition diagram of FIG. 4, cell in the table is hold, and DR in the table is reset.

[0092] After a further predetermined time has elapsed, the state transitions to the idle state indicated by 040 in the state transition diagram of Figure 4. No operation is performed on the memory cell(s) or data register(s) specified by the address signal received at the same time as the ACT command. Therefore, in the idle state indicated by 040 in the state transition diagram of Figure 4, both cell and DR are in hold.

[0093] The state transition shown in Figure 4 allows for the accumulation of electric charge in the floating body without deviating from the specifications of current SDRAM, and sets potentials suitable for writing "0" and "1" to memory cells (groups) consisting of a single transistor without a capacitor, which distinguishes the data to be stored based on the amount of electricity stored.This makes it possible to prevent simultaneous writing of "0" and "1" to cells to be written to "0" and cells to be written to "1" that are connected to the same word line. In addition, low power consumption is achieved by performing the erase operation only once when the first WR command or WRA command is input.

[0094] Examples of state transitions of the SDRAM according to the first embodiment of the present invention shown in FIG. 4 are shown in waveform diagrams in FIGS. 5 to 17 show only the signal lines related to this embodiment, and the command signal and address signal input to the clock synchronous dynamic semiconductor memory device from outside the device are represented as a set of signals, respectively, as "command" and "address." The signal lines to which the command signal and address signal are input are not completely independent, and a signal input on one signal line may become an address signal at some timing and a command signal at another timing. Data input / output between the clock synchronous dynamic semiconductor memory device and the outside of the device is represented as DQ.

[0095] To enable understanding of the features of this embodiment, the waveform of the selected word line (WL) of the sub-cell array selected by the address signal input in synchronization with the ACT command, the waveform of the unselected word line (WL) of the sub-memory cell array selected by the address signal input in synchronization with the ACT command, the waveform of the word line (WL) of the sub-cell array that is unselected by the address signal input in synchronization with the ACT command, the waveform of the bit line (BL) connected to the cell to be written to "1" of the sub-cell array selected by the address signal input in synchronization with the ACT command, the waveform of the bit line (BL) connected to the cell to be written to "0" of the sub-cell array selected by the address signal input in synchronization with the ACT command, and the waveform of the source line (SL) of the sub-cell array selected by the address signal input in synchronization with the ACT command are shown.

[0096] The SDRAM has the configuration shown in Figures 1 and 2, and the sub-cell array has the configuration shown in Figure 29, for example. The sub-cell array shown in Figure 29 relates to the fourth embodiment described below. The memory cell stores electric charge in the floating body, and the stored data is distinguished by the amount of electric charge. A specific circuit diagram of the memory cell is shown in Figure 29(A). The symbol for the memory cell is shown in Figure 29(B), and is arranged as symbol 104 in Figure 30. As an example of the physical structure of the memory cell, a schematic diagram of a cross section perpendicular to the extension direction of the word line (WL) is shown in Figure 29(C).

[0097] The meanings of the symbols representing the potentials of the word lines (WL), bit lines (BL), and source lines (SL) shown in Figures 5 to 17 and Figures 20 to 26 are summarized in the table of Figure 27. Specific examples of the potentials are shown in the tables of Figures 28(A) and 28(B). FIG. 28(A) shows a case where impact ionization is used as a method for writing "1" to a memory cell using an NMOS transistor, and FIG. 28(B) shows a case where BTBT (Band to Band Tunneling) is used to write "1" to a memory cell using an NMOS transistor.

[0098] The table in Figure 27 will be explained below. "Write" indicates that the sub-cell array is in a write state, "Erase" indicates that the sub-cell array is in an erase state, "Read" indicates that the sub-cell array is in a read state, and "Idle" indicates that the sub-cell array is in an idle state. The idle state is a state in which no "write", "erase" or "read" operation is being performed on the memory cells (group) of the sub-cell array, but the memory cells must still retain data.

[0099] In the "As sub-cell array" column, "selected" indicates that the sub-cell array is selected by the address signal input in synchronization with the ACT command, and "not selected" indicates that the sub-cell array is not selected by the address signal input in synchronization with the ACT command. In the column "In Selected Sub-Cell Array," "Selected" indicates that the sub-cell array is in a selected state by the address signal input in synchronization with the ACT command, and that the word line (WL), bit line (BL), or source line (SL) is in a selected state by the address signal input in synchronization with the ACT command; "Not Selected" indicates that the sub-cell array is in a selected state by the address signal input in synchronization with the ACT command, and that the word line (WL) is in a non-selected state by the address signal input in synchronization with the ACT command. In this embodiment, all bit lines (BL) and source lines (SL) of the selected sub-cell array are in the "selected" state. Therefore, in Figure 27, there are no "selected" items for the bit lines (BL) and source lines (SL) of the sub-cell array, and no "unselected" items within the cell array. The same applies to the source line (SL). If the "As a sub-cell array" column is "Not selected," then "In the selected sub-cell array" becomes meaningless, so if the "As a sub-cell array" column is "Not selected," the "In the selected sub-cell array" column is marked with a "-."

[0100] When a sub-cell array is in a non-selected state due to an address signal input in synchronization with an ACT command, the word lines (WL), bit lines (BL), and source lines (SL) of the non-selected sub-cell array are all non-selected, and the non-selected sub-cell array is in an idle state even if a read operation, a write operation, or an erase operation is being performed on the memory cells of the selected sub-cell array.

[0101] In the memory cell according to this embodiment, which accumulates electric charges in the floating body and distinguishes the stored data based on the amount of electric charge, if the memory cell is idle for a certain period of time after writing data, the data will be lost, and therefore a refresh operation is required, just like a memory cell consisting of one transistor and one capacitor. A refresh operation for a memory cell is an operation in which data is read from the memory cell and the same data that was read is written back to the memory cell. Refreshing can be considered a combination of reading and writing, and is not specifically listed as an item in Figure 27.

[0102] VIWL is the word line (WL) potential in the idle state. VRWL is the selected word line (WL) potential of the selected sub-cell array during read. The unselected word line (WL) potential of the selected sub-cell array during read is VIWL, the same as in the idle state. VWWLH is the potential of the selected word line (WL) of the selected sub-cell array during write. The potential of the unselected word lines (WL) of the selected sub-cell array during write is VWWLL. VEWLH is the potential of the selected word line (WL) of the selected sub-cell array during erasure, and VEWLL is the potential of the unselected word lines (WL) of the selected sub-cell array during erasure. The word line (WL) potential of the unselected sub-cell arrays is VIWL.

[0103] VRBL is the bit line (BL) potential of the selected sub-cell array during read. Depending on the method of biasing the bit line during read, the data in the memory cell may be slightly different, whether it is "0" or "1." Here, we assume that a read method is used in which a constant voltage, VRBL, is applied to the bit line (BL) and the current value of the memory cell determines whether it is "0" or "1." VEBL is the bit line (BL) potential of the selected sub-cell array during erasure. VWBL is the bit line (BL) potential when writing "1" to the selected sub-cell array. According to this embodiment, since writing "0" only requires maintaining the state of the memory cell after erasure, the bit line (BL) potential when writing "0" to the selected sub-cell array and the source line (SL) potential of the selected sub-cell array are made the same, 0V, so as not to flow current. The source line (SL) potential of the selected sub-cell array is 0 V when the memory cell is written or read, and is set to the same potential as the bit line to reduce unnecessary power consumption when erasing. When the sub-cell array is in an idle state, the bit line (BL) and source line (SL) potentials are floating and do not need to be biased.

[0104] Specific examples of potentials corresponding to Figure 27 are shown in Figures 28(A) and 28(B). The meanings of the items "selected," "unselected," "write," "erase," "read," and "idle" in the table are the same as in Figure 27. The valence indicates the voltage value and is measured in volts (V). FIG. 28A shows a case where it is assumed that one transistor constituting a memory cell is an NMOS transistor, and the following operating method is assumed. Writing is performed by passing current from the bit line (BL) to the source line (SL) at 0V, causing impact ionization using the word line (WL) potential, accumulating the generated holes in the floating body, and discharging the generated electrons to the bit line. Erasing is performed by applying a bias condition that causes the PN junction formed by the diffusion layer connecting the floating body to the bit line or source line to be forward-biased, thereby discharging the holes accumulated in the floating body to the bit line or source line.

[0105] The potential of the floating body varies depending on the number of holes stored in the floating body, and even if the same potential is biased to the word line, the current flowing from the bit line to the source line will differ. This is how the data in the memory cell is determined to be "1" or "0." In the idle state, the word line potential is biased so that the PN junction formed by the diffusion layer connecting the floating body and the bit line or source line is not forward biased but is slightly reverse biased so that any accumulated holes are not released.

[0106] Figure 28(B) shows an example of voltage conditions when one of the transistors constituting the memory cell is an NMOS transistor, and a method is used to write "1" using the BTBT (Band to Band Tunneling) phenomenon (sometimes called the GIDL (Gate Induced Drain Leakage) phenomenon) rather than the impact ionization phenomenon, and to accumulate a group of holes in the floating body, which is the storage node.

[0107] Operation waveform diagrams showing the features of the first embodiment are shown in FIGS. In the waveform diagrams of FIGS. 5 to 17, the burst length is set to 8 (BL8). Figure 5 shows an operational waveform diagram of a series of sequences in which an ACT command is issued to activate the memory cell(s) at the bank address and row address specified by ADr, an RD command is issued to read the memory cell(s) at the bank address and column address specified by ADc, and a PRE command is issued to transition the active memory cell(s) at the bank address and row address specified by ADr to an idle state.

[0108] The operational waveforms shown in FIG. 5 can be compared with the state transition diagram shown in FIG. 3 as follows: 5, an ACT command is input from an external device of the SDRAM at time T01 shown in the operation waveform diagram of FIG. 5, thereby transitioning from the idle state indicated by 030 in the state transition diagram of FIG. 3 to the activated state indicated by 031 in the state transition diagram of FIG. 3, and transitioning to the active state indicated by 032 in the state transition diagram of FIG. 3 by an automatic sequence without a command, and transitioning to the read state indicated by 033 in the state transition diagram of FIG. 3 by reception of an RD command input from an external device of the SDRAM at time T04 shown in the operation waveform diagram of FIG. 5, and transitioning to the precharge state indicated by 037 in the state transition diagram of FIG. 3 by reception of a PRE command input from an external device of the SDRAM at time T07 shown in the operation waveform diagram of FIG. 5, and transitioning to the idle state indicated by 030 in the state transition diagram of FIG. 3 by an automatic sequence without a command, and then transitioning to the ACT command input from an external device of the SDRAM at time T08 shown in the operation waveform diagram of FIG. 5.

[0109] The operation waveforms shown in FIG. 5 are compared with the state transition diagram of the first embodiment shown in FIG. 4 as follows. In the state transition diagram shown in FIG. 4, from the idle state indicated by 040, by receiving an ACT command input from an external device of the SDRAM at time T01 shown in the operation waveform diagram of FIG. 5 and an address signal ADr input from an external device of the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the activated state indicated by 041 in the state transition diagram of FIG. 4, and by an automatic sequence without a command, transition to the active state indicated by 042 in the state transition diagram of FIG. 4, and transition to the active state indicated by 043 in the state transition diagram of FIG. 5, by receiving an address signal ADr input from an external device of the SDRAM at time T04 shown in the operation waveform diagram of FIG. 4, by accepting the RD command, the state transitions to the read state indicated by 043 in the state transition diagram shown in FIG. 4, and further, by accepting a PRE command input from a device external to the SDRAM at time T07 shown in the operation waveform diagram of FIG. 5 and an address signal ADr input from a device external to the SDRAM in synchronization with the PRE command, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 045 in the state transition diagram shown in FIG. 4, and further, by an automatic sequence without a command, transitions to the idle state indicated by 040 in the state transition diagram shown in FIG. 4. At time T08 shown in the operational waveform diagram of FIG. 5, an ACT command input from a device external to the SDRAM is accepted. However, the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T08 shown in the operational waveform diagram of FIG. 5 is ADp, which is different from ADr. Therefore, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of FIG. 4. This is the sequence.

[0110] Furthermore, the operating waveforms of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment shown in FIG. 5 will be explained in comparison with the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When an ACT command input from an external device to the SDRAM is received at time T01 shown in the operation waveform diagram of Fig. 5, the state transition diagram of Fig. 3 transitions from the idle state indicated by 030 to the activated state indicated by 031. In the state transition diagram of Fig. 4, the state transition diagram of Fig. 4 transitions from the idle state indicated by 040 to the activated state indicated by 041. In synchronization with the timing of receiving the ACT command, an address signal input from a device external to the SDRAM is received at time T01 shown in the operational waveform diagram of FIG. 5. In the operational waveform diagram of FIG. 5, this signal is designated ADr. The address signal from the device external to the SDRAM is discriminated by the address receiver and address decoder denoted by 112 in FIG. 1, and the word line (WL) of the designated bank address and row address is biased from potential VIWL to potential VRWL at time T02 by the global word line selected and driven by the row decoder and global word line driver denoted by 130 in FIG. 2, and further by the global word line and local word line driver denoted by 134 in FIG. 2. The potentials of the word lines (WL)(s) of the addresses not designated by ADr and the word lines (WL)(s) of the sub-cell array(s) remain at VIWL by the global word line driven in a non-selected state by the row decoder and global word line driver denoted by 130 in FIG. 2, and further by the global word line and local word line driver denoted by 134 in FIG. 2.

[0111] The source line (SL) (group) of the sub-cell array designated by the ADr is biased from the floating state to 0V at time T02. The bit line (BL) (group) of the sub-cell array specified by ADr is biased from a floating state to a potential VRBL at time T02, passing through 0 V. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and the converted voltage is used to discriminate the data into "1" or "0", and the data is then stored in each data register associated with each bit line (BL). That is, the data read from each memory cell specified by the ADr is written to each data register specified by the ADr corresponding to each memory cell. Therefore, the data held in the memory cell(s) specified by the ADr is copied to the data register(s) specified by the ADr.

[0112] At time T03 shown in the operation waveform diagram of Figure 5, when data storage in the data register is completed, the potential of the word line (WL) specified by the ADr is driven to VIWL, and the bit line (BL) (group) specified by the ADr of the sub-cell array begins to discharge to 0V at time T03, after which the bit line (BL) (group) becomes floating together with the source line (SL) (group) specified by the ADr. In the state transition diagram of FIG. 3, the state has been shifted to the active state indicated by 032, and in the state transition diagram of FIG. The potentials of the word lines, bit lines, and source lines continue to be held until time T04 shown in the waveform diagram of Figure 5. Therefore, the floating body state of each memory cell specified by ADr is maintained. Meanwhile, the data register(s) specified by ADr hold the same data as that held by the memory cell(s) specified by ADr.

[0113] After tRCD (ACT Command to internal read or write delay time) has elapsed since the ACT command was input, at time T04 shown in the operation waveform diagram of Figure 5, when the RD command input from a device external to the SDRAM is received, the address signal input in synchronization with the RD command, the bank address specified by ADc, and the data of the memory cell(s) at the column address are read out to a device external to the SDRAM. In the state transition diagram of Fig. 3, this is the read state indicated by 033, and in the state transition diagram of Fig. 4, it transitions to the read state indicated by 043. After CL (Column Latency) has elapsed since the RD command was accepted at time T04 shown in the operation waveform diagram of Fig. 5, data output starts at time T05 shown in the operation waveform diagram of Fig. 5. Since the BL8 setting is used, data is output eight times. In essence, among the data register(s) specified by ADr that hold the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADc and BL8 is read out to a device external to the SDRAM. Among the data register(s) specified by ADr, the data register(s) other than the data register(s) specified by ADc and BL8 are in a data holding state. 5, from time T04 to time T07, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintains a floating state. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained.

[0114] After the RD command is input, the PRE command can be input at time T07, which is the time tRTP (Internal READ Command to PRECHARGE Command delay). When the SDRAM according to the first embodiment receives a PRE command input from an external device at time T07 shown in the waveform diagram of Fig. 5, it receives an address signal ADr input from an external device in synchronization with the PRE command, and the sub-cell array specified by the address signal ADr enters an idle state. From time T07 to time T08 shown in the waveform diagram of Fig. 5, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain a floating state. In the state transition diagram of Figure 3, the state has shifted to the precharge state indicated by 037, and in the state transition diagram of Figure 4, the state has shifted to the precharge state indicated by 045. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Thereafter, by an automatic sequence without a command, the state transitions from the precharge state indicated by 037 to the idle state indicated by 030 in the state transition diagram of Fig. 3, and from the precharge state indicated by 045 to the idle state indicated by 040 in the state transition diagram of Fig. 4. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is maintained in the reset state.

[0115] At time T08 shown in the operational waveform diagram of FIG. 5, an ACT command is received from a device external to the SDRAM. However, since the address signal received at time T08 shown in the operational waveform diagram of FIG. 5 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of FIG. 4. Therefore, until the ACT command and ADp are received as an address signal synchronized with the ACT command, even after time T08 shown in the operation waveform diagram of Figure 5, the potential of each word line (WL) remains at VIWL, and each bit line (BL) and each source line (SL) remains in a floating state. However, the SDRAM transitions from the idle state 030 to the activated state 031 shown in the state transition diagram of FIG.

[0116] Figure 6 shows the operational waveform diagram of a series of sequences in which an ACT command is issued to activate the memory cell(s) at the bank address and row address specified by ADr, an RDA command is issued to read the memory cell(s) at the bank address and column address specified by ADc, and then an automatic sequence without a command transitions the active memory cell(s) at the bank address and row address specified by ADr to the idle state.

[0117] The operational waveforms shown in FIG. 6 can be compared with the state transition diagram shown in FIG. 3 as follows: In the state transition diagram shown in Fig. 3, upon receiving an ACT command input from an external device of the SDRAM at time T01 shown in the operation waveform diagram of Fig. 6, the SDRAM transitions from the idle state indicated by 030 in the state transition diagram shown in Fig. 3 to the activated state indicated by 031 in the state transition diagram, and then transitions to the active state indicated by 032 in the state transition diagram of Fig. 3 by an automatic sequence without a command, and transitions to the read state indicated by 035 in the state transition diagram of Fig. 3 by receiving an RDA command input from an external device of the SDRAM at time T04 shown in the operation waveform diagram of Fig. 6. After a predetermined time has elapsed since the reception of the RDA command, the SDRAM transitions to the precharge state indicated by 037 in the state transition diagram of Fig. 3 by an automatic sequence without a command, and then transitions to the idle state indicated by 030 in the state transition diagram of Fig. 3 by an automatic sequence without a command, and then transitions to the ACT command input from an external device of the SDRAM at time T08 shown in the operation waveform diagram of Fig. 6.

[0118] The operation waveforms shown in FIG. 6 can be compared with the state transition diagram of the first embodiment shown in FIG. 4 as follows. In the state transition diagram shown in FIG. 4, the memory cell(s) and data register(s) specified by ADr transition from the idle state indicated by 040 to the activated state indicated by 041 in the state transition diagram of FIG. 4 by receiving an ACT command input from a device external to the SDRAM at time T01 shown in the operation waveform diagram of FIG. 6 and an address signal ADr input from a device external to the SDRAM in synchronization with the ACT command. The memory cell(s) and data register(s) specified by ADr transition to the active state indicated by 042 in the state transition diagram of FIG. 4 by an automatic sequence without a command. The memory cell(s) and data register(s) transition to the read state indicated by 044 in the state transition diagram of FIG. 4 by receiving an RDA command input from a device external to the SDRAM at time T04 shown in the operation waveform diagram of FIG. 6. After a predetermined time has elapsed, by an automatic sequence without a command, at time T04 shown in the operation waveform diagram of Fig. 6, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state shown by 045 in the state transition diagram of Fig. 4, and by an automatic sequence without a command, transition to the idle state shown by 040 in the state transition diagram of Fig. 4. At time T08 shown in the operation waveform diagram of Fig. 6, an ACT command input from a device external to the SDRAM is accepted, but the address signal input in synchronization with the ACT command from the device external to the SDRAM at time T08 shown in the operation waveform diagram of Fig. 6 is ADp, which is different from ADr, so the memory cell(s) and data register(s) specified by ADr remain in the idle state shown by 040 in the state transition diagram of Fig. 4. This is the sequence.

[0119] Furthermore, the operating waveforms of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment shown in FIG. 6 will be explained in comparison with the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When an ACT command input from an external device to the SDRAM is received at time T01 shown in the operation waveform diagram of Figure 6, the state transition diagram of Figure 3 transitions from the idle state indicated by 030 to the activated state indicated by 031. In the state transition diagram of Figure 4, the state transition diagram of Figure 4 transitions from the idle state indicated by 040 to the activated state indicated by 041. In synchronization with the timing of receiving the ACT command, an address signal input from a device external to the SDRAM is received at time T01 shown in the operational waveform diagram of FIG. 6. In the operational waveform diagram of FIG. 6, this signal is designated ADr. The address signal from the device external to the SDRAM is discriminated by the address receiver and address decoder denoted by 112 in FIG. 1, and the word line (WL) of the designated bank address and row address is biased from potential VIWL to potential VRWL at time T02 by the global word line selected and driven by the row decoder and global word line driver denoted by 130 in FIG. 2, and further by the global word line and local word line driver denoted by 134 in FIG. 2. The potentials of the word lines (WL)(s) of the addresses not designated by ADr and the word lines (WL)(s) of the sub-cell array(s) remain at VIWL by the global word line driven in a non-selected state by the row decoder and global word line driver denoted by 130 in FIG. 2, and further by the global word line and local word line driver denoted by 134 in FIG. 2.

[0120] The source line (SL) (group) of the sub-cell array designated by the ADr is biased from the floating state to 0V at time T02 shown in the operation waveform diagram of FIG. The bit line (BL) (group) of the sub-cell array specified by the ADr goes from a floating state to 0V, and then is biased to the potential VRBL at time T02 shown in the operation waveform diagram of Fig. 6. The current flowing through each bit line (BL) via each memory cell is converted to a voltage by each BL sense amplifier connected to each bit line (BL), and the converted voltage is used to discriminate the data into "1" or "0", and then, while discriminating, the data is stored in each data register associated with each bit line (BL). That is, the data read from each memory cell specified by the ADr is written to each data register specified by the ADr corresponding to each memory cell. Therefore, the data held in the memory cell(s) specified by the ADr is copied to the data register(s) specified by the ADr.

[0121] At time T03 shown in the operation waveform diagram of Figure 6, when data storage in the data register is completed, the potential of the word line (WL) specified by the ADr is driven to VIWL, and the bit line (BL) (group) of the sub-cell array specified by the ADr begins to discharge to 0V, and then the bit line (BL) (group) becomes floating together with the source line (SL) (group) specified by the ADr. In the state transition diagram of FIG. 3, the state has been shifted to the active state indicated by 032, and in the state transition diagram of FIG. The potentials of the word lines, bit lines, and source lines continue to be held until time T04 shown in the waveform diagram of Figure 6. Therefore, the floating body state of each memory cell specified by ADr is maintained. Meanwhile, the data register(s) specified by ADr hold the same data as that held by the memory cell(s) specified by ADr.

[0122] After tRCD (ACT Command to internal read or write delay time) has elapsed since the ACT command was issued, at time T04 shown in the operation waveform diagram of Figure 6, when the RDA command is issued from a device external to the SDRAM, the address signal input in synchronization with the RDA command, the bank address specified by ADc, and the data of the memory cell(s) at the column address are read out to a device external to the SDRAM. In the state transition diagram of Figure 3, the read state is indicated by 035, and in comparison with the state transition diagram of Figure 4, the read state is indicated by 044. After CL (Column Latency) has elapsed since the RDA command was accepted at time T04 shown in the operation waveform diagram of Figure 6, data output begins at time T05 shown in the operation waveform diagram of Figure 6. Since the BL8 setting is used, data is output eight times. In essence, among the data register(s) specified by ADr that hold the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADc and BL8 is read out to a device external to the SDRAM. Among the data register(s) specified by ADr, the data register(s) other than the data register(s) specified by ADc and BL8 are in a data holding state. 6, from time T04 to time T07, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintains a floating state. Therefore, the state of the floating body of each memory cell specified by the ADr is maintained.

[0123] After the RDA command is received and tRTP (Internal READ Command to PRECHARGE Command delay) has elapsed, at time T07 shown in the waveform diagram of Fig. 6, the sub-cell array specified by ADr enters the idle state due to an automatic sequence within the SDRAM. From time T07 to time T08 shown in the waveform diagram of Fig. 6, the potential of each word line (WL) is VIWL, and each bit line (BL) and each source line (SL) maintain a floating state. In the state transition diagram, the state has shifted to the precharge state 037 in FIG. 3 and to the precharge state 045 in FIG. 4. The floating body state of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Thereafter, by an automatic sequence without a command, the state transitions from the precharge state indicated by 037 to the idle state indicated by 030 in the state transition diagram of Fig. 3, and from the precharge state indicated by 045 to the idle state indicated by 040 in the state transition diagram of Fig. 4. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is maintained in the reset state.

[0124] At time T08 shown in the operational waveform diagram of FIG. 6, an ACT command is received from a device external to the SDRAM. However, since the address signal received at time T08 shown in the operational waveform diagram of FIG. 6 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of FIG. 4. Therefore, until the ACT command and ADp are received as an address signal synchronized with the ACT command, even after time T08 shown in the operation waveform diagram of Figure 6, the potential of each word line (WL) remains at VIWL, and each bit line (BL) and each source line (SL) remains in a floating state. However, the SDRAM transitions from the idle state 030 to the activated state 031 shown in the state transition diagram of FIG.

[0125] Figure 7 shows an operational waveform diagram of a series of sequences in which an ACT command is issued to activate the memory cell(s) at the bank address and row address specified by ADr, a WR command is issued to write to the memory cell(s) at the bank address and column address specified by ADc, and a PRE command is issued to transition the active memory cell(s) at the bank address and row address specified by ADr to an idle state.

[0126] The operational waveforms shown in FIG. 7 can be compared with the state transition diagram shown in FIG. 3 as follows: In the state transition diagram shown in Fig. 3, the SDRAM transitions from the idle state indicated by 030 in the state transition diagram to the activated state indicated by 031 in the state transition diagram shown in Fig. 3 by receiving an ACT command input from an external device at time T11 in the operation waveform diagram shown in Fig. 7, and transitions to the active state indicated by 032 in the state transition diagram shown in Fig. 3 by an automatic sequence without a command. In the state transition diagram shown in Fig. 3, the SDRAM transitions to the write state indicated by 034 in the state transition diagram shown in Fig. 3 by receiving a WR command input from an external device at time T14 in the operation waveform diagram shown in Fig. 7. Furthermore, in the state transition diagram shown in Fig. 3, the SDRAM transitions to the precharge state indicated by 037 in the state transition diagram shown in Fig. 3 by receiving a PRE command input from an external device at time T19 in the operation waveform diagram shown in Fig. 7, and transitions to the idle state indicated by 030 in the state transition diagram shown in Fig. 3 by an automatic sequence without a command. In addition, in the operation waveform diagram shown in Fig. 7, the SDRAM transitions to the ACT command input from an external device at time T22 in the operation waveform diagram shown in Fig. 7.

[0127] The operation waveforms shown in FIG. 7 are compared with the state transition diagram of the first embodiment shown in FIG. 4 as follows. 7, an ACT command is input from an external device of the SDRAM at time T11 shown in the operation waveform diagram of FIG. 7, and upon receiving an address signal ADr input from an external device of the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition from the idle state indicated by 040 in the state transition diagram of FIG. 4 to the activated state indicated by 041 in the state transition diagram of FIG. 4, and transitions to the active state indicated by 042 in the state transition diagram of FIG. 4 by an automatic sequence without a command. Upon receiving a WR command input from an external device of the SDRAM at time T14 shown in the operation waveform diagram of FIG. 7, the memory cell(s) and data register(s) transition to the write state indicated by 046 in the state transition diagram of FIG. 4, and transitions to the active state indicated by 047 in the state transition diagram of FIG. 4 by an automatic sequence without a command. By receiving a PRE command input from a device external to the SDRAM at time T19 shown in the operation waveform diagram of Fig. 7 and an address signal ADr input from a device external to the SDRAM in synchronization with the PRE command, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram of Fig. 4, and then by an automatic sequence without a command, transition to the idle state indicated by 040 in the state transition diagram of Fig. 4 via the precharge state indicated by 045 in the state transition diagram of Fig. 4. An ACT command input from a device external to the SDRAM is received at time T22 shown in the operation waveform diagram of Fig. 7, but the address signal input from a device external to the SDRAM in synchronization with the ACT command at time T22 shown in the operation waveform diagram of Fig. 7 is ADp, which is different from ADr, so the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of Fig. 4.

[0128] Furthermore, the operating waveforms of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment shown in FIG. 7 will be explained in comparison with the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When an ACT command input from an external device to the SDRAM is received at time T11 shown in the operation waveform diagram of Figure 7, the state transition diagram of Figure 3 transitions from the idle state indicated by 030 to the activated state indicated by 031. In the state transition diagram of Figure 4, the state transition diagram of Figure 4 transitions from the idle state indicated by 040 to the activated state indicated by 041.

[0129] In synchronization with the timing of receiving the ACT command, an address signal is received as an input signal from a device external to the SDRAM at time T11 shown in the operational waveform diagram of Fig. 7. In the operational waveform diagram of Fig. 7, this is indicated by ADr. The address signal from the device external to the SDRAM is discriminated by the address receiver and address decoder shown as 112 in Fig. 1, and the word line (WL) of the specified bank address and row address is biased from potential VIWL to potential VRWL at time T12 shown in the operational waveform diagram of Fig. 7 by the global word line selected and driven by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and the local word line driver shown as 134 in Fig. 2. The potential of the word line (WL)(s) of the address not specified by the ADr and the word line (WL)(s) of the sub-cell array(s) remains at VIWL by the row decoder shown as 130 in FIG. 2 and the global word line driven in the unselected state by the global word line driver, and further by the global word line and the local word line driver shown as 134 in FIG. 2.

[0130] The source line (SL) (group) of the sub-cell array designated by the ADr is biased from the floating state to 0V at time T12 shown in the operation waveform diagram of FIG. The bit line (BL) (group) of the sub-cell array specified by the ADr is biased from a floating state to 0V, and then to the potential VRBL at time T12 shown in the operation waveform diagram of Fig. 7. The current flowing through each bit line (BL) via each memory cell is converted to a voltage by each BL sense amplifier connected to each bit line (BL), and the converted voltage is used to discriminate the data into "1" or "0", and then, while discriminating, the data is stored in each data register associated with each bit line (BL). That is, the data read from each memory cell specified by the ADr is written to each data register specified by the ADr corresponding to each memory cell. Therefore, the data held in the memory cell(s) specified by the ADr is copied to the data register(s) specified by the ADr.

[0131] 7, when data storage in the data register is completed, the potential of the word line (WL) specified by the ADr is driven to the potential VIWL, the bit line (BL)(s) of the sub-cell array specified by the ADr starts to discharge to 0 V, and then the bit line (BL)(s) and the source line (SL)(s) specified by the ADr go into a floating state. This results in a transition to the active state indicated by 032 in the state transition diagram of FIG. 3, and to the active state indicated by 042 in the state transition diagram of FIG. 4. The states of the potentials of the word lines, bit lines, and source lines continue until time T15 shown in the waveform diagram of Figure 7. Therefore, the floating body state of each memory cell specified by ADr is maintained. Meanwhile, the data register(s) specified by ADr hold the same data as the data held by the memory cell(s) specified by ADr.

[0132] After tRCD (ACT Command to internal read or write delay time) has elapsed since the ACT command was received, at time T14 shown in the operation waveform diagram of Figure 7, when the first WR command is received from a device external to the SDRAM after the ACT command was received, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr, which are input in synchronization with the ACT command. This results in a transition to the write state shown as 034 in the state transition diagram of Figure 3 and the write state shown as 046 in the state transition diagram of Figure 4.

[0133] The potential of the word line of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VEWLH by the global word line selected and driven by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VEWLL by the global word line driven to the unselected state by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2, from the time T15 also shown in the operation waveform diagram in Fig. 7. The word line(s) belonging to the subarrays whose addresses are not specified by the ADr remain at the potential VIWL due to the global word lines driven in the unselected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further due to the global word lines and the local word line driver shown as 134 in FIG. 2.

[0134] The source line(s) and bit line(s) of the sub-cell array specified by the ADr are biased from the floating state to the potential VEBL from time T15 shown in the operation waveform diagram of Figure 7. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0135] With the above potential settings, if holes are stored in the floating body of the memory cell(s) connected to the word line of the bank address and row address specified by ADr, due to the relationship between the potential of each floating body and the potential of the bit line and source line, the holes are discharged. Depending on the potential relationship, electrons may be injected. The memory cells connected to the word line of the bank address and row address specified by ADr, including memory cells that did not originally have holes stored in their floating bodies, no longer have holes stored in their floating bodies, and are considered to be erased. At this point, the data held in the memory cell(s) specified by the ADr will be erased, but the SDRAM of the first embodiment rewrites the remaining data that has been copied to the data register(s) specified by the ADr into the memory cell(s) after receiving the PRE command, so the data in the memory cell(s) will not be lost. On the other hand, among the memory cells (groups) connected to word lines of bank addresses and row addresses not specified by ADr, the memory cells (groups) belonging to the unselected sub-cell array are in an idle state, and the sub-cell array is in a selected state. The relationship between the potential of each floating body of the memory cells (groups) connected to the unselected word line (groups) and the potential of the bit line and source line is almost the same as in the idle state, so the charge of the floating body is maintained.

[0136] To complete the erase operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr start to discharge to 0V at time T16, a time set within the SDRAM device from time T15 shown in the waveform diagram of Figure 7, and then the bit line(s) (BL) and the source line(s) (SL) specified by ADr enter a floating state. The potential of the word line of the sub-cell array specified by ADr is biased from VEWLH or VEWLL to VIWL at time T16 shown in the waveform diagram of Figure 7, and the sub-cell array specified by ADr enters an idle state. The potentials of the word lines, bit lines, and source lines continue to be in the same state until time T20 shown in the waveform diagram of Fig. 7. Therefore, the state of the floating body of each memory cell specified by ADr is maintained.

[0137] Since the burst length is 8 (BL8) at time T17, which is a predetermined time (CWL; CAS Write Latency) after the WR command is received, 8 sets of data are sequentially input from the DQ signal line of FIG. 1, as shown in the operation waveform diagram of FIG. 7. The input data is sensed and amplified by the data input receiver shown in FIG. 1, and then stored in the data input register shown in FIG. 1. After storage, the data is written from the data input register shown in FIG. 1 by the IO driver shown in FIG. 1 at the address specified by ADc, which is input in synchronization with the WR command and exists in 133 of FIG. 2 associated with the sub-cell array at the address specified by ADr. The above operation in response to the WR command is the same as that of a clock-synchronized dynamic semiconductor memory device using memory cells each consisting of one transistor and one capacitor. However, in a clock synchronous dynamic semiconductor memory device using memory cells each consisting of one transistor and one capacitor, input data is written to the memory cell(s) at the address specified by the ADr, the ADc, and BL8, whereas in the clock synchronous dynamic semiconductor memory device of this embodiment, data is not written to the memory cell(s), but input data is only written to the data register(s) specified by the ADr, which are present in 133 in Fig. 2 and which are specified by the ADc and BL8. Therefore, among the data register(s) specified by the ADr, the data register(s) not specified by the ADc and BL8 hold the same data as the memory cell connectable to the same bit line (BL) specified by the ADr.

[0138] During data input, no data is written to the memory cells, so at time T16 shown in the waveform diagram of Figure 7, the potential of the selected word line begins to be biased to VIWL, and the potentials of the selected bit lines and source lines are discharged to 0V and then floating. Unselected word lines are biased to VIWL, and unselected bit lines and unselected source lines were also discharged to 0V at some previous stage and then floating. The above-mentioned states of the potentials of the word lines, bit lines, and source lines continue until time T20 shown in the waveform diagram of Figure 7.

[0139] Data is input from a device external to the SDRAM via a DQ signal line, and the input signal is sensed and amplified by a data input receiver shown in 118 of Fig. 1 and then stored in a data input register shown in 119 of Fig. 1. After storage, the process of writing data from the data input register shown in 119 of Fig. 1 to a data register specified by ADc and BL8, which exists in 133 of Fig. 2, among the data register(s) specified by ADr, is performed by an IO driver shown in 123 of Fig. 1, and the process of erasing memory cells connected to the word line of the bank address and row address specified by ADr are performed in parallel, and the operations are independent of each other. Therefore, depending on the CWL (CAS Write Latency) setting and the clock cycle, the timing of the erase operation start time and the data input start time may vary, and there is no problem if they do. The timing of the erase operation end time and the data input completion time may also vary, and there is no problem if they do. When both the write operation of the input data to the data register specified by ADr and ADc and the erase operation of the memory cell(s) connected to the word line of the bank address and row address specified by ADr are completed, an automatic sequence will cause the state to transition to the active state 032 in the state transition diagram shown in Figure 3 or to the active state 047 in the state transition diagram shown in Figure 4. Each memory cell specified by the ADr maintains its erased state. Of the data register(s) specified by the ADr, the data register(s) that are not specified by the ADc and BL8 and have not been written to retain the data that the memory cell(s) specified by the ADr held before being erased. Of the data register(s) specified by the ADr, the data register(s) that are specified by the ADc and BL8 and have been written to retain the written data.

[0140] The fact that no inconvenience occurs even if data writing to the memory cells is not completed will be described when explaining the operating waveforms of the SDRAM according to the first embodiment in FIGS.

[0141] After the data is input, the PRE command can be input at time T19 when tWR (Write Recovery Time) has elapsed. When the SDRAM according to the first embodiment receives a PRE command at time T19 shown in the operation waveform diagram of Fig. 7, it starts writing data from the data register(s) specified by the ADr to the memory cell(s) connected to the word line of the bank address and row address specified by the ADr. This results in a transition to the precharge state indicated by 037 in the state transition diagram of Fig. 3 and the precharge state indicated by 053 in the state transition diagram of Fig. 4. Since "0" data has already been written by the erase operation, the write sequence here writes "1" to the memory cell(s) corresponding to the data registers holding "1" data, and the memory cells corresponding to the data registers holding "0" data are maintained in the state where "0" data has already been written.

[0142] The potential of the word line (WL) of the bank address and row address specified by the ADr is biased from the potential VIWL to the potential VWWLH at time T20 shown in the operation waveform diagram of Figure 7 by the global word line selected and driven by the row decoder and global word line driver shown in 130 of Figure 2, and further by the global word line and local word line driver. Of the word line(s) not specified by the ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VWWLL at time T20 shown in the operation waveform diagram of Figure 7 by the global word line and local word line driver driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2. The word line(s) belonging to the sub-array of the address not specified by the ADr remain at the potential VIWL by the global word line driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2, and further by the global word line and local word line driver. The source line(s) of the sub-cell array designated by ADr are biased from the floating state to 0V at time T20 shown in the operation waveform diagram of FIG. The bit line(s) of the sub-cell array specified by ADr are biased in potential according to the data stored in the data register(s) corresponding to the bit line(s), and if the data in the data register is "0", the bit line (BL) is biased from the floating state to 0V at time T20, and if the data in the data register is "1", the bit line (BL) is biased from the floating state to potential VWBL at time T20. On the other hand, the source line(s) and bit line(s) of the sub-cell arrays not specified by the ADr remain in a floating state.

[0143] With the above potential settings, among the memory cells (group) connected to the word line of the bank address and row address specified by ADr, memory cells with VWBL biased to the bit line (BL) pass current, causing impact ionization, and the holes (group) generated by impact ionization accumulate in the floating body of the memory cell, and the electrons (group) similarly generated by impact ionization are discharged to the bit line (BL), resulting in data "1" being written to the memory cell. On the other hand, memory cells with 0V biased to the bit line (BL) do not pass current because the potentials of the bit line (BL) and source (line) are the same, and therefore impact ionization does not occur, so the floating body of the memory cell maintains the erased state, and data "0" is written. That is, data is read from each data register specified by ADr, and the read data is written to each memory cell specified by ADr corresponding to the data register. In addition to the data written by the WR command, the data lost by the erase operation is copied and saved in the data register(s). Therefore, no data is lost in the memory cells due to the erase operation.

[0144] Among the memory cells (groups) connected to word lines of bank addresses and row addresses not specified by ADr, memory cells connected to unselected word lines (groups) in the selected sub-cell array do not conduct current due to the potential relationship between the word lines and the source lines, so impact ionization does not occur and hole (groups) do not accumulate in the floating body. Furthermore, if memory cell devices are designed and manufactured appropriately, the potential relationship between the floating body of the memory cell, the bit line, and the word line will prevent the band-to-band tunneling (BTBT) phenomenon (sometimes called the gate-induced drain leakage (GIDL) phenomenon) from occurring, and hole (groups) will not accumulate in the floating body. Furthermore, the potential relationship between the word line, floating body, and bit line of the memory cell will prevent hole (groups) from being released into the bit line or source line. As a result, the charge in the floating body of each memory cell connected to an unselected word line(s) in the sub-cell array that is in the selected state is maintained among the memory cells (groups) connected to the word lines of the bank address and row address not specified by ADr.

[0145] The memory cells (group) connected to the word lines of the bank addresses and row addresses not specified by ADr are in an idle state, and therefore the floating body state of each memory cell is maintained.

[0146] To complete the write operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr are floated at time T21, a time set within the SDRAM device from time T20 shown in the waveform diagram of Figure 7. The potential of the word line of the sub-cell array specified by ADr is biased from VWWLH or VWWLL to 0V at time T21. The potentials of the word lines, bit lines, and source lines remain at the above-mentioned states until time T22 shown in the waveform diagram of Figure 7. By an automatic sequence without a command, the state transitions to the precharge state indicated by 045 in the state transition diagram of Fig. 4. In the state transition diagram of Fig. 3, the state remains in the precharge state indicated by 037. The state of the floating body of each memory cell specified by the ADr is maintained, and the data register specified by the ADr is reset. Furthermore, an automatic sequence without a command causes the device to transition to the idle state indicated by 030 in the state transition diagram of Fig. 3 and to the idle state indicated by 040 in the state transition diagram of Fig. 4. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr is maintained in the reset state.

[0147] At time T22 shown in the operational waveform diagram of FIG. 7, an ACT command is received from a device external to the SDRAM. However, since the address signal received at time T22 shown in the operational waveform diagram of FIG. 7 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of FIG. 4. Therefore, until the ACT command and ADp are received as an address signal synchronized with the ACT command, even after time T22 shown in the operation waveform diagram of Figure 7, the potential of each word line (WL) remains at VIWL, and each bit line (BL) and each source line (SL) remains in a floating state. However, the SDRAM transitions from the idle state 030 to the activated state 031 shown in the state transition diagram of FIG.

[0148] Figure 8 shows the operational waveform diagram of a series of sequences in which an ACT command is issued to activate the memory cell(s) at the bank address and row address specified by ADr, a WRA command is issued to write to the memory cell(s) at the bank address and column address specified by ADc, and then an automatic sequence without a command transitions the active memory cell(s) at the bank address and row address specified by ADr to the idle state.

[0149] The operation waveforms shown in FIG. 8 can be compared with the state transition diagram shown in FIG. 3 as follows. In the state transition diagram shown in Fig. 3, the SDRAM transitions from the idle state indicated by 030 in the state transition diagram to the activated state indicated by 031 in the state transition diagram shown in Fig. 3 by receiving an ACT command input from an external device at time T11 shown in the operation waveform diagram of Fig. 8, then transitions to the active state indicated by 032 in the state transition diagram shown in Fig. 3 by an automatic sequence without a command, and transitions to the write state indicated by 034 in the state transition diagram shown in Fig. 3 by receiving a WRA command input from an external device at time T14 shown in the operation waveform diagram of Fig. 8. After a predetermined time has elapsed since receiving data input from an external device, the SDRAM transitions to the precharge state indicated by 037 in the state transition diagram shown in Fig. 3 by an automatic sequence, and transitions to the idle state indicated by 030 in the state transition diagram shown in Fig. 3 by an automatic sequence without a command. This is the sequence in which the SDRAM receives an ACT command input from an external device at time T22 shown in the operation waveform diagram of Fig. 8.

[0150] The operation waveforms shown in FIG. 8 can be compared with the state transition diagram of the first embodiment shown in FIG. 4 as follows. From the idle state indicated by 040 in the state transition diagram shown in FIG. 4, by receiving an ACT command input from a device external to the SDRAM at time T11 shown in the operation waveform diagram of FIG. 8 and an address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the activated state indicated by 041 in the state transition diagram shown in FIG. 4, transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command, and transition to the write state indicated by 050 in the state transition diagram shown in FIG. 4 by receiving a WRA command input from a device external to the SDRAM at time T14 shown in the operation waveform diagram of FIG. 8. After a predetermined time has elapsed, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in Fig. 4, and by an automatic sequence without a command, the memory cell(s) and data register(s) specified by the ADr transition to the idle state indicated by 040 in the state transition diagram shown in Fig. 4 via the precharge state indicated by 045 in the state transition diagram shown in Fig. 4. An ACT command input from a device external to the SDRAM is accepted at time T22 in the operation waveform diagram shown in Fig. 8, but the address signal input in synchronization with the ACT command from the device external to the SDRAM at time T22 in the operation waveform diagram shown in Fig. 8 is ADp, which is different from ADr, so the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram shown in Fig. 4. This is the sequence.

[0151] Furthermore, the operating waveforms of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment shown in FIG. 8 will be explained in comparison with the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When an ACT command input from an external device to the SDRAM is received at time T11 shown in the operation waveform diagram of Figure 8, the state transition diagram of Figure 3 transitions from the idle state indicated by 030 to the activated state indicated by 031. In the state transition diagram of Figure 4, the state transition diagram of Figure 4 transitions from the idle state indicated by 040 to the activated state indicated by 041.

[0152] In synchronization with the timing of receiving the ACT command, an address signal is received as an input signal from a device external to the SDRAM at time T11 shown in the operation waveform diagram of Fig. 8. In the operation waveform diagram of Fig. 8, this is indicated as ADr. The address signal from the device external to the SDRAM is discriminated by the address receiver and address decoder shown as 112 in Fig. 1, and the word line (WL) of the specified bank address and row address is biased from potential VIWL to potential VRWL at time T12 shown in the operation waveform diagram of Fig. 8 by the global word line selected and driven by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and the local word line driver shown as 134 in Fig. 2. The potential of the word line (WL)(s) of the address not specified by the ADr and the word line (WL)(s) of the sub-cell array(s) remains at VIWL by the row decoder shown as 130 in FIG. 2 and the global word line driven in the unselected state by the global word line driver, and further by the global word line and the local word line driver shown as 134 in FIG. 2.

[0153] The source line (SL) (group) of the sub-cell array designated by the ADr is biased from the floating state to 0V at time T12 shown in the operation waveform diagram of FIG. The bit line (BL) (group) of the sub-cell array specified by the ADr goes from a floating state to 0V, and then is biased to the potential VRBL at time T12 shown in the operation waveform diagram of Fig. 8. The current flowing through each bit line (BL) via each memory cell is converted to a voltage by each BL sense amplifier connected to each bit line (BL), and the converted voltage is used to discriminate the data into "1" or "0", and then, while discriminating, the data is stored in each data register associated with each bit line (BL). That is, the data read from each memory cell specified by the ADr is written to each data register specified by the ADr corresponding to each memory cell. Therefore, the data held in the memory cell(s) specified by the ADr is copied to the data register(s) specified by the ADr.

[0154] 8, when data storage in the data register is completed, the potential of the word line (WL) specified by the ADr is driven to the potential VIWL, the bit line (BL)(s) of the sub-cell array specified by the ADr starts to discharge to 0 V, and then the bit line (BL)(s) enters a floating state together with the source line (SL)(s) specified by the ADr. This results in a transition to the active state indicated by 032 in the state transition diagram of FIG. 3, and to the active state indicated by 042 in the state transition diagram of FIG. 4. The potentials of the word lines, bit lines, and source lines continue to be maintained until time T15 shown in the waveform diagram of Figure 8. Therefore, the floating body state of each memory cell specified by ADr is maintained. Meanwhile, the data register(s) specified by ADr hold the same data as that held by the memory cell(s) specified by ADr.

[0155] After tRCD (ACT Command to internal read or write delay time) has elapsed since the ACT command was received, at time T14 shown in the operation waveform diagram of Figure 8, if a WRA command is received from an external device of the SDRAM without receiving a single WR command since the ACT command was received, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr input in synchronization with the ACT command. In comparison with the state transition diagram, the state has transitioned to write state 036 in the state transition diagram shown in Figure 3, and to write state 050 in the state transition diagram shown in Figure 4.

[0156] The potential of the word line of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VEWLH by the global word line selected and driven by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VEWLL by the global word line driven to the unselected state by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2, from the time T15 also shown in the operation waveform diagram in Fig. 8. The word line(s) belonging to the subarrays whose addresses are not specified by the ADr remain at the potential VIWL due to the global word lines driven in the unselected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further due to the global word lines and the local word line driver shown as 134 in FIG. 2.

[0157] The source line(s) and bit line(s) of the sub-cell array specified by the ADr are biased from the floating state to the potential VEBL from time T15 shown in the operation waveform diagram of Figure 8. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0158] By setting the potentials as described above, as described in the explanation of the operating waveform diagram in Figure 7 for the SDRAM of the first embodiment, the memory cell(s) connected to the word line of the bank address and row address specified by ADr are erased. At this point, the data held in the memory cell(s) specified by the ADr will be erased, but after the SDRAM of the first embodiment transitions to state 053 shown in the state transition diagram of Figure 4, it rewrites the data that has been copied to the data register(s) specified by the ADr and remains in the memory cell(s), so no data loss occurs in the memory cell(s). On the other hand, among the memory cells (groups) connected to word lines of bank addresses and row addresses not specified by ADr, the memory cells (groups) belonging to the unselected sub-cell array are in an idle state, and the sub-cell array is in a selected state. The relationship between the potential of each floating body of the memory cells (groups) connected to the unselected word line (groups) and the potential of the bit line and source line is almost the same as in the idle state, so the charge of the floating body is maintained.

[0159] To complete the erase operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr start discharging to 0V at time T16, a time set within the SDRAM device from time T15 shown in the waveform diagram of Figure 8, and then enter a floating state. The potential of the word line of the sub-cell array specified by ADr is biased from VEWLH or VEWLL to VIWL at time T16 shown in the waveform diagram of Figure 8, and the sub-cell array specified by ADr enters an idle state. The potentials of the word lines, bit lines, and source lines continue to be in the same state until time T20 shown in the waveform diagram of Fig. 7. Therefore, the state of the floating body of each memory cell specified by ADr is maintained.

[0160] Since the burst length is 8 (BL8) from time T17, which is a predetermined time (CWL; CAS Write Latency) after the WRA command is received, 8 sets of data are sequentially input from the DQ signal line of FIG. 1, as shown in the operation waveform diagram of FIG. 8. The input data is sensed and amplified by the data input receiver shown in 118 of FIG. 1 and then stored in the data input register shown in 119 of FIG. 1. After storage, the data is written from the data input register shown in 119 of FIG. 1 to the data register specified by the ADc and BL8, which exists in 133 of FIG. 2, by the IO driver shown in 123 of FIG. 1, among the data register(s) specified by the ADr. Meanwhile, among the data register(s) specified by the ADr, the data registers that are not specified by the ADc and BL8 hold the same data as the memory cells that can be connected to the same bit line (BL) specified by the ADr.

[0161] During data input, no writing to the memory cells is performed, so at time T16 shown in the waveform diagram of Figure 8, the potential of the selected word line begins to be biased to VIWL, and the potentials of the selected bit lines and source lines are discharged to 0V and then floating. Unselected word lines are biased to VIWL, and unselected bit lines and unselected source lines are also discharged to 0V at some previous stage and then floating. The above-mentioned states of the potentials of the word lines, bit lines, and source lines continue until time T20 shown in the waveform diagram of Figure 8.

[0162] As described in the explanation of the operational waveforms in Figure 7, the operation of writing input data to the data register in the area indicated by 133 in Figure 2, which is specified by ADc and BL8 among the data register(s) specified by ADr, and the erase operation of the memory cell(s) connected to the word line of the bank address and row address specified by ADr are performed in parallel and independently. Therefore, depending on the CWL (CAS Write Latency) setting value and the clock period, the timing of the erase operation start time and the data input start time may vary, and there is no problem if they do. The timing of the erase operation end time and the data input completion time may also vary, and there is no problem if they do. When both the write operation of the input data to the data register specified by ADr and ADc and the erase operation of the memory cell(s) connected to the word line of the bank address and row address specified by ADr are completed, an automatic sequence will transition to the active state 032 in the state transition diagram shown in Figure 3 or the active state 047 in the state transition diagram shown in Figure 4. Each memory cell specified by the ADr maintains its erased state. Of the data register(s) specified by the ADr, the data register(s) that are not specified by the ADc and BL8 and that have not been written to retain the data that the memory cell(s) specified by the ADr held before being erased. Of the data register(s) specified by the ADr, the data register(s) that are specified by the ADc and BL8 and that have been written to retain the written data.

[0163] The fact that no inconvenience occurs even if data writing to the memory cells is not completed will be described when explaining the operating waveforms of the SDRAM according to the first embodiment in FIGS.

[0164] After the data input is complete, at time T19 after tWR (Write Recovery Time) has elapsed, an automatic sequence follows the SDRAM specifications to transition to the precharge state indicated by 037 in the state transition diagram of Fig. 3, even without inputting a PRE command. The SDRAM according to the first embodiment transitions the memory cell(s) and data register(s) specified by the ADr to the precharge state indicated by 053 in Fig. 4. That is, at time T19 shown in the operation waveform diagram of Fig. 8, it starts writing the data in the data register(s) specified by the ADr to the memory cell(s) connected to the word line of the bank address and row address specified by the ADr. Since "0" data has already been written by the erase operation, the write sequence here writes "1" to the memory cell(s) corresponding to the data registers holding "1" data, and maintains the state in which "0" data is already written to the memory cells corresponding to the data registers holding "0" data.

[0165] The potential of the word line (WL) of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VWWLH at time T20 shown in the operation waveform diagram of Figure 8 by the global word line selected and driven by the row decoder and global word line driver shown in 130 of Figure 2, and further by the global word line and local word line driver. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VWWLL at time T20 shown in the operation waveform diagram of Figure 8 by the global word line and local word line driver driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2. The word line(s) belonging to the sub-array of the address not specified by ADr remain at the potential VIWL by the global word line driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2, and further by the global word line and local word line driver. The source line(s) of the sub-cell array designated by ADr are biased from the floating state to 0V at time T20 shown in the operation waveform diagram of FIG. The bit line(s) of the sub-cell array specified by ADr are biased in potential according to the data stored in the data register(s) corresponding to the bit line(s). If the data in the data register is "0", the bit line (BL) is biased from the floating state to 0V at time T20, and if the data in the data register is "1", the bit line (BL) is biased from the floating state to potential VWBL at time T20. On the other hand, the source line(s) and bit line(s) of the sub-cell arrays not specified by the ADr remain in a floating state.

[0166] As a result of the above potential settings, as described in the explanation of the operating waveform diagram of Figure 7 for the SDRAM of the first embodiment, among the memory cells (group) connected to the word line of the bank address and row address specified by ADr, data "1" is written to the memory cells (group) whose bit line (BL) is biased with VWBL, while in the memory cells (group) whose bit line (BL) is biased with 0V, the floating body of each memory cell remains in the erased state and data "0" is written to them. That is, data is read from each data register specified by ADr, and the read data is written to each memory cell specified by ADr corresponding to the data register. In addition to the data written by the WR command or WRA command, the data lost by the erase operation is copied and saved in the data register(s). Therefore, no data is lost in the memory cells due to the erase operation. The memory cells (group) connected to the word lines of the bank addresses and row addresses not specified by ADr are in an idle state, and therefore the floating body state of each memory cell is maintained.

[0167] To complete the write operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr are floated at time T21, a time set within the SDRAM device from time T20 shown in the waveform diagram of Figure 8. The potential of the word line of the sub-cell array specified by ADr is biased from VWWLH or VWWLL to 0V at time T21. The potentials of the word lines, bit lines, and source lines remain at the above-mentioned states until time T22 shown in the waveform diagram of Figure 8. By an automatic sequence without a command, the state transitions to the precharge state indicated by 045 in the state transition diagram of Fig. 4. In the state transition diagram of Fig. 3, the state remains in the precharge state indicated by 037. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Furthermore, an automatic sequence without a command causes the device to transition to the idle state indicated by 030 in the state transition diagram of Fig. 3 and to the idle state indicated by 040 in the state transition diagram of Fig. 4. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr is maintained in the reset state.

[0168] At time T22 shown in the operational waveform diagram of FIG. 8, an ACT command is received from a device external to the SDRAM. However, since the address signal received at time T22 shown in the operational waveform diagram of FIG. 8 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of FIG. 4. Therefore, until the ACT command and ADp are received as an address signal synchronized with the ACT command, even after time T22 shown in the operation waveform diagram of Figure 8, the potential of each word line (WL) remains at VIWL, and each bit line (BL) and each source line (SL) remains in a floating state. However, the SDRAM transitions from the idle state 030 to the activated state 031 shown in the state transition diagram of FIG.

[0169] Figure 9 shows an operational waveform diagram of a series of sequences in which an ACT command is issued to activate the memory cell(s) at the bank address and row address specified by ADr, data is written to the memory cell(s) at the bank address and column address specified by ADc, data is then read from the memory cell(s) at the address specified by ADd, which has the same bank address as ADc but a different column address, and a PRE command is issued to transition the memory cell(s) at the bank address and row address specified by ADr, which are in the active state, to the idle state. The operational waveform diagram shown in Figure 10 differs from the operational waveform diagram shown in Figure 9 in that after writing to the memory cell(s) at the bank address and column address specified by ADc, reading is performed from the memory cell(s) at the bank address and column address specified by the same ADc. The only difference between the operational waveform diagram shown in FIG. 9 and the operational waveform diagram shown in FIG. 10 is that the column address input in synchronization with the WR command and the column address input in synchronization with the RD command are different (FIG. 9) or the same (FIG. 10). Therefore, the operational waveform diagram shown in FIG. 9 and the operational waveform diagram shown in FIG. 10 will be explained together.

[0170] The operational waveforms shown in FIGS. 9 and 10 can be compared with the state transition diagram shown in FIG. 3 as follows: In the state transition diagram shown in FIG. 3, the SDRAM transitions from the idle state indicated by 030 to the activated state indicated by 031 in the state transition diagram shown in FIG. 3 by receiving an ACT command input from a device external to the SDRAM at time T31 in the operation waveform diagrams shown in FIGS. 9 and 10, and transitions to the active state indicated by 032 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. In the state transition diagram shown in FIG. 3, the SDRAM transitions to the write state indicated by 034 in the state transition diagram shown in FIG. 3 by receiving a WR command input from a device external to the SDRAM at time T34 in the operation waveform diagrams shown in FIGS. 9 and 10, and transitions to the read state indicated by 033 in the state transition diagram shown in FIG. 3. By accepting a PRE command input from a device external to the SDRAM at time T42 in the operational waveform diagrams shown in Figures 9 and 10, the SDRAM transitions to the precharge state indicated by 037 in the state transition diagram shown in Figure 3, and by an automatic sequence without a command, the SDRAM transitions to the idle state indicated by 030 in the state transition diagram shown in Figure 3. This is the sequence in which an ACT command input from a device external to the SDRAM is accepted at time T45 in the operational waveform diagrams shown in Figures 9 and 10.

[0171] The operational waveforms shown in FIGS. 9 and 10 can be compared with the state transition diagram of the first embodiment shown in FIG. 4 as follows. 9 and 10, the memory cell(s) and data register(s) designated by ADr transition from the idle state indicated by 040 in the state transition diagram shown in FIG. 4 to the activated state indicated by 041 in the state transition diagram shown in FIG. 4 by receiving an ACT command input from a device external to the SDRAM at time T31 shown in FIGS. 9 and 10 and an address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, and then transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. At time T34 shown in FIGS. 9 and 10, the memory cell(s) and data register(s) transition from the idle state indicated by 040 in the state transition diagram shown in FIG. 4 by receiving an ACT command input from a device external to the SDRAM, and then transition to the active state indicated by 047 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command. By accepting an RD command input from an external device of the SDRAM at time T39 shown in the operation waveform diagrams of Figures 9 and 10, the SDRAM transitions to the read state indicated by 048 in the state transition diagram shown in Figure 4. By accepting a PRE command input from an external device of the SDRAM at time T42 shown in the operation waveform diagrams of Figures 9 and 10, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in Figure 4, and then by an automatic sequence without a command, transitions to the idle state indicated by 040 in the state transition diagram shown in Figures 9 and 10 via the precharge state indicated by 045 in the state transition diagram shown in Figure 4. At time T45 shown in the operation waveform diagrams of Figures 9 and 10, an ACT command input from a device external to the SDRAM is accepted. However, the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T45 shown in the operation waveform diagrams of Figures 9 and 10 is ADp, which is different from ADr. Therefore, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram shown in Figure 4. This is the sequence.

[0172] Furthermore, the operating waveforms of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment shown in Figures 9 and 10 will be explained in reference to the state transition diagram shown in Figure 3 and the state transition diagram of the first embodiment shown in Figure 4. When an ACT command input from an external device to the SDRAM is received at time T31 shown in the operation waveform diagrams of Figures 9 and 10, the state transition diagram of Figure 3 transitions from the idle state indicated by 030 to the activated state indicated by 031. In the state transition diagram of Figure 4, the state transition diagram of Figure 4 transitions from the idle state indicated by 040 to the activated state indicated by 041.

[0173] In synchronization with the timing of receiving the ACT command, an address signal is received as an input signal from a device external to the SDRAM at time T31 shown in the operational waveform diagrams of Figures 9 and 10. This is indicated by ADr in the operational waveform diagrams of Figures 9 and 10. The address signal from the device external to the SDRAM is discriminated by the address receiver and address decoder shown as 112 in Figure 1, and the word line (WL) of the specified bank address and row address is biased from potential VIWL to potential VRWL at time T32 shown in the operational waveform diagrams of Figures 9 and 10 by a global word line selected and driven by a row decoder and global word line driver shown as 130 in Figure 2, and further by the global word line and a local word line driver shown as 134 in Figure 2. The potential of the word line (WL)(s) of the address not specified by the ADr and the word line (WL)(s) of the sub-cell array(s) remains at VIWL by the row decoder shown as 130 in FIG. 2 and the global word line driven in the unselected state by the global word line driver, and further by the global word line and the local word line driver shown as 134 in FIG. 2.

[0174] The source line (SL) (group) of the sub-cell array designated by the ADr is biased from the floating state to 0V at time T32 shown in the operation waveform diagrams of FIGS. The bit line (BL) (group) of the sub-cell array specified by the ADr is biased from a floating state to 0V, and then to the potential VRBL at time T32 shown in the operation waveform diagrams of Figures 9 and 10. The current flowing through each bit line (BL) via each memory cell is converted to a voltage by each BL sense amplifier connected to each bit line (BL), and the converted voltage is used to discriminate the data into "1" or "0", and then, while discriminating, the data is stored in each data register associated with each bit line (BL). That is, the data read from each memory cell specified by the ADr is written to each data register specified by the ADr corresponding to each memory cell. Therefore, the data held in the memory cell(s) specified by the ADr is copied to the data register(s) specified by the ADr.

[0175] 9 and 10, when data storage in the data register is completed, the potential of the word line (WL) specified by the ADr is driven to the potential VIWL, the bit line (BL)(s) of the sub-cell array specified by the ADr starts to discharge to 0 V, and then the bit line (BL)(s) enters a floating state together with the source line (SL)(s) specified by the ADr. This results in a transition to the active state indicated by 032 in the state transition diagram of FIG. 3 and the active state indicated by 042 in the state transition diagram of FIG. 4. The potentials of the word lines, bit lines, and source lines continue to be maintained until time T35 shown in the waveform diagrams of Figures 9 and 10. Therefore, the floating body state of each memory cell specified by ADr is maintained. Meanwhile, the data register(s) specified by ADr hold the same data as that held by the memory cell(s) specified by ADr.

[0176] After tRCD (ACT Command to internal read or write delay time) has elapsed since the ACT command was received, at time T34 shown in the operation waveform diagrams of Figures 9 and 10, when the first WR command is received from a device external to the SDRAM after the ACT command was received, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr, which are input in synchronization with the ACT command. This results in a transition to the write state shown as 034 in the state transition diagram of Figure 3 and the write state shown as 046 in the state transition diagram of Figure 4.

[0177] The potential of the word line of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VEWLH by the global word line selected and driven by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VEWLL by the global word line driven to the unselected state by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2, from the time T35 shown in the operation waveform diagrams of Fig. 9 and 10. The word line(s) belonging to the subarrays whose addresses are not specified by the ADr remain at the potential VIWL due to the global word lines driven in the unselected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further due to the global word lines and the local word line driver shown as 134 in FIG. 2.

[0178] The source line(s) and bit line(s) of the sub-cell array specified by the ADr are biased from the floating state to the potential VEBL from time T35 shown in the operation waveform diagrams of Figures 9 and 10. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0179] By setting the potentials as described above, as described in the explanation of the operating waveform diagram in Figure 7 for the SDRAM of the first embodiment, the memory cell(s) connected to the word line of the bank address and row address specified by ADr are erased. At this point, the data held in the memory cell(s) specified by the ADr will be erased, but the SDRAM of the first embodiment rewrites the remaining data that has been copied to the data register(s) specified by the ADr into the memory cell(s) after receiving the PRE command, so the data in the memory cell(s) will not be lost. On the other hand, among the memory cells (groups) connected to word lines of bank addresses and row addresses not specified by ADr, the memory cells (groups) belonging to the unselected sub-cell array are in an idle state, and the sub-cell array is in a selected state. The relationship between the potential of each floating body of the memory cells (groups) connected to the unselected word line (groups) and the potential of the bit line and source line is almost the same as in the idle state, so the charge of the floating body is maintained.

[0180] 9 and 10, after a time set within the SDRAM device has elapsed since time T35, the source line(s) and bit line(s) of the sub-cell array specified by ADr start to discharge to 0V at time T37, and thereafter the bit line(s) (BL) and the source line(s) (SL) specified by ADr enter a floating state. The potential of the word line of the sub-cell array specified by ADr changes from VEWLH or VEWLL to VIWL at time T37 shown in the operation waveform diagrams of FIGS. 9 and 10, and the sub-cell array specified by ADr enters an idle state. The potentials of the word lines, bit lines, and source lines continue to be in the same state until time T43 shown in the operation waveform diagrams of Figures 9 and 10. Therefore, the state of the floating body of each memory cell specified by ADr is maintained.

[0181] Since the burst length is 8 (BL8) from time T36, which is a predetermined time (CWL; CAS Write Latency) after the WR command is received, 8 sets of data are sequentially input from the DQ signal line of FIG. 1, as shown in the operation waveform diagrams of FIGS. 9 and 10. The input signals are sensed and amplified by the data input receiver shown in 118 of FIG. 1 and then stored in the data input register shown in 119 of FIG. 1. After storage, the data is written from the data input register shown in 119 of FIG. 1 to the data register(s) specified by the ADr, which are specified by the ADc and BL8 and exist within 133 of FIG. 2, by the IO driver shown in 123 of FIG. 1. Meanwhile, the data register(s) not specified by the ADc and BL8 among the data register(s) specified by the ADr hold the same data as the memory cell connectable to the same bit line (BL) specified by the ADr.

[0182] 7 for the SDRAM according to the first embodiment, the write operation to the data register in the area 133 in FIG. 2, which is specified by ADc and BL8 among the data register(s) specified by ADr, and the erase operation to the memory cell(s) connected to the word line of the bank address and row address specified by ADr, are performed in parallel and independently, so depending on the WL (Write Latency) setting value and the clock period, the timing of the erase operation start time and the data input start time may differ, and there is no problem if they do. The timing of the erase operation end time and the data input completion time may also differ, and there is no problem if they do. When both the write operation of the input data to the data register specified by ADr and ADc and the erase operation of the memory cell(s) connected to the word line of the bank address and row address specified by ADr are completed, an automatic sequence will cause the state to transition to the active state 032 in the state transition diagram shown in Figure 3 or to the active state 047 in the state transition diagram shown in Figure 4. The memory cell(s) specified by the ADr remain in the erased state, and the data register(s) specified by the ADr retain the data that the memory cell(s) specified by the ADr held before being erased.

[0183] Each unselected word line is biased to VIWL, and the unselected bit lines and unselected source lines are in a floating state after being discharged to 0 V at some previous stage. Therefore, the floating body state of each memory cell specified by ADr is maintained.

[0184] After the data input is complete, the RD command can be input at time T39 after tWTR (Delay from start of internal WRITE transaction to internal Read command) has elapsed. When the RD command is input at time T39 shown in the operation waveform diagrams of Figures 9 and 10, acceptance of the RD command causes a transition from the write state 034 to the read state 033 in the state transition diagram of Figure 3. In the state transition diagram of Figure 4, acceptance of the RD command causes a transition from the active state 047 to the read state 048. In the operation waveform diagram of Figure 9, in response to the RD command received from a device external to the SDRAM at time T39, the address signal input in synchronization with the RD command, the bank address specified by ADc, and the data of the memory cell(s) at the column address are read out to a device external to the SDRAM. Also, in the operation waveform diagram of Figure 10, in response to the RD command received from a device external to the SDRAM at time T39, the address signal input in synchronization with the RD command, the bank address specified by ADc, and the data of the memory cell(s) at the column address are read out to a device external to the SDRAM. Data output starts at time T40 after CL (Column Latency) has elapsed since the RD command is received at time T39 shown in the operation waveform diagrams of FIGS. 9 and 10. Since the setting is BL8, data is output eight times. 9, of the data register(s) specified by ADr that hold the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADd and BL8 is read out to a device external to the SDRAM. Of the data register(s) specified by ADr, the data register(s) other than the data register(s) specified by ADd and BL8 are in a data holding state. 10, the data of the data register(s) specified by ADr, which are designated by ADc and BL8, are read out to a device external to the SDRAM. Of the data register(s) specified by ADr, the data register(s) other than the data register(s) designated by ADc and BL8 are in a data retention state.

[0185] In the waveform diagram of FIG. 9, when the RD command is input at time T39, data from the memory cell(s) at the bank address and column address specified by ADd, which are different from the ADc specified at time T34 in the waveform diagram of FIG. 9, is read to a device external to the SDRAM. By accepting the ACT command, the data from the memory cell(s) at the bank address and row address specified by ADr, which was written inside the SDRAM, is copied to the data register(s) at the bank address specified by ADr. Since this is different from the ADc to be written at time T34 in the waveform diagram of FIG. 9, no data has been written to the data register(s) specified by ADd and the burst length, and the data remains in the state where it was read from the memory cell(s) upon accepting the ACT command. Specifying ADd and reading with the RD command means specifying a column address from among the memory cell(s) at the bank address and row address specified by ADr, and reading the data to a device external to the SDRAM. Since the column address of the data register corresponds to the column address of the memory cell, the data of the memory cell(s) at the bank address and column address specified by ADd can be read from the data register(s) at the bank address and column address specified by ADd without any problems.

[0186] In the operation waveform diagram of Figure 10, when the RD command is input at time T39, data from the memory cell(s) with the bank address and column address specified by the same ADc as the ADc specified at time T34 shown in the operation waveform diagram of Figure 10 is read out to a device external to the SDRAM. According to this embodiment, the writing of the bank address and column address specified by ADc and burst length at time T34 shown in the operation waveform diagram of FIG. 10 to the memory cell(s) is not completed at time T39, but in the process from time T34 to time T38 shown in the operation waveform diagram of FIG. 10, the writing of the bank address and column address specified by ADc and burst length to the data register(s) is completed. Reading by the RD command is essentially reading from the data register(s), so data written by the write operation after time T34 shown in the operation waveform diagram of FIG. 10 can be read without any problem.

[0187] Although not shown as a waveform diagram, even if a rewrite request is made by receiving a WR command for the same address until the PRE command is received, only the data in the data register(s) is rewritten and no writing is performed to the memory cell(s). In the operation of the SDRAM, the RD command and the WR command may be issued multiple times after the ACT command is received until the PRE command is received, but since data exchange with external devices of the SDRAM is performed via a data register, there is no inconvenience in terms of the operation of not immediately writing to memory cells upon receiving a WR command, which is a feature of this embodiment.

[0188] If an ACT command is issued by specifying an address different from ADr in the same sub-cell array as the sub-cell array in which data has not yet been written to the memory cell, data corruption will occur even in the current SDRAM that uses memory cells consisting of one transistor and one capacitor, and this is prohibited as an operating specification, and the same is true for the SDRAM of this embodiment. Therefore, there will be no inconvenience with the operation of not immediately writing to the memory cell upon receiving the WR command, which is a feature of this embodiment.

[0189] After the RD command is received and tRTP (Internal READ Command to PRECHARGE Command delay) has elapsed, the PRE command can be input at time T42 shown in the operation waveform diagrams of FIGS. 9 and 10, the SDRAM according to the first embodiment starts writing data from the data register to the memory cell(s) connected to the word line of the bank address and row address specified by ADr. This results in a transition to the precharge state indicated by 037 in the state transition diagram of FIG. 3 and the precharge state indicated by 053 in the state transition diagram of FIG. 4. Since "0" data has already been written by the erase operation, the write sequence here writes "1" to the memory cell(s) corresponding to the data registers holding "1" data, and the memory cells corresponding to the data registers holding "0" data are maintained in the state where "0" data has already been written.

[0190] The potential of the word line (WL) of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VWWLH at time T43 shown in the operation waveform diagrams of Figures 9 and 10 by the global word line selected and driven by the row decoder and global word line driver shown in 130 of Figure 2, and further by the global word line and local word line driver. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VWWLL at time T43 shown in the operation waveform diagrams of Figures 9 and 10 by the global word line and local word line driver driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2. The word line(s) belonging to the sub-array of the address not specified by ADr remain at the potential VIWL by the global word line driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2, and further by the global word line and local word line driver. The source line(s) of the sub-cell array designated by ADr are biased from the floating state to 0V at time T43 shown in the operation waveform diagrams of FIGS. The bit line(s) of the sub-cell array specified by the ADr are biased in potential according to the data stored in the data register(s) specified by the ADr corresponding to the bit line(s), and if the data in the data register is "0", the bit line (BL) is biased from the floating state to 0V at time T43, and if the data in the data register is "1", the bit line (BL) is biased from the floating state to potential VWBL at time T43. On the other hand, the source line(s) and bit line(s) of the sub-cell arrays not specified by the ADr remain in a floating state.

[0191] 7 for the SDRAM according to the first embodiment, data "1" is written to the memory cells (group) whose bit lines (BL) are biased with VWBL among the memory cells (group) connected to the word lines of the bank address and row address specified by ADr. On the other hand, the floating bodies of the memory cells (group) whose bit lines (BL) are biased with 0V maintain the erased state, and data "0" is written to the memory cells (group). That is, data is read from each data register specified by ADr, and the read data is written to each memory cell specified by ADr corresponding to the data register. In addition to the data written by the WR command, the data lost by the erase operation is copied and saved in the data register(s). Therefore, no data is lost in the memory cells due to the erase operation. The memory cells (group) connected to the word lines of the bank addresses and row addresses not specified by ADr are in an idle state, and therefore the floating body state of each memory cell is maintained.

[0192] To complete the write operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr are floated at time T44, a time set within the SDRAM device after time T43 shown in the waveform diagrams of Figures 9 and 10. The potential of the word line of the sub-cell array specified by ADr begins to discharge from VWWLH or VWWLL to 0V at time T44 shown in the waveform diagrams of Figures 9 and 10. The potentials of the word lines, bit lines, and source lines remain at the above-mentioned states until time T45 shown in the waveform diagrams of Figures 9 and 10. By an automatic sequence without a command, the state transitions to the precharge state indicated by 045 in the state transition diagram of Fig. 4. In the state transition diagram of Fig. 3, the state remains in the precharge state indicated by 037. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Furthermore, an automatic sequence without a command causes the device to transition to the idle state indicated by 030 in the state transition diagram of Fig. 3 and to the idle state indicated by 040 in the state transition diagram of Fig. 4. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr is maintained in the reset state.

[0193] At time T45 shown in the operational waveform diagrams of Figures 9 and 10, an ACT command is received from a device external to the SDRAM. However, since the address signal received at time T45 shown in the operational waveform diagrams of Figures 9 and 10 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of Figure 4. Therefore, until the ACT command and ADp are received as an address signal synchronized with the ACT command, even after time T45 shown in the operation waveform diagrams of Figures 9 and 10, the potential of each word line (WL) remains at VIWL, and each bit line (BL) and each source line (SL) remains in a floating state. However, the SDRAM transitions from the idle state 030 to the activated state 031 shown in the state transition diagram of FIG.

[0194] Figure 11 shows the operational waveform diagram of a series of sequences in which an ACT command is issued to activate the memory cell(s) at the bank address and row address specified by ADr, data is written to the memory cell(s) at the bank address and column address specified by ADc, and then an RDA command is used to read from the memory cell(s) at the address specified by ADd, which has the same bank address as ADc but a different column address, and then an automatic sequence without a command transitions the memory cell(s) at the bank address and row address specified by ADr, which are currently in the active state, to the idle state. The operational waveform diagram shown in Figure 12 differs from the operational waveform diagram shown in Figure 11 in that after writing to the memory cell(s) at the bank address and column address specified by ADc, reading is performed from the memory cell(s) at the bank address and column address specified by the same ADc. The only difference between the operational waveform diagram shown in FIG. 11 and the operational waveform diagram shown in FIG. 12 is that the column address input in synchronization with the WR command and the column address input in synchronization with the RDA command are different (FIG. 11) or the same (FIG. 12). Therefore, the operational waveform diagram shown in FIG. 11 and the operational waveform diagram shown in FIG. 12 will be explained together.

[0195] The operational waveforms shown in FIGS. 11 and 12 can be compared with the state transition diagram shown in FIG. 3 as follows: In the state transition diagram shown in FIG. 3, the SDRAM transitions from the idle state indicated by 030 to the activated state indicated by 031 in the state transition diagram shown in FIG. 3 by receiving an ACT command input from an external device of the SDRAM at time T31 shown in the operation waveform diagrams of FIGS. 11 and 12, and transitions to the active state indicated by 032 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. In the state transition diagram shown in FIG. 3, the SDRAM transitions to the write state indicated by 034 in the state transition diagram shown in FIG. 3 by receiving a WR command input from an external device of the SDRAM at time T34 shown in the operation waveform diagrams of FIGS. 11 and 12, and transitions to the read state indicated by 035 in the state transition diagram shown in FIG. 3 by receiving an RDA command input from an external device of the SDRAM at time T39 shown in the operation waveform diagrams of FIGS. 11 and 12. After a predetermined time has elapsed since the RDA command was accepted, an automatic sequence without a command causes the SDRAM to transition to the precharge state indicated by 037 in the state transition diagram shown in Fig. 3, and then to the idle state indicated by 030 in the state transition diagram shown in Fig. 3. This is the sequence in which an ACT command input from a device external to the SDRAM is accepted at time T45 shown in Figs. 11 and 12.

[0196] The operating waveforms shown in FIGS. 11 and 12 will be explained in conjunction with the state transition diagram of the first embodiment shown in FIG. 11 and 12, an ACT command is input from an external device of the SDRAM at time T31 shown in the operation waveform diagrams of FIGS. 11 and 12, and upon receiving an address signal ADr input from an external device of the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition from the idle state indicated by 040 in the state transition diagram of FIG. 4 to the activated state indicated by 041 in the state transition diagram of FIG. 4, and transitions to the active state indicated by 042 in the state transition diagram of FIG. 4 by an automatic sequence without a command. Upon receiving a WR command input from an external device of the SDRAM at time T34 shown in the operation waveform diagrams of FIGS. 11 and 12, the memory cell(s) and data register(s) transition to the write state indicated by 046 in the state transition diagram of FIG. 4, and transitions to the active state indicated by 047 in the state transition diagram of FIG. 4 by an automatic sequence without a command. By receiving an RDA command input from a device external to the SDRAM at time T39 shown in the operation waveform diagrams of Figures 11 and 12, the SDRAM transitions to the read state indicated by 051 in the state transition diagram shown in Figure 18. After a predetermined time has elapsed, at time T42 shown in the operation waveform diagrams of Figures 11 and 12, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in Figure 4, and then, by an automatic sequence without a command, transitions to the idle state indicated by 040 in the state transition diagram shown in Figure 4 via the precharge state indicated by 045 in the state transition diagram shown in Figure 4. At time T45 shown in the operational waveform diagrams of Figures 11 and 12, an ACT command input from a device external to the SDRAM is accepted. However, the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T45 shown in the operational waveform diagrams of Figures 11 and 12 is ADp, which is different from ADr. Therefore, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram shown in Figure 4. This is the sequence.

[0197] Furthermore, the operating waveforms of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment shown in Figures 11 and 12 will be explained in comparison with the state transition diagram shown in Figure 3 and the state transition diagram of the first embodiment shown in Figure 4. When an ACT command input from an external device to the SDRAM is received at time T31 shown in the operation waveform diagrams of Figures 11 and 12, the state transition diagram of Figure 3 transitions from the idle state indicated by 030 to the activated state indicated by 031. In the state transition diagram of Figure 4, the state transition diagram of Figure 4 transitions from the idle state indicated by 040 to the activated state indicated by 041.

[0198] In synchronization with the timing of receiving the ACT command, an address signal is received as an input signal from a device external to the SDRAM at time T31 shown in the operational waveform diagrams of Figures 11 and 12. This is indicated by ADr in the operational waveform diagrams of Figures 11 and 12. The address signal from the device external to the SDRAM is discriminated by the address receiver and address decoder shown as 112 in Figure 1, and the word line (WL) of the specified bank address and row address is biased from potential VIWL to potential VRWL at time T32 shown in the operational waveform diagrams of Figures 11 and 12 by a global word line selected and driven by a row decoder and global word line driver shown as 130 in Figure 2, and further by the global word line and a local word line driver shown as 134 in Figure 2. The potential of the word line (WL)(s) of the address not specified by the ADr and the word line (WL)(s) of the sub-cell array(s) remains at VIWL by the row decoder shown as 130 in FIG. 2 and the global word line driven in the unselected state by the global word line driver, and further by the global word line and the local word line driver shown as 134 in FIG. 2.

[0199] The source line (SL) (group) of the sub-cell array designated by the ADr is biased from the floating state to 0V at time T32 shown in the operation waveform diagrams of FIGS. The bit line (BL) (group) of the sub-cell array specified by the ADr is biased from a floating state to 0V, and then to the potential VRBL at time T32 shown in the operation waveform diagrams of Figures 11 and 12. The current flowing through each bit line (BL) via each memory cell is converted to a voltage by each BL sense amplifier connected to each bit line (BL), and after or while the data is discriminated as "1" or "0" by the converted voltage, it is stored in each data register associated with each bit line (BL). That is, the data read from each memory cell specified by the ADr is written to each data register specified by the ADr corresponding to each memory cell. Therefore, the data held in the memory cell(s) specified by the ADr is copied to the data register(s) specified by the ADr.

[0200] 11 and 12, when data storage in the data register is completed, the word line (WL) potential specified by the ADr is driven to the potential VIWL, the bit line (BL)(s) of the sub-cell array specified by the ADr starts to discharge to 0 V, and then the bit line (BL)(s) enters a floating state together with the source line (SL)(s) specified by the ADr. This results in a transition to the active state indicated by 032 in the state transition diagram of FIG. 3, and to the active state indicated by 042 in the state transition diagram of FIG. 4. The potentials of the word lines, bit lines, and source lines continue to be maintained until time T35 shown in the waveform diagrams of Figures 11 and 12. Therefore, the floating body state of each memory cell specified by ADr is maintained. Meanwhile, the data register(s) specified by ADr hold the same data as the data held by the memory cell(s) specified by ADr.

[0201] After tRCD (ACT Command to internal read or write delay time) has elapsed since the ACT command was received, at time T34 shown in the operation waveform diagrams of Figures 11 and 12, when the first WR command is received from a device external to the SDRAM after the ACT command was received, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr, which are input in synchronization with the ACT command. This results in a transition to the write state shown as 034 in the state transition diagram of Figure 3 and the write state shown as 046 in the state transition diagram of Figure 4.

[0202] The potential of the word line of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VEWLH by the global word line selected and driven by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VEWLL by the global word line driven to the unselected state by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2, from the time T35 shown in the operation waveform diagrams of Fig. 11 and Fig. 12. The word line(s) belonging to the subarrays whose addresses are not specified by the ADr remain at the potential VIWL due to the global word lines driven in the unselected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further due to the global word lines and the local word line driver shown as 134 in FIG. 2.

[0203] The source line(s) and bit line(s) of the sub-cell array specified by the ADr are biased from the floating state to the potential VEBL from time T35 shown in the operation waveform diagrams of Figures 11 and 12. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0204] By setting the potentials as described above, as described in the explanation of the operating waveform diagram in Figure 7 for the SDRAM of the first embodiment, the memory cell(s) connected to the word line of the bank address and row address specified by ADr are erased. At this point, the data held in the memory cell(s) specified by the ADr will be erased, but after the SDRAM of the first embodiment transitions to state 053 shown in the state transition diagram of Figure 4, it rewrites the data that has been copied to the data register(s) specified by the ADr and remains in the memory cell(s), so no data loss occurs in the memory cell(s). On the other hand, among the memory cells (groups) connected to word lines of bank addresses and row addresses not specified by ADr, the memory cells (groups) belonging to the unselected sub-cell array are in an idle state, and the sub-cell array is in a selected state. The relationship between the potential of each floating body of the memory cells (groups) connected to the unselected word line (groups) and the potential of the bit line and source line is almost the same as in the idle state, so the charge of the floating body is maintained.

[0205] 11 and 12, after a time set within the SDRAM device has elapsed since time T35, the source line(s) and bit line(s) of the sub-cell array specified by ADr start to be discharged to 0V at time T37, and thereafter the bit line(s) (BL) and the source line(s) (SL) specified by ADr are set to a floating state. The potential of the word line of the sub-cell array specified by ADr is biased from VEWLH or VEWLL to VIWL at time T37 shown in the operation waveform diagrams of FIGS. 11 and 12, and the sub-cell array specified by ADr enters an idle state. The potentials of the word lines, bit lines, and source lines continue to be in the above-described state until time T43 shown in the operation waveform diagrams of Figures 11 and 12. Therefore, the state of the floating body of each memory cell specified by ADr is maintained.

[0206] 11 and 12, after a predetermined time (CWL; CAS Write Latency) has elapsed since the WR command was accepted, starting at time T36, as shown in the waveform diagrams of FIGS. 11 and 12, the burst length is 8 (BL8). Therefore, as shown in the waveform diagrams of FIGS. 11 and 12, 8 sets of data are sequentially input from the DQ signal line of FIG. 1, and the input signals are sensed and amplified by the data input receiver shown in 118 of FIG. 1 and then stored in the data input register shown in 119 of FIG. 1. After storage, the data is written from the data input register shown in 119 of FIG. 1 to the data register(s) specified by the ADr, which are present in 133 of FIG. 2, and which are specified by the ADc and BL8, by the IO driver shown in 123 of FIG. 1. Meanwhile, the data register(s) not specified by the ADc and BL8, among the data register(s) specified by the ADr, hold the same data as the memory cell connectable to the same bit line (BL) specified by the ADr.

[0207] 7, the write operation to the data register in the area 133 in FIG. 2, which is specified by ADc and BL8 among the data register(s) specified by ADr, and the erase operation to the memory cell(s) connected to the word line of the bank address and row address specified by ADr, are performed in parallel and independently, so depending on the WL (Write Latency) setting value and the clock period, the timing of the erase operation start time and the data input start time may differ, and there is no problem if they do. The timing of the erase operation end time and the data input completion time may also differ, and there is no problem if they do. When both the write operation of the input data to the data register specified by ADr and ADc and the erase operation of the memory cell(s) connected to the word line of the bank address and row address specified by ADr are completed, an automatic sequence will cause the state to transition to the active state 032 in the state transition diagram shown in Figure 3 or to the active state 047 in the state transition diagram shown in Figure 4. Each memory cell specified by the ADr maintains its erased state. Of the data register(s) specified by the ADr, the data register(s) that are not specified by the ADc and BL8 and that have not been written to retain the data that the memory cell(s) specified by the ADr held before being erased. Of the data register(s) specified by the ADr, the data register(s) that are specified by the ADc and BL8 and that have been written to retain the written data.

[0208] Each unselected word line is biased to VIWL, and the unselected bit lines and unselected source lines are in a floating state after being discharged to 0 V at some previous stage. Therefore, the floating body state of each memory cell specified by ADr is maintained.

[0209] After the data input is complete, the RDA command can be input at time T39 after tWTR (Delay from start of internal WRITE transaction to internal Read command) has elapsed. When the RDA command is input at time T39 shown in the operation waveform diagrams of Figures 11 and 12, acceptance of the RDA command causes a transition from the write state 034 to the read state 035 in the state transition diagram of Figure 3. In the state transition diagram of Figure 4, acceptance of the RDA command causes a transition from the write state 046, which was in the active state 047 by the automatic sequence, to the read state 051. In the operation waveform diagram of Figure 11, an RDA command received from a device external to the SDRAM at time T39 causes the address signal input in synchronization with the RDA command, the bank address specified by ADd, and the data of the memory cell(s) at the column address to be read out to a device external to the SDRAM. Also, in the operation waveform diagram of Figure 12, an RDA command received from a device external to the SDRAM at time T39 causes the address signal input in synchronization with the RDA command, the bank address specified by ADc, and the data of the memory cell(s) at the column address to be read out to a device external to the SDRAM. Data output starts at time T40 after CL (Column Latency) has elapsed since the RDA command is accepted at time T39 shown in the operation waveform diagrams of FIGS. 11 and 12. Since the BL8 setting is used, data is output eight times. In the case of the operation waveform diagram of Figure 11, essentially, of the data register(s) specified by ADr that hold the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADd and BL8 are read out to a device external to the SDRAM. Of the data register(s) specified by ADr, the data register(s) other than the data register(s) specified by ADd and BL8 are in a data holding state. 12, the data of the data register(s) specified by ADr, which are designated by ADc and BL8, are read out to a device external to the SDRAM. The data register(s) other than the data register(s) specified by ADc and BL8 are in a data retention state.

[0210] As described in the explanation of the operating waveforms in Figures 9 and 10, in the SDRAM of the first embodiment, it does not matter whether the bank address and column address specified when the RDA command is input at time T39 shown in the operating waveform diagrams of Figures 11 and 12 are the same as or different from the bank address and column address specified when the WR command is input at time T34 shown in the operating waveform diagrams of Figures 11 and 12, and no inconvenience occurs if the writing of data to the memory cells is not completed.

[0211] 11 and 12, after the lapse of tRTP (Internal READ Command to PRECHARGE Command delay) from the receipt of the RDA command, even without inputting a PRE command, an automatic sequence causes the SDRAM to transition to the precharge state indicated by 037 in the state transition diagram of Fig. 3. The SDRAM of the first embodiment transitions the memory cell(s) and data register(s) specified by the ADr to the precharge state indicated by 053 in the state transition diagram of Fig. 4. At time T43 shown in the operation waveform diagrams of Figures 11 and 12, the data write operation of the data register(s) specified by the ADr to the memory cell(s) connected to the word line of the bank address and row address specified by the ADr is started. Since "0" data has already been written by the erase operation, the write sequence here writes "1" to the memory cell(s) corresponding to the data registers holding "1" data, and maintains the state in which "0" data is already written to the memory cells corresponding to the data registers holding "0" data.

[0212] The potential of the word line (WL) of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VWWLH at time T43 shown in the operation waveform diagrams of Figures 11 and 12 by the global word line selected and driven by the row decoder and global word line driver shown in 130 of Figure 2, and further by the global word line and local word line driver. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VWWLL at time T43 shown in the operation waveform diagrams of Figures 11 and 12 by the global word line and local word line driver driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2. The word line(s) belonging to the sub-array of the address not specified by ADr remain at the potential VIWL by the global word line driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2, and further by the global word line and local word line driver. The source line(s) of the sub-cell array designated by ADr are biased from the floating state to 0V at time T43 shown in the operation waveform diagrams of FIGS. The bit line(s) of the sub-cell array specified by ADr are biased in potential according to the data stored in the data register(s) corresponding to the bit line(s), and if the data in the data register is "0", the bit line (BL) is biased from the floating state to 0V at time T43, and if the data in the data register is "1", the bit line (BL) is biased from the floating state to potential VWBL at time T43.

[0213] 7 for the SDRAM according to the first embodiment, data "1" is written to the memory cells (group) whose bit lines (BL) are biased with VWBL among the memory cells (group) connected to the word lines of the bank address and row address specified by ADr. On the other hand, the floating bodies of the memory cells (group) whose bit lines (BL) are biased with 0V maintain the erased state, and data "0" is written to the memory cells (group). That is, data is read from each data register specified by ADr, and the read data is written to each memory cell specified by ADr corresponding to the data register. In addition to the data written by the WR command, the data lost by the erase operation is copied and saved in the data register(s). Therefore, no data is lost in the memory cells due to the erase operation. The memory cells (group) connected to the word lines of the bank addresses and row addresses not specified by ADr are in an idle state, so the floating body state of each memory cell is maintained.

[0214] To complete the write operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr are floated at time T44 shown in the waveform diagrams of Figures 11 and 12, after a time set within the SDRAM device has elapsed from time T43 shown in the waveform diagrams of Figures 11 and 12. The potential of the word line of the sub-cell array specified by ADr is biased from VWWLH or VWWLL to 0V at time T44 shown in the waveform diagrams of Figures 11 and 12. The potentials of the word lines, bit lines, and source lines remain in this state until time T45 shown in the waveform diagrams of Figures 11 and 12. By an automatic sequence without a command, the state transitions to the precharge state indicated by 045 in the state transition diagram of Fig. 4. In the state transition diagram of Fig. 3, the state remains in the precharge state indicated by 037. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Furthermore, an automatic sequence without a command causes the device to transition to the idle state indicated by 030 in the state transition diagram of Fig. 3 and to the idle state indicated by 040 in the state transition diagram of Fig. 4. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr is maintained in the reset state.

[0215] The memory cells (group) connected to the word lines of the bank addresses and row addresses not specified by ADr are in an idle state, and therefore the floating body state of each memory cell is maintained. However, the SDRAM transitions from the idle state 030 to the activated state 031 shown in the state transition diagram of FIG.

[0216] At time T45 shown in Figures 11 and 12, an ACT command is received from a device external to the SDRAM. However, since the address signal received at time T45 shown in Figures 11 and 12 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of Figure 4. Therefore, until the ACT command and ADp are received as an address signal synchronized with the ACT command, even after time T45 shown in the operation waveform diagrams of Figures 11 and 12, the potential of each word line (WL) remains at VIWL, and each bit line (BL) and each source line (SL) remains in a floating state. However, the SDRAM transitions from the idle state 030 to the activated state 031 shown in the state transition diagram of FIG.

[0217] Figure 13 shows an operational waveform diagram of a series of sequences in which an ACT command is issued to activate the memory cell(s) at the bank address and row address specified by ADr, reading from the memory cell(s) at the bank address and column address specified by ADc, writing to the memory cell(s) at the address specified by ADd, which has the same bank address as ADc but a different column address, and issuing a PRE command to transition the memory cell(s) at the bank address and row address specified by ADr, which are in the active state, to the idle state. The operational waveform diagram shown in Figure 14 differs from the operational waveform diagram shown in Figure 13 in that after reading from the memory cell(s) at the bank address and column address specified by ADc, writing is performed to the memory cell(s) at the bank address and column address specified by the same ADc. The only difference between the operational waveform diagram shown in FIG. 13 and the operational waveform diagram shown in FIG. 14 is that the column address input in synchronization with the RD command and the column address input in synchronization with the WR command are different (FIG. 13) or the same (FIG. 14). Therefore, the operational waveform diagram shown in FIG. 13 and the operational waveform diagram shown in FIG. 14 will be explained together.

[0218] The operational waveforms shown in FIGS. 13 and 14 can be compared with the state transition diagram shown in FIG. 3 as follows: In the state transition diagram shown in FIG. 3, the SDRAM transitions from the idle state indicated by 030 to the activated state indicated by 031 in the state transition diagram shown in FIG. 3 by receiving an ACT command input from an external device of the SDRAM at time T51 shown in the operation waveform diagrams of FIGS. 13 and 14, and transitions to the active state indicated by 032 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. In the state transition diagram shown in FIG. 3, the SDRAM transitions to the read state indicated by 033 in the state transition diagram shown in FIG. 3 by receiving an RD command input from an external device of the SDRAM at time T54 shown in the operation waveform diagrams of FIGS. 13 and 14, and transitions to the write state indicated by 034 in the state transition diagram shown in FIG. 3 by receiving a WR command input from an external device of the SDRAM at time T57 shown in the operation waveform diagrams of FIGS. 13 and 14. By accepting a PRE command input from an external device to the SDRAM at time T62 shown in the operation waveform diagrams of Figures 13 and 14, the SDRAM transitions to the precharge state indicated by 037 in the state transition diagram shown in Figure 3, and then transitions to the idle state indicated by 030 in the state transition diagram shown in Figure 3 by an automatic sequence without a command. This is the sequence in which an ACT command input from an external device to the SDRAM is accepted at time T65.

[0219] The operating waveforms shown in FIGS. 13 and 14 will be explained in conjunction with the state transition diagram of the first embodiment shown in FIG. In the state transition diagram shown in FIG. 4, from the idle state indicated by 040, upon receiving an ACT command input from a device external to the SDRAM at time T51 shown in the operation waveform diagrams of FIGS. 13 and 14 and an address signal ADr input from a device external to the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the activated state indicated by 041 in the state transition diagram shown in FIG. 4, transition to the active state indicated by 042 in the state transition diagram shown in FIG. 4 by an automatic sequence without a command, and transition to the read state indicated by 043 in the state transition diagram shown in FIG. 4 upon receiving an RD command input from a device external to the SDRAM at time T54 shown in the operation waveform diagrams of FIGS. 13 and 14. Furthermore, by accepting a WR command input from a device external to the SDRAM at time T57 shown in the operation waveform diagrams of Figures 13 and 14, the SDRAM transitions to the write state indicated by 046 in the state transition diagram shown in Figure 4, and further transitions to the active state indicated by 047 in the state transition diagram shown in Figure 4 by an automatic sequence without a command. By accepting a PRE command input from a device external to the SDRAM at time T62 shown in the operation waveform diagrams of Figures 13 and 14 and an address signal ADr input from a device external to the SDRAM in synchronization with the PRE command, the memory cell(s) and data register(s) specified by the ADr transition to the precharge state indicated by 053 in the state transition diagram shown in Figure 4, and further transitions to the idle state indicated by 040 in the state transition diagram shown in Figure 4 by an automatic sequence without a command via the precharge state indicated by 045 in the state transition diagram shown in Figure 4. At time T65 shown in the operation waveform diagrams of Figures 13 and 14, an ACT command input from a device external to the SDRAM is accepted. However, since the address signal input in synchronization with the ACT command from a device external to the SDRAM at time T65 shown in the operation waveform diagrams of Figures 13 and 14 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram shown in Figure 4. This is the sequence.

[0220] Furthermore, the operating waveforms of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment shown in Figures 13 and 14 will be explained in conjunction with the state transition diagram shown in Figure 3 and the state transition diagram of the first embodiment shown in Figure 4. When an ACT command input from an external device to the SDRAM is received at time T51 shown in the operation waveform diagrams of Figures 13 and 14, the state transition diagram of Figure 3 transitions from the idle state indicated by 030 to the activated state indicated by 031. In the state transition diagram of Figure 4, the state transition diagram of Figure 4 transitions from the idle state indicated by 040 to the activated state indicated by 041. In synchronization with the timing of receiving the ACT command, an address signal input from a device external to the SDRAM is received at time T51 shown in the operational waveform diagrams of Figures 13 and 14. This is indicated by ADr in the operational waveform diagrams of Figures 13 and 14. The address signal from the device external to the SDRAM is discriminated by an address receiver and address decoder indicated by reference numeral 112 in Figure 1, and the word line (WL) of the specified bank address and row address is biased from potential VIWL to potential VRWL at time T52 shown in the operational waveform diagrams of Figures 13 and 14 by a global word line selected and driven by a row decoder and global word line driver indicated by reference numeral 130 in Figure 2, and further by the global word line and local word line driver indicated by reference numeral 134 in Figure 2. The potential of the word lines (WL) (groups) of the addresses not specified by the ADr and the word lines (WL) (groups) of the sub-cell array (groups) remains at VIWL due to the global word lines driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2, and further due to the global word lines and the local word line driver shown in 134 of Figure 2.

[0221] The source line (SL) (group) of the sub-cell array designated by the ADr is biased from the floating state to 0V at time T52 shown in the operation waveform diagrams of FIGS. The bit line (BL) (group) of the sub-cell array specified by the ADr goes from a floating state to 0V, and then is biased to the potential VRBL at time T52 shown in the operation waveform diagrams of Figures 13 and 14. The current flowing through each bit line (BL) via each memory cell is converted to a voltage by each BL sense amplifier connected to each bit line (BL), and after or while the data is discriminated as "1" or "0" by the converted voltage, it is stored in each data register associated with each bit line (BL). That is, the data read from each memory cell specified by the ADr is written to each data register specified by the ADr corresponding to each memory cell. Therefore, the data held in the memory cell(s) specified by the ADr is copied to the data register(s) specified by the ADr.

[0222] 13 and 14, when data storage in the data register is completed, the word line (WL) potential specified by the ADr is driven to VIWL, and the bit line (BL)(group) of the sub-cell array specified by the ADr starts discharging to 0V at time T53, after which the bit line (BL)(group) and the source line (SL)(group) specified by the ADr become floating. This results in a transition to the active state indicated by 032 in the state transition diagram of FIG. 3, and to the active state indicated by 042 in the state transition diagram of FIG. 4. The potentials of the word lines, bit lines, and source lines continue to be maintained until time T58 shown in the waveform diagrams of Figures 13 and 14. Therefore, the floating body state of each memory cell specified by ADr is maintained. Meanwhile, the data register(s) specified by ADr hold the same data as that held in the memory cell(s) specified by ADr.

[0223] When an RD command is input from a device external to the SDRAM at time T54 shown in the operation waveform diagrams of Figures 13 and 14, after tRCD (ACT Command to internal read or write delay time) has elapsed since the ACT command was received, the address signal input in synchronization with the RD command, and the data of the memory cell(s) at the bank address and column address specified by ADc are read out to a device external to the SDRAM. In the state transition diagram of Figure 3, this is the read state indicated by 033, and in the state transition diagram of Figure 4, it transitions to the read state indicated by 043. After CL (Column Latency) has elapsed since the RD command was received at time T54 shown in the waveform diagrams of Figures 13 and 14, data output begins at time T55 shown in the waveform diagrams of Figures 13 and 14. Since the BL8 setting is used, data is output eight times. In essence, among the data register(s) specified by ADr that hold the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADc and BL8 is read out to a device external to the SDRAM. Among the data register(s) specified by ADr, the data register(s) other than the data register(s) specified by ADc and BL8 are in a data holding state.

[0224] After the READ to WRITE command delay time has elapsed since the RD command was received, at time T57 shown in the operation waveform diagrams of Figures 13 and 14, when the first WR command is received after the ACT command is received from a device external to the SDRAM, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr, which are input in synchronization with the ACT command. This results in a transition to the write state shown as 034 in the state transition diagram of Figure 3 and the write state shown as 046 in the state transition diagram of Figure 4.

[0225] The potential of the word line of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VEWLH by the global word line selected and driven by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VEWLL by the global word line driven to the unselected state by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and a local word line driver shown as 134 in Fig. 2, from the time T58 shown in the operation waveform diagrams of Fig. 13 and Fig. 14. The word line(s) belonging to the subarrays whose addresses are not specified by the ADr remain at the potential VIWL due to the global word lines driven in the unselected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further due to the global word lines and the local word line driver shown as 134 in FIG. 2.

[0226] The source line(s) and bit line(s) of the sub-cell array specified by ADr are biased from the floating state to the potential VEBL from time T58 shown in the operation waveform diagrams of Figures 13 and 14. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by ADr remain in the floating state.

[0227] By setting the potentials as described above, as described in the explanation of the operating waveform diagram in Figure 7 for the SDRAM of the first embodiment, the memory cell(s) connected to the word line of the bank address and row address specified by ADr are erased. At this point, the data held in the memory cell(s) specified by the ADr will be erased, but the SDRAM of the first embodiment rewrites the remaining data that has been copied to the data register(s) specified by the ADr into the memory cell(s) after receiving the PRE command, so the data in the memory cell(s) will not be lost. On the other hand, among the memory cells (groups) connected to word lines of bank addresses and row addresses not specified by ADr, the memory cells (groups) belonging to the unselected sub-cell array are in an idle state, and the sub-cell array is in a selected state. The relationship between the potential of each floating body of the memory cells (groups) connected to the unselected word line (groups) and the potential of the bit line and source line is almost the same as in the idle state, so the charge of the floating body is maintained.

[0228] To complete the erase operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr start discharging to 0V at time T60, a time set within the SDRAM device after time T58 shown in the operation waveform diagrams of Figures 13 and 14, and then enter a floating state. The potential of the word line of the sub-cell array specified by ADr is biased from VEWLH or VEWLL to VIWL at time T60 shown in the operation waveform diagrams of Figures 13 and 14, and the sub-cell array specified by ADr enters an idle state. The potentials of the word lines, bit lines, and source lines continue to be in the above-described state until time T63 shown in the operation waveform diagrams of Figures 13 and 14. Therefore, the state of the floating body of each memory cell specified by ADr is maintained.

[0229] The operation starts at time T59 shown in the operational waveform diagrams of FIGS. 13 and 14, which is a predetermined WL (Write Latency) time after the WR command is received, and since the burst length is 8 (BL8), 8 sets of data are input sequentially from the DQ signal line shown in FIG. 1, as shown in the operational waveform diagrams of FIGS. 13 and 14. The input data is sensed and amplified by the data input receiver shown as 118 in FIG. 1, and then stored in the data input register shown as 119 in FIG. 1. In the case of the operation waveform diagram of Figure 13, after storing in the data input register, the data is written from the data input register shown as 119 in Figure 1 to the data register(s) in the area 133 in Figure 2, which are specified by the ADd and BL8 among the data register(s) specified by the ADr, by the IO driver shown as 123 in Figure 1. On the other hand, among the data register(s) specified by the ADr, the data register(s) not specified by the ADd and BL8 hold the same data as the memory cell connectable to the same bit line (BL) specified by the ADr. 14, after storing in the data input register, the data is written from the data input register shown as 119 in Fig. 1 to the data register(s) in the area 133 in Fig. 2, which are specified by the ADc and BL8 among the data register(s) specified by the ADr, by the IO driver shown as 123 in Fig. 1. On the other hand, among the data register(s) specified by the ADr, the data register(s) not specified by the ADc and BL8 hold the same data as the memory cell connectable to the same bit line (BL) specified by the ADr. In the case of the SDRAM according to the first embodiment, depending on the WR command, writing is not performed in the memory cell(s), and input data is only written to the data register present in 133 in Fig. 2 associated with the sub-cell array of the address specified by ADr and ADd (in the case of the operational waveform diagram of Fig. 13) or ADc (in the case of the operational waveform diagram of Fig. 14), and further BL8. The fact that no inconvenience occurs even if data writing to the memory cells is not completed was mentioned when explaining the operational waveforms of Figs. 9 and 10 for the SDRAM according to the first embodiment. Furthermore, as mentioned when explaining the operating waveforms of the SDRAM according to the first embodiment in Figures 9 and 10, it does not matter whether the bank address and column address specified when the RD command is issued are the same as or different from the bank address and column address specified when the WR command is issued.

[0230] 7, the write operation to the data register(s) in the area 133 in FIG. 2, which is specified by ADc and BL8 among the data register(s) specified by ADr, and the erase operation to the memory cell(s) connected to the word line of the bank address and row address specified by ADr, are performed in parallel and independently, so depending on the WL (Write Latency) setting value and the clock period, the timing of the erase operation start time and the data input start time may differ, and there is no problem if they do. The timing of the erase operation end time and the data input completion time may also differ, and there is no problem if they do. The waveform diagrams shown in FIGS. 13 and 14 are examples in which the timing of erase completion and data input timing are different from those in the operation waveform diagrams shown in FIGS. When both the write operation of the input data to the data register specified by ADr and ADc (in the case of the operation waveform diagram of Figure 13) or ADd (in the case of the operation waveform diagram of Figure 14) and the erase operation of the memory cell(s) connected to the word line of the bank address and row address specified by ADr are completed, an automatic sequence will cause the state to transition to the active state 032 in the state transition diagram shown in Figure 3 or to the active state 047 in the state transition diagram shown in Figure 4. Each memory cell designated by ADr maintains the erased state. In the case of the operation waveform diagram of Figure 13, among the data register(s) specified by the ADr, the data register(s) that are not specified by the ADd and BL8 and have not been written to retain the data that were held before the memory cell(s) specified by the ADr were erased.In the case of the operation waveform diagram of Figure 13, among the data register(s) specified by the ADr, the data register(s) that are specified by the ADd and BL8 and have been written to retain the written data. In the case of the operation waveform diagram of Figure 14, among the data register(s) specified by the ADr, the data register(s) that are not specified by the ADc and BL8 and have not been written to retain the data that were held before the memory cell(s) specified by the ADr were erased.In the case of the operation waveform diagram of Figure 14, among the data register(s) specified by the ADr, the data register(s) that are specified by the ADc and BL8 and have been written to retain the written data.

[0231] After the data input is complete, the PRE command can be input at time T62 after tWR (WRITE Recovery Time) has elapsed. 13 and 14, the SDRAM according to the first embodiment starts writing data from the data register to the memory cell(s) connected to the word line of the bank address and row address specified by ADr. The state transitions to the precharge state indicated by 037 in the state transition diagram of FIG. 3, and to the precharge state indicated by 053 in the state transition diagram of FIG. 4. Since "0" data has already been written by the erase operation, the write sequence here writes "1" to the memory cell(s) corresponding to the data registers holding "1" data, and the memory cells corresponding to the data registers holding "0" data are maintained in the state where "0" data has already been written.

[0232] The potential of the word line of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VWWLH at time T63 shown in the operation waveform diagrams of Figures 13 and 14 by the global word line selected and driven by the row decoder and global word line driver shown in Figure 2, and further by the global word line and local word line driver. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VWWLL at time T63 shown in the operation waveform diagrams of Figures 13 and 14 by the global word line and local word line driver driven in the unselected state by the row decoder and global word line driver shown in Figure 2. The word line(s) belonging to the sub-array of the address not specified by ADr remain at the potential VIWL by the global word line driven in the unselected state by the row decoder and global word line driver shown in Figure 2, and further by the global word line and local word line driver. The source line(s) of the sub-cell array designated by ADr are biased from the floating state to 0V at time T63 shown in the operation waveform diagrams of FIGS. The bit line(s) of the sub-cell array specified by ADr are biased in potential according to the data stored in the data register(s) corresponding to the bit line(s), and when the data in the data register is "0", the bit line (BL) is biased from the floating state to 0V at time T63 shown in the operation waveform diagrams of Figures 13 and 14, and when the data in the data register is "1", the bit line (BL) is biased from the floating state to potential VWBL at time T63. On the other hand, the source line(s) and bit line(s) of the sub-cell arrays not specified by the ADr remain in a floating state.

[0233] With the above potential settings, among the memory cells (group) connected to the word line of the bank address and row address specified by ADr, the memory cells (group) whose bit lines (BL) are biased with VWBL pass a current, which causes impact ionization, and the generated holes (group) accumulate in the floating body of each memory cell, and the electrons (group) are discharged to the bit line (BL), thereby writing data "1." On the other hand, in the memory cells (group) whose bit lines (BL) are biased with 0V, the bit line (BL) and source (line) have the same potential, so no current passes, and therefore no impact ionization occurs, and the floating body of each memory cell maintains the erased state, meaning that data "0" has been written. That is, data is read from each data register specified by ADr, and the read data is written to each memory cell specified by ADr corresponding to the data register. In addition to the data written by the WR command, the data lost by the erase operation is copied and saved in the data register(s). Therefore, no data is lost in the memory cells due to the erase operation. The memory cells (group) connected to the word lines of the bank addresses and row addresses not specified by ADr are in an idle state, and therefore the floating body state of each memory cell is maintained.

[0234] To complete the write operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr are floated at time T64, a time set within the SDRAM device after time T63 shown in the waveform diagrams of Figures 13 and 14. The potential of the word line of the sub-cell array specified by ADr is biased from VWWLH or VWWLL to 0V at time T64, and the sub-cell array specified by ADr enters an idle state. The potentials of the word lines, bit lines, and source lines remain constant until time T65 shown in the waveform diagrams of Figures 13 and 14. By an automatic sequence without a command, the state transitions to the precharge state indicated by 045 in the state transition diagram of Fig. 4. In the state transition diagram of Fig. 3, the state remains in the precharge state indicated by 037. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Furthermore, by an automatic sequence without a command, the state transitions to the idle state indicated by 030 in the state transition diagram of Fig. 3 and to the idle state indicated by 040 in the state transition diagram of Fig. 4. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is maintained in the reset state.

[0235] At time T65 shown in the operational waveform diagrams of Figures 13 and 14, an ACT command is received from a device external to the SDRAM. However, since the address signal received at time T65 shown in the operational waveform diagrams of Figures 13 and 14 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of Figure 4. Therefore, until the ACT command and ADp are received as an address signal synchronized with the ACT command, even after time T65 shown in the operation waveform diagrams of Figures 13 and 14, the potential of each word line (WL) remains at VIWL, and each bit line (BL) and each source line (SL) remains in a floating state. However, the SDRAM transitions from the idle state 030 to the activated state 031 shown in the state transition diagram of FIG.

[0236] Figure 15 shows the operational waveforms of a series of sequences in which an ACT command is issued to activate the memory cell(s) at the bank address and row address specified by ADr, data is read from the memory cell(s) at the bank address and column address specified by ADc, and then a WRA command is used to write to the memory cell(s) at the address specified by ADd, which has the same bank address as ADc but a different column address, and then an automatic sequence without a command transitions the memory cell(s) at the bank address and row address specified by ADr, which are currently in the active state, to the idle state. The operational waveform diagram shown in Figure 16 differs from the operational waveform diagram shown in Figure 15 in that after reading from the memory cell(s) at the bank address and column address specified by ADc, writing is performed to the memory cell(s) at the bank address and column address specified by the same ADc. The only difference between the operational waveform diagram shown in FIG. 15 and the operational waveform diagram shown in FIG. 16 is that the column address input in synchronization with the RD command and the column address input in synchronization with the WRA command are different (FIG. 15) or the same (FIG. 16). Therefore, the operational waveform diagram shown in FIG. 15 and the operational waveform diagram shown in FIG. 16 will be explained together.

[0237] The operating waveforms shown in FIGS. 15 and 16 will be explained in reference to the state transition diagram shown in FIG. In the state transition diagram shown in FIG. 3, the SDRAM transitions from the idle state indicated by 030 to the activated state indicated by 031 in the state transition diagram shown in FIG. 3 by receiving an ACT command input from an external device of the SDRAM at time T51 shown in the operation waveform diagrams of FIGS. 15 and 16, and transitions to the active state indicated by 032 in the state transition diagram shown in FIG. 3 by an automatic sequence without a command. In the state transition diagram shown in FIG. 3, the SDRAM transitions to the read state indicated by 033 in the state transition diagram shown in FIG. 3 by receiving an RD command input from an external device of the SDRAM at time T54 shown in the operation waveform diagrams of FIGS. 15 and 16, and transitions to the write state indicated by 036 in the state transition diagram shown in FIG. 3 by receiving a WRA command input from an external device of the SDRAM at time T57 shown in the operation waveform diagrams of FIGS. 15 and 16. After a predetermined time has elapsed since the SDRAM accepted data input from an external device, at time T62 shown in the operation waveform diagrams of Figures 15 and 16, an automatic sequence without a command causes the SDRAM to transition to the precharge state indicated by 037 in the state transition diagram shown in Figure 3, and then another automatic sequence without a command causes the SDRAM to transition to the idle state indicated by 030 in the state transition diagram shown in Figure 3. This is the sequence in which an ACT command input from an external device to the SDRAM is accepted at time T65 shown in the operation waveform diagrams of Figures 15 and 16.

[0238] The operational waveforms shown in FIGS. 15 and 16 can be compared with the state transition diagram of the first embodiment shown in FIG. 4 as follows. From the idle state indicated by 040 in the state transition diagram shown in Fig. 4, upon receiving an ACT command input from an external device of the SDRAM at time T51 shown in the operation waveform diagrams of Fig. 15 and 16 and an address signal ADr input from an external device of the SDRAM in synchronization with the ACT command, the memory cell(s) and data register(s) specified by the ADr transition to the activated state indicated by 041 in the state transition diagram shown in Fig. 4, transition to the active state indicated by 042 in the state transition diagram shown in Fig. 4 by an automatic sequence without a command, and transition to the read state indicated by 043 in the state transition diagram shown in Fig. 4 upon receiving an RD command input from an external device of the SDRAM at time T54 shown in the operation waveform diagrams of Fig. 15 and 16. Furthermore, upon receiving a WRA command input from an external device of the SDRAM at time T57 shown in the operation waveform diagrams of Fig. 15 and 16, transition to the write state indicated by 050 in the state transition diagram shown in Fig. 4. 15 and 16, after a predetermined time has elapsed, the memory cell(s) and data register(s) specified by ADr transition to the precharge state indicated by 053 in the state transition diagram shown in Fig. 4, and then transition to the idle state indicated by 040 in the state transition diagram shown in Fig. 4 via the precharge state indicated by 045 in the state transition diagram shown in Fig. 4 by an automatic sequence without a command. An ACT command input from a device external to the SDRAM is accepted at time T65 indicated in the operation waveform diagrams of Fig. 15 and 16, but the address signal input in synchronization with the ACT command from the device external to the SDRAM at time T65 indicated in the operation waveform diagrams of Fig. 15 and 16 is ADp, which is different from ADr, so the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram shown in Fig. 4.

[0239] Furthermore, the operating waveforms of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment shown in Figures 15 and 16 will be explained in reference to the state transition diagram shown in Figure 3 and the state transition diagram of the first embodiment shown in Figure 4. When an ACT command input from an external device to the SDRAM is received at time T51 shown in the operation waveform diagrams of Figures 15 and 16, the state transition diagram of Figure 3 transitions from the idle state indicated by 030 to the activated state indicated by 031. In the state transition diagram of Figure 4, the state transition diagram of Figure 4 transitions from the idle state indicated by 040 to the activated state indicated by 041. In synchronization with the timing of receiving the ACT command, an address signal input from a device external to the SDRAM is received at time T51 shown in the operational waveform diagrams of Figures 15 and 16. In the operational waveform diagrams of Figures 15 and 16, this signal is indicated as ADr. The address signal from the device external to the SDRAM is discriminated by an address receiver and address decoder indicated by reference numeral 112 in Figure 1, and the word line (WL) of the specified bank address and row address is biased from potential VIWL to potential VRWL at time T52 shown in the operational waveform diagrams of Figures 15 and 16 by a global word line selected and driven by a row decoder and global word line driver indicated by reference numeral 130 in Figure 2, and further by the global word line and local word line driver indicated by reference numeral 134 in Figure 2. The potential of the word lines (WL) (groups) of the addresses not specified by the ADr and the word lines (WL) (groups) of the sub-cell array (groups) remains at VIWL due to the global word lines driven in the unselected state by the row decoder and global word line driver shown in 130 of Figure 2, and further due to the global word lines and the local word line driver shown in 134 of Figure 2.

[0240] The source line (SL) (group) of the sub-cell array designated by the ADr is biased from the floating state to 0V at time T52 shown in the operation waveform diagrams of FIGS. The bit line (BL) (group) of the sub-cell array specified by ADr is biased from a floating state to a potential VRBL at time T52, passing through 0 V. The current flowing through each bit line (BL) via each memory cell is converted into a voltage by each BL sense amplifier connected to each bit line (BL), and the converted voltage is used to discriminate the data into "1" or "0", and the data is then stored in each data register associated with each bit line (BL). That is, the data read from each memory cell specified by the ADr is written to each data register specified by the ADr corresponding to each memory cell. Therefore, the data held in the memory cell(s) specified by the ADr is copied to the data register(s) specified by the ADr.

[0241] 15 and 16, when data storage in the data register is completed, the word line (WL) potential specified by the ADr is driven to VIWL, and the bit line (BL)(group) of the sub-cell array specified by the ADr starts discharging to 0V at time T53, after which the bit line (BL)(group) and the source line (SL)(group) specified by the ADr become floating. This results in a transition to the active state indicated by 032 in the state transition diagram of FIG. 3, and to the active state indicated by 042 in the state transition diagram of FIG. 4. The potentials of the word lines, bit lines, and source lines continue to be maintained until time T58 shown in the waveform diagrams of Figures 15 and 16. Therefore, the floating body state of each memory cell specified by ADr is maintained. Meanwhile, the data register(s) specified by ADr hold the same data as that held by the memory cell(s) specified by ADr.

[0242] When an RD command is input from a device external to the SDRAM at time T54 shown in the operation waveform diagrams of Figures 15 and 16, after tRCD (ACT Command to internal read or write delay time) has elapsed since the ACT command was received, the address signal input in synchronization with the RD command, and the data of the memory cell(s) at the bank address and column address specified by ADc are read out to a device external to the SDRAM. In the state transition diagram of Figure 3, this is the read state indicated by 033, and in the state transition diagram of Figure 4, it transitions to the read state indicated by 043. After CL (Column Latency) has elapsed since the RD command was received at time T54 shown in the waveform diagrams of Figures 15 and 16, data output begins at time T55 shown in the waveform diagrams of Figures 15 and 16. Since the BL8 setting is used, data is output eight times. In essence, among the data register(s) specified by ADr that hold the same data as the memory cell(s) specified by ADr, the data of the data register(s) specified by ADc and BL8 is read out to a device external to the SDRAM. Among the data register(s) specified by ADr, the data register(s) other than the data register(s) specified by ADc and BL8 are in a data holding state.

[0243] After the READ to WRITE command delay time has elapsed since the RD command was received, at time T57 shown in the operation waveform diagrams of Figures 15 and 16, if a WRA command is received from a device external to the SDRAM without receiving a single WR command since the ACT command was received, an erase operation is performed on the memory cell(s) connected to the word line of the bank address and row address specified by ADr, which are input in synchronization with the ACT command. This results in a transition to the write state shown as 036 in the state transition diagram of Figure 3 and the write state shown as 050 in the state transition diagram of Figure 4.

[0244] The potential of the word line of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VEWLH by the global word line selected and driven by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and the local word line driver shown as 134 in Fig. 2. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VEWLL by the global word line driven to the unselected state by the row decoder and global word line driver shown as 130 in Fig. 2, and further by the global word line and the local word line driver shown as 134 in Fig. 2, from the time T58 shown in the operation waveform diagrams of Fig. 15 and 16. The word line(s) belonging to the subarrays whose addresses are not specified by the ADr remain at the potential VIWL due to the global word lines driven in the unselected state by the row decoder and global word line driver shown as 130 in FIG. 2, and further due to the global word lines and the local word line driver shown as 134 in FIG. 2.

[0245] The source line(s) and bit line(s) of the sub-cell array specified by the ADr are biased from the floating state to the potential VEBL from time T58 shown in the operation waveform diagrams of Figures 15 and 16. On the other hand, the source line(s) and bit line(s) of the sub-cell array not specified by the ADr remain in the floating state.

[0246] By setting the potentials as described above, as described in the explanation of the operating waveform diagram in Figure 7 for the SDRAM of the first embodiment, the memory cell(s) connected to the word line of the bank address and row address specified by ADr are erased. At this point, the data held in the memory cell(s) specified by the ADr will be erased, but after the SDRAM of the first embodiment transitions to state 053 shown in the state transition diagram of Figure 4, it rewrites the data that has been copied to the data register(s) specified by the ADr and remains in the memory cell(s), so no data loss occurs in the memory cell(s). On the other hand, among the memory cells (groups) connected to word lines of bank addresses and row addresses not specified by ADr, the memory cells (groups) belonging to the unselected sub-cell array are in an idle state, and the sub-cell array is in a selected state. The relationship between the potential of each floating body of the memory cells (groups) connected to the unselected word line (groups) and the potential of the bit line and source line is almost the same as in the idle state, so the charge of the floating body is maintained.

[0247] To complete the erase operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr are discharged to 0V and then placed in a floating state at time T60, a time set within the SDRAM device after time T58 shown in the operation waveform diagrams of Figures 15 and 16. The potential of the word line of the sub-cell array specified by ADr is biased from VEWLH or VEWLL to VIWL at time T60 shown in the operation waveform diagrams of Figures 15 and 16, and the sub-cell array specified by ADr enters an idle state. The potentials of the word lines, bit lines, and source lines continue to be in the above-described state until time T63 shown in the operation waveform diagrams of Figures 15 and 16. Therefore, the state of the floating body of each memory cell specified by ADr is maintained.

[0248] 15 and 16, which is a predetermined WL (Write Latency) time after the WRA command is received, and since the burst length is 8 (BL8), 8 sets of data are sequentially input from the DQ signal line shown in FIG. 1 as shown in the operation waveform diagrams of FIG. 15 and 16, and the input data is sensed and amplified by the data input receiver shown as 118 in FIG. 1 and then stored in the data input register shown as 119 in FIG. 1. In the case of the operation waveform diagram of FIG. 15, after being stored in the data input register, the data is written from the data input register shown as 119 in FIG. 1 to the data register(s) in the area 133 in FIG. 2, which is specified by the ADd and BL8 among the data register(s) specified by the ADr, by the IO driver shown as 123 in FIG. 1. On the other hand, among the data register(s) specified by the ADr, the data registers that are not specified by the ADd and BL8 hold the same data as the memory cells that can be connected to the same bit line (BL) specified by the ADr. 16, after storing in the data input register, the data is written from the data input register shown as 119 in FIG. 1 to the data register(s) in the area 133 in FIG. 2, which are specified by the ADc and BL8 among the data register(s) specified by the ADr, by the IO driver shown as 123 in FIG. 1. On the other hand, among the data register(s) specified by the ADr, the data register(s) not specified by the ADc and BL8 hold the same data as the memory cell connectable to the same bit line (BL) specified by the ADr. In the SDRAM according to the first embodiment, depending on the WRA command, writing is not performed to the memory cell(s), and input data is only written to ADr and ADd (in the case of the operational waveform diagram of FIG. 15) or ADc (in the case of the operational waveform diagram of FIG. 16), and also to the data register present in 133 in FIG. 2 associated with the sub-cell array of the address specified by BL8. The fact that no inconvenience occurs even if data writing to the memory cells is not completed was mentioned when explaining the operational waveforms of the SDRAM according to the first embodiment in FIGS. 9 and 10. Furthermore, as mentioned when explaining the operating waveforms of the SDRAM according to the first embodiment in Figures 9 and 10, it does not matter whether the bank address and column address specified when the RD command is issued are the same as or different from the bank address and column address specified when the WRA command is issued.

[0249] 7, the write operation to the data register(s) in the area 133 in FIG. 2, which is specified by ADc and BL8 among the data register(s) specified by ADr, and the erase operation to the memory cell(s) connected to the word line of the bank address and row address specified by ADr, are performed in parallel and independently, so depending on the WL (Write Latency) setting value and the clock period, the timing of the erase operation start time and the data input start time may differ, and there is no problem if they do. The timing of the erase operation end time and the data input / output completion time may also differ, and there is no problem if they do.

[0250] After data input is complete, at time T62 after tWR (Write Recovery Time) has elapsed, even without inputting a PRE command, an automatic sequence transitions to the precharge state indicated by 037 in the state transition diagram of FIG. 3 in accordance with the SDRAM specifications. In the SDRAM of this embodiment, the memory cells and data registers that were in the active state transition to the precharge state indicated by 053 in FIG. 4. That is, at time T62 shown in the operation waveform diagram of FIG. 8, a write operation of the data in the data register(s) specified by ADr to the memory cell(s) connected to the word line of the bank address and row address specified by ADr is started. A transition is made to the precharge state indicated by 037 in the state transition diagram of FIG. 3 and the precharge state indicated by 053 in the state transition diagram of FIG. 4. Since "0" data has already been written by the erase operation, the write sequence here writes "1" to the memory cell(s) corresponding to the data registers holding "1" data, and the memory cells corresponding to the data registers holding "0" data are maintained in the state where "0" data has already been written.

[0251] The potential of the word line of the bank address and row address specified by ADr is biased from the potential VIWL to the potential VWWLH at time T63 shown in the operation waveform diagrams of Figures 15 and 16 by the global word line selected and driven by the row decoder and global word line driver shown in Figure 2, and further by the global word line and local word line driver. Of the word line(s) not specified by ADr, the unselected word line(s) whose sub-cell array is in the selected state are biased from the potential VIWL to the potential VWWLL at time T63 shown in the operation waveform diagrams of Figures 15 and 16 by the global word line and local word line driver driven in the unselected state by the row decoder and global word line driver shown in Figure 2. The word line(s) belonging to the sub-array of the address not specified by ADr remain at the potential VIWL by the global word line driven in the unselected state by the row decoder and global word line driver shown in Figure 2, and further by the global word line and local word line driver. The source line(s) of the sub-cell array designated by ADr are biased from the floating state to 0V at time T63 shown in the operation waveform diagrams of FIGS. The bit line(s) of the sub-cell array specified by ADr are biased in potential according to the data stored in the data register(s) corresponding to the bit line(s). If the data in the data register is "0", the bit line (BL) is biased from the floating state to 0V at time T63 shown in the operation waveform diagrams of Figures 15 and 16. If the data in the data register is "1", the bit line (BL) is biased from the floating state to potential VWBL at time T63. On the other hand, the source line(s) and bit line(s) of the sub-cell arrays not specified by the ADr remain in a floating state.

[0252] With the above potential settings, among the memory cells (group) connected to the word line of the bank address and row address specified by ADr, the memory cells (group) whose bit lines (BL) are biased with VWBL pass a current, which causes impact ionization, and the generated holes (group) accumulate in the floating body of each memory cell, and the electrons (group) are discharged to the bit line (BL), thereby writing data "1." On the other hand, in the memory cells (group) whose bit lines (BL) are biased with 0V, the bit line (BL) and source (line) have the same potential, so no current passes, and therefore no impact ionization occurs, and the floating body of each memory cell maintains the erased state, meaning that data "0" has been written. That is, data is read from each data register specified by ADr, and the read data is written to each memory cell specified by ADr corresponding to the data register. In addition to the data written by the WR command or WRA command, the data lost by the erase operation is copied and saved in the data register(s). Therefore, no data is lost in the memory cells due to the erase operation.

[0253] The memory cells (group) connected to the word lines of the bank addresses and row addresses not specified by ADr are in an idle state, and therefore the floating body state of each memory cell is maintained.

[0254] To complete the write operation, the source line(s) and bit line(s) of the sub-cell array specified by ADr are floated at time T64, a time set within the SDRAM device from time T63 shown in the waveform diagrams of Figures 15 and 16. The potential of the word line of the sub-cell array specified by ADr is biased from VWWLH or VWWLL to 0V at time T64, and the sub-cell array specified by ADr enters an idle state. The potentials of the word lines, bit lines, and source lines remain constant until time T65 shown in the waveform diagrams of Figures 15 and 16. By an automatic sequence without a command, the state transitions to the precharge state indicated by 045 in the state transition diagram of Fig. 4. In the state transition diagram of Fig. 3, the state remains in the precharge state indicated by 037. The state of the floating body of each memory cell specified by the ADr is maintained, and each data register specified by the ADr is reset. Furthermore, an automatic sequence without a command causes the device to transition to the idle state indicated by 030 in the state transition diagram of Fig. 3 and to the idle state indicated by 040 in the state transition diagram of Fig. 4. The state of the floating body of each memory cell designated by the ADr is maintained, and each data register designated by the ADr is maintained in the reset state.

[0255] At time T65 shown in the operational waveform diagrams of Figures 15 and 16, an ACT command is received from a device external to the SDRAM. However, since the address signal received at time T65 shown in the operational waveform diagrams of Figures 15 and 16 is ADp, which is different from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state indicated by 040 in the state transition diagram of Figure 4. Therefore, until the ACT command and ADp are received as an address signal synchronized with the ACT command, even after time T65 shown in the operation waveform diagrams of Figures 15 and 16, the potential of each word line (WL) remains at VIWL, and each bit line (BL) and each source line (SL) remains in a floating state. However, the SDRAM transitions from the idle state 030 to the activated state 031 shown in the state transition diagram of FIG.

[0256] Figure 17 shows an operational waveform diagram for a sequence in which an ACT command is issued to activate the memory cell(s) at the bank address and row address specified by ADr, and a PRE command is issued to transition the active memory cell(s) at the bank address and row address specified by ADr to an idle state.

[0257] In the first embodiment, the operational waveforms in FIG. 17 are compared with the state transition diagram in FIG. 3 as follows. The operation waveforms in Fig. 17 transition from the idle state indicated by 030 in the state transition diagram of Fig. 3 to the activated state indicated by 031 in the state transition diagram of Fig. 3 by accepting an ACT command input from an external device at time TC1 shown in the operation waveform diagram of Fig. 17, transition to the active state indicated by 032 in the state transition diagram of Fig. 3 by an automatic sequence without a command, transition to the precharge state indicated by 037 in the state transition diagram of Fig. 3 by accepting a PRE command input from an external device at time TC4 shown in the operation waveform diagram of Fig. 17, and then transition to the idle state indicated by 030 in the state transition diagram of Fig. 3 by an automatic sequence without a command. This is the sequence in which an ACT command input from an external device of the SDRAM is accepted at time TC5 shown in the operation waveform diagram of Fig. 17.

[0258] In the first embodiment, the operational waveforms in FIG. 17 are compared with the state transition diagram in FIG. 4 as follows. The operation waveforms in Fig. 17 transition from the idle state 040 shown in the state transition diagram of Fig. 4 to the activated state 041 shown in the state transition diagram of Fig. 4 by receiving an ACT command input from an external device at time TC1 shown in the operation waveform diagram of Fig. 17 and an address signal ADr received in synchronization with the ACT command. Furthermore, an automatic sequence transitions to the active state 042 shown in the state transition diagram of Fig. 4. By receiving a PRE command input from an external device at time TC4 shown in the operation waveform diagram of Fig. 17, the device transitions to the precharge state of 045 shown in the state transition diagram of Fig. 4, and after a predetermined time has passed, it transitions to the idle state of 040 shown in the state transition diagram of Fig. 4 by an automatic sequence without a command. An ACT command input from an external device is received at time TC5 shown in the operation waveform diagram of Fig. 17, but since the address signal received at time TC5 shown in the operation waveform diagram of Fig. 17 is ADp, which differs from ADr, the memory cell(s) and data register(s) specified by ADr remain in the idle state of 040 shown in the state transition diagram of Fig. 4. This is the sequence.

[0259] Furthermore, the operating waveforms of the word lines (WL), bit lines (BL), and source lines (SL) of the SDRAM according to the first embodiment shown in FIG. 17 will be explained in comparison with the state transition diagram shown in FIG. 3 and the state transition diagram of the first embodiment shown in FIG. 4. When an ACT command input from an external device to the SDRAM is received at time TC1 shown in the operation waveform diagram of Fig. 17, the state transition diagram of Fig. 3 transitions from the idle state indicated by 030 to the activated state indicated by 031. In the state transition diagram of Fig. 4, the state transition diagram of Fig. 4 transitions from the idle state indicated by 040 to the activated state indicated by 041. In synchronization with the timing of receiving the ACT command, an address signal input from a device external to the SDRAM is received at time TC1 shown in the operational waveform diagram of FIG. 17. In the operational waveform diagram of FIG. 17, this signal is indicated as ADr. The address signal from the device external to the SDRAM is discriminated by the address receiver and address decoder indicated by 112 in FIG. 1, and the word line (WL) of the designated bank address and row address is biased from potential VIWL to potential VRWL at time TC2 by the global word line selected and driven by the row decoder and global word line driver indicated by 130 in FIG. 2, and further by the global word line and local word lin...

Claims

1. A clock synchronous semiconductor memory device having a memory cell array on a semiconductor substrate, the memory cells being arranged in a matrix in two directions perpendicular to each other in a plan view, a data register for temporarily storing data between the memory cell array and an input / output terminal of the clock synchronous semiconductor memory device; Furthermore, the clock synchronous semiconductor memory device has an instruction set which is a collection of instructions (commands) for operating the clock synchronous semiconductor memory device, The instruction set is an active command for selecting the memory cell; a precharge command for releasing the selected state of the memory cell; a write command for inputting data from the input / output terminal; a plurality of auto-precharge commands for releasing the selected state of the memory cell regardless of the precharge command; data inputted from the input / output terminal of the clock synchronous semiconductor memory device is written into the data register in response to the write command; After receiving the precharge command or any one of the plurality of auto-precharge commands, the data stored in the data register is written to the memory cell selected by the active command while the selected state of the memory cell is released.

2. A clock synchronous semiconductor memory device comprising:

2. The instruction set includes: a read command for outputting data from the input / output terminal, a write command with auto precharge for inputting data from the input / output terminal and releasing the selected state of the memory cell after completing the data input, and a read command with auto precharge for outputting data from the input / output terminal and releasing the selected state of the memory cell after starting the data output, In response to the write command, data input from the input / output terminal is written to the data register; After the precharge command is accepted, or after a first time has elapsed since the read command with auto precharge is accepted, or after a second time different from the first time has elapsed since the write command with auto precharge is accepted, an operation of writing the data stored in the data register to the memory cell selected by the active command is started.

2. The clock synchronous semiconductor memory device according to claim 1.

3. The data registers are disposed adjacent to the memory cell array, and the number of the data registers is equal to the number of memory cells selected by the active command.

2. The clock synchronous semiconductor memory device according to claim 1.

4. The data registers are disposed adjacent to the memory cell array, and the number of the data registers is equal to the number of memory cells selected by the active command in the memory cell array disposed adjacent to the data registers.

2. The clock synchronous semiconductor memory device according to claim 1.

5. The memory cell has a structure including a MOS field effect transistor in which at least a part of a floating body serving as a storage node becomes a current path.

2. The clock synchronous semiconductor memory device according to claim 1.

6. Data that can be stored in the memory cell is a binary logic level, After the data stored in the selected memory cell is written to the data register by the active command, a write operation of data of one of the two-valued logics is performed on all of the selected memory cells.

3. The clock synchronous semiconductor memory device according to claim 2.

7. Data that can be stored in the memory cell is a binary logic level, The data stored in the data register is written to the memory cell selected by the active command by a signal different from a control signal for writing data of one of the two logic values ​​to all the selected memory cells.

7. The clock synchronous semiconductor memory device according to claim 6.

8. An operation of inputting data via the input / output terminal, or an operation of outputting data via the input / output terminal; An operation of writing data of one of the two logic values ​​to all the selected memory cells is performed independently and in parallel.

7. The clock synchronous semiconductor memory device according to claim 6.

9. By receiving the write command or the auto-precharge write command, a write operation of data of one of the two-valued logics is performed on all of the selected memory cells.

7. The clock synchronous semiconductor memory device according to claim 6.

10. Only when either the write command or the auto-precharge write command is received first after the active command is received, a write operation of data of one of the two logic values ​​is performed on all of the selected memory cells by the write command or the auto-precharge write command.

10. The clock synchronous semiconductor memory device according to claim 9.

11. Even if the read command or the auto-precharge read command is received, a write operation of data of one of the two-valued logics is performed on all of the selected memory cells.

10. The clock synchronous semiconductor memory device according to claim 9.

12. Only when any one of the write command, the write command with auto precharge, the read command, or the read command with auto precharge is first received after the active command is received, a write operation of data of one of the two logic values ​​is performed on all of the selected memory cells.

12. The clock synchronous semiconductor memory device according to claim 11.

13. One end of the memory cell is connected to a bit line, and the other end is connected to a source line. Data stored in the memory cell is determined by the amount of current flowing between the bit line and the source line. The extension direction of the bit line and the extension direction of the source line are arranged in parallel.

2. The clock synchronous semiconductor memory device according to claim 1.

14. The bit line connected to one end of one of the memory cells and the source line connected to the other end of the memory cell are in different wiring layers, and all of the bit lines in the memory cell array are in the same wiring layer, and all of the source lines are in the same wiring layer.

14. The clock synchronous semiconductor memory device according to claim 13.

15. The bit line connected to one end of one of the memory cells and the source line connected to the other end of the memory cell are in different wiring layers, and the bit lines formed in different wiring layers exist in the memory cell array.

14. The clock synchronous semiconductor memory device according to claim 13.

16. The bit line connected to one end of one of the memory cells and the source line connected to the other end of the memory cell are in different wiring layers, and the source lines formed in different wiring layers exist in the memory cell array.

14. The clock synchronous semiconductor memory device according to claim 13.

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