Micro light emitting device, growth substrate and manufacturing method

Abstract

To realize a micro light-emitting element that is both minute and highly efficient.SOLUTION: A micro light emitting element (100) includes a nitride semiconductor layer (14) in which an N-type layer (11), a light emitting layer (12) and a P-type layer (13) are stacked, and a plurality of V-pits (40), when viewed in the stacking direction of the nitride semiconductor layer (14), are respectively located at positions corresponding to the vertices of a polygon in an area of the nitride semiconductor layer (14).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to micro light emitting devices, growth substrates and methods of manufacture. [Background technology]

[0002] There is known an image display element in which a plurality of micro light-emitting elements constituting pixels are arranged on a substrate (backplane). For example, in the technology disclosed in Patent Document 1, a minute light-emitting diode (LED) array that emits visible light is arranged on a drive circuit substrate on which a drive circuit is formed.

[0003] Such image display elements are small yet have high brightness and durability, and are therefore expected to be used as display elements for glasses-like devices, head-up displays (HUDs), and the like.

[0004] When incorporating an image display element into a glasses-type terminal, it is necessary to efficiently capture the generated light into the optical system, and it is necessary to suppress the divergence of the light emitted from the image display element. In Patent Document 1, a reflective wall is provided around the light-emitting diode to suppress the divergence of the light emitted to the outside. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Publication No. 2018 / 0090058 Summary of the Invention [Problem to be solved by the invention]

[0006] In image display elements for glasses-type terminals and head-up displays, in order to realize bright display, it is necessary to control the light distribution so that the light emitted from the pixels is concentrated forward. For this reason, light distribution control elements such as reflectors, microlenses, photo crystals, and antenna elements are used in combination with micro-light-emitting elements. In order to make these light distribution control elements function efficiently, it is necessary to make the micro-light-emitting elements serving as light sources as small as possible. On the other hand, in order to increase the resolution of the image display element, the pixel size becomes smaller, and in order to arrange the micro-light-emitting elements and the reflecting walls therein, the micro-light-emitting elements must be much smaller than the pixel size. For example, if the pixel size is 5 to 2 μm, the length of one side of the micro-light-emitting element must be 2.5 to 1 μm at the longest, and is preferably even smaller than 1 μm.

[0007] As described above, in order to realize a micro- or sub-micron-sized micro-light-emitting element, it is necessary to finely process a nitride semiconductor such as gallium nitride that constitutes the micro-light-emitting element. However, compound semiconductors such as nitride semiconductors are prone to defects on the processed surface, and the light-emitting efficiency is easily reduced. Therefore, in order to realize a high-resolution image display element, it is important to realize a fine micro-light-emitting element without reducing the light-emitting efficiency.

[0008] One aspect of the present invention has been made in consideration of the above problems, and an object of the present invention is to realize a micro-light-emitting element that is fine and has high light-emitting efficiency. [Means for solving the problem]

[0009] In order to solve the above problems, a micro light-emitting device according to one aspect of the present invention includes an N-type layer and Emitting layer and P type layer And stacked The nitride semiconductor layer includes a nitride semiconductor layer, and when viewed in a stacking direction of the nitride semiconductor layer, 6 V Pit Cross section of In the region of the nitride semiconductor layer, Sho Roku Vertex of a rectangle IncludesEach is placed in a different position. Cage , The length of one side is 5 μm or less .

[0010] In order to solve the above problems, a growth substrate according to one aspect of the present invention comprises: Manufacture micro light-emitting devices with a side length of 5 μm or less. A growth substrate for growing a nitride semiconductor layer, the growth substrate having a surface having a protrusion Sho Roku Vertex of a rectangle Includes Unit cells including an array of protrusions arranged at positions are arranged in a two-dimensional array.

[0011] In order to solve the above problems, a method for manufacturing a micro light-emitting element according to one aspect of the present invention includes a step of growing a nitride semiconductor layer on a growth substrate, and a step of removing a part of the nitride semiconductor layer to form a plurality of mesa portions. The length of one side is 5 μm or less A method for manufacturing a micro light emitting device, comprising: Sho Roku Vertex of a rectangle Includes Unit cells including a protrusion array arranged at a position are arranged in a two-dimensional array, and the mesa portion is formed in a central region of the protrusion array. Effect of the Invention

[0012] According to one aspect of the present invention, a micro light-emitting element that is fine and has high light-emitting efficiency can be realized. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view of a micro light-emitting element according to a first embodiment of the present invention. [Diagram 2] 2 is a schematic plan view of the AA cross section of FIG. 1. FIG. [Figure 3A] 2 is a schematic diagram showing a planar arrangement of unit cells of protrusions formed on the surface of a growth substrate used in manufacturing a micro light-emitting element according to embodiment 1. FIG. [Figure 3B] FIG. 2 is a schematic diagram showing a planar arrangement of V-pits formed after growing a nitride semiconductor layer. [Figure 3C] 10 is a schematic diagram showing a planar arrangement of unit cells of a protrusion according to a modified example of the first embodiment. FIG. [Figure 4] 2A to 2C are cross-sectional views illustrating a manufacturing process of the micro light-emitting element according to the first embodiment. [Diagram 5] 2A to 2C are cross-sectional views illustrating a manufacturing process of the micro light-emitting element according to the first embodiment. [Figure 6] 2A to 2C are cross-sectional views illustrating a manufacturing process of the micro light-emitting element according to the first embodiment. [Figure 7] 3A to 3C are schematic cross-sectional views of a nitride semiconductor layer in a manufacturing process of the micro light-emitting device according to the first embodiment. [Figure 8] 4 is a flowchart showing a manufacturing process of the micro light-emitting element according to the first embodiment. [Figure 9] FIG. 5 is a schematic cross-sectional view of a micro light-emitting element according to a second embodiment of the present invention. [Figure 10] 5A to 5C are cross-sectional views illustrating a manufacturing process of the micro light-emitting element according to the second embodiment. [Figure 11] 5A to 5C are cross-sectional views illustrating a manufacturing process of the micro light-emitting element according to the second embodiment. [Figure 12] 5A to 5C are cross-sectional views illustrating a manufacturing process of the micro light-emitting element according to the second embodiment. [Figure 13] 11 is a graph showing the luminance distribution of a micro light-emitting element according to an embodiment and a micro light-emitting element according to a comparative example. [Figure 14A] FIG. 1 is a schematic cross-sectional view of a nitride semiconductor layer according to a conventional technique. [Figure 14B] 1 is a surface image of a light-emitting layer in a nitride semiconductor layer according to the prior art, observed by AFM. [Figure 14C] FIG. 1 is a schematic plan view showing an arrangement of protrusions on a surface of a growth substrate according to a conventional technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] [Embodiment 1] (Overall structure of image display element) A micro light-emitting element according to a first embodiment of the present invention, which is used in an image display element, will be described below. First, a rough overall structure of the image display element will be described. The image display element is flat, and a pixel region in which a plurality of micro light-emitting elements are arranged is formed on the first surface side. A drive circuit board is arranged on the surface side opposite to the first surface of the micro light-emitting element. The drive circuit board supplies a current to the micro light-emitting element formed in the pixel region to control light emission. The micro light-emitting element is arranged on the first surface side of the drive circuit board, and although the following description will be given taking the case where light is emitted to the first surface side as an example, the light emission direction is not limited to the first surface side.

[0015] The micro-light-emitting elements may be arranged in an array in the pixel region. Arranged in an array means that they are arranged regularly or according to a predetermined rule. The micro-light-emitting elements emit light in a direction opposite to the drive circuit board. The emitted light is referred to as emitted light. Unless otherwise specified, the surface from which the micro-light-emitting element emits light is called a light-emitting surface. In addition, in the description of the configuration of the image display element, unless otherwise specified, the light-emitting surface is called the upper surface (first surface), the surface opposite to the light-emitting surface side is called the lower surface (second surface), and the lateral surfaces other than the upper surface and the lower surface are called side surfaces. These names are expressions that correspond to the directions in a cross section perpendicular to the light-emitting surface when the light-emitting surface is viewed facing upward. Similarly, the light-emitting direction is called upward, and the opposite direction is called downward. In addition, the direction perpendicular to the light-emitting surface and toward the air is also called forward.

[0016] The micro light emitting device is a light emitting diode device including a nitride semiconductor layer, which allows the realization of a micro light emitting device capable of emitting light in the wavelength range from ultraviolet to red.

[0017] The micro light emitting element has an anode electrode and a cathode electrode, and is connected to a driving electrode on a driving circuit board. The electrodes and protective film of the micro light emitting element, other than the nitride semiconductor layer, are not directly related to the present invention, so detailed description thereof may be omitted below.

[0018] In the driving circuit board, a micro light emitting element driving circuit for controlling the current supplied to each micro light emitting element is arranged (bonded) in an area facing the pixel area. In addition, in the driving circuit board, a row selection circuit for selecting each row of the micro light emitting elements arranged in a two-dimensional matrix, a column signal output circuit for outputting a light emission signal to each column, an image processing circuit for calculating a light emission signal based on an input signal, an input / output circuit, etc. are arranged outside the area facing the pixel area. On the surface of the bonding surface side of the driving circuit board, a P-drive electrode (second drive electrode) and an N-drive electrode (first drive electrode) for connecting with the micro light emitting element are arranged. The driving circuit board is generally a silicon substrate (semiconductor substrate) on which an LSI is formed, or a glass substrate or a plastic substrate on which a TFT (thin film transistor) is formed, and can be manufactured by a known technology, so its function and configuration will not be described in detail.

[0019] The shape of the micro light-emitting element when viewed from a direction perpendicular to the pixel region is not particularly limited. The shape of the micro light-emitting element may be various planar shapes such as a rectangle, a polygon, a circle, an ellipse, etc. In many cases, the maximum length (width) of the micro light-emitting element when viewed from a direction perpendicular to the pixel region is 5 μm or less, but is not limited to this. In addition, an image display element often has 3,000 or more micro light-emitting elements integrated in a pixel region, but is not limited to this.

[0020] (Problems with the Prior Art) Next, in order to clarify the features of this embodiment, the configuration of the conventional micro light-emitting device and its problems will be described. Note that components corresponding to those in this embodiment will be described by using the same reference numerals as those in this embodiment.

[0021] 14A shows a schematic cross-sectional view of a V-pit in a conventional nitride semiconductor layer. The inside of the V-pit is filled with a multiple quantum well layer constituting a light emitting layer 12 and a P-type layer 13. A multilayer film having the same layer structure as the multiple quantum well layer is deposited on the facet of the V-pit.

[0022] FIG. 14B shows an image of the surface of a conventional nitride semiconductor layer observed by AFM (Atomic Force Microscopy) after the growth of the nitride semiconductor layer was stopped after the growth of the light emitting layer 12. The black areas are the openings of the V pits. FIG. 14B shows an observation of an area of ​​5 μm square, and the density of the V pits is 1.5E8 / cm 2 (1.5×10 8 / cm 2 ) The length (diameter) of the V pit opening at the end of the growth of the light-emitting layer 12 is preferably about 100 nm to 300 nm, and if it is larger or smaller than this, the light-emitting characteristics of the light-emitting layer will deteriorate. When the P-type layer 13 is grown, the V pit opening (hole) is filled and the surface is flattened. Although it is difficult to see in Figure 14B, the planar shape of the V pit opening is often hexagonal, and the facet surface of the V pit is thought to be composed of a specific crystal plane of the nitride semiconductor.

[0023] In the conventional manufacturing method, it is possible to control the position in the depth direction of the epitaxial layer where the formation of the V pit starts (the starting point of the V pit) during the growth of the nitride semiconductor layer 14. However, since the position where the V pit occurs in the horizontal direction cannot be controlled, the position where the V pit occurs in the horizontal plane is random, as shown in FIG. 14B. In other words, it is not possible to control how many V pits a micro light emitting element contains per unit area, or where the V pits are formed in the micro light emitting element. Therefore, in micro light emitting elements formed by the conventional method, there is a large variation in the number of V pits contained per unit area and the position of the V pits in the plane of the micro light emitting element. In the conventional method, the plane density of the V pits is 1E8 pits / cm 2 ~5E8 pieces / cm 2 In other words, the area of ​​the light-emitting layer of a micro light-emitting element is about 1 μm 2 In this case, the average number of V pits is about 1 to 5. For example, if the V pit distribution is a planar density of 1E8 pits / cm 2 Assuming a Poisson distribution of , one micro light emitting element (1 μm 2 In most cases, the number of V pits included in the disk is between 0 and 4, but there are also cases where the number is even greater.

[0024] Since the V pit itself does not have a light-emitting layer intentionally formed, it does not emit light, or even if it does emit light, the intensity of the light emission is low. Therefore, as described above, the number of V pits contained in the micro light-emitting element varies greatly, which means that the light-emitting efficiency of the micro light-emitting element varies greatly.

[0025] In addition, there is another factor of variation in light emission intensity, in that the effect of V pits present on the outer periphery of the light emitting layer of the micro light emitting element is minor, while the effect of V pits present in the center is major. When processing the mesa portion of the micro light emitting element, the light emitting layer 12 on the periphery of the mesa portion has low light emission efficiency due to processing damage, so even if there is a V pit on the periphery of the mesa portion, the effect is minor. However, the effect of a V pit present in the center of the mesa portion on the light emission intensity is significant. As described above, in a micro light emitting element having a fine mesa portion of micron size, there is a problem in that the randomness of the V pits causes large variations in light emission efficiency.

[0026] In contrast, the embodiment of the present invention can reduce the variation in luminous efficiency of the micro light-emitting device of the above-mentioned conventional technology. Specifically, since the V-pit occurs mainly due to threading dislocations existing in the nitride semiconductor layer 14, the micro light-emitting device 100 of the present embodiment can be realized by controlling the position where the threading dislocations occur. The configuration and manufacturing method of the micro light-emitting device 100 according to the present embodiment will be described below with reference to the drawings.

[0027] (Configuration of the micro light emitting element 100) The configuration of the micro light-emitting element 100 according to the first embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a schematic cross-sectional view of the micro light-emitting element 100 according to the first embodiment. Fig. 1 is a view taken along the line BB in Fig. 2. Fig. 2 is a schematic plan view of the micro light-emitting element 100 taken along the line AA in Fig. 1 (also referred to as a horizontal cross-section), that is, as viewed in the stacking direction of the nitride semiconductor layers 14. Hereinafter, viewing in the stacking direction of the nitride semiconductor layers 14 is also referred to as a planar view.

[0028] The micro light emitting element 100 includes a nitride semiconductor layer 14 in which an N-type layer 11, a light emitting layer 12, and a P-type layer 13 are stacked, and when viewed in the stacking direction of the nitride semiconductor layer 14, a plurality of V pits 40 are arranged at positions corresponding to the vertices of a polygon in the region of the nitride semiconductor layer 14. The micro light emitting element 100 includes an N-electrode 24N connected to the N-type layer 11, and a P-electrode 23P connected to the P-type layer 13. As shown in FIG. 1 and FIG. 2, most of the side surface of the nitride semiconductor layer 14 on the P-type layer 13 side is surrounded by the facets of the plurality of V pits 40.

[0029] The region of the nitride semiconductor layer 14 is a region in which the N-type layer 11, the light emitting layer 12, and the P-type layer 13 are at least partially laminated when viewed in the lamination direction of the nitride semiconductor layer 14 in one micro light emitting element 100. For example, the region of the nitride semiconductor layer 14 is a region of a mesa portion described later. However, the V pit 40 does not have to be entirely disposed within the region of the nitride semiconductor layer 14. For example, a plurality of V pits 40 formed at positions corresponding to the vertices of a polygon may be partially removed by etching or the like in the formation process of the micro light emitting element 100. It is difficult to strictly control the position of the V pit 40. Therefore, "the V pit 40 is disposed at a position corresponding to the vertex of a polygon" means that, for example, the vertices of the polygon are disposed within the cross section of the V pit 40 when viewed in a plane.

[0030] The polygon is preferably an n-gon, where n is an integer, and n is greater than or equal to 6. This is because, when the facet surface of the V pit 40 is viewed in a plan view, it is likely to be an n-gon, where n is greater than or equal to 6. In particular, when the facet surface of the V pit 40 is viewed in a plan view, it is likely to be a regular hexagon, and therefore the polygon is particularly preferably a regular hexagon. By arranging the V pit 40 at a position corresponding to the vertex of a regular hexagon, the light-emitting layer 12 surrounded by six V pits 40 is likely to be a regular hexagon when viewed in a plan view. In this embodiment, the polygon is a regular hexagon.

[0031] Furthermore, when the light emitting layer 12 is viewed in the stacking direction of the nitride semiconductor layer 14, an end of the light emitting layer 12 contacts with each facet surface of the multiple V pits 40. The end of the light emitting layer 12 is the end on the side surface of the light emitting layer 12 in FIG. 1. As shown in FIG. 1, the end on the side surface of the light emitting layer 12 contacts with the facet surface of the V pit 40.

[0032] In addition, when the light emitting layer 12 is viewed in the stacking direction of the nitride semiconductor layer 14, the facet surface to which the end of the light emitting layer 12 contacts has a shape similar to a polygon. This polygon is the shape of the arrangement of the convex parts formed on the growth substrate for growing the nitride semiconductor layer 14, as described later. As shown in FIG. 1 and FIG. 2, the end on the side surface side of the light emitting layer 12 abuts on the facet surfaces of the multiple V pits 40. When the light emitting layer 12 is viewed in a plane, the abutting facet surface has a shape similar to the shape of the arrangement of the convex parts formed on the growth substrate. In the example shown in FIG. 1 and FIG. 2, the horizontal end of the light emitting layer 12 abuts on the facet surfaces of six V pits 40, and the abutting part has a hexagonal shape when viewed in a plane. This hexagon is similar to the hexagonal shape of the arrangement of the convex parts formed on the growth substrate.

[0033] The V pit 40 is a V-shaped depression in cross section that occurs during the growth of the N-type layer 11. As described above, the V pit 40 is mainly caused by threading dislocations. The surface of the depression of the V pit 40 has a facet surface that is specific to the V pit 40. In the next stage of growing the light-emitting layer 12, the light-emitting layer 12 is thinly formed on the surface of the depression of the V pit 40. In the next stage of growing the P-type layer 13, the P-type layer 13 grows so as to fill the depression of the V pit 40. In this embodiment, the pyramidal depression formed during the growth of the light-emitting layer 12 from the N-type layer 11 and the P-type layer 13 filling the depression are collectively referred to as the V pit 40.

[0034] The facet surface of the V-pit is a specific crystal surface formed when the nitride semiconductor layer 14 is grown, and is different from the surface that is processed by plasma etching or the like after the nitride semiconductor layer 14 is formed.

[0035] In Fig. 1, the length of one side of the nitride semiconductor layer 14 including the light emitting layer 12 is called the mesa dimension. The length of the micro light emitting element 100 is represented by the mesa dimension. As shown in Fig. 2, when viewed from the P-type layer 13 side, a plurality of V pits 40 are arranged on the outer periphery of the nitride semiconductor layer 14. In other words, the V pits 40 are not arranged in the central region of the nitride semiconductor layer 14.

[0036] 2, adjacent V pits 40 are not in contact with each other, but may be in contact with each other. In the micro light emitting element 100, light is emitted from the light emitting layer 12 in a portion (light emitting region 3) where there are no V pits 40 in the center on the P-type layer 13 side.

[0037] As shown in FIG. 2, the P-electrode 23P is formed in a range covering the light-emitting region 3 when viewed from below. The P-electrode 23P may be formed in a range covering not only the light-emitting region 3 but also at least partially the V-pit 40. In this embodiment, as shown in FIG. 1, the N-type layer 11 is T-shaped, and the N-electrode 24N is disposed on the lower side (the drive circuit board 50 side) of the horizontally extending portion. The N-electrode 24N is preferably a metal film having high reflectivity. In the example shown in FIG. 1, the N-type layer 11 is continuous (i.e., shared) between adjacent micro light-emitting elements 100, but may be independent for each micro light-emitting element 100.

[0038] In this embodiment, as shown in Fig. 2, for one micro light-emitting element 100, six V pits 40 are arranged at positions corresponding to the vertices of a regular hexagon when viewed from below. A light-emitting region 3 is arranged in a central region surrounded by the six V pits 40. By arranging the V pits 40 at positions corresponding to the vertices of a polygon in this way, a region in which the V pits 40 are not formed is created in the central region of the polygon. By making this region in which the V pits 40 are not formed the light-emitting region 3, a light-emitting region 3 that is less susceptible to the influence of the V pits 40 can be formed.

[0039] The polygon in which the V pits 40 are arranged is not limited to a hexagon, but may be an n-sided polygon. However, n is an integer of 4 or more, and more preferably 6 or more. The polygon does not have to be a regular polygon. However, in order to form a micro light-emitting element as fine as possible, a regular polygon is preferable. Furthermore, since the facet surface of the V pit 40 is a regular hexagon in a plan view as shown in FIG. 2, the polygon is preferably a hexagon. Furthermore, a regular hexagon is more preferable. In this way, by arranging the V pits 40 at positions corresponding to the vertices of a regular hexagon, a region without the V pits 40 in the central region can be formed.

[0040] (Effect of the micro light emitting element 100) As described above, in the micro light-emitting element 100 according to this embodiment, when viewed in the stacking direction of the nitride semiconductor layer 14, the multiple V pits 40 are arranged in the region of the nitride semiconductor layer 14 at positions corresponding to the vertices of a polygon (a regular hexagon in this embodiment). Therefore, no V pits 40 are formed in the central region of the light-emitting layer 12. This region where no V pits 40 are formed can be used as the light-emitting region, so that it is possible to suppress a decrease in light-emitting efficiency due to the V pits 40. Therefore, according to this embodiment, a micro light-emitting element that is fine and has high light-emitting efficiency can be realized.

[0041] (Configuration of Growth Substrate 10) Next, the configuration of the growth substrate 10 for growing the nitride semiconductor layer 14 of the micro light emitting device 100 according to this embodiment and the manufacturing method of the micro light emitting device 100 will be described with reference to Fig. 3 to Fig. 6. First, the growth substrate 10 will be described. Fig. 3A is a schematic diagram of the planar arrangement of convex portions formed on the surface of the growth substrate 10 and V pits formed in the nitride semiconductor layer corresponding to the convex portions.

[0042] In this embodiment, as in the conventional technology, a sapphire substrate (C-plane) is used as the growth substrate 10. However, the configuration of the growth substrate 10 differs from that of the conventional technology. The growth substrate 10 has protrusions 20 on its growth surface (surface). Specifically, as shown in FIG. 3A, the protrusions 20 are disposed at positions corresponding to the vertices of a polygon. In the example shown in FIG. 3A, the polygon is a regular hexagon.

[0043] A structure in which the convex portions 20 are arranged at positions corresponding to the vertices of a polygon is called a set of convex arrays. A region including a set of convex arrays is called a unit cell 5. A plurality of unit cells 5 are arranged in a two-dimensional array on the growth surface. As an example, as shown in FIG. 3A, the unit cells 5 can be arranged adjacent to each other in the vertical and horizontal directions on the surface of the growth substrate 10. The arrangement pattern of the unit cells 5 in the two-dimensional array is not limited to the method shown in FIG. 3A. For example, as shown in FIG. 3C, the unit cells 5 may be arranged with a shift of half the length of one side of the unit cells 5 every other row. The arrangement pattern of the convex array is not limited to a regular hexagon, and may be a polygon with a different number of corners.

[0044] The unit cell 5 corresponds to one micro light-emitting element 100. That is, the center of the convex array is the light-emitting region of the micro light-emitting element 100. A cross-sectional view taken along the CC line in FIG. 3A is shown in FIG. 4 at 4001. As shown in FIG. 3A and FIG. 4 at 4001, the surface of the growth substrate 10 for growing a nitride semiconductor layer has a convex array in which the convex portions 20 are arranged at positions corresponding to the vertices of a polygon (a regular hexagon in this embodiment), and the unit cells 5 including the convex array are arranged in a two-dimensional array. The polygon is preferably an n-gon, where n is an integer, and is most preferably a regular hexagon.

[0045] The shape of the protrusions 20 is preferably a cone or a truncated cone. The height of the protrusions 20 is preferably 1 to 3 μm. The distance between the protrusions 20 can be changed according to the size of the micro light-emitting element 100. The height of the protrusions 20 can also be changed according to the distance between the protrusions 20. In this embodiment, the distance between the protrusions 20 is preferably 1 μm or less, and the height is also preferably 1 μm or less. The distance between two protrusions 20 facing each other across the center of the unit cell 5 is preferably approximately equal to the dimensions (e.g., mesa dimensions) of the lower surface of the nitride semiconductor layer 14 shown in FIG. 1.

[0046] (Effect of growth substrate 10) As described above, on the surface of the growth substrate 10 according to this embodiment, unit cells 5 including a convex array in which the convex portions 20 are arranged at positions corresponding to the vertices of a polygon are arranged in a two-dimensional array. With this configuration, it is possible to grow the nitride semiconductor layer 14 in which no V-pits 40 are formed in the central region of the light-emitting layer 12. Therefore, it is possible to manufacture a micro light-emitting element that is fine and has high light-emitting efficiency.

[0047] (Method of manufacturing the micro light emitting element 100) Next, a method for manufacturing the micro light-emitting element 100 will be described. Figures 4 to 6 are cross-sectional views showing the manufacturing process of the micro light-emitting element 100 according to this embodiment. In the micro light-emitting element 100, the V-pits 40 are formed at positions corresponding to the vertices of a regular hexagon.

[0048] First, a nitride semiconductor layer 14 is grown on a growth substrate 10 shown in 4001 of Fig. 4. In detail, as shown in Fig. 7, a buffer layer 21, a non-doped layer (not shown), and an N-type layer 11 are sequentially laminated on the surface of the growth substrate 10. The difference from the growth method of the prior art is that the distance between the protrusions 20 is small and the height is also low, so that the thickness of the non-doped layer and the N-type layer is thin overall.

[0049] In the initial stage of growth of the buffer layer 21, almost no film is attached to the slopes of the protrusions 20, and the gallium nitride layer is selectively deposited on the flat portions, so that the protrusions 20 are surrounded by the facets of the GaN (gallium nitride) layer (diagonal broken lines in FIG. 7. The inside of the broken lines is the portion that grows first). In this way, dislocations generated in the center of the unit cell 5 are bent by the facets (see FIG. 7), preventing the dislocations from progressing upward. In parallel with the increase in the growth film thickness, the facets move toward the apexes of the protrusions 20, and the growth surface becomes flat. From this point on, dislocations mainly grow upward from the apexes of the protrusions 20. The facets formed during this growth are likely to be hexagonal when viewed in the stacking direction, so the arrangement of the protrusions 20 in the unit cell 5 is preferably hexagonal, and most preferably regular hexagonal.

[0050] The growth surface is flat in a region where the height from the plane (flat region without convex portions) of the growth substrate 10 slightly exceeds the height of the convex portions 20. In the conventional technology, a thick non-doped layer and an N-type layer are deposited to improve crystallinity. However, if the growth film thickness is increased after the growth surface is flattened, the probability that dislocations will be displaced horizontally from the apex of the convex portions 20 increases. Therefore, in this embodiment, the film thickness deposited after the growth surface is flattened is minimized. Specifically, the thickness T1 (see FIG. 7) of the gallium nitride layer from the height of the apex of the convex portions 20 to the start point of the V-pit 40 is preferably equal to or less than the mesa dimension, and more preferably equal to or less than half the mesa dimension. As a result, the thickness from the plane of the growth substrate 10 to the surface of the N-type layer 11 is about two to three times the height of the convex portions 20, which is about half the thickness of the nitride semiconductor layer 14 in the conventional technology.

[0051] After the growth surface is flattened, the growth is quickly switched to N-type GaN growth, and after the N-type GaN is grown to a predetermined thickness, the formation of the V-pit 40 is started. The most commonly used method for starting the formation of the V-pit 40 is to lower the growth temperature. The method for forming the V-pit, the method for forming a multilayer film including an InGaN layer in parallel with the growth of the V-pit, and improving the crystallinity, and the structure of the multilayer film are well known, and therefore will not be described in detail here.

[0052] After the V pit 40 grows to a certain size, a multiple quantum well layer that will become the light emitting layer 12 is formed, and then a P-type layer 13 is formed. Within the V pit, the multiple quantum well layer is formed along the inner wall of the V pit, thinner than the flat portion. The inside of the V pit is finally filled with a P-type layer. As shown in FIG. 7, in this embodiment, a V pit 40 is formed above the apex of the protrusion 20. In plan view, as shown in FIG. 3B, six V pits 40 are arranged on the outer periphery, and an area without a V pit is formed in the center.

[0053] However, as described above, the position of the V pit cannot be completely controlled, so there are cases where the V pit is horizontally shifted from the predetermined position, as in V pit A in Fig. 3B, and cases where the V pit is formed at a point other than the apex of the protrusion 20, as in V pit B and V pit C. However, in general, there is no V pit in the center of the unit cell 5, and it is possible to form an arrangement in which the V pits surround the periphery of the center.

[0054] Returning to FIG. 4, after the nitride semiconductor layer 14 is grown, the P electrode 23P is formed as shown in 4002 of FIG. 4. The P electrode 23P is formed to cover the center of the unit cell, that is, the area where the V pit 40 is not present. The P electrode 23P may cover a part of the V pit 40. Next, as shown in 4003 of FIG. 4, a part of the nitride semiconductor layer 14 around the P electrode 23P is removed by dry etching to form the mesa portion 16 and the separation groove 15. At this time, a part of the separated V pit 40 remains at the end of the mesa portion 16, and the facet surface constituting the V pit 40 remains in most of the periphery of the mesa portion 16. The mesa portion 16 is an example of the "region of the nitride semiconductor layer" described in the claims.

[0055] Next, as shown in 5001 of FIG. 5, an N-electrode 24N is formed at the bottom of the separation groove 15. Next, as shown in 5002 of FIG. 5, a protective film 17 is formed. The protective film 17 is preferably a transparent insulating film such as a silicon oxide film. Next, as shown in 5003 of FIG. 5, a contact hole 18 is formed in the protective film 17 to expose the P-electrode 23P. Next, as shown in 6001 of FIG. 6, a connection electrode 19 is formed on the P-electrode 23P. Next, as shown in 6002 of FIG. 6, the substrate formed up to 6001 of FIG. 6 is reversed and bonded to the drive circuit substrate 50. As a result, the P-drive electrode 51 and the connection electrode 19 arranged on the surface of the drive circuit substrate 50 are connected, and a path for passing a current from the drive circuit substrate 50 to the micro light-emitting element 100 is formed. Although not shown, the N-drive electrode 52 and the N-electrode 24N arranged on the surface of the drive circuit substrate 50 are also connected at the same time. Next, as shown in 6003 of FIG. 6, the growth substrate 10 is peeled off, and the upper surface of the N-type layer 11 is polished, thereby completing the micro light emitting element 100.

[0056] The manufacturing method of the micro light-emitting element 100 described above can be explained as follows. That is, the manufacturing method of the micro light-emitting element 100 in this embodiment includes the following steps, as shown in flow S1 of FIG. 8. That is, in step S11, the nitride semiconductor layer 14 is grown on the growth substrate 10. Next, in step S12, a part of the nitride semiconductor layer 14 is removed to form a plurality of mesas 16. In the manufacturing method of this embodiment, unit cells 5 including a convex array in which the convex portions 20 are arranged at positions corresponding to the vertices of a polygon are arranged in a two-dimensional array on the surface of the growth substrate 10. Also, the mesa portion 16 is provided in the central region of the convex array.

[0057] According to the above manufacturing method, when viewed in the stacking direction of the nitride semiconductor layer 14, a plurality of V pits 40 are formed in the region of the nitride semiconductor layer 14 at positions corresponding to the vertices of a polygon. Therefore, no V pits 40 are formed in the central region of the light emitting layer 12. Since the region where the V pits 40 are not formed can be used as the light emitting region, it is possible to suppress a decrease in light emitting efficiency due to the V pits 40. Therefore, a micro light emitting element that is fine and has high light emitting efficiency can be realized.

[0058] Another method for manufacturing the micro light emitting element 100 includes the following steps. As shown in flow S2 of FIG. 8, first, in step S21, a nitride semiconductor layer 14 is grown on a growth substrate 10. The nitride semiconductor layer 14 includes a laminated structure in which an N-type layer 11, an emission layer 12, and a P-type layer 13 are laminated. Next, in step S22, a part of the nitride semiconductor layer 14 is removed to form a plurality of mesas 16. Each of the plurality of mesas 16 includes a nitride semiconductor layer 14 (i.e., an N-type layer 11, an emission layer 12, and a P-type layer 13). Furthermore, in step S23, a P-electrode is formed in each mesa 16, covering at least a central portion of the mesa 16 and connected to the P-type layer 13. Next, in step S24, an N-electrode 24N is formed in each mesa 16 to connect to the N-type layer 11.

[0059] According to the above manufacturing method, it is possible to realize a micro light emitting device that is fine and has high light emitting efficiency, and includes a nitride semiconductor layer that includes an N-type layer, a light emitting layer, and a P-type layer.

[0060] (Modification) Figures 4 to 6 illustrate the manufacturing process of a micro light-emitting element 100 connected to a driving circuit board 50. However, instead of the driving circuit board 50, a transfer substrate may be attached to the micro light-emitting element 100, the growth substrate 10 may be peeled off, and the individual micro light-emitting elements 100 may be separated and then transferred to another driving circuit board 50 (not shown).

[0061] (Effects of the First Embodiment) As described above, according to this embodiment, a plurality of V pits 40 are formed at positions corresponding to the vertices of a regular hexagon in the nitride semiconductor layer 14 of the micro light emitting element 100. Therefore, the V pits 40 are not formed in the area surrounded by the V pits 40. Since the area where the V pits 40 are not formed can be used as the light emitting area, it is possible to suppress the reduction in light emitting efficiency caused by the V pits 40. Therefore, it is possible to realize a micro light emitting element that is fine and has high light emitting efficiency. In other words, it is possible to realize a micro light emitting element of micron size or submicron size that is suitable for a high resolution image display element, has high brightness, and consumes low power.

[0062] In the conventional technology, as shown in Fig. 14C, a closest-packed arrangement in which protrusions are arranged at the vertices of an equilateral triangle with sides of about 3 µm is provided over the entire growth surface. In this embodiment, it is only necessary to change the size and arrangement of the protrusions of the growth substrate of the conventional technology, and the materials and equipment of the conventional technology can be used, so there is no cost problem in applying this embodiment to the production of the micro light-emitting element 100.

[0063] [Embodiment 2] (Configuration of the micro light emitting element 100a) Next, the configuration and manufacturing method of the micro light-emitting element 100a according to the second embodiment of the present invention will be described with reference to Fig. 9 and Figs. 10 to 12. For convenience of explanation, the same reference numerals are given to members having the same functions as those described in the above embodiments, and the explanations thereof will not be repeated.

[0064] Fig. 9 is a schematic cross-sectional view of the micro light-emitting element 100a according to this embodiment. In the micro light-emitting element 100 of the first embodiment, the light emitting surface 130 is disposed on the N-type layer 11 side, but in this embodiment, as shown in Fig. 9, the P-type layer 13 is disposed on the light emitting surface 130 side, which is different. That is, in the first embodiment, the opening side of the V pit 40 (the side with a larger diameter when viewed from above) is disposed on the drive circuit board 50 side, whereas in the micro light-emitting element 100a of this embodiment, the opening side of the V pit is disposed on the light emitting surface 130 side.

[0065] 9, the nitride semiconductor layer 14 constituting the micro light emitting element 100a is completely separated from the adjacent micro light emitting element 100a by a protective film 17. In addition, the P electrode 23Pa in this embodiment is preferably a transparent electrode that transmits light because the emitted light passes through it.

[0066] (Method of manufacturing the micro light emitting element 100a) Next, a method for manufacturing the micro light emitting device 100a will be described with reference to Fig. 10 to Fig. 12. As in the first embodiment, the growth substrate 10 shown in Fig. 3A (4001 in Fig. 4) is used as a growth substrate for manufacturing the micro light emitting device 100a. The process of growing the nitride semiconductor layer 14 on the growth substrate 10 is the same as the process described in the first embodiment.

[0067] After the nitride semiconductor layer 14 is grown on the growth substrate 10, as shown in 1001 of Fig. 10, the nitride semiconductor layer 14 side is bonded to a transfer substrate 30 via an adhesive layer 31. Next, as shown in 1002 of Fig. 10, the growth substrate 10 is peeled off, and the nitride semiconductor layer 14 is polished to adjust the thickness to be used for the micro light emitting element 100a.

[0068] Next, as shown in 1003 of FIG. 10, a metal film 24L that will become an N electrode is deposited. Then, as shown in 1101 of FIG. 11, the metal film 24L and the nitride semiconductor layer 14 are divided using photolithography and dry etching techniques. Specifically, the nitride semiconductor layer 14 is divided into mesa portions 16a together with the metal film 24L by the dividing grooves 15a for each micro light emitting element 100a, and the metal film 24L is divided into N electrodes 24Na. As in the first embodiment, most of the sidewall of the mesa portion 16a is covered by the cross section of the V pit 40.

[0069] Next, as shown in 1102 of FIG. 11, the mesa portion 16a is covered with the protective film 17a, and the N electrode 24N is exposed. In 1102 of FIG. 11, the division groove 15a is completely filled with the protective film 17a. Such a structure can be formed by depositing a thick protective film 17a and polishing it by CMP. However, the protective film 17a may cover the periphery including the upper part of the mesa portion 16a, and the protective film 17a on the N electrode 24N may be removed by photolithography and dry etching techniques. Note that, before depositing the metal film 24L, the nitride semiconductor layer 14 may be divided, the protective film 17a may be deposited, the mesa portion 16a may be exposed, and then the N electrode 24N may be formed.

[0070] Next, as shown in 1103 of Fig. 11, the N electrode 24N side is attached to the drive circuit board 50a. At this time, the N electrode 24N is connected to the N drive electrodes 52a arranged on the surface of the drive circuit board 50. Then, as shown in 1201 of Fig. 12, the transfer substrate 30 and the adhesive layer 31 are peeled off. Furthermore, as shown in 1202 of Fig. 12, the P electrode 23Pa is deposited. A method for connecting the P electrode 23Pa to the P drive electrode 51a (not shown) on the drive circuit board 50a can be applied using known techniques, so a description thereof will be omitted.

[0071] (Effects of the second embodiment) In this embodiment, too, the same effect as in embodiment 1 can be obtained. That is, in this embodiment, too, in the micro light emitting element 100a, a plurality of V pits 40 are formed in the region of the nitride semiconductor layer 14 at positions corresponding to the vertices of a regular hexagon, and V pits 40 are not formed in the region surrounded by the V pits 40. Since the region where the V pits 40 are not formed can be used as the light emitting region, it is possible to suppress the reduction in light emitting efficiency caused by the V pits 40. Therefore, a micro light emitting element that is fine and has high light emitting efficiency can be realized.

[0072] [Additional Notes] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. The technical scope of the present invention also includes embodiments obtained by appropriately combining the technical means disclosed in the different embodiments. Furthermore, new technical features can be formed by combining the technical means disclosed in the respective embodiments.

[0073] 〔summary〕 The micro light-emitting element according to aspect 1 of the present invention includes a nitride semiconductor layer in which an N-type layer, an emission layer, and a P-type layer are stacked, and when viewed in the stacking direction of the nitride semiconductor layer, a plurality of V pits are arranged in the region of the nitride semiconductor layer at positions corresponding to the vertices of a polygon.

[0074] According to the above configuration, the V pits are arranged at positions corresponding to the vertices of a polygon, and no V pits are formed in the area surrounded by the V pits. Therefore, the reduction in luminous efficiency caused by the V pits is suppressed. Therefore, a micro light emitting element that is fine and has high luminous efficiency can be realized.

[0075] A micro light-emitting element according to aspect 2 of the present invention may be such that, in aspect 1 above, when the light-emitting layer is viewed in the stacking direction of the nitride semiconductor layers, an end of the light-emitting layer is in contact with each facet surface of the multiple V-pits.

[0076] According to the above-mentioned configuration, no V-pit is formed in the center of the light-emitting layer, so that a micro light-emitting element that is fine and has high light-emitting efficiency can be realized.

[0077] A micro light-emitting element according to aspect 3 of the present invention may be configured in such a way that, in the above-mentioned aspect 2, when the light-emitting layer is viewed in the stacking direction of the nitride semiconductor layers, the multiple facet surfaces to which the ends of the light-emitting layer contact may have a shape similar to the polygon.

[0078] According to the above-mentioned configuration, no V-pit is formed in the center of the light-emitting layer, so that a micro light-emitting element that is fine and has high light-emitting efficiency can be realized.

[0079] The micro light-emitting element according to Aspect 4 of the present invention is any one of Aspects 1 to 3, wherein the polygon is an n-sided polygon, where n≧6 (n is an integer).

[0080] According to the above configuration, a micro light emitting element that is fine and has high light emitting efficiency can be realized.

[0081] A micro light-emitting element according to a fifth aspect of the present invention may be configured such that, in the fourth aspect, the polygon is a regular hexagon.

[0082] According to the above-mentioned configuration, it is possible to realize a micro light-emitting element that is fine and has high light-emitting efficiency in the most efficient manner.

[0083] A growth substrate according to a sixth aspect of the present invention is a growth substrate for growing a nitride semiconductor layer, and unit cells including a convex array in which the convex portions are arranged at positions corresponding to the vertices of a polygon are arranged in a two-dimensional array on a surface of the growth substrate.

[0084] According to the above configuration, it is possible to grow the nitride semiconductor layer 14 without the V-pit 40 formed in the central region of the light emitting layer 12. Therefore, it is possible to manufacture a micro light emitting element that is fine and has high light emitting efficiency.

[0085] A growth substrate according to a seventh aspect of the present invention may be, in the above-mentioned sixth aspect, an n-sided polygon, where n≧6 (n is an integer).

[0086] According to the above configuration, it is possible to manufacture a micro light-emitting element that is fine and has high light-emitting efficiency.

[0087] A growth substrate according to an eighth aspect of the present invention is the same as that of the seventh aspect, in which the polygon is a regular hexagon.

[0088] According to the above-mentioned configuration, it is possible to most efficiently manufacture a micro light-emitting element that is fine and has high light-emitting efficiency.

[0089] A method for manufacturing a micro-light-emitting element according to aspect 9 of the present invention includes the steps of growing a nitride semiconductor layer on a growth substrate and removing a portion of the nitride semiconductor layer to form a plurality of mesa portions, wherein unit cells including a convex array in which the convex portions are arranged at positions corresponding to the vertices of a polygon are arranged in a two-dimensional array on a surface of the growth substrate, and the mesa portion is formed in a central region of the convex array.

[0090] According to the above-mentioned configuration, it is possible to manufacture a micro light-emitting element including a nitride semiconductor layer 14 in which no V-pit 40 is formed in the central region of the light-emitting layer 12. Therefore, it is possible to manufacture a micro light-emitting element that is fine and has high light-emitting efficiency.

[0091] A manufacturing method for a micro light-emitting element according to aspect 10 of the present invention may be such that, in the above-mentioned aspect 9, the nitride semiconductor layer includes a layered structure in which an N-type layer, an emission layer, and a P-type layer are layered, and each of the multiple mesa portions includes the nitride semiconductor layer, and further includes a step of forming a P-electrode in each of the mesa portions, covering at least a central portion of the mesa portion and connected to the P-type layer, and a step of forming an N-electrode in each of the mesa portions, connected to the N-type layer.

[0092] According to the above configuration, it is possible to manufacture a micro light emitting element that is fine and has high light emitting efficiency, and includes a nitride semiconductor layer that includes an N-type layer, a light emitting layer, and a P-type layer. EXAMPLES

[0093] Example 1 Next, an example will be described. The micro light-emitting element 100 described in the first embodiment was produced by the above-mentioned manufacturing method. However, the micro light-emitting element 100 is very small and difficult to evaluate individually. Therefore, after the produced micro light-emitting element 100 is attached to a drive circuit board 50, the individual micro light-emitting elements 100 are accessed using the circuit of the drive circuit board 50, and the light emission intensity is measured. The drive circuit board 50 used for the evaluation was capable of operating 352×198 pixels. Of these, the luminance of more than 900 pixels was evaluated.

[0094] The luminance of the micro light-emitting element 100 using the nitride semiconductor layer 14 according to this embodiment was compared with that of a micro light-emitting element using a conventional nitride semiconductor layer (comparative example) as a comparative example. The micro light-emitting elements were formed using the same process.

[0095] The arrangement pitch of the micro light-emitting elements 100 of this embodiment (the length of one side of the unit cell 5) was 8.2 μm, and the length of one side of the mesa portion 16 (mesa dimension) was 2.5 μm. The emission wavelength was 450 nm. The protrusions 20 were conical with a height of 1.5 μm and a bottom diameter of 1.5 μm, and the protrusion array was a regular hexagon with a distance between opposing sides of 2.2 μm.

[0096] The shape of the micro light emitting device of the comparative example is the same as that of the micro light emitting device 100 of the embodiment, and was manufactured using a growth substrate on which protrusions having a diameter of 3 μm and a height of 2 μm were arranged in a close-packed manner, as shown in FIG. 14C.

[0097] The frequency distribution of the luminance of the micro light-emitting device 100 of Example 1 and the micro light-emitting device of the comparative example is shown in Fig. 13. The luminance is normalized by setting the maximum value obtained for the nitride semiconductor layer sample of the comparative example to 100. The luminance of the micro light-emitting device of the prior art is represented by an open bar graph, and the luminance of the micro light-emitting device 100 of the present embodiment is represented by a filled bar graph.

[0098] As shown in FIG. 13, it can be seen that the micro light emitting device 100 of this embodiment can achieve a much tighter luminance distribution than the comparative example. The standard deviation of the luminance distribution is 8.9 in the comparative example, whereas it is 2.8 in the configuration of this embodiment, which is approximately 1 / 3 smaller. In the micro light emitting device 100 of this embodiment, the nitride semiconductor layer is thinner than in the comparative example, so that the maximum characteristics are slightly lower than those of the comparative example, but the effect of reducing the variation is very large. Furthermore, the reduction in the thickness of the nitride semiconductor layer shortens the epitaxial growth time, which is a positive factor for reducing costs.

[0099] As described above, it has been found that by arranging the convex portions 20 within the unit cell 5 at positions corresponding to the vertices of a polygon, growing the nitride semiconductor layer 14, and forming the nitride semiconductor layer 14 in the central part of the polygon as the mesa portion 16 of the micro light-emitting element 100, with the central region being the light-emitting region 3, it is possible to form a micro light-emitting element 100 with little variation in light-emitting intensity. [Explanation of symbols]

[0100] 100 Micro light emitting element 130 Light emitting surface 3. Light-emitting area 5. Unit Cell 10, 10b growth substrate 11 N-type layer 12 Emitting layer 13 P type layer 14 Nitride semiconductor layer 15, 15a dividing groove 16, 16a Mesa section 17, 17a Protective film 18 Contact Hole 19 Connection electrode 20 Convex 21 Buffer layer 23P, 23Pa P electrode 24L metal membrane 24N, 24Nb N electrode 25 Embedded material 30 Transfer substrate 31 Adhesive layer 40 V Pit 50, 50a drive circuit board 51 P driving electrode 52, 52a N drive electrode

Claims

1. a nitride semiconductor layer in which an N-type layer, a light emitting layer, and a P-type layer are stacked, When viewed in a stacking direction of the nitride semiconductor layer, cross sections of six V pits are arranged at positions including vertices of a regular hexagon in a region of the nitride semiconductor layer, The length of one side is 5 μm or less. A micro light-emitting element characterized by:

2. The micro light-emitting element according to claim 1 , characterized in that, when the light-emitting layer is viewed in the stacking direction of the nitride semiconductor layers, an end of the light-emitting layer is in contact with a facet surface of each of the multiple V-pits.

3. The micro light-emitting element according to claim 2, characterized in that, when the light-emitting layer is viewed in the stacking direction of the nitride semiconductor layers, the multiple facet surfaces to which the ends of the light-emitting layer contact have a shape similar to the regular hexagon.

4. A growth substrate for growing a nitride semiconductor layer for producing a micro-light-emitting device having a side length of 5 μm or less, comprising: A growth substrate, characterized in that unit cells, each including a convex array in which the convex portions are arranged at positions including vertices of a regular hexagon, are arranged in a two-dimensional array on the surface of the growth substrate.

5. growing a nitride semiconductor layer on a growth substrate; A method for manufacturing a micro light emitting device having a side length of 5 μm or less, the method comprising the steps of: removing a portion of the nitride semiconductor layer to form a plurality of mesa portions; a unit cell including a convex array in which the convex portions are arranged at positions including vertices of a regular hexagon is arranged in a two-dimensional array on a surface of the growth substrate; The method for manufacturing a micro light-emitting element, wherein the mesa portion is formed in a central region of the array of protrusions.

6. the nitride semiconductor layer includes a stacked structure in which an N-type layer, a light emitting layer, and a P-type layer are stacked, each of the mesa portions includes the nitride semiconductor layer; forming a P-electrode on each of the mesas, the P-electrode covering at least a central portion of the mesa and connected to the P-type layer; The method according to claim 5 , further comprising the step of forming an N-electrode in each of the mesas, the N-electrode being connected to the N-type layer.

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