Read retries to selectively disable on-die ECC

Abstract

To provide a memory controller which allows a host to receive data from a specific memory device without mis-corrections.SOLUTION: A memory device that performs internal ECC (error checking and correction) can selectively return read data after applying the internal ECC or without applying the internal ECC, in response to different read commands from a memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without applying the internal ECC.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present description relates generally to memory devices and more particularly to selective application of internal error checking and correction (ECC). [Background technology]

[0002] Error handling in memory subsystems can be referred to as RAS (reliability, availability, serviceability) to refer to the error handling used to meet RAS expectations. RAS expectations often include expectations for full SDDC (single device data correction) capability, where errors resulting from full device failure can be corrected. However, future generations of memory subsystems will not have enough ECC (error checking and correction) bits to provide full SDDC as more data is provided from fewer devices. While x4 (4-bit wide data interface per device) DRAM (Dynamic Random Access Memory) devices provide 4B (4 bytes) of data from a single device under DDR4 (Double Data Rate, version 4, JESD79-4, first published by JEDEC in September 2012), DDR5 (DDR version 5 currently under discussion by JEDEC) x4 DRAM devices provide 8B of data from a single device. In HBM (e.g., High Bandwidth Memory DRAM JESD235A, first published by JEDEC in November 2015), a single device provides a full 32B of read data.

[0003] Furthermore, while on-die ECC can generally provide correction of single-bit errors (SBEs), if a device has a multi-bit error (MBE), the memory device ECC circuitry may introduce additional errors by miscorrecting the MBE as an SBE. Such miscorrection is referred to as aliasing, and the ECC syndromes generated based on the multi-bit error may match columns of the code matrix, resulting in Positive New bit By mistake Invert Let it happen So, for example, a two-bit error might be "corrected" into a three-bit error by the internal ECC.

[0004] A memory controller may be able to apply more robust ECC at the system level by applying data from multiple memory devices, however, aliasing can result in uncorrectable errors that the memory controller would otherwise be able to correct. [Brief description of the drawings]

[0005] The following description includes discussion of figures with illustrations given as examples of implementations. The drawings should be understood as examples and not as limitations. As used herein, reference to one or more examples should be understood as a description of specific features, structures or characteristics included in at least one implementation of the present invention. Phrases such as "in one example" or "in an alternative example" appearing in this specification provide examples of implementations of the present invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive.

[0006] [Figure 1] FIG. 1 is a block diagram of an example system in which a host selectively provides a command to perform a retry read in which the memory disables on-memory ECC.

[0007] [Diagram 2] FIG. 1 is a block diagram of an example system in which a host selectively provides commands to cause a memory to perform a retry read that disables on-memory ECC based on a repeat read command.

[0008] [Figure 3A] FIG. 1 is a block diagram of an example memory architecture that may implement selective bypass of memory device ECC.

[0009] [Figure 3B] FIG. 2 is a block diagram of an example memory controller that receives uncorrected read data.

[0010] [Figure 4A] FIG. 1 is a block diagram of an example 64-bit data architecture of a memory architecture that enables selective memory device ECC bypass.

[0011] [Figure 4B] FIG. 1 is a block diagram of an example 128-bit data architecture of a memory architecture that enables selective memory device ECC bypass.

[0012] [Diagram 5] FIG. 2 illustrates an example state diagram of a memory subsystem with selective memory device ECC bypass.

[0013] [Figure 6] FIG. 13 is a flow diagram of an example process for selectively bypassing on-die ECC.

[0014] [Figure 7] FIG. 1 is a block diagram of an example of an on-die error checking and correction (ECC) subsystem that implements selective on-die ECC bypass.

[0015] [Figure 8] FIG. 1 is a block diagram of an example of a memory subsystem that can implement selective on-die ECC bypass.

[0016] [Figure 9] FIG. 1 is a block diagram of an example computing system that can implement selective on-die ECC bypass.

[0017] [Figure 10] FIG. 1 is a block diagram of an example of a mobile device that can implement selective on-die ECC bypass.

[0018] Specific details and implementation descriptions are provided below, including non-limiting descriptions of figures that may show some or all of the examples and other potential implementations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] As described herein, memory devices that implement internal ECC (error checking and correction) can selectively return read data with or without applying the internal ECC in response to different read commands from a memory controller. In response to a normal read command, the memory device can typically apply the ECC and return corrected data. In response to a retry command, the memory device can return read data without applying the internal ECC.

[0020] Next generation memory devices are expected to have a much smaller ratio of data lines per device to the total number of bits per read operation (channel shrink). In addition, ECC bits may be repurposed for poisoning, directory, security, or other uses. Therefore, it is unlikely that there will be enough ECC bits to provide full SDDC (single device data correction) capability in future generation memory devices. Achieving the same RAS (reliability, availability, serviceability) expectations within a memory system relies on ECC manipulation by the host or memory controller. Memory controller manipulation is hindered by ECC aliasing, which can be countered by selective use of internal ECC by the memory device.

[0021] A retry read command, which results in the memory device sending data without enabling internal ECC (e.g., SBE (single bit error) correction), allows the host to receive data from the particular memory device without miscorrection. The host can compare the aliased corrected data with the uncorrected data to identify errors introduced by the internal ECC. Such an operation can allow the host to convert DUE (detectable but uncorrectable error) errors to CE (correctable error) errors. Thus, the host can improve the RAS coverage of the memory subsystem. RAS coverage can be targeted, for example, for up to 16b (bits) or up to 32b, depending on the memory architecture.

[0022] Testing of a 32GB (gigabyte) x4 RDIMM (registered dual in-line memory module) showed that full device failure is not a common form of failure. In terms of errors that could be identified, the number of SBEs was far greater than any other error. The rate of SBEs continues to increase in memory devices due to smaller patterning and shrinking feature sizes, and the use of VRT (variable retention time). The next most common was MBE (multi-bit error), followed by row error (or cache line error). Internal or on-die ECC is generally effective at dealing with SBEs, but can alias MBEs to DUE errors.

[0023] In one example, the memory controller generates a retry command (alternatively, a read retry command, or a retry read command) in response to detecting a DUE in data from a group of memory devices. For example, as part of applying the internal ECC, the memory devices may generate a DUE command if the internal ECC detects an error that the memory device cannot correct internally. markIn one example, the memory controller can detect the DUE from the data and ECC check bits received from the memory device.

[0024] There are various mechanisms that the memory controller can use to generate a retry command. In one example, the memory controller places a memory device or a group of memory devices in a read retry mode or equivalent state, and the memory controller sets one or more configuration bits of the memory device. The one or more configuration bits may be, for example, a field in a mode register or other configuration register.

[0025] In one example, the memory controller and memory device include a retry command encoding as part of the command protocol. For example, while a standard read command is defined by a particular encoding of CA (command and address) bits, a read retry command may also be defined. It is understood that such a read retry command may be included in the command protocol along with other commands, such as read, write, refresh, or other commands. The command encoding should be different from other commands in the protocol unless the command is used in conjunction with a retry mode triggered by a configuration setting.

[0026] In one example, the memory controller triggers a retry command with a successive or series of read commands. A successive command or series of the same command can refer to the memory controller issuing the same command without any intervening commands. Certain intervening commands may be allowed by the protocol. In one example, issuing the "same command" refers to the same command encoding with the same address. Thus, the encoding may include a series of identical CA bit encodings.

[0027] In one example, for the consecutive read command mechanism to function, the memory device may include circuitry to decode commands as the same command. Thus, the memory device may internally decode a series of commands as a trigger for a read command. If the purpose of the retry command is to provide uncorrected data for comparison with the previous corrected data, the series of commands may cause the memory device to return data in response to decoding the original read command, and subsequently decode the retry command and return the same data without applying the internal ECC.

[0028] It will be appreciated that a memory controller may be coupled to a single memory device. However, system level correction by the memory controller may be performed in conjunction with a host controller for a single memory device. In The memory devices will not differ. Typically, memory devices are used in groups. A memory controller is coupled to multiple memory devices or a group of memory devices through a memory channel, where the memory devices share command and address signal lines (e.g., with a multi-drop bus), and each memory device has a dedicated data line (DQ and associated strobe or clock (DQS) line) coupled between the memory device and the memory controller. Other control signal lines may also be shared (e.g., multiple devices in a rank may share a device enable (EN) signal line or an alert signal line) or may be unique.

[0029] 1 is a block diagram of an example system in which a host selectively provides a command to perform a retry read in which the memory disables on-memory ECC. System 100 represents an element of a computer system. System 100 may be considered to represent an element of a memory system or memory subsystem, provided that a memory system is considered part of a computer system.

[0030] System 100 includes a host 110, which represents a hardware and software platform for a computer system including a memory. Host 110 includes a processor 112, which may be any type of processor, microprocessor, central processing unit (CPU), graphics processing unit (GPU), or other controller or processor that executes instructions that may require access to memory. Processor 112 may be a single-core processor. In one example, processor 112 is a multi-core processor.

[0031] Host 110 represents circuitry in host 110 that manages access to memory 130. M The processor 112 includes a memory controller 120. In one example, the memory controller 120 is part of the processor die (integrated memory controller or on-die controller). In one example, the memory controller 120 is a circuit integrated into a system-on-chip (SOC) that includes the processor 112 and the memory controller 120. Such a SOC may also include a peripheral controller, a communication controller, a graphics controller, or other circuits.

[0032] In one example, memory controller 120 includes command (CMD) logic 122, which represents logic for generating commands to memory 130 in response to a request for memory access by processor 112. Command logic 122 may include circuitry and firmware or code logic on memory controller 120. In one example, command logic 122 may include logic for generating commands to memory 130 in response to a request for memory access by processor 112. of Command Encoding haveBased on the encoding of the command by the command logic 122, in one example, a command (CMD) decoder 132 of the memory 130 interprets the command as a retry command that causes the memory device to return read data without applying the internal ECC.

[0033] The memory controller 120 includes an ECC 124, which represents host-side error checking and correction logic. The ECC 124 performs system-level ECC, which refers to error checking and correction of data received from the memory devices 130. In one example, the ECC 124 includes circuitry for performing ECC operations on data received from the memory 130. In one example, the ECC 124 generates ECC check bits to be sent along with the write data for a write command.

[0034] Memory controller 120 includes I / O (input / output) 128, which represents hardware for interfacing with memory 130. The hardware may include pins, balls, or other connectors for interfacing with signal lines on a connection board (e.g., a SOC or a motherboard) of system 100 that provides an electrical interconnection between memory controller 120 and memory 130. The I / O 128 hardware may include driver and receiver circuitry (including termination hardware, clock / timing circuits, signal phase control such as a delay-locked loop (DLL) or phase-locked loop (PLL), or other hardware).

[0035] Memory 130 represents an individual memory device, such as a DRAM (Dynamic Random Access Memory) device or an SDRAM (Synchronous DRAM) device. System 100 shows multiple memory devices, each labeled as memory 130. Memory 130 includes I / O 138, which represents the memory device's hardware for interfacing and communicating with a memory controller. Bus 150 represents one or more groups of signal lines or traces for electrically / communicatively connecting memory 130 and memory controller 120. The hardware of I / O 138 may be the same as or similar to I / O 128 of the memory controller and will not be described separately.

[0036] Memory 130 includes a command (CMD) decoder 132, which represents circuitry and logic that decodes commands received from memory controller 120. The commands may include read commands, write commands, refresh commands, or other commands. In one example, command decoder 132 includes logic for decoding a retry command.

[0037] The memory 130 includes an ECC 134, which stands for on-die ECC or on-device ECC. The ECC 134 checks the data before the memory 130 provides the data to the memory controller 120. TheThe ECC 134 operates in the memory 130 to correct data errors in the data. It is understood that the operation of the ECC 134 in the memory 130 is different from the operation of the ECC 124 in the memory controller 120. The memory controller 120 calculates the ECC and transmits check bits, which can be stored in one or more of the multiple memory devices. Some memory devices may only store data, while other memory devices may only store ECC check bits. For example, a common architecture includes 10x4, i.e., 10 memory devices, 8 of which store data and 2 of which store ECC information, with the memory devices having a x4 data interface. Adding more devices for ECC increases costs due to increased components and channel pinouts for additional signal lines to connect to the additional devices.

[0038] Therefore, ECC124 ensures that all data bits are encrypted. Against ECC and transmit it to all memory devices as a whole. ECC 134 operates within memory 130 to check and correct errors within the memory device before returning some of the bits stored therein. It is understood that the RAS performance of system-level ECC is expected to be higher than the RAS performance of ECC within an individual device due to the availability of more ECC information.

[0039] The memory 130 includes a register 136, which represents a configuration register of the memory 130. For example, the register 136 may be a mode register. The register 136 includes one or more fields for storing configuration information of the memory 130. In one example, the register 136 includes a register 136 indicating when the memory controller 120 places the memory 130 in a retry command mode. do The retry command mode includes a field for storing one or more bits of information that can be set to retry the specified mode or modes of the memory 130. Specific Behavior In the retry command mode, the command decoder 132 butWhen a read command is received, The command decoder 132 The read command is decoded as a command to trigger a read without applying ECC 134. Thus, memory 130 reads data from array 140 and returns the data to memory controller 120 without applying internal ECC. Such a mode may be an alternative to a retry command based on the command encoding by command logic 122.

[0040] The memory 130 includes an array 140 for storing data. The array 140 represents an array of addressable memory locations. Typically, the array 140 is addressable by at least rows (e.g., word lines) and columns (e.g., bit lines). The array 140 may be subdivided into various banks or sub-banks, or other divisions. The array 140 stores data and ECC data. It is understood that the data may include data written from the memory controller 120. In one example, some or all of the data written by the memory controller to the selected memory device may be system ECC data. The ECC in the array 140 represents local ECC data or ECC check bits generated by the ECC 134 for internal ECC.

[0041] Bus 150 provides electrical and communication connections between memory controller 120 and memory 130. The dashed box pointing to bus 150 illustrates one example of a command (CMD) sequence 152. Command sequence 152 is understood as one non-limiting example of a command sequence in which a retry command is used.

[0042] In one example, the read command but , transmitted from the memory controller 120 to the memory 130 (controller from Memory fart , C→M). In response to a read command, memory 130 reads from array 140 ofAccess data and use ECC134 to decode the codeword data Apply ECC operations to Local or internal ECC check bits Add After applying the internal ECC, the memory 130 returns the corrected data to the memory controller 120 (memory from controller fart , i.e. M→C).

[0043] In one example, "corrected" data simply refers to data that has been checked and corrected by ECC 134, and does not necessarily mean data that is error-free. ECC 134 may be effective at correcting an SBE, but may alias additional bit errors if the data read from array 140 already has an MBE. In one example, memory 130 may report a DUE indication if it fails to properly correct the data. mark ECC134 specifies that mark In one example, the memory controller 120 receives the read data and detects the DUE.

[0044] In one example, the memory controller 120 detects an uncorrected or uncorrectable error or M In data from Mori 130 It should have been corrected already In response to detecting another error, it sends a retry command to memory 130. The retry command triggers memory 130 to read the same data again and return the uncorrected data to memory controller 120 without applying ECC 134.

[0045] In one example, the memory controller 120 includes a fault detector 126. In one example, after sending the retry command, the memory controller 120 can perform fault detection by the fault detector 126 to identify which memory device returned data with an error. Standard fault detection or proprietary fault detection can be used. The specific process of fault detection is outside the scope of this disclosure. The fault detector 126 detects whether the memory controller 120: Not yet Identify and correct errors 、 Performs system-level ECC and provide correction of data. Make it possible.

[0046] In one example, the memory controller 120 uses a retry command on all data to detect a single bit error. identification In such an example, when using a command encoding or retry mode, application of the retry command is not necessarily in response to detection of an error. Thus, the retry command may be issued without first sending a normal read command. In run-time operation of the memory device, in one example, the retry command is not sent until a read command is sent. In one example, memory controller 120 may generate a map of SBEs to enable better RAS coverage. In one example, based on the map of errors and other fault detections, memory controller 120 may take pages offline based on detection of too many errors. vinegar It is possible.

[0047] 2 is a block diagram of an example system in which a host selectively provides commands to cause a memory to perform a retry read that disables on-memory ECC based on a repeat read command. System 200 provides an example system according to system 100 of FIG. 1. System 200 more specifically illustrates a retry command architecture as indicated by a series of repeat read commands. For simplicity, only one memory device is shown, but it can be understood that more than one memory device may be used and a typical implementation will include multiple memory devices.

[0048] Host 210 represents a host platform of system 200. Host 210 includes processor 212 and memory controller 220. The above description of processor 112 of system 100 may also apply to processor 212 of host 210. The above description of memory controller 120, command logic 122, ECC 124, fault detector 126, and I / O 128 of system 100 may also apply to memory controller 220, ECC 224, fault detector 226, and I / O 228, respectively, of system 200.

[0049] The above descriptions of memory 130, command decoder 132, ECC 134, I / O 138, and array 140 of system 100 may also apply to memory 230, command (CMD) decoder 232, ECC 234, I / O 238, and array 240, respectively. Similarly, the above descriptions of bus 150 may apply to bus 250.

[0050] With respect to command (CMD) logic 222, command logic 222 issues retry commands by issuing successive read commands to the same address. Although the command sequence on bus 250 is not specifically shown, the same command sequence as described with respect to bus 150 may also be applied to bus 250. The retry commands in the sequence are more specifically retry commands triggered by the repetition of a read command of system 200.

[0051] In one example, the memory 230 includes an address register or other storage element for storing address data of the read command. In one example, when the command decoder 232 detects a read command, command The decoder is Read Address of the read command (ADDR) of In register 262 This triggers the memory 230 to store the address in the register 262. The memory 230 can compare the address in the register 262 with the previous read address (ADDR-1) in the register 264. The comparator 266 These It can determine if the addresses are the same and issue a retry ready output in response to the comparison.

[0052] In one example, the comparison is made only in response to successive read commands. Thus, for example, the operation of comparator 266 is enabled (or gated) based on another comparison that the current command is the same as the previous command. control In one example, the circuitry of memory 230 may convert the address of any access command into In register 262 When the next access command is received, the address is pushed to the register 264 so that it can be replaced with the address of the next access command. In such an implementation, the memory 230 detects whether the command is a read command. Judgment that or the command is a read command And The previous command was also a read command. Was (For example, two read commands are received in succession. indicators) and Read retry output based on the judgment of Gating Control etc. , additional circuitry may be provided to control read retry decoding. Such logic may be gated by the output Can't control , or may be used by circuitry within comparator 266 to generate a read retry encoding output.

[0053] Similar or additional logic may be added to ensure that no intervening commands have been received. For example, memory 230 may be configured to reset the read / write state if no intervening commands have been received between two read commands, such as a current command and a subsequent read command (which may alternatively be considered a current read command and a previous read command). Only to , decoding of successive commands will result in read retries of Circuitry may be provided to ensure that the read command is followed by a CAS command. When referring to an intervening command, it is understood that a read command followed by a CAS command may be considered to be one read command. Thus, a CAS command is not considered an intervening command for purposes of comparison if the CAS command is part of a sequence that triggers the execution of a read operation.

[0054] Thus, in one example, memory 230 compares the read command address to the previous read command address. If the read command addresses match, in one example, memory 230 reads the of Data may be accessed and returned to memory controller 220 as raw data without applying ECC by ECC 234. Such operations may accommodate retry commands without requiring new command encodings or retry modes.

[0055] FIG. 3A shows a memory device by3 is a block diagram of an example of a memory architecture that may implement selective bypass of ECC. Memory segment 302 represents a portion of a memory array for providing data to a data channel to which a memory device is connected. Segment 302 shows two portions of 64b of data with 8b of ECC data. Diagram 304 shows the architecture of segment 302 with a driver.

[0056] Schematic 304 may include sub-word line (SWL) drivers that drive 8 bits of data to each side. As shown, the dashed boxes are driven by the driver (DRVR) in the middle of the bit. R It shows 16 bits of data. The left bit of the driver can be considered as the left sub-array or left arm of the driver. Similarly, the right bit of the driver can be considered as the right sub-array or right arm of the driver.

[0057] Diagram 306 shows a close-up view of one driver and its associated subarray. The left subarray as the left arm and the right subarray as the right arm are specifically labeled in diagram 306. It is understood that right and left are relative terms and simply refer to the orientation in the diagram. In actual implementations, the bits considered left or right may be swapped. Thus, the description of left and right arms simply refers to the driver between a group of bits or memory cells or memory locations driving the bits to either physical side of the driver circuit to reduce the length of signal lines that need to be driven between the driver circuit and the memory cells or bit cells of the memory array.

[0058] D Driven in each direction from the active components of the driver Bit exists As shown in the figure, 1 One arm failed And , one subarray becomes inaccessible, so Failure of one arm (SWL arm)It is understood that this results in an 8b failure. A driver failure (SWL driver failure) results in a 16b failure, considering that both arms become inaccessible.

[0059] As described herein, failure of one arm or driver may result in: Can be aliased into additional bit errors This can result in multi-bit errors. Data from each portion can be selectively fed to ECC hardware, which can be either hard-coded circuitry that implements the code matrix, or a controller with software / firmware that implements the operations to implement the code matrix. Application of ECC can be selectively bypassed by disabling ECC in response to a retry command.

[0060] 3B is a block diagram of an example of a memory controller receiving uncorrected read data. Memory controller 310 illustrates an example of a memory controller consistent with memory controller 120 of system 100 or memory controller 220 of system 200. Memory controller 310 performs a check on the data received from segment 302, which may be a segment of a memory array.

[0061] In one example, memory controller 310 includes circuitry for receiving read data, as indicated by data receive 312. In one example, memory controller 310 includes registers 314 for storing received data from I / O hardware, and a register 316 for storing the received data if internal ECC is enabled in the memory device. Okeru In response to a read command , if internal ECC is enabled on the memory device and a register 316 for storing a previous version of the received data. In one example, the memory controller 310 updates the data in the register 314, which represents the data received in response to a retry command, if an error is detected. of A comparison is made with the data in register 316, which represents the data received in response to a normal read command. That is The memory controller 310 issues a retry command. Done , receive raw data (register 314) to compare with corrected data (register 316) Already done .

[0062] The comparator 318 may be a bit-by-bit comparison that generates a fault detection output that may indicate a difference between a bit of corrected data and uncorrected data. In one example, the memory controller 310 applies the fault detection output to detect errors in the data to perform error correction. Such fault detection may identify the source of the error.

[0063] In addition to SBEs, which can be corrected with internal ECC in the memory device, other common failure modes include failure of a sub-word line (SWL) driver, either the entire driver or one branch of the driver. The SWL driver may have an architecture that drives 8 bits on one arm and 8 bits on another arm or branch. A failure of one arm or branch may result in an 8-bit failure, and a driver failure may result in a 16-bit failure. In either scenario, the 8-bit data on the arm may result in an alias error. If the memory controller 310 is attempting to cover a 16b fault, the aliasing was done The data appears with one extra bit that was incorrectly corrected, turning an otherwise correctable error into an uncorrectable error. can result .

[0064] In one example, the memory controller comprises: raw Provides data, i.e. data without internal ECC applied Should That Instructing memory Encoding for the read CAS (column address strobe) haveSend a retry command. In one example, the memory controller 310 places the memory in a retry command mode via configuration to receive uncorrected or raw read data. In one example, the memory controller 310 issues consecutive read commands to the same address to trigger a retry command. death, child in the case of teeth 、 Neither separate modes nor different command encodings are required. In one such example, a memory (such as that described with reference to FIG. 2) can decode a sequence of commands as a retry command.

[0065] In response to the retry command, the memory , i.e. The retry data from the memory device 310 returns data that has not had the single-bit correction applied, thereby allowing the memory controller 310 to receive data that is free of aliased errors. Thus, the retry data from the memory has errors that are contained within, for example, an 8b, 16b, or 32b boundary as predefined by the RAS controller correction capabilities. The retry data also has single-bit errors from the memory device that would have corrected the SBE.

[0066] In response to the retry data, in one example, the memory controller 120 compares the original data with the retry data. If any of the retry data has a single-bit miscompare, in one example, the memory controller 310 inverts the single bit. Thus, application of the comparison of the data can indicate an alias error and enable the memory controller 310 to correct the alias error.

[0067] 4A is a block diagram of an example of a 64-bit data architecture of a memory architecture that allows selective memory device ECC bypass. Diagram 402 represents elements that may be incorporated into a system such as system 100 or system 200. Diagram 402 represents a core memory architecture for a 64-bit data architecture, such as a DDR4 implementation. As shown, the memory core performs a 128b internal prefetch and includes 8bECC for internal ECC. Diagram 402 specifically illustrates a x4 architecture, although a x8 implementation may use the full 128 bits of prefetch data.

[0068] In the illustrated x4 implementation, 4×16=64, so based on four signal lines with a burst length of 16 (BL16), 64 bits can be exchanged with the host or associated memory controller per memory access transaction. Whereas the light shaded blocks of diagram 402 represent the top half, the unshaded blocks represent the bottom half and vice versa. The dark shaded bits represent ECC bits. As shown, the 64b of data can be fetched from the bottom half or from the top half, or split between the top and bottom halves. These half splits suggest the use of only 4b of each 8b from the subarray.

[0069] Schematic 402 illustrates an I / O circuit 462 for interfacing with four DQ (data) signal lines (DQ[3:0]). Have 4 illustrates an application of memory device 412. Memory device 412 comprises memory array 420, which is shown separated into different sub-arrays in prefetch 430. It is understood that if not all prefetched data is used, all prefetched data may be placed in the sense amplifiers, and then only selected data is used for memory access, as indicated by select 442. Thus, prefetch 430 may represent data in the sense amplifiers, and select 442 may represent data sent to the I / O for a read operation. 、Represents data from the sense amplifier.

[0070] For example, data can be placed into a sense amplifier, and then addressing operates to select a particular portion of the data to be written for a write operation or read for a read operation. Addressing can select data in any manner that makes sense for the architecture. In one example, a portion of the prefetched data is selected for an access operation. As shown, 4 of the 8 bits are selected from each sub-array.

[0071] In one example, the bits selected for a read operation, i.e., selected 442, may be provided to an ECC circuit 452. The ECC circuit 452 represents the on-device or internal ECC logic of the memory device 412. In one example, the ECC circuit 452 may be considered or referred to as an ECC engine. The ECC circuit 452 may: workman Apply ECC to read data to correct errors Then, the data is provided to the I / O circuit 462 so that it can be output to the host (not shown in detail). .

[0072] In one example, the memory device 412 includes an ECC bypass 472, which represents a mechanism for providing raw read data to a host without applying the internal ECC. In one example, the ECC circuitry 452 includes a bypass 472 for selectively bypassing the operation of the ECC circuitry. of In one example, the ECC circuit 452 performs the operation every time death , there are alternative data paths that provide data without applying ECC, which can be multiplexed or selected in the I / O circuit 462 .

[0073] In response to the retry command, the memory device 412 disables the ECC circuitry. death ,Route raw data to bypass the ECC circuitry mosquito , Or teeth 、 Is there an alternative route to selectively output raw data? of In either case, bypassing the ECC circuitry 452 may be considered as disabling ECC. Thus, the memory device 412 may apply ECC in response to a normal read command and bypass application of ECC in response to a retry command.

[0074] FIG. 4B is a block diagram of an example of a 128-bit data architecture of a memory architecture that allows selective memory device ECC bypass. Diagram 404 represents elements that may be incorporated into a system such as system 100 or system 200. Diagram 404 represents a core memory architecture such as a DDR5 implementation. As shown, the memory core performs 128b internal prefetch and has 8bECC for internal ECC. In a x4 implementation, 4×32=128, so based on four signal lines with a burst length of 32 (BL32), 128 bits can be exchanged with a host or associated memory controller per memory access transaction. Thus, as shown, both the top half of the array and the bottom half of the array each provide 64b of data. The top half can be based on the architecture and addressing structure of the memory, which is not specifically shown in diagram 404. The light shaded blocks of diagram 404 represent the top half, and the unshaded blocks represent the bottom half, and vice versa. The dark shaded bits represent the ECC bits.

[0075] Diagram 404 illustrates the application of a memory device 414 with I / O circuitry 464 for interfacing with four DQ (data) signal lines (DQ[3:0]). Memory device 414 includes a memory array 420, which is shown separated into different sub-arrays in prefetch 430. Select 444 selects one of the sub-arrays for a read operation. To Sent to I / O R, It represents the data from the sense amplifiers and may contain all 128 prefetched bits.

[0076] In one example, the bits selected for a read operation, i.e., selected 444, may be provided to an ECC circuit 454. The ECC circuit 454 represents the on-device or internal ECC logic of the memory device 414. In one example, the ECC circuit 454 may be considered or referred to as an ECC engine. The ECC circuit 454 may: workman Apply ECC to read data to correct errors The data is then provided to I / O circuitry 462 for output to a host (not specifically shown).

[0077] In one example, the memory device 414 includes an ECC bypass 474, which represents a mechanism for providing raw read data to a host without applying the internal ECC. In one example, the ECC circuitry 454 includes a bypass 474 for selectively bypassing the operation of the ECC circuitry. of In one example, the ECC circuit 454 performs the operation every time death , there are alternative data paths that provide data without applying ECC, which can be multiplexed or selected in the I / O circuitry 464 .

[0078] In response to the retry command, the memory device 414 disables the ECC circuitry. death ,Route raw data to bypass the ECC circuitry mosquito , Or provides another path to selectively output raw data mosquito Bypassing the ECC circuitry 454 by either of the above may be considered as disabling ECC. Thus, the memory device 414 may apply ECC in response to a normal read command and bypass application of ECC in response to a retry command.

[0079] 5 is an example of a state diagram for a memory subsystem with selective memory device ECC bypass. Diagram 500 shows the states of a retry sequence for a retry command according to any example herein. The left-most column shows the various states, and the other columns show the states of DRAM0, DRAM1, DRAM2, and the host RAS, respectively.

[0080] State 510 represents the state of the original DRAM. State 520 represents the state of the DRAM enabling ECC to read data. State 530 represents the state of the DRAM disabling ECC to read data. State 540 represents operations by the host to perform fault detection. In one example, the host issues a PFD (Permanent Fault Detect) sequence to detect DRAMs with MBE. The host can perform operations iteratively to perform detection until a fault is detected. State 550 represents operations by the host to perform various DRAMs. do Hosting new data Leave Represents the state to be generated.

[0081] For state 510, consider an example where DRAM0 has 8 bit errors, DRAM1 has 1 bit error, and DRAM2 has no errors. These Data from the DRAM is sent to the host. I SDDC Code Protection in the state of having When presented to the host, In this example The SDDC code is 8 b correction, resulting in a DUE.

[0082] In state 520, These DRAM devices apply ECC to read values. So DRAM0 may have an aliasing problem because it may miscorrect an 8-bit error by flipping another bit. So an 8-bit error becomes an 8-bit error with a +1 bit aliased error. On-die ECC corrects the error on DRAM1. death, no data is changed on DRAM2. Therefore, both DRAM1 and DRAM2 have 0 errors with 0 alias errors. However, due to the 8-bit error in DRAM0, the host detects a DUE.

[0083] In response to detection of a DUE by the host, in one example, the host transitions to state 530 to disable ECC in the DRAMs and retry the read. In response to a retry command in state 530, DRAM0 returns an 8-bit error with no aliasing errors, DRAM1 returns a 1b error, and DRAM2 returns data with no errors. It is understood that there is an error in the uncorrected data that results in a DUE in the host.

[0084] In one example, in state 540, the host performs a PFD operation to detect MBE. In one example, the host issues a fixed write pattern (e.g., AAAAh) command followed by a precharge command to close the page. Closing the page ensures that the data is moved from the sense amplifiers to the DRAM cells. In one example, the host then issues a read command to the same address and then compares the data to the write pattern. Such an operation results in: DRAM0 Returns multiple errors. vinegar So, multi-bit error is in DRAM0. identification It is possible.

[0085] At state 550, the host can identify the 8b error in DRAM0 and remove the alias error. Using the corrected data, DRAM1 and DRAM2 for, The data workman No error, DRAM0 for Only 8b errors to make a certain state The RAS result at the host is a correctable error (CE) rather than a DUE.

[0086] 6 is a flow diagram of an example process for selectively bypassing on-die ECC. Process 600 illustrates a process for selectively applying on-die ECC to a read operation. Process 600 may be performed by a system according to system 100 or system 200. In one example, at 602, a host sends a read command to a memory device. In one example, a retry command may be used without first sending a read command that uses ECC. At 604, in response to the read command, the memory device decodes the read command.

[0087] In one example, the memory device determines whether the read command is a normal read command or a retry command. If the read command is a normal read command (NO at 606), then the memory device typically performs ECC internally (608). At 610, the memory device performs ECC checks (611). execution This may include error detection and correction. The memory device then returns the corrected data to the host at 612. As discussed above, such operations may result in aliasing errors.

[0088] After the memory device returns the data with the internal ECC applied, the host determines whether the received data is for a retry command or a normal command. If the data is not for a retry command, at NO branch 616, the host can determine whether the data results in a DUE. If the data does not contain a DUE error, at NO branch 622, the host processes the data, at 626.

[0089] In one example, if the host identifies a DUE at 622, YES branch, the host sends a read retry command to the memory at 624. In one example, the retry command is received at the memory device and the memory device decodes the read command at 604. In response to the retry command at 606, YES branch, the memory device decodes the read command as a retry command. In response to the retry command, the memory device disables ECC and reads the data at 614. In the case of reading with ECC disabled at 612, the memory device returns raw data to the host.

[0090] If the data received at the host is for a retry command, YES branch of 616, in one example, the host performs fault detection, 618. Fault detection allows the host to identify where aliasing errors may exist in the memory data. In one example, the host performs error correction, 620, based on information gathered from comparing the raw data to the memory corrected data.

[0091] 7 is a block diagram of an example of an on-device ECC engine for implementing selective on-die ECC bypass. System 700 provides an example of on-die ECC circuitry for a system according to system 100 or system 200. Host 710 includes a memory controller or equivalent or alternative circuitry or component that manages access to memory 720. Host 710 performs external ECC on data read from memory 720. Memory 720 performs ECC on data read from memory 720 before sending data to host 710. The Implements on-die ECC to check and correct data.

[0092] The system 700 illustrates a write path 732 in the memory 720. The write path 732 represents the path of data being written from the host 710 to the memory 720. The host 710 provides data 742 to the memory 720 for writing to the memory array. In one example, the memory 720 generates check bits 744 in a check bit generator 722 and stores them with the data in the memory. The check bits 744 may be referred to as ECC bits and may enable the memory 720 to correct errors that may occur when writing to and reading from the memory array. The data 742 and check bits 744 may be included as a codeword in 746 that is written to the memory resource.

[0093] A read path 734 is provided from the memory 720 to the host 710. On the other hand 7 represents a path of data being read. In one example, at least certain hardware components of the write path 732 and the read path 734 are the same hardware. In one example, the memory 720 fetches a codeword out 752 in response to a read command from the host 710. The codeword may include data 754 and check bits 756. The data 754 and check bits 756 may correspond to the data 742 and check bits 744, respectively, written in the write path 732. Thus, a read can access the data and the ECC bits.

[0094] Error correction in the read path 734 is used to detect errors and (in the case of single-bit errors) selectively correct the errors. To It is understood that the process of calculating the H matrix may include the application of an XOR (exclusive-or) tree to a corresponding H matrix. The structure of the XOR tree may be designed to implement the H matrix. As understood in the art, the H matrix refers to a Hamming code parity check matrix that indicates how a linear combination of the digits of a codeword is equal to zero. Thus, the rows of the H matrix are each a part of a codeword. elementor the parity check that must be satisfied for a digit formula In one example, the memory 720 includes a syndrome decode 724. The syndrome decode 724 enables the memory to apply check bits 756 to the data 754 to detect errors in the read data. The syndrome decode 724 can generate a syndrome 758 that is used to generate appropriate error information for the read data. The data 754 can also be forwarded to an error correction 728 for correction of detected errors.

[0095] In one example, the syndrome decode 724 sends the syndrome 758 to the syndrome generator 726 to generate an error vector. In one example, the check bit generator 722 and the syndrome generator 726 are fully specified by the corresponding H matrix for the memory device. In one example, if there are no errors in the read data (e.g., zero syndrome 758), the syndrome generator 726 generates a no error signal 762. In one example, if there are multiple errors in the read data (e.g., non-zero syndrome 758 that does not match any column of the corresponding H matrix), the syndrome generator 726 generates a detect error signal 762. was done DUE (detected) indicates an uncorrected error was done The memory 720 generates a DUE (Uncorrected Error) signal 764. The DUE signal 764 may indicate a multi-bit error that the memory 720 was unable to correct by the internal ECC.

[0096] In one example, if there is a single bit error (e.g., a non-zero syndrome 758 that matches one column of the corresponding H matrix), the syndrome generator 726 can generate a CE (corrected error) signal with an error location 760, which indicates the corrected error to the error correction logic 728. markThe error correction 728 can apply the corrected errors to the specified locations in the data 754 to generate corrected data 766 to be output to the host 710. In one example, the error correction 728 also generates check bits 768, which include check bits for the read data.

[0097] The check bit 768 is sent to the host 710. R It can be considered an error vector that indicates the state of errors in the read data. It results in a zero syndrome (no errors 762) condition and corrected data 766. Let It is understood that the corrected SBE will have the same check bits 768 that indicate no error to the host 710. Thus, the check bits 768 do not provide information about the SBE in the memory 720, only the multi-bit error. In one example, the system 700 writes the corrected data back to the memory array.

[0098] In one example, the read path 734 includes a retry command 770, which represents logic of the system 700 for responding to the retry command. In one example, in response to the retry command, the memory 720 forwards the data 754 as uncorrected data 772. The path that outputs the uncorrected data 772 from the retry command 770 may be considered an ECC bypass path, in this case, No ECC circuitry is applied to the read path 734. A retry command 770 may have an input that indicates that the received read command is a retry command. Thus, the other paths are not used to output data to the host 710, but the retry path provides raw data 754, i.e., data as it is retrieved from the memory array without the application of internal ECC.

[0099] 8 is a block diagram of an example of a memory subsystem that can implement selective on-die ECC bypass. System 800 includes elements of a processor and memory subsystem of a computing device. System 800 is one example of a system that may incorporate a system compatible with system 100 or system 200.

[0100] In one example, the memory 840 is connected to the memory controller 820. reading Before returning the data, The The memory 840 includes an on-die ECC 882 for performing ECC on read data. In one example, the memory 840 includes a bypass 884 for selectively bypassing the on-die ECC 882. The bypass of the internal ECC can be according to any description herein, and the memory 840 performs a read in response to a retry command. The memory 840 returns raw data from the memory array 860 based on the retry command instead of performing ECC on the data before returning the data.

[0101] Processor 810 represents a processing unit of a computing platform that may run an operating system (OS) and applications, which may collectively be referred to as a host or user of memory. The OS and applications perform operations that result in memory access. Processor 810 may include one or more separate processors. Each of the separate processors may include a single processing unit, a multi-core processing unit, or a combination thereof. The processing units may be a primary processor, such as a CPU (Central Processing Unit), a peripheral processor, such as a GPU (Graphics Processing Unit), or a combination thereof. Memory access may also be initiated by devices such as a network controller or a hard disk controller. Such devices may be integrated with or attached to the processor in some systems, via a bus (e.g., PCI Express), or a combination thereof. System 800 may be implemented as a SoC (System on a Chip) or with stand-alone components.

[0102] References to memory devices can apply to a variety of memory types. Memory devices often refer to volatile memory technology. Volatile memory is memory whose state (and the data stored in it) is indeterminate when power to the device is removed. Non-volatile memory refers to memory whose state is determinate even when power to the device is removed. Dynamic volatile memory requires the data stored in the device to be refreshed in order to maintain its state. One example of dynamic volatile memory includes dynamic random access memory (DRAM) or some derivative of synchronous DRAM (SDRAM). The memory subsystems described herein may be volatile memory based on DDR4 (Double Data Rate (DDR) version 4, JESD79-4, first published by JEDEC (Joint Electron Device Engineering Council) in September 2012), LPDDR4 (Low Power DDR version 4, JESD209-4, first published by JEDEC in August 2014), WIO2 (Wide I / O 2 (WideIO2), JESD229-2, first published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235A, first published by JEDEC in November 2015), DDR5 (DDR version 5, currently under discussion by JEDEC), LPDDR5 (LPDDR version 5, JESD209-5, first published by JEDEC in February 2019), HBM2 (HBM version 2, currently under discussion by JEDEC), or other or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

[0103] In one example, in addition to or alternatively to volatile memory, reference to a memory device may refer to a non-volatile memory device whose state is determined even when power to the device is interrupted. In one example, the non-volatile memory device is a block addressable memory device, such as NAND (non-AND) or NOR (non-OR) technology. Thus, the memory device may also include future generations of non-volatile devices, such as three-dimensional cross-point memory devices, other byte-addressable non-volatile memory devices. The memory device may include a non-volatile byte-addressable medium that stores data based on the resistance state of a memory cell or the phase of a memory cell. In one example, the memory device may use a chalcogenide phase change material (e.g., chalcogenide glass). In one example, the memory device can be or include multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM) or switched phase change memory (PCMS), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) memory incorporating memristor technology, or spin transfer torque (STT)-MRAM, or any combination of the above, or other memories.

[0104] Memory controller 820 represents one or more memory controller circuits or devices for system 800. Memory controller 820 represents control logic that generates memory access commands in response to execution of operations by processor 810. Memory controller 820 accesses one or more memory devices 840. Memory devices 840 can be DRAM devices according to any of those mentioned above. In one example, memory devices 840 are organized and managed as different channels. Each channel couples to buses and signal lines that couple multiple memory devices in parallel. Each channel is independently operable. Thus, each channel is independently accessed and controlled, and timing, data transfer, command and address exchange, and other operations are separate for each channel. Coupling may refer to electrical coupling, communicative coupling, physical coupling, or combinations thereof. Physical coupling may include direct contact. Electrical coupling includes interfaces or interconnects that allow electricity to flow between components or allow signaling between components, or both. A communicative coupling includes any connection, including wired or wireless, that allows the components to exchange data.

[0105] In one example, the settings for each channel are controlled by a separate mode register or other register settings. In one example, each memory controller 820 manages a separate memory channel, although system 800 can be configured to have multiple channels managed by a single controller or multiple controllers on a single channel. In one example, memory controller 820 is part of host processor 810, such as logic implemented on the same die or in the same package space as the processor.

[0106] The memory controller 820 includes I / O interface logic 822 that couples to a memory bus, such as the memory channel mentioned above. The I / O interface logic 822 (and the I / O interface logic 842 of the memory device 840) may include pins, pads, connectors, signal lines, traces or wires, or other hardware that connects to the device, or a combination thereof. The I / O interface logic 822 may include a hardware interface. As shown, the I / O interface logic 822 includes at least a driver / transceiver for the signal lines. Generally, wires in an integrated circuit interface couple with pads, pins or connectors to interface with signal lines or traces or other wires between devices. The I / O interface logic 822 may include drivers, receivers, transceivers or terminations or other circuits or combinations of circuits for exchanging signals on the signal lines between the devices. The exchange of signals includes at least one of sending or receiving. Although I / O 822 is shown coupled from memory controller 820 to I / O 842 of memory device 840, it is understood that in implementations of system 800 where groups of memory devices 840 are accessed in parallel, multiple memory devices may include I / O interfaces to the same interface of memory controller 820. In implementations of system 800 that include one or more memory modules 870, I / O 842 may include interface hardware of the memory modules in addition to interface hardware on the memory devices themselves. Other memory controllers 820 include separate interfaces to other memory devices 840.

[0107] The bus between the memory controller 820 and the memory devices 840 may be implemented as multiple signal lines coupling the memory controller 820 to the memory devices 840. The bus may typically include at least a clock (CLK) 832, a command / address (CMD) 834, and write data (DQ) and read data (DQ) 836, as well as zero or more other signal lines 838. In one example, the bus or connection between the memory controller 820 and the memory may be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal line for CMD may be referred to as a "C / A bus" (or ADD / CMD bus, or some other name indicating the transfer of command (C or CMD) and address (A or ADD) information), and the signal lines for write and read DQ may be referred to as a "data bus." In one example, the independent channels have different clock signals, C / A bus, data bus, and other signal lines. Thus, the system 800 may be considered to have multiple "buses" in the sense that independent interface paths may be considered separate buses. In addition to the lines explicitly shown, it is understood that the buses may include at least one of a strobe signaling line, an alert line, an auxiliary line, or other signal lines, or combinations thereof. It is also understood that serial bus technology may be used for the connection between the memory controller 820 and the memory devices 840. One example of a serial bus technology is the transmission of high speed data with 8B10B encoding and an embedded clock over a single differential pair of signals in each direction. In one example, CMD 834 represents a signal line shared with multiple memory devices in parallel. In one example, multiple memory devices share the encoding command signal line of CMD 834, each with a separate chip select (CS_n) signal line for selecting an individual memory device.

[0108] In the example of the system 800, it is understood that the bus between the memory controller 820 and the memory devices 840 includes an auxiliary command bus CMD 834 and an auxiliary bus DQ 836 for carrying write data and read data. In one example, the data bus may include bidirectional lines for read data and write / command data. In another example, the auxiliary bus DQ 836 may include a unidirectional write signal line for writes and data from the host to the memory, and a unidirectional line for read data from the memory to the host. Other signals 838 may accompany the bus or sub-bus, such as a strobe line DQS, according to the selected memory technology and system design. Based on the design of the system 800, or implementation if a design supports multiple implementations, the data bus may have more or less bandwidth per memory device 840. For example, the data bus may support memory devices having either a x4 interface, a x8 interface, a x16 interface, or other interfaces. The W in the definition "xW" is an integer that refers to the interface size or interface width of the memory device 840, representing the number of signal lines for exchanging data with the memory controller 820. The interface size of the memory device is the controlling factor as to how many memory devices can be used simultaneously per channel in the system 800 or coupled in parallel to the same signal lines. In one example, high bandwidth memory devices, wide interface devices or stacked memory configurations or combinations thereof can enable a wider interface, such as a x128 interface, a x256 interface, a x512 interface, a x1024 interface or other data bus interface width.

[0109] In one example, the memory device 840 and the memory controller 820 exchange data over the data bus in bursts or in a series of consecutive data transfers. A burst corresponds to a number of transfer cycles related to the bus frequency. In one example, a transfer cycle can be a full clock cycle of transfers occurring on the same clock or strobe signal edge (e.g., rising edge). In one example, a full clock cycle, referring to a cycle of the system clock, is divided into a number of unit intervals (UIs). Each UI is a transfer cycle. For example, a double data rate transfer triggers on both edges (e.g., rising and falling) of the clock signal. A burst can last for a configured number of UIs. This can be a configuration stored in a register or triggered on the fly. For example, a series of eight consecutive transfer periods can be considered a burst length 8 (BL8), and each memory device 840 can transfer data in each UI. Thus, a x8 memory device operating at BL8 can transfer 84 bits of data (8 data signal lines x 8 data bits transferred per line via the burst). It will be understood that this simple example is illustrative only and is not limiting.

[0110] Memory devices 840 represent memory resources for system 800. In one example, each memory device 840 is a separate memory die. In one example, each memory device 840 can be an interface with multiple (e.g., two) channels per device or die. Each memory device 840 includes I / O interface logic 842 with a bandwidth determined by the implementation of the device (e.g., x16 or x8 or some other interface bandwidth). The I / O interface logic 842 allows the memory device to interface with memory controller 820. The I / O interface logic 842 can include a hardware interface and respond to the I / O 822 of the memory controller, but at the memory device end. In one example, multiple memory devices 840 are connected in parallel to the same command and data bus. In another example, multiple memory devices 840 are connected in parallel to the same command bus and connected to different data buses. For example, system 800 can be configured with multiple memory devices 840 coupled in parallel. Each memory device responds to commands by accessing its internal memory resources 860. For a write operation, each memory device 840 can write a portion of an entire data word, and for a read operation, each memory device 840 can fetch a portion of an entire data word, with the remaining bits of the word being provided or received in parallel by the other memory device.

[0111] In one example, memory device 840 is located directly on a motherboard of a computing device or a host system platform (e.g., a PCB (printed circuit board) on which processor 810 is located). In one example, memory device 840 may be organized into memory module 870. In one example, memory module 870 represents a dual in-line memory module (DIMM). In one example, memory module 870 represents another organization of multiple memory devices for sharing at least a portion of the access or control circuitry. The circuitry may be a separate circuit, separate device, or separate board from the host system platform. Memory module 870 may include multiple memory devices 840, and memory modules may include support for multiple separate channels to the memory devices located and included therein. In another example, memory device 840 may be integrated into the same package as memory controller 820, for example, by a technology such as multi-chip module (MCM), package-on-package, through silicon via (TSV) or other technology or combinations thereof. Similarly, in one example, multiple memory devices 840 may be incorporated into a memory module 870, which itself may be incorporated into the same package as the memory controller 820. It will be understood that in these and other implementations, the memory controller 820 may be part of the host processor 810.

[0112] Each of the memory devices 840 includes one or more memory arrays 860. The memory arrays 860 represent addressable memory locations or storage locations of data. Typically, the memory arrays 860 are managed as rows of data and accessed via control of wordlines (rows) and bitlines (individual bits within a row). The memory arrays 860 may be organized as separate channels, ranks, and banks of memory. A channel may refer to an independent control path to storage locations in the memory device 840. A rank may refer to a common location across multiple memory devices in parallel (e.g., the same row address in different devices). A bank may refer to a sub-array of memory locations in the memory device 840. In one example, a bank of memory is divided into sub-banks with at least a portion of the shared circuitry (e.g., drivers, signal lines, control logic) for the sub-banks. This allows for separate addressing and access. It is understood that channels, ranks, banks, sub-banks, banks, or other organization of memory locations, and combinations of such organization may overlap in their application to physical resources. For example, the same physical memory location may be accessed through a particular channel as a particular bank that may also belong to a rank. Thus, the organization of memory resources is understood inclusively, not exclusively.

[0113] In one example, memory device 840 includes one or more registers 844. Registers 844 represent one or more storage devices or memory locations that provide configuration or settings for operation of the memory device. In one example, registers 844 can provide memory locations in memory device 840 for storing data accessed by memory controller 820 as part of control or management operations. In one example, registers 844 include one or more mode registers. In one example, registers 844 include one or more general-purpose registers. Configuration of locations in registers 844 can configure memory device 840 to operate in different "modes." Command information can trigger different operations in memory device 840 based on the mode. Additionally or alternatively, different modes can also trigger different operations from address information or other signal lines depending on the mode. Settings in registers 844 can indicate configuration of I / O settings (e.g., timing, termination or ODT (on-die termination) 846, driver configurations or other I / O settings).

[0114] In one example, the memory device 840 includes an ODT 846 as part of the interface hardware associated with the I / O 842. The ODT 846 may be configured as described above and may provide a setting of impedance applied to the interface to specified signal lines. In one example, the ODT 846 is applied to the DQ signal lines. In one example, the ODT 846 is applied to the command signal lines. In one example, the ODT 846 is applied to the address signal lines. In one example, the ODT 846 may be applied to any combination of the foregoing. The ODT setting may be changed based on whether the memory device is a selected target or non-target device of an access operation. The ODT 846 setting may affect the timing and reflection of the signaling on the termination lines. Careful control over the ODT 846 may enable faster operation with better matching of the applied impedance and load. ODT 846 may be applied to certain signal lines of the I / O interfaces 842, 822 (eg, ODT for DQ lines or ODT for CA lines), but not necessarily to all signal lines.

[0115] The memory device 840 includes a controller 850 that represents control logic within the memory device for controlling internal operations within the memory device. For example, the controller 850 decodes commands sent by the memory controller 820 and generates internal operations to execute or satisfy the commands. The controller 850 may be referred to as an internal controller and is separate from the host's memory controller 820. The controller 850 may determine which mode is selected based on the register 844 and may configure operations for accessing the memory resources 860 or internal execution of other operations based on the selected mode. The controller 850 generates control signals to control the routing of bits within the memory device 840 to provide an appropriate interface for the selected mode and to send commands to the appropriate memory locations or addresses. The controller 850 includes a command logic 852 that can decode command encodings received on the command and address signal lines. Thus, the command logic 852 may be or include a command decoder. The command logic 852 enables the memory device to identify commands and generate internal operations to carry out the requested command.

[0116] Referring back to memory controller 820, memory controller 820 includes command (CMD) logic 824, which represents logic or circuitry for generating commands to be sent to memory device 840. Generating a command may refer to preparing a pre-scheduled command or a queued command for transmission. Generally, signaling within a memory subsystem includes address information within or accompanying a command to indicate or select one or more memory locations where the memory device should execute the command. In response to scheduling a transaction for memory device 840, memory controller 820 can issue a command via I / O 822 to cause memory device 840 to execute the command. In one example, controller 850 of memory device 840 receives and decodes the command and address information received from memory controller 820 via I / O 842. Based on the received command and address information, controller 850 can execute the command by controlling the timing of operations of logic and circuitry within memory device 840. Controller 850 is responsible for compliance with standards or specifications, such as timing and signaling requirements, within memory device 840. Memory controller 820 can implement compliance with standards or specifications through scheduling and control of accesses.

[0117] The memory controller 820 includes a scheduler 830, which represents logic or circuitry for generating and ordering transactions to be sent to the memory device 840. From one perspective, the main function of the memory controller 820 can be said to be to schedule memory accesses and other transactions to the memory device 840. Such scheduling can include generating the transactions themselves to implement requests for data by the processor 810 and to maintain data integrity (e.g., using refresh-related commands). A transaction can include one or more commands, and thus can result in the transfer of commands or data or both in one or more timing cycles, such as a clock cycle or unit interval. A transaction can be for an access, such as a read or write or related command or combination thereof. Other transactions can include memory management commands for configuration, settings, data integrity, or other commands or combinations thereof.

[0118] The memory controller 820 typically includes logic, such as a scheduler 830, to enable transaction selection and ordering to improve performance of the system 800. Thus, the memory controller 820 can select which of the outstanding transactions should be sent to the memory device 840 and in what order. This is typically accomplished using logic that is much more complex than a simple first-in, first-out algorithm. The memory controller 820 manages the transmission of transactions to the memory device 840 and manages the timing associated with the transactions. In one example, transactions have deterministic timing. The timing can be managed by the memory controller 820 and used in determining how to schedule transactions in the scheduler 830.

[0119] In one example, the memory controller 820 includes refresh (REF) logic 826. The refresh logic 826 is used for memory resources that are volatile, but may need to be refreshed to maintain a deterministic state. In one example, the refresh logic 826 indicates the location of the refresh and the type of refresh to perform. The refresh logic 826 can trigger a self-refresh in the memory device 840 or can perform an external refresh (which may be referred to as an auto-refresh command) by sending a refresh command, or a combination thereof. In one example, the controller 850 in the memory device 840 includes refresh logic 854 for applying the refresh in the memory device 840. In one example, the refresh logic 854 generates an internal operation to perform the refresh according to the external refresh received from the memory controller 820. The refresh logic 854 can determine whether a refresh is directed to the memory device 840 and which memory resource 860 to refresh in response to the command.

[0120] 9 is a block diagram of an example of a computing system that can implement selective on-die ECC bypass. System 900 represents a computing device according to any of the examples herein and may be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device or other electronic device. System 900 is one example of a system that may incorporate a system compatible with system 100 or system 200.

[0121] In one example, memory 930 includes an on-die ECC 992 for performing ECC on read data before returning the data to memory controller 922. In one example, memory 930 includes a bypass 994 for selectively bypassing ECC 992. The bypass of the internal ECC can be according to any description herein, and memory 930 performs a read in response to a retry command. Memory 930 returns raw data from the memory array instead of performing ECC on the data before returning the data based on the retry command.

[0122] System 900 includes a processor 910. Processor 910 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core or other processing hardware, or combination thereof, to provide processing or execution of instructions for system 900. Processor 910 controls the overall operation of system 900 and may be or include one or more programmable general-purpose or application-specific microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0123] In one example, the system 900 includes an interface 912 coupled to the processor 910. The interface 912 may represent a higher speed or high throughput interface for a system component that requires a higher bandwidth connection, such as the memory subsystem 920 or the graphics interface component 940. The interface 912 represents an interface circuit that may be a standalone component or may be integrated into a processor die. The interface 912 may be integrated on the processor die as a circuit or integrated into a system-on-chip as a component. If present, the graphics interface 940 interfaces to a graphics component for providing a visual display to a user of the system 900. The graphics interface 940 may be a standalone component or may be integrated into the processor die or system-on-chip. In one example, the graphics interface 940 can drive a high definition (HD) display or an ultra high definition (UHD) display that provides output to a user. In one example, the display may include a touch screen display. In one example, graphics interface 940 generates a display based on data stored in memory 930, or based on operations performed by processor 910, or both.

[0124] The memory subsystem 920 represents the main memory of the system 900 and provides storage for data values ​​used in the execution of codes or routines executed by the processor 910. The memory subsystem 920 may include one or more memory devices 930, such as one or more types of random access memory (RAM), such as read-only memory (ROM), flash memory, DRAM, 3DXP (three-dimensional crosspoint) or other memory devices or combinations of such devices. The memory 930 stores and hosts, among other things, an operating system (OS) 932 for providing a software platform for the execution of instructions within the system 900. Additionally, applications 934 may be executed on the software platform of the OS 932 from the memory 930. The applications 934 represent programs. The programs have their own operating logic for the execution of one or more functions. The processes 936 represent agents or routines that provide auxiliary functions to the OS 932 or one or more applications 934 or a combination thereof. The OS 932, the applications 934 and the processes 936 provide the software logic for providing the functionality for the system 900. In one example, memory subsystem 920 includes a memory controller 922, which is a memory controller that generates and issues commands to memory 930. It is understood that memory controller 922 may be a physical part of processor 910 or a physical part of interface 912. For example, memory controller 922 may be an integrated memory controller that is integrated into a circuit with processor 910, such as integrated into a processor die or a system on a chip.

[0125] Although not specifically shown, it is understood that system 900 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or other. A bus or other signal lines may communicatively or electrically couple components to each other, or may communicatively and electrically couple components. A bus may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits, or combinations thereof. A bus may include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport Architecture bus or an Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other buses, or combinations thereof.

[0126] In one example, the system 900 includes an interface 914 that may be coupled to the interface 912. The interface 914 may be a slower interface than the interface 912. In one example, the interface 914 represents an interface circuit that may include standalone components and integrated circuits. In one example, multiple user interface and / or peripheral components are coupled to the interface 914. The network interface 950 provides the system 900 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. The network interface 950 may include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a Universal Serial Bus (USB) or other wired or wireless standards-based or proprietary interface. The network interface 950 may exchange data with remote devices. Such exchange may include transmitting data stored in memory or receiving data stored in memory.

[0127] In one example, the system 900 includes one or more input / output (I / O) interfaces 960. The I / O interfaces 960 may include one or more interface components through which a user interacts with the system 900 (e.g., voice, alphanumeric, haptic / touch or other interfaces). The peripheral interfaces 970 may include any hardware interfaces not specifically mentioned above. Peripheral generally refers to devices that connect dependently to the system 900. A dependent connection is one in which the system 900 provides a software or hardware platform on which operations are performed and with which a user interacts.

[0128] In one example, the system 900 includes a storage subsystem 980 for storing data in a non-volatile manner. In one example, in certain system implementations, at least certain components of the storage 980 may overlap with components of the memory subsystem 920. The storage subsystem 980 includes a storage device 984. The storage device 984 may be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic disks, solid state disks, 3DXP disks, or optical-based disks, or combinations thereof. The storage 984 holds code or instructions and data 986 in a persistent state (i.e., the value is retained even if power to the system 900 is interrupted). While the storage 984 may be generally considered to be a "memory," the memory 930 is typically an execution or operating memory for providing instructions to the processor 910. While the storage 984 is non-volatile, the memory 930 may include a volatile memory (i.e., the value or state of the data is indeterminate if power to the system 900 is interrupted). In one example, the storage subsystem 980 includes a controller 982 for interfacing with the storage 984. In one example, the controller 982 may be a physical part of the interface 914 or the processor 910, or may include circuitry or logic in both the processor 910 and the interface 914.

[0129] The power source 902 provides power to the components of the system 900. More specifically, the power source 902 typically interfaces with one or more power supplies 904 in the system 900 to provide power to the components of the system 900. In one example, the power supply 904 includes an AC-DC (alternating current-direct current) adapter for plugging into a wall outlet. Such an AC power source can be a renewable energy (e.g., solar power) power source 902. In one example, the power source 902 includes a DC power source, such as an external AC-DC converter. In one example, the power source 902 or the power supply 904 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, the power source 902 can include an internal battery or fuel cell power source.

[0130] 10 is a block diagram of an example of a mobile device that can implement selective on-die ECC bypass. System 1000 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wearable computing device or other mobile or embedded computing device. It is understood that not all components of such a device are shown in system 1000, although certain of these components are generally shown. System 1000 is one example of a system that may incorporate a system compatible with system 100 or system 200.

[0131] In one example, the memory 1062 is connected to a memory controller 1064. reading The memory 1062 includes an on-die ECC 1092 for running ECC on read data before returning the data. In one example, the memory 1062 includes a bypass 1094 for selectively bypassing the ECC 1092. The bypass of the internal ECC can be according to any description herein, and the memory 1062 performs a read in response to a retry command. The memory 1062 returns raw data from the memory array based on the retry command instead of running ECC on the data before returning the data.

[0132] The system 1000 includes a processor 1010 that performs the main processing operations of the system 1000. The processor 1010 may include one or more physical devices such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing means. The processing operations performed by the processor 1010 include the execution of an operating platform or operating system on which applications and device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to connecting the system 1000 to another device, or combinations thereof. The processing operations may also include operations related to audio I / O, display I / O, or other interfaces, or combinations thereof. The processor 1010 can execute data stored in memory. The processor 1010 can write or edit data stored in memory.

[0133] In one example, the system 1000 includes one or more sensors 1012. The sensors 1012 represent embedded sensors or interfaces to external sensors, or a combination thereof. The sensors 1012 enable the system 1000 to monitor or detect one or more conditions of the environment or device in which the system 1000 is implemented. The sensors 1012 may include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological attributes), or other sensors, or combinations thereof. The sensors 1012 may also include sensors for biometric authentication systems, such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize features of a user. The sensors 1012 should be understood broadly and not as a limitation on the many different types of sensors that may be implemented with the system 1000. In one example, the one or more sensors 1012 couple to the processor 1010 via a front-end circuit integrated into the processor 1010. In one example, the one or more sensors 1012 couple to the processor 1010 via another component of the system 1000.

[0134] In one example, system 1000 includes an audio subsystem 1020 that represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. The audio functionality may include a speaker or headphone output and a microphone input. Devices for such functionality may be integrated into or connected to system 1000. In one example, a user interacts with system 1000 by providing voice commands that are received and processed by processor 1010.

[0135] The display subsystem 1030 represents hardware (e.g., display devices) and software components (e.g., drivers) that provide a visual display for presentation to a user. In one example, the display includes a haptic component or touch screen element for a user to interact with the computing device. The display subsystem 1030 includes a display interface 1032 that includes a particular screen or hardware device used to provide a display to a user. In one example, the display interface 1032 includes logic separate from the processor 1010 (such as a graphics processor) for performing at least some processing related to the display. In one example, the display subsystem 1030 includes a touch screen device that provides both output and input to a user. In one example, the display subsystem 1030 includes a high definition (HD) display or an ultra high definition (UHD) display that provides output to a user. In one example, the display subsystem includes or drives a touch screen display. In one example, the display subsystem 1030 generates display information based on data stored in memory, or based on operations performed by the processor 1010, or both.

[0136] The I / O controller 1040 represents hardware devices and software components related to interaction with a user. The I / O controller 1040 may operate to manage hardware that is part of the audio subsystem 1020 or the display subsystem 1030 or both. In addition, the I / O controller 1040 represents connection points for additional devices to connect to the system 1000 through which a user may interact with the system. For example, devices that may be attached to the system 1000 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, buttons / switches, or other I / O devices for use with a particular application, such as a card reader, or other devices.

[0137] As mentioned above, the I / O controller 1040 can interact with the audio subsystem 1020 or the display subsystem 1030, or both. For example, input through a microphone or other audio device may provide input or commands for one or more applications or functions of the system 1000. Additionally, audio output may be provided instead of or in addition to a display output. In another example, if the display subsystem includes a touch screen, the display device also functions as an input device that may be managed, at least in part, by the I / O controller 1040. Additional buttons or switches may also be present on the system 1000 to provide I / O functions managed by the I / O controller 1040.

[0138] In one example, the I / O controller 1040 manages devices such as accelerometers, cameras, light or other environmental sensors, gyroscopes, a global positioning system (GPS) or other hardware or sensors 1012 that may be included in the system 1000. The inputs may be part of direct user interaction as well as providing environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, applying a flash for a camera or other features).

[0139] In one example, the system 1000 includes a power management 1050 that manages battery power usage and functions related to battery charging and power saving operation. The power management 1050 manages power from a power source 1052 that provides power to the components of the system 1000. In one example, the power source 1052 includes an AC-DC (alternating current-direct current) adapter for plugging into a wall outlet. Such an AC power source can be a renewable energy source (e.g., solar power, motion-based power). In one example, the power source 1052 includes only DC power that can be provided by a DC power source such as an external AC-DC converter. In one example, the power source 1052 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, the power source 1052 can include an internal battery or a fuel cell power source.

[0140] The memory subsystem 1060 includes a memory device 1062 for storing information in the system 1000. The memory subsystem 1060 may include non-volatile (state does not change when power to the memory device is interrupted) or volatile (state is indeterminate when power to the memory device is interrupted) memory devices or a combination thereof. The memory 1060 may store application data, user data, music, photos, documents or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the system 1000. In one example, the memory subsystem 1060 includes a memory controller 1064 (which may also be considered part of the control unit of the system 1000 and potentially part of the processor 1010). The memory controller 1064 includes a scheduler that generates and issues commands to control access to the memory device 1062.

[0141] The connections 1070 include hardware devices (e.g., wireless or wired connectors and communication hardware or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to enable the system 1000 to communicate with external devices. The external devices can be other computing devices, separate devices such as wireless access points or base stations, and peripherals such as headsets, printers or other devices. In one example, the system 1000 exchanges data with the external devices for storage in memory or for display on a display device. The exchanged data can include data to be stored in memory or data already stored in memory for reading, writing or editing the data.

[0142] The connection 1070 may include multiple different types of connections. For generalization, the system 1000 is shown with a cellular connection 1072 and a wireless connection 1074. The cellular connection 1072 generally refers to a cellular network connection provided by a wireless carrier, such as provided via GSM (Global System for Mobile Communications) or variants or derivatives thereof, or CDMA (Code Division Multiple Access) or variants or derivatives thereof, TDM (Time Division Multiplexing) or variants or derivatives thereof, LTE (Long Term Evolution, also referred to as "4G"), 5G, or other cellular service standards. The wireless connection 1074 refers to a wireless connection that is not cellular and may include a personal area network (such as Bluetooth), a local area network (such as WiFi), or a wide area network (such as WiMAX), or other wireless communications, or a combination thereof. Wireless communications refers to the transfer of data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communications occur by means of a solid communications medium.

[0143] The peripheral connections 1080 include hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) for making the peripheral connections. It is understood that the system 1000 may comprise peripheral devices that are peripheral to other computing devices ("out" 1082) and that are connected to the system 1000 ("from" 1084). The system 1000 typically has a "docking" connector that connects to other computing devices for purposes such as managing (e.g., downloading, uploading, modifying, synchronizing) content on the system 1000. In addition, the docking connector may enable the system 1000 to connect to certain peripherals that allow the system 1000 to control content that is output to, for example, an audiovisual system or other system.

[0144] In addition to proprietary docking connectors or other proprietary connection hardware, system 1000 may make peripheral connections 1080 through common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a number of different hardware interfaces), MiniDisplayPort (MDP), DisplayPort including High-Definition Multimedia Interface (HDMI®), or other types.

[0145] Generally with respect to the description herein, in one example, a memory controller includes a hardware interface coupled to a memory device and command logic that generates a retry command for the memory device, the retry command being configured to trigger the memory device to return read data without applying error checking and correction (ECC) by an ECC circuit of the memory device.

[0146] In one example, the command logic may include a of In one example, the command logic is adapted to generate a command having a command encoding: In one example, the command logic is adapted to generate a series of consecutive read commands to the same address to indicate a retry command. In one example, the command logic is adapted to generate a mode register write command to set a mode register of the memory device to a retry command mode, the command logic being adapted to: R To show the try command , the memory device While in retry command mode To In one example, the command logic is adapted to generate a retry command in response to receiving erroneous data received in response to a previous read command. In one example, the hardware interface is adapted to generate a retry command in response to receiving an indication of a detected uncorrectable error (DUE) from the memory device in response to a previous read command. MarkThe command logic receives the DUE instruction from the memory device. mark In one example, the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard.

[0147] Generally speaking, in one example, the memory device may include: In response to a read command, receiving read data and applying ECC to the read data within the memory device; Correction an error checking and correction (ECC) circuit that returns corrected data; and a hardware interface that receives a retry command after a read command, and in response to the retry command: The hardware interface is ECC by ECC circuit but Applicable Not yet A hardware interface adapted to return read data.

[0148] In one example, the retry command may be of In one example, the retry command includes a series of read commands with no other intervening commands. In one example, the memory device further includes a register that stores an address of the read command, and the memory device further includes a register that stores an address of the read command, and the address of the read command stored in the register is 、The memory device is adapted to decode the successive read commands as a retry command if the address of the read command matches the address of a subsequent read command sent without other intervening commands. In one example, the memory device further comprises a mode register storing a field to indicate a retry command mode, and the retry command includes a read command received in the retry command mode. In one example, the hardware interface is adapted to bypass the ECC circuitry to return the read data without applying ECC. In one example, the ECC circuitry detects the ECC error and returns the read data to trigger the host to send a retry command. was done An uncorrectable error (DUE) is indicated to the host. In one example, the memory device includes a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard.

[0149] Generally with respect to the description herein, in one example, a system includes a memory device having error checking and correction (ECC) circuitry that internally applies ECC to read data in response to a read command and returns the corrected data in response to the read command, and a memory controller having command logic that generates a read command and generates a retry command after the read command, where the retry command triggers the memory device to return the read data without applying ECC by the memory device's ECC circuitry.

[0150] In one example, the retry command may be of In one example, the retry command includes a sequence of read commands with no other intervening commands, and the memory device is adapted to decode the sequence of read commands as the retry command. In one example, the memory device further includes a mode register that stores a field to indicate a retry command mode, and the memory controller is adapted to: To indicate a retry command, Memory device R While in try command mode To , and transmits a read command. In one example, the memory device includes a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. In one example, the system further includes one or more of a host processor device coupled to the memory controller, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery that provides power to the system.

[0151] The flow diagrams illustrated herein provide examples of sequences of various process actions. The flow diagrams may depict operations performed by software or firmware routines as well as physical operations. The flow diagrams may depict an example of an implementation of states of a finite state machine (FSM), which may be implemented in hardware and / or software. Although shown in a particular sequence or order, unless otherwise noted, the order of operations may be changed. Thus, the illustrated diagrams should be understood as merely examples, and processes may be performed in different orders and some operations may be performed in parallel. Additionally, one or more actions may be omitted, and therefore not all implementations may perform all actions.

[0152] To the extent that various operations or functions are described herein, they may be described or defined as software code, instructions, configurations, and / or data. The content may be directly executable (in "object" or "executable" format), source code, or differential code (in "delta" or "patch" code). The software content described herein may be provided via a product in which the content is stored, or via a method of operating a communications interface to transmit data through the communications interface. A machine-readable storage medium may cause a machine to perform the described functions or operations, and includes any mechanism for storing information in a form accessible by a machine (e.g., computing device, electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface may include any mechanism for interfacing with any of the hardwired, wireless, optical, etc. media for communicating with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communications interface may be configured by providing configuration parameters and / or sending signals to prepare the communications interface to provide data signals describing the software content. The communications interface may be accessed via one or more commands or signals sent to the communications interface.

[0153] Various components described herein may be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. A component may be implemented as a software module, a hardware module, dedicated hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), an embedded controller, a hardwired circuit, etc.

[0154] In addition to what is described herein, various modifications can be made to the disclosed contents and implementations of the present invention without departing from the scope thereof. Therefore, the descriptions and examples herein should be interpreted in an illustrative, rather than a limiting sense. The scope of the present invention should be determined solely by reference to the claims that follow. (Item 1) A hardware interface coupled to a memory device; command logic for generating a retry command for the memory device; Equipped with The retry command is configured to trigger the memory device to return read data without applying error checking and correction (ECC) by an ECC circuit of the memory device. (Item 2) The memory controller of item 1, wherein the command logic is configured to generate a command having a command encoding to indicate the retry command. (Item 3) The memory controller of item 1, wherein the command logic is configured to generate a series of consecutive read commands to the same address to indicate the retry command. The command logic is configured to generate a mode register write command to set a mode register of the memory device to a retry command mode; 2. The memory controller of claim 1, wherein the command logic is configured to generate a read command to be sent while the memory device is in the retry command mode to indicate the retry command. (Item 5) The memory controller of item 1, wherein the command logic is configured to generate the retry command in response to receiving erroneous data received in response to a previous read command. (Item 6) A memory controller as described in Item 5, wherein the hardware interface is configured to receive an indication of a detected uncorrectable error (DUE) from the memory device in response to the previous read command, and the command logic is configured to generate the retry command in response to the indication of the DUE from the memory device. (Item 7) The memory controller of item 1, wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. (Item 8) A memory device, an error checking and correction (ECC) circuit for receiving read data, applying ECC to the read data within the memory device, and returning corrected data in response to a read command; a hardware interface that receives a retry command after the read command, the hardware interface being configured in response to the retry command to return the read data without applying ECC by the ECC circuit; A memory device comprising: (Item 9) The memory device of item 8, wherein the retry command includes a command having a command encoding to indicate the retry command. (Item 10) The memory device of item 8, wherein the retry command includes a series of read commands with no other intervening commands. (Item 11) A memory device as described in Item 10, further comprising a register for storing an address of the read command, wherein the memory device is configured to decode the series of read commands as the retry command if the address of the read command stored in the register matches the address of a subsequent read command sent without any other intervening commands. (Item 12) Further comprising a mode register for storing a field for indicating a retry command mode, 9. The memory device of claim 8, wherein the retry command includes a read command received in the retry command mode. (Item 13) The memory device of item 8, wherein the hardware interface is configured to bypass the ECC circuitry to return the read data without applying ECC. (Item 14) The memory device of item 8, wherein the ECC circuit is configured to indicate a detected uncorrectable error (DUE) to the host to trigger the host to send the retry command. (Item 15) The memory device of item 8, wherein the memory device includes a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. (Item 16) A memory device having an error checking and correction (ECC) circuit that internally applies ECC to read data in response to a read command and returns corrected data in response to the read command; a memory controller having command logic for generating the read command and generating a retry command after the read command; Equipped with The retry command is adapted to trigger the memory device to return read data without applying ECC by the ECC circuitry of the memory device. (Item 17) The system described in item 16, wherein the retry command includes a command having a command encoding to indicate the retry command. (Item 18) The system described in Item 16, wherein the retry command includes a series of read commands with no other intervening commands, and the memory device is configured to decode the series of read commands as the retry command. (Item 19) The memory device further includes a mode register that stores a field for indicating a retry command mode, 20. The system of claim 16, wherein the memory controller is configured to send a read command while the memory device is in the retry command mode to indicate the retry command. (Item 20) The system of item 16, wherein the memory device includes a synchronous dynamic random access memory (SDRAM) device compatible with the double data rate (DDR) standard. 21. A host processor device coupled to the memory controller. a display communicatively coupled to the host processor; a network interface communicatively coupled to the host processor; or a battery for powering said system; Item 17. The system of item 16, further comprising one or more of:

Claims

1. a hardware interface coupled to the memory device; command logic that generates a retry command for the memory device; Equipped with The command logic generates the retry command in response to receiving an indication of a detected uncorrectable error (DUE) transmitted from the memory device in response to a previous read command; The retry command triggers the memory device to return read data without applying error checking and correction (ECC) by an ECC circuit of the memory device.

2. A first register for storing aliased corrected read data to which the ECC has been applied, the read data having been received in response to the previous read command; a second register for storing uncorrected read data without the ECC applied thereto received in response to the retry command; and 2. The memory controller of claim 1, further comprising: a comparator that compares the aliased corrected read data in the first register with the uncorrected read data in the second register and converts the DUE to a correctable error (CE) based on a comparison result.

3. The memory controller of claim 1 , wherein the command logic generates a command having a command encoding to indicate the retry command.

4. 2. The memory controller of claim 1, wherein the command logic generates a series of consecutive read commands to a same address to indicate the retry command.

5. the command logic generates a mode register write command to set a mode register of the memory device to a retry command mode; 2. The memory controller of claim 1, wherein the command logic generates a read command to send to indicate the retry command while the memory device is in the retry command mode.

6. The memory controller of claim 1 , wherein the command logic receives aliased error data transmitted along with the DUE from the memory device in response to the previous read command.

7. The memory controller of any preceding claim, wherein the memory devices comprise synchronous dynamic random access memory (SDRAM) devices compatible with the Double Data Rate (DDR) standard.

8. 1. A memory device comprising: an error checking and correction (ECC) circuit responsive to a read command to receive read data, apply ECC to the read data within the memory device, and return corrected data; a hardware interface receiving a retry command after the read command, the hardware interface returning the read data without applying ECC by the ECC circuit in response to the retry command; Equipped with A memory device, wherein the ECC circuit indicates a detected uncorrectable error (DUE) to a host to trigger the host to send the retry command.

9. The memory device of claim 8 , wherein the retry command comprises a command having a command encoding to indicate the retry command.

10. The memory device of claim 8 , wherein the retry command comprises a series of read commands with no other intervening commands.

11. 11. The memory device of claim 10, further comprising a register that stores an address of the read command, wherein the memory device decodes the series of read commands as the retry command if the address of the read command stored in the register matches an address of a subsequent read command sent without any other intervening commands.

12. a mode register storing a field for indicating a retry command mode; The memory device of claim 8 , wherein the retry command comprises a read command received in the retry command mode.

13. The memory device of any one of claims 8 to 12, wherein the hardware interface bypasses the ECC circuitry in order to return the read data without ECC applied.

14. The memory device of any one of claims 8 to 13, wherein the memory device comprises a Synchronous Dynamic Random Access Memory (SDRAM) device compatible with the Double Data Rate (DDR) standard.

15. a memory device having an error checking and correction (ECC) circuit that, in response to a read command, applies an ECC internally to read data and returns corrected data to a memory controller, the ECC circuit detecting that the corrected data includes a detected uncorrectable error (DUE) and returning an indication of the DUE to the memory controller along with the corrected data; a memory controller having command logic for generating the read command and for generating a retry command in response to the indication of the DUE received from the memory device after the read command; Equipped with The retry command triggers the memory device to return read data without applying ECC by the ECC circuitry of the memory device.

16. The system of claim 15 , wherein the retry command comprises a command having a command encoding to indicate the retry command.

17. 16. The system of claim 15, wherein the retry command comprises a series of read commands with no other intervening commands, and the memory device decodes the series of read commands as the retry command.

18. the memory device further comprising a mode register storing a field for indicating a retry command mode; 16. The system of claim 15, wherein the memory controller sends a read command to indicate the retry command while the memory device is in the retry command mode.

19. The system of any one of claims 15 to 18, wherein the memory device comprises a synchronous dynamic random access memory (SDRAM) device compatible with the Double Data Rate (DDR) standard.

20. a host processor device coupled to the memory controller; a display communicatively coupled to the host processor; a network interface communicatively coupled to the host processor; or a battery for powering said system; The system of any one of claims 15 to 19, further comprising one or more of:

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