Composite Board

Abstract

To provide a composite substrate capable of realizing a device with small light propagation loss and capable of being driven at a low voltage.SOLUTION: A composite substrate according to an embodiment of the present invention includes an indium phosphide substrate, a barrier layer formed directly on the indium phosphide substrate, and a silicon substrate, and the barrier layer and the silicon substrate are directly bonded, and an amorphous layer is formed at the bonding interface between the barrier layer and the silicon substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a composite substrate. [Background technology]

[0002] In the fields of optical communication, millimeter wave to terahertz wave communication, optical information processing, optical computing, and the like, it is expected that a technology for integrating and integrating optical devices and electronic devices (photonics-electronics convergence technology) will be put to practical use. For example, a composite substrate including a silicon substrate on which an optical circuit and a driving IC circuit are formed, and an indium phosphide (InP) substrate on which a light source, a photodiode, an optical modulator, and the like are formed is being developed. Such a composite substrate can be typically manufactured by a process including bonding a silicon substrate on which an optical circuit and a driving IC circuit are formed, and an InP substrate; and subjecting the InP substrate bonded to the silicon substrate to a semiconductor processing process such as epitaxial growth, etching, and sputtering to form a light source, a photodiode, an optical modulator, and the like. However, such a composite substrate may cause optical propagation loss and / or a high driving voltage in the resulting device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 2675519 Summary of the Invention [Problem to be solved by the invention]

[0004] A primary object of the present invention is to provide a composite substrate capable of realizing a device that has a small optical propagation loss and can be driven at a low voltage. [Means for solving the problem]

[0005] A composite substrate according to an embodiment of the present invention includes an indium phosphide substrate, a barrier layer formed directly on the indium phosphide substrate, and a silicon substrate, the barrier layer and the silicon substrate being directly bonded to each other, and an amorphous layer being formed at the bonding interface between the barrier layer and the silicon substrate. In one embodiment, a bonding layer is formed directly on the silicon substrate, the barrier layer is directly bonded to the bonding layer, and an amorphous layer is formed at the bonding interface between the barrier layer and the bonding layer. In one embodiment, a low refractive index layer is formed on the silicon substrate. In one embodiment, an optical circuit is formed on the silicon substrate. In one embodiment, the barrier layer is a conductive layer. In one embodiment, the barrier layer is composed of indium oxide or indium tin oxide. In one embodiment, the indium phosphide substrate has a thickness of 500 nm or less. Effect of the Invention

[0006] According to an embodiment of the present invention, in a composite substrate including a silicon substrate and an indium phosphide (InP) substrate, a predetermined barrier layer is directly formed on the InP substrate, thereby making it possible to obtain a composite substrate capable of realizing a device that has small optical propagation loss and can be driven at a low voltage. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a composite substrate according to one embodiment of the present invention. [Diagram 2] 2 is a schematic cross-sectional view of a composite substrate according to another embodiment of the present invention. [Diagram 3] 1 is a schematic cross-sectional view of a composite substrate according to yet another embodiment of the present invention. [Figure 4] 1 is a schematic cross-sectional view of a composite substrate according to yet another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to these embodiments. Note that the drawings are schematic for ease of viewing, and the ratio of length, width, and thickness, as well as the shape, may differ from the actual ones.

[0009] A. Overall structure of the composite board FIG. 1 is a schematic cross-sectional view of a composite substrate according to an embodiment of the present invention. The composite substrate 100 in the illustrated example includes an indium phosphide (InP) substrate 10, a barrier layer 21, and a silicon substrate 30. In the embodiment of the present invention, the barrier layer 21 is formed directly on the InP substrate 10. The barrier layer 21 can be formed on the surface of the InP substrate 10 by, for example, sputtering. By forming the barrier layer directly on the InP substrate, the InP substrate is not directly irradiated with inert gas or plasma during direct bonding (described later), so that damage to the InP substrate can be suppressed, and the migration and intrusion of impurities into the InP substrate can be significantly suppressed, and therefore the occurrence of damage in the InP substrate and the progression of the damage associated with the semiconductor processing process can be significantly suppressed. Representative examples of impurities include the inert gas or plasma used in direct bonding and silicon in the silicon substrate.

[0010] The surface roughening of an InP substrate caused by exposure to an inert gas is described in detail in the following document: Journal of surface analysis Vol.10 No.3 250-255,2003 According to this document, for example, when argon ions are irradiated onto an InP substrate, phosphorus (P) is selectively sputtered, causing In to precipitate, resulting in surface roughness. In a state where such surface roughness exists, damage often occurs when performing semiconductor processing such as epitaxial growth and etching. According to the above-described configuration of the embodiment of the present invention, surface roughness of the InP substrate can be significantly suppressed, and damage during the semiconductor processing can be significantly suppressed. As a result, a composite substrate can be obtained that can realize a device that has small optical propagation loss and can be driven at a low voltage.

[0011] In the embodiment of the present invention, the barrier layer 21 and the silicon substrate 30 are directly bonded. In this specification, "direct bonding" means that the components of the composite substrate (the barrier layer 21 and the silicon substrate 30 in the example of FIG. 1) are bonded without the use of an adhesive. The form of direct bonding can be appropriately set depending on the configuration of the layers or substrates to be bonded to each other. More specifically, the direct bonding may be performed by plasma bonding or a surface activation method. For example, the surface activation method can be performed by the following procedure. In a high vacuum chamber (e.g., 1×10 -6A neutralizing beam is irradiated to each of the bonding surfaces of the components (layers or substrates) to be bonded at a pressure of about 100 Pa. This activates each bonding surface. Next, the activated bonding surfaces are brought into contact with each other in a vacuum atmosphere and bonded at room temperature. The load during this bonding can be, for example, 100 N to 20,000 N. In one embodiment, when performing surface activation using the neutralizing beam, an inert gas is introduced into the chamber, and a high voltage is applied from a DC power source to an electrode placed in the chamber. With this configuration, electrons are moved by an electric field generated between the electrode (positive electrode) and the chamber (negative electrode), and a beam of atoms and ions is generated by the inert gas. Of the beams that reach the grid, the ion beam is neutralized by the grid, and a beam of neutral atoms is emitted from the high-speed atom beam source. The atomic species that constitute the beam is preferably an inert gas element (for example, argon (Ar), neon (Ne), krypton (Kr), helium (He), nitrogen (N), or xenon (Xe)). The voltage during activation by beam irradiation is, for example, 0.5 kV to 2.0 kV, and the current is, for example, 50 mA to 200 mA.

[0012] The InP substrate 10 and the silicon substrate 30 are integrated by the above-mentioned direct bonding. Such integration allows the optical device and the electronic device to be highly integrated and allows ultra-miniaturization to be realized. Furthermore, since there is no need to bond the optical device and the electronic device by wire bonding or the like, stray capacitance can be significantly suppressed. Such advantages of integrating the InP substrate and the silicon substrate have been theoretically understood. However, when actually attempting to integrate, it was found that the inert gas or plasma used in the direct bonding and / or silicon of the silicon substrate migrates to the InP substrate, causing damage in the InP substrate, and that the damage also progresses in the optical device (e.g., photodiode, optical modulator) formed on the InP substrate by epitaxial growth or the like. As a result, in the obtained device, problems such as light propagation loss and / or high driving voltage often occur, making it difficult to achieve sufficient performance. Furthermore, due to such problems, when integrating the InP substrate and the silicon substrate (typically, the optical device and the electronic device), it was necessary to integrate the InP substrate and the silicon substrate on which the device was formed beforehand, respectively. According to the embodiment of the present invention, such problems can be significantly suppressed by forming a specific barrier layer directly on the InP substrate, and it is possible to realize the integration of the InP substrate and the silicon substrate with sufficient performance, which has been desired for a long time but has been difficult to realize. Furthermore, the InP substrate and the silicon substrate can be integrated to form a composite substrate, and the composite substrate (particularly the InP substrate) can be subjected to a semiconductor processing process. In addition, by performing the integration by directly bonding the barrier layer 21 and the silicon substrate 30, it is possible to effectively suppress the peeling of the composite substrate, and as a result, it is possible to effectively suppress damage (e.g., cracks) of the InP substrate caused by such peeling. Furthermore, by directly bonding without using an adhesive, it is possible to eliminate the adverse effects caused by the deterioration and deformation of the adhesive, and therefore it is possible to realize high reliability. In addition, there is no dielectric loss due to the adhesive.

[0013] Typically, an amorphous layer 40 is formed at the bonding interface between the barrier layer 21 and the silicon substrate 30 .

[0014] FIG. 2 is a schematic cross-sectional view of a composite substrate according to another embodiment of the present invention. In the composite substrate 101 shown in the figure, a bonding layer 22 is formed directly on a silicon substrate 30, and the barrier layer 21 and the bonding layer 22 are directly bonded to each other. An amorphous layer 40 is formed at the bonding interface between the barrier layer 21 and the bonding layer 22. By forming the bonding layer, a synergistic effect can be obtained with the effect of forming the barrier layer. That is, the migration and intrusion of impurities (particularly silicon of the silicon substrate) into the InP substrate can be further significantly suppressed. As a result, in the obtained device, the optical propagation loss can be further suppressed and it is possible to operate at a lower voltage.

[0015] In the embodiment of the present invention, a low refractive index layer may be formed on the silicon substrate 30. The low refractive index layer contributes to improving the confinement efficiency of an optical waveguide formed on a silicon substrate or an InP substrate, and to achieving a velocity matching condition for realizing high-speed modulation operation, and may also function as an insulating film. The low refractive index layer may be made of a material having a smaller refractive index than silicon or InP. The low refractive index layer is made of, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), magnesium fluoride (MgF2), or calcium fluoride (CaF2). The low refractive index layer is typically formed directly on the silicon substrate. By forming a low refractive index layer on the silicon substrate, it is possible to reduce stray capacitance, and as a result, it is possible to reduce signal delay and leakage current in the resulting device. When a low refractive index layer is formed on a silicon substrate, the low refractive index layer 50 and the barrier layer 21 may be directly bonded to each other, as in the composite substrate 102 of FIG. 3, and an amorphous layer 40 may be formed at the bonding interface between the barrier layer 21 and the low refractive index layer 50; or the barrier layer 21 and a bonding layer 22 formed directly on the low refractive index layer 50 may be directly bonded to each other, as in the composite substrate 103 of FIG. 4, and an amorphous layer 40 may be formed at the bonding interface between the barrier layer 21 and the bonding layer 22.

[0016] The components (substrates or layers) of the composite substrate will be specifically described below.

[0017] B.InP substrate The InP substrate can typically function as a substrate for an optical device. Here, in this specification, "light" is a concept that includes electromagnetic waves. The optical device can be formed on the InP substrate by any appropriate semiconductor processing process (e.g., epitaxial growth, etching, sputtering). As the optical device, any appropriate optical device according to the purpose can be adopted. In one embodiment, the optical device is an optical device that cannot be realized on a silicon substrate. With such a configuration, the effect of the composite substrate becomes remarkable. Specific examples of the optical device include a light source, a diode (e.g., a photodiode), an optical modulator, an optical delay device, and an optical deflector. Examples of the light source include a semiconductor laser such as a photonic crystal (LEAP) laser, a DFB laser, a DBR laser, and a VCSEL (vertical cavity surface emitting laser); and an active element that can oscillate, emit, and / or receive millimeter waves to terahertz waves. Examples of diodes include resonant tunneling diodes, Schottky diodes, Uni-Traveling-Carrier Photodiodes (UTC-PDs), avalanche photodiodes, and Single Photon Avalanche Diodes (SPADs). Examples of optical modulators include Mach-Zehnder modulators and electroabsorption modulators.

[0018] In one embodiment, the thickness of the InP substrate is preferably 500 nm or less, more preferably 480 nm or less, and further preferably 460 nm or less. If the thickness of the InP substrate is in such a range, it is possible to significantly suppress cracks when the composite substrate is subjected to a semiconductor processing process (epitaxial growth, etching, patterning) caused by the difference in the thermal expansion coefficient between InP (about 5 ppm / K) and silicon (about 3 ppm / K), and the resulting device characteristics becoming insufficient. The lower limit of the thickness of the InP substrate may be, for example, 100 nm. The InP substrate may be typically thinned by any appropriate method after integration with the silicon substrate. The InP substrate having such a thickness may typically be used for optical applications (for example, wavelengths used are 1 μm to 2 μm). When the InP substrate is used for millimeter wave to terahertz wave applications, the thickness of the InP substrate may be, for example, about 50 μm.

[0019] The inert gas element concentration in the InP substrate is preferably 5 atomic % or less, more preferably 2 atomic % or less. The lower limit of the inert gas element concentration in the InP substrate is preferably as small as possible, and the lower limit may be, for example, 0.1 atomic %. The inert gas element is typically derived from the neutral atomic beam during direct bonding. Therefore, the inert gas element may be, for example, argon (Ar), neon (Ne), krypton (Kr), helium (He), nitrogen (N) or xenon (Xe). According to the embodiment of the present invention, by forming a barrier layer, the migration and intrusion of the inert gas element used in direct bonding into the InP substrate can be significantly suppressed. As a result, such a very small inert gas element concentration can be realized. With such an inert gas element concentration, the occurrence of damage in the InP substrate and the progression of the damage accompanying the semiconductor processing process can be significantly suppressed. This makes it possible to realize a device that has small light propagation loss and can be driven at a low voltage.

[0020] The silicon concentration in the InP substrate is preferably 5 atomic % or less, more preferably 2 atomic % or less. The lower the silicon concentration in the InP substrate, the more preferable it is, and the lower limit may be, for example, 0.1 atomic %. As in the case of the above-mentioned inert gas element, according to the embodiment of the present invention, the migration and intrusion of silicon from the silicon substrate into the InP substrate can be significantly suppressed by forming a barrier layer. As a result, such a very small silicon concentration can be realized. As in the case of the above-mentioned inert gas element, such a silicon concentration can significantly suppress the occurrence of damage in the InP substrate and the progression of the damage accompanying the semiconductor processing process. This makes it possible to realize a device with small light propagation loss and capable of low voltage operation. By further forming a bonding layer, the effect can be further remarkable.

[0021] C. Silicon substrate An optical circuit may be formed on the silicon substrate, an electronic circuit (e.g., a driving IC circuit) may be formed, or both an optical circuit and an electronic circuit may be formed. Preferably, an optical circuit is formed on the silicon substrate. By forming an optical circuit, it becomes possible to form a circuit finer than the limit of the line width of an electronic circuit. As a result, it is possible to obtain effects such as an improvement in operating speed (operating frequency), an improvement in integration density (higher density), and a reduction in power consumption per operating frequency. Since the silicon substrate has excellent circuit multiplexing and branching properties, it is possible to form a good optical circuit (optical waveguide).

[0022] The thickness of the silicon substrate is preferably 150 μm to 1200 μm, more preferably 200 μm to 700 μm, and further preferably 250 μm to 550 μm. If the thickness of the silicon substrate is within this range, damage and warping of the composite substrate can be effectively suppressed even when a semiconductor processing process is carried out.

[0023] As described above, a low refractive index layer may be formed on the silicon substrate. The thickness of the low refractive index layer varies depending on the wavelength of the electromagnetic wave used. When the wavelength is 1 μm, the thickness of the low refractive index layer is preferably 0.1 μm to 10 μm, and more preferably 0.5 μm to 5 μm.

[0024] D. Barrier Layer The barrier layer may have any suitable structure as long as it has a predetermined barrier function (function capable of suppressing migration and intrusion of impurities into the InP substrate). Specific examples of materials constituting the barrier layer include indium oxide such as indium oxide (IO) and indium tin oxide (ITO); and amorphous silicon. Indium oxide is preferable. Indium oxide not only suppresses the diffusion of inert gases and silicon and suppresses damage, but also has the additional advantage of being less likely to become an impurity in the InP substrate because it is an indium compound like InP.

[0025] The barrier layer is preferably a conductive layer. With this configuration, when the InP substrate is thinned, the resonance within the substrate can be well suppressed. More specifically, when the InP substrate is thinned (for example, to about 50 μm) for use in a device for millimeter waves to terahertz waves, the silicon substrate can function as a reinforcing substrate (support substrate). In this case, the total thickness of the InP substrate and the silicon substrate is the thickness that affects the resonance. That is, even if the InP substrate is thinned, if the total thickness is the thickness that causes resonance (thickness of the wavelength size of millimeter waves to terahertz waves), the effect of thinning the InP substrate may not be obtained. In contrast, by making the barrier layer between the InP substrate and the silicon substrate a conductive layer, the barrier layer (conductive layer) functions as a ground layer, and it is possible to prevent an electric field from existing below the barrier layer (on the silicon substrate side). As a result, since only the thickness of the InP substrate is related to the resonance, the thickness of the InP substrate is thinned to a desired range, and the resonance within the substrate can be well suppressed.

[0026] The thickness of the barrier layer may be any appropriate thickness. The thickness of the barrier layer is preferably 0.1 nm to 0.5 μm, and more preferably 2 nm to 0.1 μm. If the thickness of the barrier layer is within this range, it is possible to prevent inert gas ions (e.g., argon ions) from reaching the InP substrate and being sputtered during direct bonding, and to prevent the diffusion of silicon atoms.

[0027] E. Bonding layer The bonding layer 22 may be made of any suitable material depending on the purpose, such as amorphous silicon or an indium-based compound.

[0028] The bonding layer 22 may have the same configuration as the barrier layer 21 (substantially the same constituent material and the same thickness), or may have a different configuration.

[0029] When the bonding layer 22 has the same structure as the barrier layer 21, there are the following advantages. When the barrier layer 21 and the bonding layer 22, which are made of different materials, are directly bonded to each other, the materials (substantially, atoms) constituting the barrier layer and the bonding layer may diffuse and migrate to each other through the amorphous layer formed at the bonding interface. As a result, the portions of the barrier layer and the bonding layer near the amorphous layer may have compositions different from those of the other portions. As a result, an unexpected increase in electrical conductivity and / or the occurrence of excessive stress may occur. By forming the barrier layer and the bonding layer from the same material, such problems can be prevented. In this case, the bonding layer and the barrier layer may each be made of indium oxide or amorphous silicon.

[0030] When the bonding layer 22 has a different structure from the barrier layer 21, the bonding layer may preferably be made of amorphous silicon, and the barrier layer may preferably be made of an indium-based compound (typically, indium oxide). Such a structure has the following advantages. By making the barrier layer out of an indium-based compound, not only can the diffusion of inert gas and silicon be suppressed and damage can be suppressed, but there is also the further advantage that, since it is an indium compound like InP, it is unlikely to become an impurity in the InP substrate. Furthermore, by making the bonding layer out of amorphous silicon, there is the further advantage that direct bonding is made easier, the conductivity is easier to control, and it is unlikely to become an impurity in the silicon substrate. These advantages and effects can be exhibited synergistically.

[0031] The thickness of the bonding layer may be any appropriate thickness. The thickness of the bonding layer is preferably 0.1 nm to 0.5 μm, and more preferably 1 nm to 0.1 μm. If the thickness of the bonding layer is in this range, there is an advantage that warping is reduced in direct bonding with the barrier layer and bonding strength can be ensured.

[0032] F. Amorphous layer The amorphous layer 40 is a layer formed at the bonding interface by direct bonding between the barrier layer 21 and an adjacent layer (silicon substrate 30, bonding layer 22, or low refractive index layer 50). The formation of the amorphous layer and the effect of the barrier layer have a synergistic effect, which can promote the impurity capture function. As the name suggests, the amorphous layer 40 has an amorphous structure and contains elements constituting the barrier layer 21 and elements constituting the adjacent layer. The amorphous layer may further contain atomic species (representatively, argon, neon, krypton, helium, nitrogen, and xenon) constituting the neutral atomic beam used for direct bonding. The content of such atomic species in the amorphous layer may be, for example, 1.5 atomic % to 2.5 atomic %.

[0033] The thickness of the amorphous layer can be, for example, 0.1 nm to 100 nm, or, for example, 2 nm to 15 nm.

[0034] The amorphous layer 40 is formed by the diffusion of atoms of the constituent materials of the barrier layer 21 and an adjacent layer at the direct junction between these layers. The upper surface of the amorphous layer forms a clear interface with the barrier layer 21, and the lower surface forms a clear interface with an adjacent layer (silicon substrate, bonding layer, or low refractive index layer). The upper surface (interface with the barrier layer 21) and the lower surface (interface with the adjacent layer) of the amorphous layer are not necessarily flat. The arithmetic mean roughness of the upper and lower surfaces of the amorphous layer may be, for example, 0.1 nm to 10 nm. Furthermore, due to such a formation process, the upper and lower portions of the amorphous layer may have different compositions. EXAMPLES

[0035] The present invention will be described in detail below with reference to examples, but the present invention is not limited to these examples.

[0036] Example 1 The composite substrate having the configuration shown in FIG. 1 was fabricated according to the following procedure. A semi-insulating, high-resistance InP substrate with a diameter of 3 inches and a thickness of 500 μm, and a silicon substrate with a diameter of 4 inches and a thickness of 525 μm were prepared. First, indium oxide was sputtered onto the InP substrate to form a barrier layer with a thickness of 0.1 μm. After forming the barrier layer, the arithmetic mean roughness of the barrier layer and silicon substrate over a 10 μm square was measured using an atomic force microscope, and both were found to be 0.2 nm over a 10 μm square. Next, the surfaces of the barrier layer and the silicon substrate were cleaned, and the barrier layer and the silicon substrate were directly bonded to integrate the InP substrate and the silicon substrate. The direct bonding was performed as follows. The InP substrate and the silicon substrate were placed in a vacuum chamber and heated for 10 -6In a vacuum of the Pa range, the bonding surfaces (barrier layer and silicon substrate surfaces) of the InP substrate and silicon substrate were irradiated with a high-speed Ar neutral atom beam (accelerating voltage 1 kV, Ar flow rate 60 sccm) for 70 seconds. After irradiation, the InP substrate and silicon substrate were left to cool for 10 minutes, and then the bonding surfaces (barrier layer and silicon substrate beam irradiated surfaces) of the InP substrate and silicon substrate were brought into contact and pressed at 4.90 kN for 2 minutes to directly bond the barrier layer and silicon substrate, thereby integrating the InP substrate and silicon substrate. It was confirmed that an amorphous layer was formed at the bonding interface between the barrier layer and silicon substrate. After bonding, the InP substrate was polished until the thickness was 460 nm, and the InP / silicon composite substrate shown in Figure 1 was obtained. No defects such as peeling were observed at the bonding interface of the obtained composite substrate.

[0037] After polishing, the argon ion concentration on the surface of the InP substrate, the InP composition ratio In / (In+P), and surface roughness were evaluated. The argon ion concentration was measured by EDX (energy dispersive X-ray analysis). The InP composition ratio was analyzed by Auger spectroscopy. The presence or absence of surface roughness was inspected by microscope observation. The results are shown in Table 1.

[0038] Example 2 A composite substrate having the configuration shown in FIG. 2 was obtained in the same manner as in Example 1, except that a bonding layer (thickness 0.03 μm) was formed on the surface of the silicon substrate using amorphous silicon, and the barrier layer and the bonding layer were directly bonded to each other. It was confirmed that an amorphous layer was formed at the bonding interface between the barrier layer and the bonding layer. The obtained composite substrate was subjected to the same evaluation as in Example 1. The results are shown in Table 1.

[0039] Example 3 A composite substrate having the configuration shown in FIG. 4 was obtained in the same manner as in Example 1, except that an optical circuit (optical waveguide) was formed on a silicon substrate, a low refractive index layer (thickness 4 μm) was formed on the surface of the silicon substrate using SiO2, a bonding layer (thickness 0.03 μm) was formed on the low refractive index layer using amorphous silicon, and the barrier layer and the bonding layer were directly bonded to each other. It was confirmed that an amorphous layer was formed at the bonding interface between the barrier layer and the bonding layer. The obtained composite substrate was subjected to the same evaluation as in Example 1. The results are shown in Table 1.

[0040] Comparative Example 1 A composite substrate was obtained in the same manner as in Example 1, except that no barrier layer was formed on the InP substrate, i.e., the InP substrate and the silicon substrate were directly bonded together. The obtained composite substrate was subjected to the same evaluation as in Example 1. The results are shown in Table 1.

[0041] [Table 1]

[0042] As is clear from Table 1, according to the embodiment of the present invention, by forming a barrier layer on the InP substrate, the concentration of argon ions that cause damage to the InP substrate is suppressed after direct bonding and polishing of the InP substrate, and no deterioration of the InP composition ratio or surface roughness is observed. Therefore, it is understood that the composite substrate of the embodiment can realize a device that has small optical propagation loss and can be driven at a low voltage. [Industrial Applicability]

[0043] A composite substrate according to an embodiment of the present invention can be suitably used in the fields of optical communications, millimeter wave to terahertz wave communications, optical information processing, optical computing, and the like. [Explanation of symbols]

[0044] 10 InP substrate 21 Barrier Layer 22 Bonding layer 30 Silicon Substrate 40 Amorphous layer 50 Low refractive index layer 100 Composite Board 101 Composite board 102 Composite Board 103 Composite Board

Claims

1. The semiconductor device includes an indium phosphide substrate, a barrier layer formed directly on the indium phosphide substrate, and a silicon substrate; the barrier layer is directly bonded to the silicon substrate; an amorphous layer is formed at a bonding interface between the barrier layer and the silicon substrate; The inert gas element concentration in the indium phosphide substrate is 0.1 atomic % to 5 atomic %. Composite board.

2. a bonding layer is formed directly on the silicon substrate, and the barrier layer and the bonding layer are directly bonded to each other; an amorphous layer is formed at a bonding interface between the barrier layer and the bonding layer; The composite substrate according to claim 1 .

3. The composite substrate according to claim 1 , wherein a low refractive index layer is formed on the silicon substrate.

4. 4. The composite substrate according to claim 1, wherein an optical circuit is formed on the silicon substrate.

5. The composite substrate according to claim 1 , wherein the barrier layer is a conductive layer.

6. The composite substrate of claim 5 , wherein the barrier layer is comprised of indium oxide or indium tin oxide.

7. 7. The composite substrate according to claim 1, wherein the indium phosphide substrate has a thickness of 500 nm or less.

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