Test circuit and method for analog neural memories in artificial neural networks - Patents.com

Abstract

To provide a test circuit and a method that use with an analog neural memory in a deep learning artificial neural network.SOLUTION: A method comprises steps of: programming, during a bit line sampling screen test, a memory cell or a set of memory cells to a particular level measuring a bit line current K times; calculating, on the basis of K measured values, an average value; and considering, when any of the K current measurements is more than a threshold less than or more than the average value, a bit line to be defective.SELECTED DRAWING: Figure 35

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 62 / 876,515, filed July 19, 2019, entitled "Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network," and U.S. Patent Application No. 16 / 569,647, filed September 12, 2019, entitled "Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network."

[0002] FIELD OF THEINVENTION A test circuit and method are disclosed for use with an analog neural memory in a deep learning artificial neural network, the analog neural memory including one or more arrays of non-volatile flash memory cells. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages.

[0004] FIG. 1 shows an artificial neural network, where the circles represent layers of inputs or neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There is typically one or more hidden layers of neurons, and an output layer of neurons that provides the output of the neural network. At each level, the neurons make decisions, either individually or together, based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technologies. In practice, practical neural networks rely on a very large number of synapses, which allows high connectivity between neurons, i.e., a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated GPU (Graphics Processing Unit) clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses required.

[0006] Applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, published as U.S. Patent Publication No. 2017 / 0337466, which is incorporated by reference. The non-volatile memory array operates as an analog neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each memory cell including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed above and insulated from a first portion of the channel region, and a non-floating gate disposed above and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs with the stored weight values ​​to generate the first plurality of outputs. An array of memory cells used in this manner may be referred to as a vector matrix multiplication (VMM) array.

[0007] Each non-volatile memory cell used in an analog neural memory system must hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate in response to erasure and programming. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be exhibited by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0008] Because each individual memory cell can store one of N different levels (where N can be greater than 2, as opposed to conventional memory cells where N is always 2), precision and accuracy are very important in operations involving VMM arrays. Testing is therefore a critical operation. For example, verification of programming operations is necessary to ensure that each individual cell or column of cells is accurately programmed to a desired value. As another example, it is important to identify bad cells or groups of cells so that they can be removed from the set of cells used to store data during operation of the VMM array.

[0009] What is needed is an improved test circuit and method for use with VMM arrays. Summary of the Invention

[0010] Test circuits and methods are disclosed for use with analog neural memories in deep learning artificial neural networks. The analog neural memories include one or more arrays of non-volatile flash memory cells. The test circuits and methods may be utilized to verify the characteristics and operability of one or more cells during screening tests, cycling tests, high temperature operating life (HTOL) tests, qualification tests, and other tests.

[0011] One embodiment includes a method of verifying values ​​programmed into a plurality of non-volatile memory cells in an array of analog neural non-volatile memory cells, the array being arranged in rows and columns, with each row coupled to a word line and each column coupled to a bit line, each word line selectively coupled to a row decoder and each bit line selectively coupled to a column decoder, the method including the steps of asserting all word lines in the array by a row decoder, asserting bit lines in the array by a column decoder, sensing currents received from the bit lines by a sense amplifier, and comparing the currents to a reference current to determine if the non-volatile memory cells coupled to the bit lines contain a desired value.

[0012] Another embodiment includes a method of measuring current drawn by a plurality of nonvolatile memory cells in an array of analog neural nonvolatile memory cells, the array being arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line, each word line selectively coupled to a row decoder, and each bit line selectively coupled to a column decoder, the method including asserting, by the row decoder, all of the word lines in the array; asserting, by the column decoder, the bit lines in the array; and measuring the current received from the bit lines.

[0013] Another method includes a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, the array being arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line, each word line selectively coupled to a row decoder and each bit line selectively coupled to a column decoder, the method including the steps of asserting all word lines in the array by the row decoder, asserting all bit lines in the array by the column decoder, performing a deep programming operation on all non-volatile memory cells in the array, and measuring the total current received from the bit lines.

[0014] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the array arranged in rows and columns, with each row coupled to a word line and each column coupled to a bit line, the method including the steps of programming a plurality of cells coupled to the bit lines; measuring current drawn by the plurality of cells at K distinct times and storing the measured values ​​at each of the K distinct times, where K is an integer; calculating an average value based on the K measured values; and identifying a bit line as a faulty bit line if any of the K measured values ​​is less than the average value by more than a first threshold or greater than the average value by more than a second threshold.

[0015] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the array arranged in rows and columns, with each row coupled to a word line and each column coupled to a bit line, the method including the steps of programming a plurality of cells coupled to the bit lines; measuring voltages at control gate lines coupled to control gate terminals of the plurality of cells at K different times and storing the measured values ​​at each of the K different times, where K is an integer; calculating an average value based on the K measured values; and identifying a bit line as a faulty bit line if any of the K measured values ​​is less than the average value by more than a first threshold or greater than the average value by more than a second threshold.

[0016] Another embodiment includes a method of testing an analog neural non-volatile memory cell for storing N different values, where N is an integer, the method including the steps of programming the cell to a target value representing one of the N values, verifying that the value stored in the cell is within a window of acceptable values ​​centered around the target value, repeating the programming and reading steps for each of the N values, and identifying the cell as defective if any of the verifying steps indicate a value stored in the cell that is outside the window of acceptable values ​​centered around the target value.

[0017] Another embodiment includes a method of compensating for leakage in an array of analog neural non-volatile memory cells, the array arranged in rows and columns, with each row coupled to a word line and each column coupled to a bit line, the method including measuring leakage for a column of non-volatile memory cells coupled to the bit lines, storing the measured leakage value, and applying the measured leakage value during a read operation of the column of non-volatile memory cells to compensate for the leakage.

[0018] Another embodiment includes a method of testing a selected non-volatile memory cell in an array of analog neural non-volatile memory cells, the method including determining a logarithmic slope coefficient for the selected non-volatile memory cell while the selected non-volatile memory cell operates in a sub-threshold region, storing the logarithmic slope coefficient, determining a linear slope coefficient for the selected non-volatile memory cell while the selected non-volatile memory cell operates in a linear region, storing the linear slope coefficient, and utilizing one or more of the logarithmic slope coefficient and the linear slope coefficient when programming the selected cell to a target current.

[0019] Another embodiment includes a method of measuring a current drawn by a column of nonvolatile memory cells in an array of analog neural nonvolatile memory cells, the array being arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line, each word line selectively coupled to a row decoder and each bit line selectively coupled to a column decoder, the method including asserting, by the row decoder, all of the word lines in the array; asserting, by the column decoder, the bit lines in the array to select columns of nonvolatile memory cells; and measuring the current received from the bit lines.

[0020] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the method including erasing non-volatile memory cells in the array by applying a series of voltages to respective terminals of the non-volatile memory cells in the array, where the voltages in the series of voltages increase over time with a fixed step size, and reading all of the non-volatile memory cells to determine the effectiveness of the erasure step.

[0021] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the method including programming the non-volatile memory cells in the array by applying a series of voltages to respective terminals of the non-volatile memory cells in the array, where the voltages in the series of voltages increase over time by a fixed step size, and reading all of the non-volatile memory cells to determine the validity of the programming step.

[0022] Another embodiment includes a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, the array being arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line, each word line selectively coupled to a row decoder and each bit line selectively coupled to a column decoder, the method including the steps of programming the plurality of non-volatile memory cells to store one of N different values, N being the number of different levels that may be stored in any of the non-volatile memory cells; measuring a current drawn by the plurality of non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of non-volatile memory cells as defective if a difference between the measured value and the target value exceeds a threshold.

[0023] Another embodiment includes a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, the memory array arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line, each word line selectively coupled to a row decoder and each bit line selectively coupled to a column decoder, the method including the steps of programming a first selection of cells among the plurality of non-volatile memory cells with a level corresponding to a smallest cell current among N levels, and programming a second selection of cells among the plurality of non-volatile memory cells with a level corresponding to a largest cell current among the N levels, each of the cells in the second selection of cells being adjacent to one or more of the cells in the first selection of cells, measuring a current drawn by the plurality of non-volatile memory cells, comparing the measured current to a target value, and identifying the plurality of non-volatile memory cells as defective if a difference between the measured value and the target value exceeds a threshold.

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[0067] [Brief description of the drawings]

[0068] [Figure 1] FIG. 1 illustrates a prior art artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] 1 illustrates another prior art split-gate flash memory cell. [Figure 7] 1 shows a prior art stacked gate flash memory cell. [Figure 8] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 9] FIG. 1 is a block diagram illustrating a vector matrix multiplication system. [Figure 10] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more vector-matrix multiplication systems. [Figure 11] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 12] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 13] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 14]4 illustrates another embodiment of a vector matrix multiplication system. [Figure 15] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 16] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 17] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 18] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 19] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 20] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 21] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 22] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 23] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 24] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 25] 1 illustrates one embodiment of a vector matrix multiplication system including test control logic. [Figure 26] 1 shows a reference current source. [Figure 27] 27 shows a reference branch circuit for use with the reference current source of FIG. 26. [Figure 28] 1 shows a sense amplifier. [Figure 29A] A verification analog-to-digital converter is shown. [Figure 29B] A verification analog-to-digital converter is shown. [Diagram 30] A high voltage generation circuit is shown. [Diagram 31] 1 illustrates an exemplary test algorithm implemented by test control logic in a vector matrix multiplication system. [Diagram 32] 1 illustrates an embodiment of a bit line neural read test. [Diagram 33] 1 illustrates one embodiment of a bit line neural measurement test. [Diagram 34] 1 illustrates one embodiment of an LSB screen test. [Diagram 35] 1 illustrates one embodiment of a bit line sampling screen test. [Diagram 36] 13 illustrates another embodiment of a bit line sampling screen test. [Figure 37] 1 illustrates one embodiment of a read window check test. [Figure 38] 1 illustrates one embodiment of a read calibration test. [Figure 39] 1 illustrates one embodiment of a read gradient test. [Diagram 40] 1 illustrates one embodiment of a readout neuron qualification test. [Diagram 41] 1 illustrates one embodiment of a soft erase test. [Diagram 42] 1 illustrates one embodiment of a soft program test. [Diagram 43] 1 illustrates one embodiment of a validation test. [Diagram 44] 1 illustrates one embodiment of a checkerboard validation test. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0069] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. Non-volatile Memory Cell

[0070] Digital non-volatile memories are well known. For example, U.S. Patent No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A wordline terminal 22 (typically coupled to a wordline) has a first portion disposed above and insulated from (and controls the conductivity of) the second portion of the channel region 18, and a second portion extending upwardly over the floating gate 20. The floating gate 20 and wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline terminal 24 is coupled to the drain region 16.

[0071] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the wordline terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim tunneling from the floating gate 20 to the wordline terminal 22 through the insulator between them.

[0072] The memory cell 210 is programmed (electrons are applied to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the source region 14 (source line terminal) towards the drain region 16. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0073] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is detected as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is detected as the programmed or "0" state.

[0074] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the Flash Memory Cell 210 of FIG. 2 [Table 1] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0075] Figure 3 shows a memory cell 310 similar to memory cell 210 of Figure 2 with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0v / -8V) during erasure, and a low or medium voltage (e.g., 0v / 2.5V) during reading. The other terminals are biased similarly to those of Figure 2.

[0076] FIG. 4 shows a four-gate memory cell 410 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0077] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 2: Operation of Flash Memory Cell 410 of FIG. [Table 2] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0078] Figure 5 shows a memory cell 510 similar to memory cell 410 of Figure 4, except that memory cell 510 does not include an erase gate (EG) terminal. Erasing is accomplished by biasing the substrate 18 to a high voltage and the control gate CG terminal 28 to a low or negative voltage. Alternatively, erasure is accomplished by biasing the word line terminal 22 to a positive voltage and the control gate terminal 28 to a negative voltage. Programming and reading are similar to those of Figure 4.

[0079] Figure 6 shows another type of flash memory cell, a three-gate memory cell 610. Memory cell 610 is identical to memory cell 410 of Figure 4, except that memory cell 610 does not have a separate control gate terminal. Erase and read operations (where erasure occurs through the use of the erase gate terminal) are similar to those of Figure 4, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line terminal during a program operation to compensate for the lack of control gate bias.

[0080] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 610 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 610 of FIG. [Table 3] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0081] Figure 7 shows another type of flash memory cell, a stacked gate memory cell 710. Memory cell 710 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate terminal 22 (coupled to a wordline) extends over the floating gate 20, separated by an insulating layer (not shown). Erase, programming, and read operations operate in a similar manner as previously described for memory cell 210.

[0082] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 710 of FIG. [Table 4]

[0083] "Read 1" is a read mode in which the cell current is output to a bit line. "Read 2" is a read mode in which the cell current is output to a source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, a source line may be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, a source line terminal may be shared by adjacent rows of memory cells.

[0084] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0085] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog, or can at a minimum store one of many discrete values ​​(such as 16 or 64 different values), making every cell in the memory array very precisely and individually adjustable, and making the memory array ideal for storing and fine-tuning the weights of the synapses of a neural network.

[0086] The methods and means described herein can be applied to other non-volatile memory technologies, such as, but not limited to, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetoresistive RAM), FeRAM (ferroelectric RAM), OTP (bi-level or multi-level one-time programmable) and CeRAM (strongly correlated electron RAM). The methods and means described herein can be applied to, but not limited to, SRAM, DRAM, and volatile memory technologies used in neural networks, such as volatile synapse cells. Neural network using non-volatile memory cell arrays

[0087] 8 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiments. This example uses the non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using the non-volatile memory array-based neural network.

[0088] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel being 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters of 3x3 pixels (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 portion of the image (i.e., called filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and given by the first synapse of CB1 to generate one pixel of the layer of feature map C1. The 3x3 filter is then shifted one pixel to the right in the input layer S0 (i.e., add a column of 3 pixels to the right and drop a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of C1, until all feature maps of layer C1 have been calculated.

[0089] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, relationships, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify square edges, or the aspect ratio of a particular feature, etc.

[0090] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling function is to average nearby positions (or a max function can be used), e.g. to reduce edge position dependency, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e. 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from consecutive non-overlapping 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e. every neuron in layer C3 connects to every neuron in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0091] Each layer of synapses is implemented using an array or part of an array of non-volatile memory cells.

[0092] 9 is a block diagram of a system that can be used for that purpose. A vector matrix multiplication (VMM) system 32 includes non-volatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM system 32 includes a VMM array 33 including non-volatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37 that decode the respective inputs to the non-volatile memory cell array 33. Inputs to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0093] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, it effectively multiplies the inputs by the weights stored in the VMM array 33 and sums them for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the input to the last layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic and is also power efficient with on-the-fly memory computations.

[0094] The outputs of the VMM array 33 are fed to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of both the positive and negative weight inputs to output a single value.

[0095] The summed output values ​​of the differential summer 38 are then fed to an activation function circuit 39 which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other non-linear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in FIG. 8) and are then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the VMM array 33 constitutes a number of synapses (receiving input from a previous layer of neurons or from an input layer such as an image database), and the summer 38 and activation function circuit 39 constitute a number of neurons.

[0096] The inputs to the VMM system 32 of FIG. 9 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels) or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs may be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0097] FIG. 10 is a block diagram illustrating the use of multiple layers of the VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 10, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM system 32a. The input conversion can also be done by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a. The input conversion can also be done by a digital-to-digital pulse (D / P) converter to convert an external digital input to a mapped digital pulse(s) to the input VMM system 32a.

[0098] The output generated by input VMM system 32a is then provided as input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as input to input VMM system (hidden level 2) 32c, and so on. The various layers of VMM system 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each of VMM systems 32a, 32b, 32c, 32d, and 32e may be a standalone physical system that includes a corresponding non-volatile memory array, or multiple VMM systems may utilize different portions of the same physical non-volatile memory array, or multiple VMM systems may utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e may also be time multiplexed to various portions of its array or neurons. The example shown in Figure 10 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. VMM Array

[0099] Figure 11 shows a neuron VMM array 1100 that is particularly suited for memory cells 310 shown in Figure 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array could be located at the bottom.

[0100] In the VMM array 1100, control gate lines such as control gate line 1103 run vertically (so that row-wise reference array 1102 is orthogonal to control gate line 1103) and erase gate lines such as erase gate line 1104 run horizontally. Here, inputs to the VMM array 1100 are provided to the control gate lines (CG0, CG1, CG2, CG3) and outputs of the VMM array 1100 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current applied to each source line (SL0, SL1, respectively) performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0101] As described herein for neural networks, the non-volatile memory cells of VMM array 1100, ie, the flash memory of VMM array 1100, are preferably configured to operate in the sub-threshold region.

[0102] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage = k * T / q, k is the Boltzmann constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is equal to (Wt / L) * u * Cox * (n-1) * Vt 2where u is the carrier mobility, and Wt and L are the width and length of the memory cell.

[0103] When using an IV log converter that converts the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or periphery memory cell.

[0104] When using an IV log converter that converts the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io]

[0105] where wp is the w of the reference or periphery memory cell.

[0106] For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout = (wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt Iin=wp * Io * e (Vg) / nVt where wa=w for each memory cell in the memory array.

[0107] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0108] Alternatively, the non-volatile memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=β * (Vgs-Vth) * Vds;β=u * Cox * Wt / L Wα(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth)

[0109] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0110] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region, or resistors can be used to linearly convert input and output currents to input and output voltages.

[0111] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * β * (Vgs-Vth) 2 ;β=u * Cox * Wt / L Wα(Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 Proportional to

[0112] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0113] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (sub-threshold, linear, or saturation).

[0114] Other embodiments for the VMM array 33 of Figure 9 are described in U.S. Patent Application Serial No. 15 / 826,345, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0115] FIG. 12 shows a neuron VMM array 1200 that is particularly suitable for the memory cells 210 shown in FIG. 2 and used as synapses between an input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 arranged in the columns of the array serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1214 (only some of which are shown) with current inputs flowing into them. The reference cells are adjusted (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0116] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200 in each memory cell. Second, it effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert to input voltages and provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1203, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which are the inputs to the next layer or the last layer. With the memory array 1203 performing the multiplication and addition functions, the need for separate multiplication and addition logic is eliminated and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on bit lines BL0-BLN, respectively, during read (inference) operations. The current placed on each bit line BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0117] Table 5 shows the operating voltages for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells, and FLT indicates floating, i.e., no voltage is applied. The rows indicate read, erase, and program operations. Table 5: Operation of VMM Array 1200 in FIG. 12 [Table 5]

[0118] FIG. 13 illustrates a neuron VMM array 1300 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of synapses and neurons between an input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 run in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that the word lines run vertically in the VMM array 1300. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current applied to each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0119] Table 6 shows the operating voltages for VMM array 1300. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1300 in FIG. 13 [Table 6]

[0120] 14 shows a neuron VMM array 1400 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of a first non-volatile reference memory cell, and a reference array 1402 of a second non-volatile reference memory cell. The reference arrays 1401 and 1402 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 to voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1412 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. The multiplexers 1412 each include a respective multiplexer 1405 and cascoding transistor 1404 to ensure a constant voltage on the bit line (e.g., BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are adjusted to a target reference level.

[0121] The memory array 1403 serves two purposes: First, it stores the weights used by the VMM array 1400. Second, the memory array 1403 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, and the reference arrays 1401 and 1402 convert these current inputs to input voltages that are fed to the control gates (CG0, CG1, CG2, and CG3) by weights stored in the memory cell array, and then adds all the results (cell currents) to produce an output that appears on BL0 through BLN and is the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0 through BLN) during a read operation. The current applied to each bit line performs a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0122] The VMM array 1400 performs one-way conditioning of the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be done, for example, using the precision programming techniques described below. If too much charge is added to the floating gate (such as an incorrect value being stored in the cell), the cell must be erased and the series of partial programming operations must be redone. As shown, two rows that share the same erase gate (such as EG0 or EG1) must be erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0123] Table 7 shows the operating voltages for the VMM array 1400. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1400 in FIG. 14 [Table 7]

[0124] FIG. 15 shows a neuron VMM array 1500 that is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of synapses and neurons between an input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 or a first non-volatile reference memory cell, and a reference array 1502 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 run vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 run horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of individual EG lines. As shown, reference arrays 1501 and 1502 convert the input currents in terminals BLR0, BLR1, BLR2 and BLR3 into control gate voltages CG0, CG1, CG2 and CG3 (through the action of diode-connected reference cells via multiplexer 1514) which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0125] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1500 in FIG. 15 [Table 8]

[0126] 16 shows a neuron VMM array 1600 that is particularly suited for the memory cell 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 1600, the input INPUT 0 , ... , INPUT N is the bit line BL 0 , ..., BLN で Receive and output OUTPUT 1 , OUTPUT 2 , OUTPUT 3 , and OUTPUT 4 is the source line SL 0 , S.L. 1 , S.L. 2 , and S.L. 3 are generated, respectively.

[0127] 17 shows a neuron VMM array 1700 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , INPUT 1 , INPUT 2 , and INPUT 3 is the source line SL 0 , S.L. 1 , S.L. 2 , and S.L. 3 and output OUTPUT 0 , ..., OUTPUT N is the bit line BL 0 , ..., B.L. N is generated.

[0128] 18 shows a neuron VMM array 1800 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the word line WL 0 , ..., W.L. M OUTPUT 0 , ..., OUTPUT N is the bit line BL0 , ..., B.L. N is generated.

[0129] 19 shows a neuron VMM array 1900 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the word line WL 0 , ..., W.L. M OUTPUT 0 , ..., OUTPUT N is the bit line BL 0 , ..., B.L. N is generated.

[0130] 20 shows a neuron VMM array 2000 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0、 ..., INPUT n are the vertical control gate lines CG 0 , ..., C.G. N Receive and output OUTPUT 1 and OUTPUT 2 is the source line SL 0 and S.L. 1 is generated.

[0131] 21 shows a neuron VMM array 2100 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT N is the bit line BL 0 , ..., B.L. N , 2901-(N-1) and 2901-N, which are respectively coupled to the gates of the bit line control gates 2901-1, 2901-2, ..., 2901-(N-1) and 2901-N. 1 and OUTPUT 2 But the source line SL 0 and S.L.1 is generated.

[0132] 22 shows a neuron VMM array 2200 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the word line WL 0 , ..., W.L. M Receive and output OUTPUT 0 , ..., OUTPUT N is the bit line BL 0 , ..., B.L. N are generated respectively.

[0133] 23 shows a neuron VMM array 2300 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the control gate line CG 0 , ..., C.G. M Receive at OUTPUT 0 , ..., OUTPUT N is the vertical source line SL 0 , ..., S.L. N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0134] 24 shows a neuron VMM array 2400 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0 , ... , INPUT M is the control gate line CG 0 , ..., C.G. MReceive at OUTPUT 0 , ..., OUTPUT N is the vertical bit line BL 0 , ..., B.L. N and each bit line BL i is coupled to the bit lines of all memory cells in column i. Test circuit and method

[0135] 25 shows a VMM system 2500. The VMM system 2500 includes a VMM array 2501 (which may be based on any of the previously described VMM array designs, such as VMM arrays 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, and 2400, or other VMM array designs), a low voltage row decoder 2502, a high voltage row decoder 2503, a column decoder 2504, a column driver 2505, control logic 2506, bias circuits 2507, an output circuit block 2508, an input VMM circuit block 2509, an algorithm controller 2510, a high voltage generator block 2511, an analog circuit block 2515, control logic 2516, and a test control logic 2517.

[0136] The input circuit block 2509 serves as an interface from an external input to the input terminals of the memory array 2501. The input circuit block 2509 may include, without limitation, a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an APC (analog-to-pulse converter), an IVC (current-to-voltage converter), an AAC (analog-to-analog converter such as a voltage-to-voltage scaler), or an FAC (frequency-to-analog converter). The output circuit block 2508 serves as an interface from the memory array output to an external interface (not shown). The output circuit block 2508 may include, without limitation, an ADC (analog-to-digital converter), an APC (analog-to-pulse converter), a DPC (digital-to-pulse converter), an IVC (current-to-voltage converter), or an IFC (current-to-frequency converter). The output circuit block 2508 may include, without limitation, an activation function, a normalization circuit, and / or a rescaling circuit.

[0137] The low voltage row decoder 2502 provides bias voltages for read and program operations, and provides decoded signals to the high voltage row decoder 2503. The high voltage row decoder 2503 provides high voltage bias signals for program and erase operations.

[0138] Algorithm controller 2510 provides control of the bit lines during program, verify, and erase operations.

[0139] The high voltage generator block 2511 includes a charge pump 2512, a charge pump regulator 2513, and a high voltage generation circuit 2514 that provide multiple voltages required for various program, erase, program verify, and read operations.

[0140] Test control logic 2517 includes various test control circuitry for performing the tests described below with reference to FIGS.

[0141] 26 illustrates a reference current source 2600 for use during a verify operation after a program operation of one or more non-volatile memory cells, or for use during other types of testing. For example, reference current source 2600 may be used for a verify operation of a single non-volatile memory cell, or for a verify operation on a column of non-volatile memory cells (e.g., all cells connected to a particular bit line) or some other grouping of non-volatile memory cells.

[0142] The reference current source 2600 is connected to a buffer mirror 2601 (output I REF 2607), an adjustable bias source 2604, and a two-dimensional array 2605 including an array of i rows and j columns of devices 2606, where a particular device 2606 is represented by the label 2606-(row)(column). Here, the reference current I REF Various combinations of devices 2606 can be actuated such that the amount of current I 2607 can be adjusted. As shown, there are 16 devices 2606 in the array 2605, each of which may be implemented by a current mirror. Reference current source 2600 essentially converts four digital inputs into a reference current bias having a value between 1 and 16 times Ibiasunit, which is provided by bias source 2604. Reference current source 2600 is essentially a thermometer-coded digital-to-current converter, and its buffered output I REF 2607 is a value that corresponds to one of 16 levels (a particular level responsive to four digital inputs) that may be stored by a memory cell in any of the aforementioned VMM arrays.

[0143] For example, bias source 2604 may provide a current Ibiasunit of 1 nA that is mirrored to device 2606. Here, a first row consists of devices 2606-11 through 2606-1j, with one device 2606 enabled at a time, from left to right. The next row may then be enabled sequentially from left to right, adding to the first column, meaning five, then six, then seven, then eight devices 2606 are enabled. By sequentially enabling devices 2606, transistor mismatch issues associated with conventional binary decoding may be avoided. The sum of the enabled devices 2606 is then mirrored by buffer mirror 2601, providing a current I REF 2607. Bias source 2604 can provide a trimmable range of current Ibiasunit, such as 50pA / 100pA / 200pA / ... / 100nA. Although array 2605 is shown here as a 4x4 array, it should be understood that array 2605 can have other dimensions, such as 32x32 or 8x32.

[0144] FIG. 27 shows a reference branch circuit 2700 that can be used in any of the devices 2606 of FIG. 26. The reference branch circuit 2700 includes NMOS transistors 2701 and 2702 configured as shown. Transistor 2702 is a current mirror bias transistor that receives a current Ibiasunit (described above with reference to FIG. 26) at its gate, and transistor 2701 is an enable transistor (allowing current mirror bias transistor 2702 to be connected to the output node OUTPUT). The current Ibiasunit is provided (not shown) from a diode-connected NMOS transistor (similar to transistor 2702) or the like.

[0145] 28 illustrates a sense amplifier 2800 that may be used in conjunction with reference current source 2600 during a verify operation or another type of test after a programming operation of a non-volatile memory cell, a column of non-volatile memory cells, or some other grouping of non-volatile memory cells. Sense amplifier 2800 generates a current I REF Receive 2607. I REF 2607 is VI REF 2814. The sense amplifier 2800 further includes an inverter 2801, a current source 2802 used to limit the current in the inverter 2801, switches 2803 and 2806, a capacitor 2804, and a cascoding NMOS transistor 2805 (which imposes a fixed voltage on the memory bit line). The sense amplifier 2800 receives a current I from a reference current source 2600. REF 2607, which may be, for example, one of 16 possible levels stored in a non-volatile memory cell of the VMM array. The sense amplifier 2800 is coupled to a cell 2808, which is a non-volatile memory cell whose contents are to be verified. The cell 2808 receives a current I when the NMOS transistor 2805 is turned on. CELL Alternatively, cell 2808 can be replaced by column 2809 (still shown as I for ease of illustration). CELL , which is the neuronal current elicited by column 2809).

[0146] In one embodiment, I REF2607 starts with the lowest possible value (e.g., the lowest of 16 possible levels that may be stored in cell 2808 or in column 2809) and then sequentially increases to each subsequent level for the verify operation. Switch 2806 may be closed to create an initial state for capacitor 2804 (such as ground or a precharge voltage that provides offset cancellation). Switch 2803 may be closed to make the input and output of inverter 2801 equal, which removes the offset from inverter 2801 for comparison in the verify operation. During the verify operation, switches 2806 and 2803 are open. CELL >=I REF In the case of 2607, the voltage at node 2810 decreases, which in turn capacitively couples through capacitor 2804 and decreases the voltage at node 2811, causing the inverter output to switch to "1", i.e., the input of inverter 2801 goes to a value of "0" and the output of inverter 2801 goes to a value of "1". CELL REF In the case of 2607, the voltage at node 2810 rises, which in turn capacitively couples through capacitor 2804 and causes the voltage at node 2811 to rise, resulting in the inverter output switching to "0", i.e., the input of inverter 2801 switches to a value of "1" and the output of inverter 2801 switches to a value of "0". REF The value of 2807 corresponds to the value stored in cell 2808 .

[0147] FIG. 29A shows a verify slope analog-to-digital converter (ADC) 2900 used in conjunction with a reference current source 2600 during a verify operation of a non-volatile memory cell 2930 or column 2931 after a program pulse operation, such as to verify whether the memory cell reaches a target current during a weight adjustment process, or to verify tailed memory bits (e.g., abnormal bits) that fail to meet the cell current requirements during another type of test. CELL 2906 is the output current from cell 2930 or column 2931. The verification ADC 2900 measures I CELL ​2906 is converted into a series of digital output bits that are output as output 2940 , which indicates the value stored in cell 2930 or column 2931 .

[0148] The verification ADC 2900 includes an operational amplifier 2901, an adjustable capacitor 2902, an operational amplifier 2904, a counter 2920, and switches 2908, 2909, and 2910. The adjustable capacitor 2902 is coupled to a current I provided by an adjustable current source 2807. REF For I CELL 2906. During the initialization phase, switch 2908 is closed. Then, Vout 2903 of the opamp 2901 and the input to the inverting input of the opamp 2901 are equal to the value of the reference voltage VREF applied to the non-inverting input of the opamp 2901. Then, switch 2908 is opened and switch 2910 is closed for a fixed period tref to reset the neuron current I CELL 2906 is integrated upwards. For a fixed period tref, Vout 2903 rises with a slope of I CELL 2906. Thereafter, for a period tmeas, a constant reference current I provided by adjustable current source 2807 is REF is integrated downwards, during which time Vout falls by opening switch 2910 and closing switch 2909, and tmeas is the time required to integrate Vout downwards to VREF.

[0149] The output of opamp 2904, EC2905, is high when VOUT2903>VREF and low otherwise. Thus, EC2905 generates a pulse whose width reflects the period tmeas, which in turn reflects the current I CELL Proportional to 2906.

[0150] Optionally, output EC2905 is input to a counter 2920, which counts the number of clock pulses 2921 received while output EC2905 is high to generate an output 2940, which is a set of digital bits representing a digital count of the number of clock pulses 2921 that occurred while EC2905 was high, which number of clock pulses is I CELL 2906 , this number corresponds to the value stored in cell 2930 or column 2931 .

[0151] FIG. 29B shows a verify ramp analog-to-digital converter 2950, ​​which includes a current source 2953 (representing the received neuron current Ineu or a single memory cell current), a switch 2954, a variable capacitor 2952, and a comparator 2951, which receives the voltage developed across the variable capacitor 2952, marked Vneu, at its non-inverting input, and a configurable reference voltage Vreframp at its inverting input, and generates an output Cout. Circuitry for removing the voltage across the variable capacitor 2952 is not shown. Vreframp is ramped up at discrete levels every comparison clock cycle. The comparator 2951 compares Vneu with Vreframp, resulting in an output Cout that is "1" when Vneu>Vreframp and "0" otherwise. Thus, the output Cout is a pulse whose width varies in response to the value of Ineu. The larger Ineu is, the longer the period during which Cout is "1", i.e., the wider the pulse width of the output Cout. A digital counter 2960 converts the output Cout into digital output bits DO[n:0] 2970, which reflect the number of clock cycles 2961 during which Cout had a value of "1". Alternatively, the ramp voltage Vreframp is a continuous ramp voltage. To reduce the conversion time by utilizing a coarse-fine ramp conversion algorithm, a multiple ramp embodiment can be performed. A first coarse reference ramp reference voltage is ramped at a high speed to obtain a subrange of each Ineu. Then, a fine reference ramp reference voltage for each subrange is used to convert the Ineu current in the corresponding subrange. More than one coarse / fine step or two subranges are possible.

[0152] Other ADC architectures may be used as the validation ADC, such as, without limitation, a flash ADC, a SAR (successive approximation register) ADC, an algorithmic ADC, a pipelined ADC, a sigma-delta ADC, and the like.

[0153] 30 illustrates an embodiment of the high voltage generation circuit 2511 described above with reference to FIG. 25. The high voltage generation circuit 2511 may be used with any of the VMM arrays described above. The high voltage generation circuit 2511 includes a charge pump 2512 and a high voltage generation circuit 2514. The charge pump 2512 receives an input 3004 and generates a high voltage 3005, which is then provided to high voltage generators 3002 and 3003. The high voltage (HV) generator (HVDAC_EG) 3002 generates a V EG 3008 in response to digital bits 3006 and a received high voltage 3005. The high voltage generator (HVDAC CGSL) 3003 generates a voltage, V, such as an incremental voltage, suitable for application to the control gate and source line terminals of a split gate flash memory cell. CG 3009 and V SL 3010 is a HV digital-to-analog converter that provides a voltage indicated at 3010 in response to the digital bit 3007 and the received high voltage 3005, respectively.

[0154] FIG. 31 illustrates the VMM system 2500 described above with reference to FIG. 25, but now shown in a test configuration. Test control logic 2517 provides control signals to other components of the VMM system 2500 (shown in FIG. 25 but not in FIG. 31), such as the VMM array 2501, row decoder 2502, column decoder 2504, input block 2509, high voltage decoder 2503, column driver 2505, high voltage generation block 2511, analog block 2515, algorithm controller 2510, and output circuit block 2508, to implement one or more test algorithms 3100. The VMM array 2501 receives control signals from row decoder 2502, which causes one or more rows to be asserted within the VMM array 2501. The VMM array 2501 provides signals from one or more bit lines to a column decoder 2504, which in turn provides outputs from one or more bit lines to an output circuit block 2508. The output circuit block 2508 may include an analog-to-digital converter block (such as the validation ADC 2900 described above with reference to FIG. 29A or the validation ramp ADC 2950 described above with reference to FIG. 29B) that provides a digital output representing the analog current received by the output circuit block 2508 from the VMM array 2501.

[0155] Table 9 includes example values ​​applied to the word lines, control gate lines, erase gate lines, source gate lines, and bit lines in VMM array 2501 during program, erase, read, and verify operations performed on individual memory cells, neuron verify and neuron read operations performed on selected bit lines coupled to columns of memory cells, and an array read operation in which all bit lines are read, with each bit line coupled to a column of memory cells. Table 9: Example Values ​​for Operations in VMM Array 2501 [Table 9]

[0156] Further details will now be provided regarding the types of tests that may be performed with reference to test algorithms 3100 shown in Figure 31 and described in further detail in Figures 32-44. These are implemented by test control logic 2517 and other components of VMM system 2500.

[0157] Referring to FIG. 32, the bitline neural read test 3101 measures the values ​​of all memory cells coupled to a bitline simultaneously. That is, the bitline neural read test 3101 reads the neurons in the VMM array. First, the row decoder 2502 asserts all wordlines in the array (step 3201). Second, a bitline is selected (asserted) by the column decoder 2504 (step 3202). Third, a read is performed on that bitline (step 3203), such as by a sense amplifier 2800 that senses the current received from the bitline. Fourth, the value of the selected bitline can be determined by comparing it to a reference current generated by the reference current source 2600 to determine whether the non-volatile memory cell, i.e., the neuron, coupled to the selected bitline contains the desired value (step 3204).

[0158] Referring to Figure 33, the bit line neural measurement test 3102 is similar to the bit line neural read test 3101. The row decoder 2502 asserts all word lines (step 3301). A bit line is selected by the column decoder 2504 (step 3302). The current drawn by that bit line during a read operation is measured (step 3303). Here, unlike the bit line neural read test 3101, the current from the selected bit line is measured without comparison to a reference current.

[0159] Referring to FIG. 34, during the LSB screen test 3103, the row decoder 2502 asserts all word lines (step 3401) and the column decoder 2504 asserts all bit lines (step 3402). Deep programming is performed on all memory cells in the VMM array 2501 (step 3403). Deep programming programs all memory cells beyond the normal program state used for speculative reads. This is done with longer program timings or higher program voltages than those normally used in operation. The total current taken from all bit lines is then measured (step 3404). The expectation is that the total current of a deep programmed array will be much less than the LSB value. In addition, each individual cell is checked to ensure that the current from the individual cell is also less than the LSB value, such as 50-100 pA. This type of test is suitable for testing during the manufacturing process to quickly identify bad die.

[0160] 35, during a bit line sampling screen test 3104, a memory cell or set of memory cells is programmed to a particular level, e.g., Lx, where x ranges from 1 to N and N is the total number of levels that can be stored in the cell (e.g., N=16) (step 3501). The bit line current (meaning the current drawn by a cell or set of cells in a selected bit line, I BL ) is measured K times (step 3502). For example, if K=8, then the bit line current is measured 8 times. The average value (I AVG ) is calculated by dividing the K measured values ​​(i.e., I BL1... I BLK ) (step 3503).

[0161] Next, the K current measurements I BL1 ...I BLK Each of the AVG (step 3504). BLi (i is in the range of i to K)>(I AVG+Threshold 3505) or I BLi <(I AVG --threshold 3506), the bit line is considered to be bad. Then, each cell on the bad bit line is checked and the bad cells are replaced with redundant cells (such as cells from a redundant row or column).

[0162] Another embodiment of the bit line sampling screen test 3104 is shown in Figure 36. By forcing a current Iref onto the bit line at K different times, the voltage V CG is measured (step 3601). For example, the voltage V CG can be swept until the bit line current matches a fixed Iref, and that particular V CG may be measured and stored. The fixed Iref may be provided by a reference current source 2600, and the operation of verifying whether the bit line current matches the fixed Iref may be performed by a sense amplifier 2800. The average value V AVG But there are K distinct V CG Then, the K measured V CG Each of the voltages is V AVG (step 3603). CGi (i is in the range of i to K)>(V AVG +Threshold 3604) or V CGi <(V AVG -threshold 3605), the bit line is considered to be bad. Then each cell on the bad bit line is checked and the bad cells are replaced with redundant cells (redundant rows or redundant columns).

[0163] During read tripoint test 3105, coarse and fine read reference current trimming is performed using different levels of Iref in a read operation. The purpose of read trip point test 3105 is to ascertain whether a selected memory cell can exceed a predefined current percentage target, such as .about.40% of a fully erased cell for an erased cell, or .about.5% of a fully programmed cell for a programmed cell. This is to ensure that the memory cell is within the main distribution and is not a tailed memory cell or tailed bit (i.e., a statistical outlier), for example, since tailed memory cells or tailed bits can cause potential reliability issues over the operational lifetime.

[0164] Referring to FIG. 37, during the read window check test 3107, the cell is tested to ensure that it can store each of the N possible levels. First, the cell is programmed to a target value representing one of the N values ​​(step 3701). Then, a verify operation is performed to determine if the value stored in the cell is within a window of acceptable values ​​3710 centered around the target value (step 3702). Steps 3701 and 3702 are repeated for each of the N values ​​(step 3703). The acceptable window 3710 may be different for each of the N values. If any instance of step 3702 performed indicates that the value stored in the cell is outside the window of acceptable values ​​centered around the target value, the cell is identified as bad. The read window check test 3107 may be performed by the sense amplifier 2800, the ADC 2900, the ADC 2950, ​​or another component. This may be useful to perform weight adjustments of the memory cells. While the above has been described in an embodiment where a fixed window is used for each of the N values ​​centered around a nominal value, it will be appreciated that in other embodiments, upper and lower thresholds are utilized for each of the N values, and that these thresholds need not be the same for all N values, so long as the range is not exceeded.

[0165] Referring to FIG. 38, during a read calibration test 3108, leakage is measured for a cell or group of cells, such as cells coupled to a bit line (step 3801), and the measured leakage (I LEAKAGE) is stored (step 3802) and the measured leakage value is later used during a read operation to compensate for leakage across various process / voltage / temperature (PVT) combinations (step 3803). In one embodiment, multiple cells are each programmed with a known value. The word lines and control gate lines are set to ground and the bit lines are set to a read bias voltage. A series of different reference currents are injected into the array and the resulting data readout is read by ADC circuit 2900 or 2950 or a sense amplifier such as sense amplifier 2800. The injected current that gives the best results (compared to the known values ​​programmed into the cells) is I LEAKAGE Then, I LEAKAGE is applied during a read operation of a selected cell to compensate for leakage occurring within the same cell, such as by subtracting the stored leakage level from the converted data during the read operation.

[0166] Referring to FIG. 39, during a read slope test 3109, IV slope factors are determined for control gate voltages for two reference currents, namely, CG1 at current IR1 and CG2 at current IR2. The first step is to determine a logarithmic slope factor for a selected non-volatile memory cell while the selected non-volatile memory cell operates in the sub-threshold region (step 3901). The second step is to store the logarithmic slope factor (step 3902). The third step is to determine a linear slope factor for a selected non-volatile memory cell while the selected non-volatile memory cell operates in the linear region (step 3903). The fourth step is to store the linear slope factor (step 3904). The fifth step is to utilize one or more of the logarithmic slope factor and the linear slope factor when programming the selected cell to a target current (step 3905).

[0167] Referring to FIG. 40, during a read neuron qualification test 3110, a neuron (bit line) is read without checking the value against a desired value. The first step is to measure the current in the bit line and store the measured value (step 4001). The second step is to run a dummy neuron read test 4010, as described below, for a predefined amount of time, such as burn-in time during the qualification process. The third step is to measure the current from the bit line (step 4003). The fourth step is to compare the measured current to the stored measured current of step 4001 (step 4004). If the difference is greater or less than a certain amount, the bit line is deemed to be a bad bit line.

[0168] The dummy neuron read test 4010 includes a series of steps. The first step is to assert all word lines in the array by the row decoder (step 4011). The second step is to assert all bit lines in the array by the column decoder to select all columns of non-volatile memory cells (step 4012). The third step is to perform a read operation (read condition) on the array without checking the read output (step 4013). The dummy neuron read test 4010 is used as a read stress on the array for burn-in purposes.

[0169] Referring to FIG. 41, during a soft erase test 3111, an entire array or sector is tested to check the erase performance of the memory array. The first step is to erase the non-volatile memory cells in the array by applying a series of voltages to the terminals of each of the non-volatile memory cells in the array, where the voltages in the series increase over time with a fixed step size (step 4101). This erases the cells in an incremental manner, for example by increasing the voltage at the erase gate in a stepwise manner from 5 to 12.5 volts in steps of 0.5 or 1 volt. Erasing in this manner reduces stress on the memory cells. The second step is to determine the effectiveness of the erase step by reading all the non-volatile memory cells to determine, for example, that the cell current after the erase of step 4101 is within an acceptable window around a nominal value (step 4102). Optionally, an endurance test may be performed to determine how many program / erase cycles it can sustain, or a background test may be performed to transition the array to an erased state.

[0170] Referring to FIG. 42, during soft program test 3112, an entire array or row or cell is tested. The first step is to program the non-volatile memory cells in the array by applying a series of voltages to the terminals of each non-volatile memory cell in the array, where the voltages in the series increase over time with a fixed step size (step 4201). The cells are programmed in an incremental manner, for example 3-10 volts with 10 mV or 0.3 V or 1 V steps, to check the program performance of the memory array. Programming in this manner reduces stress on the memory cells. The second step is to determine the validity of the programming step, for example by reading all the non-volatile memory cells to determine that the cell current after programming in step 4201 is within an acceptable window around a nominal value (step 4202). Optionally, an endurance test or background test may be utilized.

[0171] Referring to FIG. 43, a read verify test 3106 may be performed. The first step is to program a plurality of non-volatile memory cells to store one of N different values, where N is the number of different levels that may be stored in any of the non-volatile memory cells (step 4301). The second step is to measure the current drawn by the plurality of non-volatile memory cells (step 4302). The third step is to compare the measured current to a target value (step 4303). The fourth step is to store the identification of the plurality of non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold factor (step 4304).

[0172] Referring to FIG. 44, a checkerboard verification test 3113 may be performed, whereby the test pattern is implemented using a checkerboard or pseudo-checkerboard pattern and only sampled levels are tested instead of all possible levels (e.g., 4 levels, i.e., L0, Ln, Ln / 4, Ln / 2, Ln / 1 ...3, Ln / 3, Ln / 4, Ln / 4, Ln / 1, Ln / 2, Ln / 3, Ln / 4, Ln / 1, Ln / 2, Ln / 3, Ln / 4, Ln / 1, Ln / 2, Ln / 3, Ln / 4, Ln / 1, Ln / 2, Ln / 3, Ln / 4, Ln / 1, Ln / 2, Ln / 3, Ln / 4, Ln / 1, Ln / 1, Ln / 2, Ln / 3, Ln / 4, Ln / 1, Ln / 2, Ln / 3, Ln / 4, L * For example, the pattern can be used to check the worst-case electric field stress in a memory array (meaning one cell is at a high electric field level and an adjacent cell is at a low electric field level).

[0173] In one embodiment, the first step is to program a first group of cells among the non-volatile memory cells with a level corresponding to the smallest cell current among the N levels (step 4401). The second step is to program a second group of cells among the non-volatile memory cells with a level corresponding to the largest cell current among the N levels (step 4402), with each of the cells in the second group of cells adjacent to one or more of the cells in the first group of cells. The third step is to measure a current drawn by the non-volatile memory cells (step 4403). The fourth step is to compare the measured current to a target value (step 4404). The fifth step is to identify the non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold (step 4405).

[0174] Table 10 includes other exemplary test patterns for physical array maps that may be used during the checkerboard verification test 3113. Table 10: Exemplary Test Patterns [Table 10]

[0175] Screening test 3114, final test 3115, qualification test 3116, and data retention test 3117 are test suites that may be performed during the manufacturing and qualification process of a wafer, die, or packaged device that includes the VMM system disclosed herein.

[0176] Screening tests 3114 may be performed on wafers during the manufacturing process. In one embodiment, the screening tests 3114 include the following test suites: First, relatively fast tests are performed to quickly identify bad wafers or dies, such as soft erase test 3111, soft program test 3112, and various stress mode tests (erase gate oxide gox, bond gate oxide cox, source line oxide sol, reverse disturb tunneling rtsts (tunneling from floating gate to word line, disturb for unselected rows), mass punch through mpt (disturb from source to drain for unselected rows), read disturb rdist (disturb from read state), etc.). Second, neural test modes are performed, such as LSB screen test 3103 and bit line sampling screen 3104 for top and bottom sectors. Although the neural test mode takes much longer than the tests performed during the first step, some time is saved by having bad wafers or dies to be screened out identified during the first, less time-consuming set of tests.

[0177] A final test 3115 may be performed on the packaged device. In one embodiment, the final test 3115 includes performing a soft erase test 3111 and a soft program test 3112. Optionally, to reduce test time, test patterns for neural applications may be utilized rather than a comprehensive test such as testing K of N levels of M sectors, or testing all N levels for a particular sector (such as the top and bottom sectors).

[0178] During qualification test 3116, dummy bit line read iterations are performed (which is the execution of a read action without actually determining the content of the read data) and endurance testing is performed by applying soft erase test 3111 and soft program test 3112. Since bit line reads are used instead of individual memory reads during neural memory application, bit line tests are performed instead of individual memory cell tests.

[0179] Data retention test 3117 may include baking the programmed wafer at an elevated temperature, such as 250° C., for example, for 24-72 hours. In one embodiment, a checkerboard or pseudo-checkerboard test pattern is imposed rather than a comprehensive test for digital memory testing. Data retention is checked against the bitline current in neural mode (instead of each memory cell as is done for digital memories) using read bitline current mode. For example, one inquiry is to check if delta IBL<+ / -p%, where delta IBL is defined as the difference of the measured bitline current from the expected bitline current. (WholeBLmeas mode, allowed percentage error from software neural net modeling for target accuracy for neural networks p%). Delta IBL is tested against neural mode to identify if the bitline output current is above or below the target, defined herein as a predefined percentage "p" of the target. Alternatively, each cell may be checked / tested at + / - delta of the target.

[0180] Other tests can be performed using the hardware and algorithms described herein.

[0181] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed between them) and "indirectly" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached" (with an intermediate material, element, or gap disposed between them), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above a substrate" can include forming the element directly on the substrate, with no intermediate materials / elements between them, and forming the element indirectly on the substrate, with one or more intermediate materials / elements between them.

Claims

1. 1. A method for testing an analog neural non-volatile memory cell for storing N distinct values, where N is an integer, the method comprising: programming the cell to a target value representing one of the N values; verifying that the value stored in the cell is within a window of acceptable values ​​centered around the target value; repeating the programming and reading steps for each of the N values, wherein the window of acceptable values ​​is a different size for each of the N values; and identifying the cell as bad if any of the verifying steps indicates a value stored in the cell that is outside a window of acceptable values ​​centered around the target value.

2. The method of claim 1 , wherein each of the non-volatile memory cells is a stacked-gate flash memory cell.

3. The method of claim 1 , wherein each of the non-volatile memory cells is a split-gate flash memory cell.

4. The method of claim 1 , wherein the cell is part of a neural network.

5. 1. A method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, the memory array being arranged in rows and columns, each row coupled to a word line and each column coupled to a bit line, each word line selectively coupled to a row decoder and each bit line selectively coupled to a column decoder, the method comprising: programming a first group of cells of the plurality of non-volatile memory cells with a level corresponding to a smallest cell current among N levels; programming a second group of cells among the plurality of non-volatile memory cells with a level corresponding to a largest cell current among the N levels, each cell in the second group of cells being adjacent to one or more of the cells in the first group of cells forming a checkerboard pattern; measuring a current drawn by the plurality of non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of non-volatile memory cells as defective if a difference between the measured current value and the target value exceeds a threshold.

6. The method of claim 5 , wherein each of the non-volatile memory cells is a stacked-gate flash memory cell.

7. The method of claim 5 , wherein each of the non-volatile memory cells is a split-gate flash memory cell.

8. The method of claim 5 , wherein the array is part of a neural network.

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