RF-DC loop

Abstract

In the RF-DC circuit of a wireless power receiving device, it is not possible to protect a device connected to the power supply voltage terminal. [Solution] In the RF-DC circuit of a wireless power receiving device, the RF-DC circuit comprises a capacitor arranged between the antenna positive terminal and a power supply voltage supply terminal, and a diode connected in parallel with the capacitor and capable of outputting overvoltage input from the antenna positive terminal to the GND output, and the RF-DC circuit is not connected to an overvoltage protection element between the antenna positive terminal and the capacitor.

Description

[Technical field]

[0001] The present disclosure relates to RF-DC circuits. [Background technology]

[0002] In recent years, wireless power transfer (WPT) has been used in various fields. By utilizing WPT, problems such as strain on wiring, breakage, and maintenance can be avoided compared to wired power transfer.

[0003] Patent Document 1 discloses a technique for providing a means for preventing breakdowns in a rectenna. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-192484 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the RF-DC circuit of a wireless power receiving device, there is a problem in that the device connected to the power supply voltage supply terminal cannot be protected. Therefore, the present disclosure has been made to solve the above problem, and has an object to provide a technique for protecting a device connected to a power supply voltage supply terminal of an RF-DC circuit. [Means for solving the problem]

[0006] In an RF-DC circuit of a wireless power receiving device, the RF-DC circuit comprises a capacitor provided between an antenna positive terminal and a power supply voltage supply terminal, and a diode connected in parallel with the capacitor and capable of outputting an overvoltage input from the antenna positive terminal to a GND output, and the RF-DC circuit is not connected to an overvoltage protection element between the antenna positive terminal and the capacitor. Effect of the Invention

[0007] According to the present disclosure, it is possible to protect a device connected to a power supply voltage supply terminal of an RF-DC circuit. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a WPT system. [Diagram 2] 1 is a block diagram illustrating an example of the configuration of a power transmitting device and a power receiving device. [Diagram 3] FIG. 2 is a block diagram showing a functional configuration of a first information processing device. [Figure 4] FIG. 4 is a block diagram showing a functional configuration of a second information processing device. [Diagram 5] FIG. 2 is a block diagram showing a functional configuration of an RF-DC circuit (first embodiment). [Figure 6] FIG. 2 is a cross-sectional view of an RF-DC circuit (first embodiment). [Figure 7] FIG. 13 is a block diagram showing a functional configuration of an RF-DC circuit (second embodiment). [Figure 8] FIG. 1 is a cross-sectional view of an RF-DC circuit (second embodiment). [Figure 9] FIG. 13 is a block diagram showing a functional configuration of an RF-DC circuit (third embodiment). [Figure 10] FIG. 1 is a first cross-sectional view of an RF-DC circuit (third embodiment). [Figure 11] FIG. 2 is a second cross-sectional view of the RF-DC circuit (third embodiment). [Figure 12] FIG. 13 is a block diagram showing a functional configuration of an RF-DC circuit (fourth embodiment). [Figure 13] FIG. 11 is a cross-sectional view of an RF-DC circuit (fourth embodiment). [Figure 14] FIG. 2 is a block diagram showing the basic hardware configuration of a computer 90. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In all the drawings explaining the embodiment, the same reference numerals are given to common components, and repeated explanations are omitted. Note that the following embodiment does not unduly limit the contents of the present disclosure described in the claims. In addition, not all of the components shown in the embodiment are essential components of the present disclosure. In addition, each figure is a schematic diagram and is not necessarily illustrated strictly.

[0010] <Summary> <1 Overall system configuration> FIG. 1 is a diagram showing the overall configuration of a WPT system 1 according to this embodiment.

[0011] The WPT system 1 shown in Fig. 1 includes, for example, a transmitter 100, a receiver 200, a first information processing device 300, and a second information processing device 400. The WPT system 1 shown in Fig. 1 is used, for example, in a building or a factory. Note that the connection between the transmitter 100 and the first information processing device 300, and the connection between the first information processing device 300 and the second information processing device 400 may be wired or wireless.

[0012] 1 shows an example in which the WPT system 1 includes three transmitters 100, but the number of transmitters 100 included in the WPT system 1 is not limited to three. The number of transmitters 100 included in the WPT system 1 may be two or less, or may be four or more.

[0013] 1 shows an example in which the WPT system 1 includes seven receivers 200, but the number of receivers 200 included in the WPT system 1 is not limited to seven. The number of receivers 200 included in the WPT system 1 may be six or less, or eight or more.

[0014] In this specification, the transmitter 100 is a (power) transmitter 100 in the sense of wirelessly transmitting power, and similarly, the receiver 200 is a (power) receiver 200 in the sense of wirelessly receiving power. As described later, the receiver 200 may transmit, for example, information on the state of the receiver 200 or information on a measurement result by a sensor to the transmitter 100 as a data signal, and the transmitter 100 may receive such a data signal. In this case, the transmitter 100 is a receiver that receives a data signal, and the receiver 200 functions as a transmitter that transmits a data signal.

[0015] 1 shows an example in which the WPT system 1 includes two first information processing devices 300, but the number of first information processing devices 300 included in the WPT system 1 is not limited to two. The number of first information processing devices 300 included in the WPT system 1 may be one, or three or more.

[0016] The transmitter 100 transmits, for example, a power supply signal or a data signal to the receiver 200. The transmitter 100 transmits the power supply signal to the receiver 200 by radio waves in the 920 MHz band, for example. The transmitter 100 transmits the data signal to the receiver 200 by radio waves in the 2.4 GHz band, for example. The transmitter 100 may transmit the data signal by radio waves in the 920 MHz band.

[0017] The power transmission signal transmitted from the transmitter 100 may be, for example, a continuous wave (CW) having a predetermined power. The frequency band of the power transmission signal is, for example, a 920 MHz band, taking into consideration the distance between the transmitter 100 and the receiver 200. If the frequency band is higher than the exemplified frequency band, it may not be possible to supply the predetermined power that allows the receiver 200 to operate unless the distance between the transmitter 100 and the receiver 200 is shortened, so an appropriate frequency band can be determined by taking into consideration a practical range (for example, the distance between the transmitter 100 and the receiver 200 is several meters).

[0018] In this case, the laws of the country in which the WPT system 1 is installed may impose restrictions on the intermittent transmission of a power transmission signal having a predetermined power. As an example, when the power transmission signal from the transmitter 100 corresponds to the provisions of a radio station stipulated in the Radio Law of Japan (regardless of whether or not a license is obtained), it may be necessary to provide a certain pause period for the power transmission signal based on the Radio Law. In this case, the power transmission signal cannot be considered as a continuous wave when considered on a certain time axis. However, it is essential to provide a pause period, and since this pause period is sufficient if it is short, the power transmission signal transmitted from the transmitter 100 can be considered as a substantially continuous continuous wave. As described above, the ratio between the duration of the power transmission signal and the pause period may be such that the power transmission signal transmitted from the transmitter 100 can be considered as a substantially continuous continuous wave, and as an example, the pause period is about 1 / 50 to 1 / 100 of the duration of the power transmission signal.

[0019] The transmitter 100 may, for example, feed power to one receiver 200 or to multiple receivers 200. The transmitter 100 may, for example, transmit a data signal to one receiver 200 or to multiple receivers 200. The transmitter 100 may, for example, transmit the same data signal as another transmitter 100, or may transmit a data signal different from that of the other transmitters 100. The transmitter 100 may, for example, transmit a predetermined command signal as a data signal to the receiver 200, or may transmit a preset signal as a data signal to the receiver 200.

[0020] The transmitter 100 receives, for example, a data signal transmitted from the receiver 200. The transmitter 100 may receive, for example, a data signal transmitted from one receiver 200, or may receive data signals transmitted from a plurality of receivers 200. The transmitter 100 transmits the data signal transmitted from the receiver 200 to the first information processing device 300. The transmitter 100 transmits information related to the state of the transmitter 100 to the first information processing device 300.

[0021] The receiver 200 receives, for example, a power supply signal or a data signal transmitted from the transmitter 100. For example, if the receiver 200 has a power storage unit, the receiver 200 converts the power supply signal transmitted from the transmitter 100 into electric power and stores the converted electric power in the power storage unit. For example, if the receiver 200 has a predetermined sensor, the receiver 200 converts the power supply signal transmitted from the transmitter 100 into electric power and drives the sensor with the converted electric power.

[0022] The receiver 200 transmits, for example, information relating to the state of the receiver 200 or information relating to the measurement results of a sensor to the transmitter 100 as a data signal.

[0023] The first information processing device 300 is an information processing device that monitors the operation of the transmitter 100 and the receiver 200 housed in the WPT system 1. For example, the first information processing device 300 determines whether the transmitter 100 or the receiver 200 is in a preset state based on information about the state of the transmitter 100 and the receiver 200 transmitted from the transmitter 100. If it is determined that the transmitter 100 or the receiver 200 is in a preset state, the first information processing device 300 transmits predetermined information to the second information processing device 400.

[0024] In addition, the first information processing device 300 accumulates information about the transmitter 100 and the receiver 200 accommodated in the WPT system 1. For example, the first information processing device 300 stores information about the states of the transmitter 100 and the receiver 200 transmitted from the transmitter 100 in a storage unit provided in the first information processing device 300.

[0025] Moreover, the first information processing device 300 controls the operation of the transmitter 100 accommodated in the WPT system 1. For example, the first information processing device 300 transmits to the transmitter 100 a predetermined instruction or information.

[0026] In addition, the first information processing device 300 controls the operation of the second information processing device 400 .

[0027] The second information processing device 400 is, for example, an information processing device operated by an administrator of the WPT system 1. When the second information processing device 400 receives a notification from the first information processing device 300 that the transmitter 100, the receiver 200, or both of them housed in the WPT system 1 are in a predetermined state, the second information processing device 400 presents to the user that the transmitter 100, the receiver 200, or both of them are in the predetermined state.

[0028] Moreover, the second information processing device 400 analyzes information on the status of the transmitter 100 and the receiver 200 stored in the first information processing device 300, and presents predetermined information to the user. The predetermined information is, for example, the following. Information regarding placement of transmitter 100 Information regarding the placement of the receiver 200 Power consumption information Information on power consumption

[0029] <1.1 Transmitter and receiver configuration> FIG. 2 is a block diagram showing an example of the configuration of the transmitter 100 and the receiver 200 shown in FIG. 1. As shown in FIG. 2, the transmitter 100 and the receiver 200 are, for example, spaced apart from each other at a predetermined interval. For example, the transmitter 100 and the receiver 200 are installed at a distance of about several meters apart. Specifically, for example, the transmitter 100 is fixedly installed at a predetermined high position provided in a high place indoors, for example, on a ceiling or a wall. The receiver 200 is installed in a predetermined device indoors, or placed near a device that requires power supply. The receiver 200 may also be carried by a user. The transmitter 100 transmits a power supply signal to the receiver 200 by radio waves of a predetermined frequency, for example, 920 MHz band. The receiver 200 converts the power supply signal transmitted from the transmitter 100 into power, and charges the device with the converted power, or supplies the converted power to the predetermined device.

[0030] The transmitter 100 includes, for example, an oscillator 101, a transmitting antenna 102, a microcomputer (controller) 103, a data transceiver 104, and a data transmitting / receiving antenna 105. The oscillator 101, the microcomputer 103, the data transceiver 104, and the data transmitting / receiving antenna 105, or at least any combination of these, may be mounted on, for example, a PCB (printed circuit board).

[0031] The oscillator 101 oscillates a signal in a predetermined frequency band, for example, the 920 MHz band. The oscillated signal may be amplified and unnecessary frequency components may be removed, if necessary.

[0032] The transmitting antenna 102 is formed so as to be capable of efficiently transmitting radio waves in the 920 MHz band, for example. The transmitting antenna 102 radiates a signal oscillated by an oscillator 101 as a power supply signal.

[0033] The microcomputer 103 controls the operation of the transmitter 100. The microcomputer 103 is realized by, for example, a semiconductor device equipped with an ARM processor. The microcomputer 103 controls, for example, the transmission of radio waves by the transmission antenna 102.

[0034] The data transceiver 104 performs processes such as converting digital data to analog data, modulating analog data, etc. The data transceiver 104 also performs processes such as demodulating a data signal received by the data transceiver antenna 105, and digitizing the demodulated data. For example, the data transceiver 104 extracts a predetermined signal from the data signal received by the data transceiver antenna 105, converts it into digital data, and transmits it to the microcomputer 103.

[0035] The data transmission / reception antenna 105 is formed to be capable of efficiently transmitting and receiving radio waves in the 2.4 GHz band, for example. The data transmission / reception antenna 105 radiates a data signal supplied from the data transceiver 104. In addition, the data transmission / reception antenna 105 receives a data signal transmitted from the receiver 200.

[0036] The receiver 200 includes, for example, a receiving antenna 201, a rectifier 202, a power management unit 203, a power storage unit 204, a microcomputer 205, a data transceiver 206, and a data transmitting / receiving antenna 207. The receiving antenna 201, the rectifier 202, the power management unit 203, the power storage unit 204, the microcomputer 205, the data transceiver 206, and the data transmitting / receiving antenna 207, or at least any combination of these, may be mounted on, for example, a PCB or an FPC (flexible printed circuit board).

[0037] The receiving antenna 201 is formed so as to be able to efficiently receive radio waves in the 920 MHz band, for example. The receiving antenna 201 receives the power supply signal radiated from the transmitting antenna 102.

[0038] The rectifier 202 rectifies the radio waves received as a power supply signal and converts them into a DC voltage.

[0039] The power management unit 203 manages the DC voltage. For example, the power management unit 203 controls a charging voltage based on the DC voltage. The power management unit 203 charges the power storage unit 204 by controlling the charging voltage. In addition, for example, when the power storage unit 204 stores power equal to or greater than a predetermined capacity, the power management unit 203 supplies the DC voltage to a connected member.

[0040] Further, the power management unit 203 releases the power stored in the power storage unit 204 in response to control from the microcomputer 205 .

[0041] The power storage unit 204 stores power in response to an instruction from the power management unit 203. The power storage unit 204 is realized by, for example, a battery or a capacitor. Furthermore, the power storage unit 204 releases the stored power in response to an instruction from the power management unit 203.

[0042] The microcomputer 205 controls the operation of the receiver 200. The microcomputer 205 is driven by a DC voltage supplied from the power management unit 203 or by power stored in the power storage unit 204. The microcomputer 205 controls the power management unit 203 to cause the power storage unit 204 to release the power stored therein.

[0043] For example, various sensors can be connected to the receiver 200. For example, a heat sensor, a temperature sensor, a light sensor, a humidity sensor, a vibration sensor, a magnetic sensor, etc. are connected to the receiver 200. In addition, a force sensor, a proximity sensor, a gas sensor, an acceleration sensor, a human sensor, an infrared sensor, an illuminance sensor, a flow rate sensor, a current sensor, a pressure sensor, etc. may be connected to the receiver 200. The sensor connected to the receiver 200 is driven by, for example, a direct current voltage supplied from the power management unit 203 or power discharged from the power storage unit 204. The microcomputer 205 continuously or intermittently monitors the voltage value at a predetermined portion of the receiver 200, the status of the sensor connected to the receiver 200, information detected by the sensor, etc. The microcomputer 205 transmits the voltage value at a predetermined portion of the receiver 200, the status of the sensor connected to the receiver 200, information detected by the sensor, etc. as digital data to the data transceiver 206. The sensor may be built into the receiver 200.

[0044] The data transceiver 206 performs processes such as converting digital data supplied from the microcomputer 205 into analog data and modulating the analog data. The data transceiver 206 also performs processes such as demodulating a data signal received by a data transceiver antenna 207 and digitizing the demodulated data. The data transceiver 206 is driven by, for example, a DC voltage supplied from the power management unit 203 or power discharged from the power storage unit 204.

[0045] The data transmission / reception antenna 207 is formed to be capable of efficiently transmitting and receiving radio waves in the 2.4 GHz band, for example. The data transmission / reception antenna 207 radiates a data signal supplied from the data transceiver 206. In addition, the data transmission / reception antenna 207 receives a data signal transmitted from the transmitter 100. For example, the data transmission / reception antenna 207 is driven by a DC voltage supplied from the power management unit 203 or power discharged from the power storage unit 204.

[0046] <2 RF-DC circuit 501> In this disclosure, the rectifier 202, the power management unit 203, and the RF-DC circuit 501 that constitutes the power storage unit 204 included in the receiver 200 will be described in detail below.

[0047] [RF-DC circuit 501 (basic configuration)] This relates to the RF-DC circuit 501 of the wireless power receiving device (receiver 200). The features of the RF-DC circuit 501 of the wireless power receiving device according to the present disclosure will be described below. The RF-DC circuit 501 of the present disclosure is configured as a semiconductor circuit. The RF-DC circuit 501 includes a capacitor (C521) provided between an antenna positive terminal (ANTP511) and a power supply voltage supply terminal (VCC513) that outputs power received from the antenna positive terminal. The RF-DC circuit 501 includes a diode (D_ESD531) that is connected in parallel with the capacitor (C521) and can output the overvoltage input from the antenna positive terminal (ANTP511) to the GND514 output. The voltage clamp circuit 541 can also protect the circuits connected after the VCC513. There is no overvoltage protection element connected between the antenna positive terminal (ANTP511) and the capacitor (C521). An overvoltage protection element (Voltage Clamp ESD541) is connected between the capacitor (C521) and the power supply voltage supply terminal (VCC513).

[0048] The overvoltage protection element can output an overvoltage to the GND514 output via the antenna positive terminal (ANTP511), the diode (D_ESD531), and the overvoltage protection element (Voltage Clamp ESD541). Specifically, when a positive overvoltage is input from the antenna positive terminal (ANTP511), it becomes forward biased and has a function of discharging a current to GND514. The overvoltage protection element (Voltage Clamp ESD541) can protect a device (such as the microcomputer 205) connected to the power supply voltage supply terminal (VCC513). The overvoltage protection element (Voltage Clamp ESD541) operates when the input voltage exceeds a predetermined voltage (set voltage), and protects a device (such as the microcomputer 205) connected to the power supply voltage supply terminal (VCC513) by outputting the input overvoltage to GND514 without outputting it to the power supply voltage supply terminal (VCC513). VCC 513 is connected to power management unit 203, and power supplied from ANTP 511 is stored in power storage unit 204 via rectifier 202 (RF-DC circuit 501 composed of a capacitor, a diode, etc.) and power management unit 203. The power stored in power storage unit 204 is supplied to microcomputer 205, data transceiver 206, data transmission / reception antenna 207, etc. via power management unit 203 on a path different from that used for storage, and drives receiver 200. Normally, the overvoltage protection element (Voltage Clamp ESD541) maintains a reverse bias state, and when an overvoltage occurs, it becomes forward biased and releases current to GND 514. The overvoltage protection element (Voltage Clamp ESD541) operates to protect devices (such as the microcomputer 205) connected to the power storage unit 204 from an overvoltage. In addition, the antenna positive terminal (ANTP511) and the antenna negative terminal (ANTN512) may be configured in a reversed manner if the circuit functions in that manner. Specifically, the antenna negative terminal (ANTN512) may be disposed at the position of the antenna positive terminal (ANTP511) in this disclosure, and the antenna positive terminal (ANTP511) may be disposed at the position of the antenna negative terminal (ANTN512) in this disclosure. In this disclosure, overvoltage includes ESD (Electro Static Discharge), EOS (Electric Over Stress, overvoltage / overcurrent stress), etc. Specifically, it is an electric signal input from the antenna 201, and includes any electric signal (voltage, current, radio wave, spatial power) that may damage the internal circuit and connected devices, etc.

[0049] A specific configuration of the RF-DC circuit 501 in a wireless power receiving device according to the present disclosure will be described in each of the following embodiments.

[0050] [RF-DC circuit 501 (first embodiment)] FIG. 5 is a block diagram showing the functional configuration of an RF-DC circuit 501 (first embodiment). FIG. 6 is a cross-sectional view of an RF-DC circuit 501 (first embodiment). The RF-DC circuit 501 (first embodiment) is formed of bulk CMOS. Bulk CMOS is a method of forming devices directly on a single silicon substrate. Compared to SOI CMOS, the manufacturing process is relatively simple and the cost is low. Compared to SOI CMOS, it has excellent heat dissipation properties because heat can be dispersed across the entire silicon substrate. Compared to SOI CMOS, there is a large parasitic capacitance between the substrate and bulk CMOS, which may affect high-frequency characteristics.

[0051] [Basic configuration of RF-DC circuit 501 (first embodiment)] The components of the RF-DC circuit 501 (first embodiment) disclosed in FIG. 5 and FIG. 6 will be described below. The ANTP 511 (antenna positive terminal) is a connection terminal on the positive side of the antenna 201, and is an input point for an RF (radio frequency) signal. ANTN512 (antenna negative terminal) is a connection terminal for the negative electrode of the antenna 201. VCC513 is a power supply voltage supply terminal (output terminal) that supplies power to devices connected to the circuit. GND514 is a ground terminal, which serves as the reference potential point of the circuit. C521 is a capacitor and is used for rectifying RF (radio frequency) signals. C_storage 522 is a storage capacitor that stores the rectified power. D_ESD531 is an ESD (electrostatic discharge) protection diode that provides protection for the C521 from overvoltages such as ESD (Electro Static Discharge) and EOS (Electric Over Stress, overvoltage / overcurrent stress). D532A and D532B are rectifying diodes that convert an RF (radio frequency) signal into a DC (direct current) voltage and store it in C_storage522. DA_ISO534A and DSub_ISO534B are isolation diodes that electrically isolate D_ESD531 from the PSUB (substrate). The Voltage Clamp ESD541 is a voltage clamp ESD (electrostatic discharge) protection device that protects circuits from overvoltage. The PSUB is a P-type substrate, which forms the substrate portion of the semiconductor device. N+ is a highly doped N-type semiconductor region. P+ is a heavily doped P-type semiconductor region. P- is a lightly doped P-type semiconductor region. STI (Shallow Trench Isolation) is a shallow trench isolation structure that provides electrical isolation between devices.

[0052] [Connections of RF-DC circuit 501 (first embodiment)] The RF-DC circuit 501 (first embodiment) includes a second diode (DA_ISO534A) and a third diode (DSub_ISO534B) connected between the antenna positive terminal (ANTP511) and a diode (D_ESD531). The diode, the second diode and the third diode are formed in a channel region on a silicon substrate. specifically, ANTP511 (antenna positive terminal) is connected to one end of C521. The other end of C521 is connected to the anode of D532B. The anode of D_ESD531 is connected between ANTP511 and one end of C521. The cathode of D_ESD531 is connected between the other end of C521 and the anode of D532B. The anode of DA_ISO534A is connected between ANTP511 and one end of C521. The cathode of DA_ISO534A is connected between DSub_ISO534B and ANTP511. The cathode of DSub_ISO534B is connected between ANTP511 and one end of C521. The anode of DSub_ISO534B is connected to ANTN512. The anode of D532A is connected to ANTN 512. The cathode of D532A is connected between C521 and the anode of D532B. The cathode of D532B is connected to VCC 513. One end of C_storage 522 is connected to VCC 513. The other end of C_storage 522 is connected to GND 514. One end of the voltage clamp ESD541 is connected between the cathode of D532B and VCC513. The other end of the voltage clamp ESD541 is connected to GND514.

[0053] [Operation of RF-DC circuit 501 (first embodiment)] When an RF signal (ANTP511 terminal input signal based on the ANTN512 terminal voltage) is input from ANTP511, this high-frequency signal reaches C521. Since D_ESD531 is connected in parallel with C521, during the positive half cycle of the RF signal, if C521 is charged to the forward voltage (Vf) of D_ESD531 or more, it will be in a reverse bias state. As a result, D_ESD531 does not affect normal RF signals, and the efficiency of the circuit can be maintained. D532A and D532B act as rectifiers, converting the RF signal to direct current (DC). During the negative half cycle of the RF signal, D532A conducts and charges C521. During the positive half cycle of the RF signal, D532B conducts and charges C_storage522. If the charging voltage to C521 is equal to or lower than the forward voltage (Vf) of D_ESD531, when the ANTP511 voltage rises, current flows through the path of D_ESD531 and D532B, charging C_storage522. This allows for efficient storage of power even in low voltage conditions. The rectified and stored power is supplied to the connected device through the VCC513 terminal. The Voltage Clamp ESD541, connected between VCC513 and GND514, provides protection in case the output voltage becomes excessive.

[0054] A case where a positive overvoltage is input from ANTP511 will be described with reference to the arrow 51 in Fig. 5. When a positive overvoltage is input from ANTP511, the current is discharged through the path of ANTP511, D_ESD531, D532B, Voltage Clamp ESD541, and GND514, so that the device connected to VCC513 is protected from the overvoltage. This makes it possible to protect the circuit and connected devices from the positive overvoltage. A case where a negative overvoltage is input from ANTP 511 will be described with reference to arrow 52 in Fig. 5. When a negative overvoltage is input from ANTP 511, the current is discharged from GND 514 through the path of D 532A and D_ESD 531, so that the device connected to VCC 513 is protected from the overvoltage. This makes it possible to protect the circuit and connected devices from the negative overvoltage.

[0055] The operation of the semiconductor circuit will be described with reference to FIG. FIG. 6 shows a semiconductor device formed on a P-type substrate (PSUB). An N+ region and a P+ region are arranged and separated by STI. DA_ISO534A is a diode that isolates the anode of D_ESD531 from the PSUB in the N+ region. Because the anode (P+) and cathode (N+:N+ region) of DA_ISO534A are shorted, no current can flow and it functions to isolate the anode of D_ESD531 from the PSUB. D_ESD531 is a diode formed between the P+ and N+ regions. When the RF signal is negative (ANTP is negative), it becomes reverse biased and does not affect the rectification function. When the RF signal is positive (ANTP is positive), it becomes forward biased, but since the cathode voltage of D_ESD531 is higher than the anode voltage during normal circuit operation, no current flows and the rectification function is not affected. Also, if the cathode voltage becomes lower than the anode for some reason, it turns on with a differential voltage equal to or greater than the forward bias voltage of D_ESD531 and assists the rectification function. It becomes forward biased during overvoltage and performs a protective function. DSub_ISO534B is When a negative overvoltage is input from ANTP511, DA_ISO534A becomes forward biased and releases the excess current to PSUB. When a positive overvoltage is input from ANTP511, D_ESD531 and D532B become forward biased and release the excess current to VCC513. As a result, the voltage of VCC513 rises, but the Voltage Clamp ESD541 limits the increased overvoltage to a constant voltage, thereby fulfilling its protective function. When a negative overvoltage is input from ANTP511, DA_ISO534A enters a voltage limiting state with D532A forward biased and D_ESD531 reverse biased (BreakDown), providing protection by dissipating excess current from ANTN512 or GND541 to ANTP511 (arrow 53 in Figure 5).

[0056] [RF-DC circuit 501 (second embodiment)] FIG. 7 is a block diagram showing the functional configuration of an RF-DC circuit 501 (second embodiment). FIG. 8 is a cross-sectional view of an RF-DC circuit 501 (second embodiment). The RF-DC circuit 501 (second embodiment) is formed of bulk CMOS.

[0057] [Basic configuration of RF-DC circuit 501 (second embodiment)] The components of the RF-DC circuit 501 (second embodiment) are different from those of the RF-DC circuit 501 (first embodiment). Specifically, the difference is that the cathode of the DA_ISO 534A and the cathode of the DSub_ISO 534B are connected to the VCC 513.

[0058] [Connection Relationship of RF-DC Circuit 501 (Second Embodiment)] The RF-DC circuit 501 (second embodiment) differs from the RF-DC circuit 501 (first embodiment) in that DSub_ISO534B is not connected to the ANTP511 terminal, and therefore does not become a parasitic capacitance of the ANTP511, resulting in more favorable power receiving efficiency. ANTP511 (antenna positive terminal) is connected to one end of C521. The other end of C521 is connected to the anode of D532B. The anode of D_ESD531 is connected between ANTP511 and one end of C521. The cathode of D_ESD531 is connected between the other end of C521 and the anode of D532B. The anode of DA_ISO 534A is connected between ANTP 511 and one end of C521. The cathode of DA_ISO 534A is connected to VCC 513. The cathode of DSub_ISO534B is connected between the cathode of DA_ISO534A and VCC513. The anode of DSub_ISO534B is connected to ANTN512. The anode of D532A is connected to ANTN512. The cathode of D532A is connected between the other end of C521 and the anode of D532B. The cathode of D532B is connected to VCC 513. One end of C_storage 522 is connected to VCC 513. The other end of C_storage 522 is connected to GND 514. One end of the voltage clamp ESD541 is connected between the cathode of D532B and VCC513. The other end of the voltage clamp ESD541 is connected to GND514.

[0059] [Operation of RF-DC circuit 501 (second embodiment)] The operation when a positive overvoltage or a negative overvoltage is input from the ANTP 511 is the same as in the first embodiment, and in the RF-DC circuit 501 (second embodiment), an effective circuit protection function against overvoltage can be realized while realizing efficient RF-DC conversion. The operation when a positive overvoltage is input from the ANTP 511 is the same as in the first embodiment, and in the RF-DC circuit 501 (second embodiment), an effective circuit protection function against overvoltage can be realized while realizing efficient RF-DC conversion. The operation when a negative overvoltage is input from ANTP511 differs from the first embodiment, and in the RF-DC circuit 501 (second embodiment), when a negative overvoltage is input from ANTP511, D532A becomes forward biased and D_ESD531 becomes reverse biased (BreakDown) voltage limiting state, and a protective operation is performed to release the excess current from ANTN512 or GND541 to ANTP511. Unlike the first embodiment, there is no connection from the ANTP511 terminal to the cathode of DSub_ISO534B, so the parasitic capacitance of DSub_ISO534B disappears, realizing efficient RF-DC conversion while providing an effective circuit protection function against overvoltage. The operation of the semiconductor circuit will be described with reference to FIG. 8 shows a semiconductor device formed on a P-type substrate (PSUB). The operation as a semiconductor circuit is different from that of the RF-DC circuit 501 (first embodiment). Specifically, when the terminal voltage of ANTP511 is higher than the VCC513 voltage by the forward voltage of D_ESD531 and DA_ISO534A or more, the forward bias of D_ESD531 or DA_ISO534A passes through a low path, and operates to store electricity in the capacitor C_storage522 connected to VCC513, which contributes to an increase in rectification efficiency. Furthermore, when the ANTP terminal voltage is negative, Dsub_ISO 534 is connected in a manner that is not visible from the ANTP terminal, as compared to RF-DC circuit 501 (first embodiment), and therefore the effect of parasitic capacitance can be minimized, thereby significantly improving rectification efficiency.

[0060] [RF-DC circuit 501 (third embodiment)] FIG. 9 is a block diagram showing the functional configuration of an RF-DC circuit 501 (third embodiment). Fig. 10 is a first cross-sectional view of the RF-DC circuit 501 (third embodiment). Fig. 11 is a second cross-sectional view of the RF-DC circuit 501 (third embodiment). The RF-DC circuit 501 (third embodiment) is formed of bulk CMOS.

[0061] [Basic configuration of RF-DC circuit 501 (third embodiment)] Description of configurations that overlap with the RF-DC circuit 501 (second embodiment) will be omitted. Q551A and Q551B are NMOS transistors, and provide a rectification function in place of diodes D532A and D532B of the RF-DC circuit 501 (first embodiment). Gate Ctrl552 is a circuit that independently controls the gate voltages of Q551A and Q551B. DBG_ISO561 is a backgate insulation diode that controls the backgates of Q551A and Q551B. DBG_ISO_Q561A is a backgate isolation diode for the Q551A, and provides electrical isolation and control between the Q551A backgate and GND514. Dsub_ISO_Q561A is a diode between the Q551A Isolation N+ (DBG_ISO_Q561A cathode) and PSUB, and is a diode to isolate the drain and source of the Q551A from PSUB (=GND513). Dsub_ISO_Q561B is a diode between the Q551B Isolation N+ (DBG_ISO=Q561C cathode) and PSUB, and is a diode to isolate the drain and source of Q551B from PSUB (=GND513). DBG_ISO=Q561C is a backgate isolation diode for Q551B, which provides electrical isolation and control between the backgate of Q551B and PSUB (GND514). Gate 565 is the gate electrode of the NMOS transistor and controls the operation of the transistor.

[0062] [Connection Relationship of RF-DC Circuit 501 (Third Embodiment)] The RF-DC circuit 501 (third embodiment) includes a fourth diode provided between the capacitor and the power supply voltage supply terminal, and a fifth diode provided between the capacitor and the GND514 output. The fourth and fifth diodes are configured as NMOS transistors (Q551B and Q551A). specifically, ANTP511 (antenna positive terminal) is connected to one end of C521, the other end of which is connected to the N1 node. The anode of the D_ESD 531 is connected between the ANTP 511 and one end of the C 521. The cathode of the D_ESD 531 is connected to the N1 node. The anode of DA_ISO 534A is connected between ANTP 511 and one end of C521. The cathode of DA_ISO 534A is connected to VCC 513. The cathode of DSub_ISO534B is connected between the cathode of DA_ISO534A and VCC513. The anode of DSub_ISO534B is connected to GND514. The anode of DBG_ISO=Q561C is connected to the N1 node. The cathode of DBG_ISO=Q561C is connected to VCC513. The drain of Q551B (NMOS) is connected to the N1 node. The source of Q551B is connected to VCC513. The gate of Q551B is connected to Gate Ctrl552. The cathode of DSub_ISO_Q561B is connected between the source of Q551B and VCC513. The anode of DSub_ISO_Q561B is connected to GND514. The drain of Q551A (NMOS) is connected to ANTN512. The source of Q551A is connected to the N1 node. The gate of Q551A is connected to Gate Ctrl552. The anode of DSub_ISO_Q561A is connected between the drain of Q551A and ANTN512. The cathode of DSub_ISO_Q561A is connected to the anode of DSub_ISO_Q561A, which is connected to ANTN512 and GND514. Gate Ctrl552 is connected to the gate of Q551A and the gate of Q551B. One end of the voltage clamp ESD541 is connected to VCC513. The other end of the voltage clamp ESD541 is connected to GND514. One end of the C_storage 522 is connected to the VCC 513. The other end of the C_storage 522 is connected to the GND 514.

[0063] [Operation of RF-DC circuit 501 (third embodiment)] Unlike the RF-DC circuit 501 (first embodiment), the RF-DC circuit 501 (third embodiment) can suppress the influence of parasitic capacitance while providing overvoltage protection in a low-cost bulk process, similar to the RF-DC circuit 501 (second embodiment). When an RF signal is input from ANTP511, this high-frequency signal reaches C521. Since D_ESD531 is connected in parallel with C521, during the positive half cycle of the RF signal, if C521 is charged to the forward voltage (Vf) of D_ESD531 or more, it will be in a reverse bias state, which will not affect normal RF signals and will maintain the efficiency of the circuit. Instead of the diodes D532A and D532B of the RF-DC circuit 501 (first embodiment), NMOS transistors Q551A and Q551B function as rectifiers to convert the RF signal to direct current (DC). The gate voltages of Q551A and Q551B are independently controlled by the Gate Ctrl552 circuit, and are set so that the Vt voltage at which the MOS turns ON is lower than the SBD Vf. During the negative half cycle of the RF signal, Q551A turns on and charges C521. During the positive half cycle of the RF signal, Q551B turns on and charges C_storage522. By controlling the NMOS gate voltage so that IsolationNMOS Vt is approximately 0.1V for SBD Vf=0.3V, the efficiency is improved by the difference of 0.2V. By setting DBG_ISO=Q561C, the back gate potential of Q551B follows the drain potential. The rectified and stored power is supplied to the connected device through the VCC513 terminal. Voltage Clamp ESD541 is connected between VCC513 and GND514 to provide protection in case the output voltage rises too high. If a negative overvoltage is input from ANTP511, the current will be discharged from GND514 through the body diode of Q551A and D_ESD531, thereby protecting the device connected to VCC513 from the overvoltage. If a positive overvoltage is input from ANTP511, the current will be discharged from D_ESD531 through the body diode of Q551B, Voltage Clamp ESD541, and GND514, thereby protecting the device connected to VCC513 from the overvoltage.

[0064] The operation of the semiconductor circuit will be described with reference to FIG. 10 and FIG. 10 and 11 show a semiconductor device formed on a P-type substrate (PSUB). An N+ region and a P+ region separated by STI are formed on a P-type substrate (PSUB). Q551B shown in Figure 11 is configured as an NMOS transistor with N+ source / drain regions in the P-well. Q551A shown in Figure 10 is configured separately as an NMOS transistor. Figure 10 is configured as an NMOS transistor with N+ source / drain regions in the P-well. DSsub_ISO_Q561B is a diode formed between the N+ region PSUB. It isolates the source / drain of Q551B from PSUB, enables operation dependent on the VCC513 potential, and suppresses parasitic effects. DBG_ISO_Q561A is a diode formed between the P+ and N+ regions of Q551A. It makes the back gate potential of Q551A follow the drain potential and optimizes the transistor characteristics. DBG_ISO=Q561C in Figure 11 is a diode formed between the P+ and N+ regions of Q551B. The backgate potential of Q551B is made to follow the drain potential, optimizing the transistor characteristics. DSub_ISO_Q561B is a diode formed between the N+ region PSUB. It isolates the source / drain of Q551B from PSUB, allows operation dependent on VCC513 potential, and suppresses parasitic effects. The gate voltage is controlled by the Gate Ctrl552 circuit, and it turns on at a Vt voltage lower than the Vf of the SBD. It turns on during the positive half cycle of the RF signal and charges the C_storage522. During normal operation, the RF signal passes through C521, and Q551A and Q551B alternately conduct to provide rectification. When a negative overvoltage is input from ANTP511, the excess current is released through the body diode of Q551A and D_ESD531. When a positive overvoltage is input from ANTP511, the excess current is released through D_ESD531 and the body diode of Q551B.

[0065] [RF-DC Circuit 501 (Fourth Embodiment)] FIG. 12 is a block diagram showing the functional configuration of an RF-DC circuit 501 (fourth embodiment). FIG. 13 is a cross-sectional view of an RF-DC circuit 501 (fourth embodiment). The RF-DC circuit 501 (fourth embodiment) is formed of SOI (Silicon-On-Insulator) CMOS. SOI CMOS is a method of forming a thin silicon layer on a silicon substrate with an insulating layer (buried oxide layer) sandwiched between them, and then fabricating devices on top of that. The manufacturing process is complicated, and generally costs more than bulk CMOS. Because the insulating layer inhibits heat conduction, self-heating is more likely to occur than with bulk CMOS. Parasitic capacitance with the substrate is significantly reduced, so even if SOI process CMOS is substituted for D532A and D532B, the structure is basically ISO2 insulation. This eliminates parasitic capacitance compared to bulk CMOS, improving high frequency characteristics and increasing efficiency.

[0066] [Basic configuration of RF-DC circuit 501 (fourth embodiment)] The RF-DC circuit 501 (fourth embodiment) is constructed using an SOI (Silicon-On-Insulator) process, is insulated and isolated from the PSUB by a BOX (SiO2), and has a process structure that has no parasitic capacitance between the PSUB substrate and the transistor or diode configuration. Description of configurations that overlap with the RF-DC circuit 501 (first embodiment) will be omitted. D_ESD531 is an ESD (electrostatic discharge) protection diode added in parallel to C521. This is a reverse-biased CAP in parallel with C521, so it has a structure that is unlikely to affect circuit operation or efficiency. It provides the function of protecting C521 from overvoltages such as ESD (Electrostatic Discharge) and EOS (Electric Over Stress, overvoltage / overcurrent stress). BOX 566 (Buried Oxide) represents the buried oxide layer that is a feature of the SOI structure, which significantly reduces the parasitic capacitance between devices. P- denotes a P-type region in the SOI layer, which forms the anode side of the D_ESD 531. N+ denotes a high concentration N-type region in the SOI layer, which forms the cathode side of the D_ESD 531. PSUB refers to the P-type substrate at the bottom of the SOI structure, which is electrically isolated from the upper device layer by the BOX566 layer. This configuration realizes effective overvoltage protection while taking advantage of the advantages of the SOI process. By adding D_ESD531 and modifying the Voltage Clamp ESD541, the overvoltage protection function can be realized while maintaining the operating efficiency of the circuit.

[0067] [Connections of RF-DC circuit 501 (fourth embodiment)] The RF-DC circuit 501 (fourth embodiment) is formed by an SOI process. For example, the RF-DC circuit 501 (fourth embodiment) is formed by SOI CMOS. In the RF-DC circuit 501 (fourth embodiment), the diode is formed in a silicon layer on an insulating layer. specifically, ANTP511 (antenna positive terminal) is connected to one end of C521. The other end of C521 is connected to the anode of D532B. The anode of D_ESD531 is connected between ANTP511 and one end of C521. The cathode of D_ESD531 is connected between the other end of C521 and the anode of D532B. The anode of D532A is connected to ANTN512. The cathode of D532A is connected between the other end of C521 and the anode of D532B. The cathode of D532B is connected to VCC513. One end of the C_storage 522 is connected to the VCC 513. The other end of the C_storage 522 is connected to the GND 514. One end of the voltage clamp ESD541 is connected between the cathode of D532B and VCC513. The other end of the voltage clamp ESD541 is connected to GND514. The D_ESD 531 is composed of a P- region (anode side) and an N+ region (cathode side), which are formed on the BOX 566 (buried oxide film) layer. The BOX566 layer electrically separates the device layer from the PSUB (P-type substrate).

[0068] [Operation of RF-DC circuit 501 (fourth embodiment)] When an RF signal is input from ANTP511, this high-frequency signal reaches C521 directly. Since D_ESD531 is connected in parallel with C521, during the positive half cycle of the RF signal, if C521 is charged to the forward voltage (Vf) of D_ESD531 or more, it will be in a reverse bias state. This means that D_ESD531 does not affect normal RF signals, and the efficiency of the circuit can be maintained. D532A and D532B act as a rectifier, converting the RF signal to direct current (DC). During the negative half-cycle of the RF signal, D532A conducts and charges C521. During the positive half-cycle of the RF signal, D532B conducts and charges C_storage522. If the charging voltage to C521 is equal to or lower than the forward voltage (Vf) of D_ESD531, when the ANTP511 voltage rises, current flows from D_ESD531 to D532B, charging C_storage522. This allows power to be stored efficiently even in a low-voltage state (arrow 64 in Figure 12). The rectified and stored power is supplied to the connected device through the VCC513 terminal. Voltage Clamp ESD541 is connected between VCC513 and GND514, providing protection even if the output voltage rises excessively (overvoltage).

[0069] 12. When a positive overvoltage is input from ANTP 511, the following description will be given with reference to arrow 61 in Fig. 12. When a positive overvoltage (electrostatic discharge, ESD) is input from ANTP 511, the current is discharged from D_ESD 531 through the path of D532B, Voltage Clamp ESD 541, and GND 514, so that the device connected to VCC 513 is protected from the overvoltage. The case where a negative overvoltage (electrostatic discharge, ESD) is input from ANTP 511 will be described with reference to arrow 62 in Fig. 12. When a negative overvoltage is input from ANTP 511, the current is discharged from GND 514 through the path of D 532A and D_ESD 531, so that the device connected to VCC 513 is protected from the overvoltage. A case where an excessive signal is input between ANTP 511 and ANTN 512 will be described with reference to arrow 63 in Fig. 12. When an excessive signal is input between ANTP 511 and ANTN 512, the current is discharged from D_ESD 531 through the path of D532B, Voltage Clamp ESD 541, and ANTN 512, so that the device connected to VCC 513 is protected from the overvoltage. The internal circuit of RF-DC circuit 501 is protected.

[0070] The operation of the semiconductor circuit will be described with reference to FIG. FIG. 13 shows a semiconductor device in which a BOX566 (buried oxide layer, SiO2) is formed on a P-type substrate (PSUB). A P-layer (silicon active layer) is formed on the BOX566 layer, and an N+ region and a P+ region separated by STI (Shallow Trench Isolation) are arranged. This structure is called the SOI process. D_ESD531 is a diode formed between the P+ and N+ regions. It is normally reverse-biased with respect to the input signal from ANTP511. When an overvoltage occurs, it becomes forward-biased, providing a protection function. The SOI structure significantly reduces the parasitic capacitance between the device and the substrate, which improves high frequency performance and increases the efficiency of RF-DC conversion. D532A and D532B function as a rectifier. Depending on the positive and negative half cycles of the RF signal, D532A and D532B are alternately conductive to charge C521 and C_storage522. D_ESD531 has no effect during normal operation, but forms a protection path in the event of an overvoltage. If a negative overvoltage is input from ANTP511, it will be released via GND514, D532A, and D_ESD531, thereby protecting the device connected to VCC513 from the overvoltage. If a positive overvoltage is input from ANTP511, it will be released via the paths D_ESD531, D532B, Voltage Clamp ESD541, and GND514, thereby protecting the device connected to VCC513 from the overvoltage. The advantages of the SOI structure include improved isolation between devices, reduced parasitic effects, reduced capacitive coupling to the substrate, and improved high frequency performance.

[0071] <Basic computer hardware configuration> 14 is a block diagram showing the basic hardware configuration of a computer 90. The computer 90 includes at least a processor 901, a main storage device 902, an auxiliary storage device 903, and a communication IF 991 (interface). These are electrically connected to each other by a communication bus 921.

[0072] The processor 901 is hardware for executing an instruction set described in a program, and is composed of an arithmetic unit, a register, a peripheral circuit, and the like.

[0073] The main memory device 902 is for temporarily storing programs, data to be processed by the programs, etc. For example, it is a volatile memory such as a DRAM (Dynamic Random Access Memory).

[0074] The auxiliary storage device 903 is a storage device for saving data and programs, such as a flash memory, a hard disk drive (HDD), a magneto-optical disk, a CD-ROM, a DVD-ROM, or a semiconductor memory.

[0075] The communication IF 991 is an interface for inputting and outputting signals for communicating with other computers via a network using a wired or wireless communication standard. The network is composed of the Internet, a LAN, various mobile communication systems constructed by wireless base stations, etc. For example, the network includes 3G, 4G, 5G mobile communication systems, LTE (Long Term Evolution), wireless networks that can connect to the Internet via a specified access point (e.g., Wi-Fi (registered trademark)), etc. In the case of wireless connection, communication protocols include, for example, Z-Wave (registered trademark), ZigBee (registered trademark), Bluetooth (registered trademark), etc. In the case of wired connection, the network also includes a network that is directly connected by a USB (Universal Serial Bus) cable or the like.

[0076] It should be noted that the computer 90 can be virtually realized by distributing all or part of each hardware configuration among multiple computers 90 and connecting them together via a network. In this way, the computer 90 is a concept that includes not only a computer 90 housed in a single housing or case, but also a virtualized computer system.

[0077] <Basic functional configuration of computer 90> A description will now be given of the functional configuration of a computer realized by the basic hardware configuration (FIG. 14) of a computer 90. The computer comprises at least the functional units of a control unit, a storage unit, and a communication unit.

[0078] The functional units of the computer 90 can also be realized by distributing all or part of the functional units among multiple computers 90 connected to each other via a network. The computer 90 is a concept that includes not only a single computer 90 but also a virtualized computer system.

[0079] The control unit is realized by the processor 901 reading out various programs stored in the auxiliary storage device 903, expanding the programs in the main storage device 902, and executing processes according to the programs. The control unit can realize functional units that perform various information processing depending on the type of program. In this way, the computer is realized as an information processing device that performs information processing.

[0080] The storage unit is realized by a main storage device 902 and an auxiliary storage device 903. The storage unit stores data, various programs, and various databases. Furthermore, the processor 901 can secure a storage area corresponding to the storage unit in the main storage device 902 or the auxiliary storage device 903 in accordance with a program. Furthermore, the control unit can cause the processor 901 to execute processes of adding, updating, and deleting data stored in the storage unit in accordance with the various programs.

[0081] The term database refers to a relational database, which is used to manage sets of data called masters and tables in a tabular format structurally defined by rows and columns, by associating them with each other. In a database, a table is called a table or master, a column in a table is called a column, and a row in a table is called a record. In a relational database, relationships between tables and masters can be set and associated. Usually, a column that serves as a primary key for uniquely identifying a record is set in each table and each master, but setting a primary key in a column is not essential. The control unit can cause the processor 901 to add, delete, or update records in a specific table or master stored in the storage unit according to various programs. Furthermore, by storing data, various programs, and various databases in the storage unit, it can be considered that the information processing device and information processing system according to the present disclosure have been manufactured.

[0082] In addition, the database and master in this disclosure may include any data structure (such as a list, a dictionary, an associative array, or an object) in which information is structurally defined. The data structure also includes data that can be considered as a data structure by combining data with a function, class, method, or the like written in any programming language.

[0083] The communication unit is realized by the communication IF 991. The communication unit realizes a function of communicating with other computers 90 via a network. The communication unit can receive information transmitted from other computers 90 and input the information to the control unit. The control unit can cause the processor 901 to execute information processing on the received information in accordance with various programs. In addition, the communication unit can transmit information output from the control unit to other computers 90.

[0084] In addition, the above-mentioned configurations, functions, processing units, processing means, etc. may be realized in part or in whole by hardware, for example, by designing them as integrated circuits. The present invention can also be realized by software program code that realizes the functions of the embodiments. In this case, a storage medium on which the program code is recorded is provided to a computer, and a processor included in the computer reads the program code stored in the storage medium. In this case, the program code itself read from the storage medium realizes the functions of the above-mentioned embodiments, and the program code itself and the storage medium storing it constitute the present invention. Examples of storage media for supplying such program code include flexible disks, CD-ROMs, DVD-ROMs, hard disks, SSDs, optical disks, magneto-optical disks, CD-Rs, magnetic tapes, non-volatile memory cards, ROMs, etc.

[0085] Furthermore, the program code for realizing the functions described in this embodiment can be implemented in a wide range of program or script languages, such as assembler, C / C++, perl, Shell, PHP, Java (registered trademark), and the like.

[0086] Furthermore, the program code of the software that realizes the functions of the embodiments may be distributed over a network and stored in a storage means such as a computer's hard disk or memory, or in a storage medium such as a CD-RW or CD-R, and the processor of the computer may read out and execute the program code stored in the storage means or storage medium.

[0087] The functions performed by the components described herein may be implemented in circuitry or processing circuitry, including general purpose processors, application specific processors, integrated circuits, ASICs (Application Specific Integrated Circuits), a CPU (a Central Processing Unit), conventional circuits, and / or combinations thereof, programmed to perform the functions described. Processors include transistors and other circuits and are considered to be circuitry or processing circuitry. A processor may be a programmed processor that executes a program stored in a memory. In this specification, a circuitry, unit, or means is hardware that is programmed to realize or performs the described functions, which may be any hardware disclosed in this specification or any hardware known to be programmed to realize or perform the described functions. If the hardware is a processor considered to be a type of circuitry, the circuitry, means, or unit is a combination of the hardware and software used to configure the hardware and / or processor.

[0088] Although several embodiments of the present disclosure have been described above, these embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and modifications are within the scope of the invention and its equivalents as described in the claims, as well as the scope and spirit of the invention.

[0089] (Additional Note) The matters described in the above embodiments will be supplemented below.

[0090] (Appendix 1) (Appendix 1) In an RF-DC circuit of a wireless power receiving device, the RF-DC circuit comprises a capacitor provided between an antenna positive terminal and a power supply voltage supply terminal, and a diode connected in parallel with the capacitor and capable of outputting an overvoltage input from the antenna positive terminal to a GND output, and the RF-DC circuit is not connected to an overvoltage protection element between the antenna positive terminal and the capacitor. This makes it possible to suppress the adverse effects on the output voltage on the power supply voltage supply terminal side caused by the parasitic capacitance of the overvoltage protection element (ESD protection element), while also suppressing overvoltages such as ESD (Electro Static Discharge) and EOS (Electric Over Stress, overvoltage / overcurrent stress) from being output from the antenna through the power supply voltage supply terminal. It is possible to protect devices connected to the power supply voltage supply terminal without using a complex circuit configuration.

[0091] (Appendix 2) (Appendix 2) 2. The RF-DC circuit of claim 1, wherein an overvoltage protection element is connected between the capacitor and a power supply voltage supply terminal, and the overvoltage protection element is capable of outputting an overvoltage to a GND output via the antenna positive terminal, a diode, and the overvoltage protection element. As a result, by placing an overvoltage protection element between the capacitor and the power supply voltage terminal, the overvoltage from the antenna can be effectively released to the GND output, which makes it possible to prevent degradation of the performance of the RF-DC circuit while protecting the device connected to the power supply voltage terminal.

[0092] (Appendix 3) (Appendix 3) 2. The RF-DC circuit of claim 1, wherein the RF-DC circuit is configured as a semiconductor circuit. By configuring the RF-DC circuit as a semiconductor circuit, it is possible to reduce the size, increase the integration density, and improve mass productivity, thereby enabling the wireless power receiving device to be made smaller and less costly.

[0093] (Appendix 4) (Appendix 4) 2. The RF-DC circuit of claim 1, wherein the RF-DC circuit includes a second diode and a third diode connected between the antenna positive terminal and the diode, the RF-DC circuit being formed in bulk CMOS, and the diode, the second diode and the third diode being formed in a channel region on a silicon substrate. As a result, the use of bulk CMOS processes makes it possible to realize RF-DC circuits at lower cost than SOI processes. Furthermore, by adding the second and third diodes, the adverse effects of parasitic diodes in bulk processes can be suppressed. This makes it possible to provide low-cost, high-performance RF-DC circuits.

[0094] (Appendix 5) (Appendix 5) 5. The RF-DC circuit of claim 4, wherein outputs of the second diode and the third diode are connected to an overvoltage protection element and a power supply voltage supply terminal. As a result, by connecting the outputs of the second and third diodes to the overvoltage protection element and the power supply voltage terminal, more efficient overvoltage protection is possible while suppressing the effects of parasitic capacitance. As a result, in a CMOS structure, high rectification efficiency can be achieved while suppressing the effects of parasitic elements.

[0095] (Appendix 6) (Appendix 6) 5. The RF-DC circuit according to claim 4, further comprising: a fourth diode provided between the capacitor and a power supply voltage supply terminal; and a fifth diode provided between the capacitor and a GND output, the fourth diode and the fifth diode being configured as NMOS transistors. As a result, by configuring the fourth and fifth diodes as NMOS transistors, the rectification efficiency of the circuit can be improved. NMOS transistors have a lower forward voltage drop compared to conventional diodes, enabling more efficient power conversion, especially in low-power wireless power receiving systems, which improves the overall system power efficiency and enables longer-range wireless power transfer and smaller receiving antennas.

[0096] (Appendix 7) (Appendix 7) 2. The RF-DC circuit of claim 1, wherein the RF-DC circuit is formed in a SOI process and the diode is formed in a silicon layer on an insulating layer. As a result, forming RF-DC circuits with SOI CMOS can reduce parasitic capacitance more than with bulk CMOS. Forming a silicon layer on an insulating layer reduces capacitive coupling with the substrate, improving high-frequency characteristics. This enables efficient operation at higher frequency bands, improving the performance and miniaturization of wireless power receiving systems. [Explanation of symbols]

[0097] RF-DC circuit 501, ANTP511 (antenna positive terminal), ANTN512 (antenna negative terminal), VCC513 (power supply voltage supply terminal), GND514 (ground terminal), C521 (capacitor), C_storage522 (storage capacitor), D_ESD531 (ESD protection diode), D532A, D532B (rectifier diode), DA_ISO534A, DSub_ISO534B (insulation diode), Voltage Clamp ESD541 (voltage clamp ESD protection element), Q551A, Q551B (NMOS transistor), Gate Ctrl552 (gate voltage control circuit), DBG_ISO561 (backgate insulating diode), DBG_ISO_Q561A (backgate insulating diode for Q551A), DSub_ISO_Q561B (backgate insulating diode for Q551B), DBG_ISO=Q561C (drain-backgate connecting diode for Q551B), Gate565 (gate electrode of NMOS transistor) 565, BOX566 (Buried Oxide, buried oxide layer) 566

Claims

1. In an RF-DC circuit of a wireless power receiving device, The RF-DC circuit includes: a capacitor provided between the antenna positive terminal and a power supply voltage supply terminal; a diode connected in parallel with the capacitor and capable of outputting an overvoltage input from the antenna positive terminal to a GND output; Equipped with An overvoltage protection element is not connected between the antenna positive terminal and the capacitor. RF-DC circuit.

2. the overvoltage protection element is connected between the capacitor and the power supply voltage supply terminal; the overvoltage protection element is capable of outputting the overvoltage to the GND output via the antenna positive terminal, the diode, and the overvoltage protection element; The RF-DC circuit of claim 1.

3. The RF-DC circuit is configured as a semiconductor circuit. The RF-DC circuit of claim 1.

4. The RF-DC circuit includes: a second diode and a third diode connected between the antenna positive terminal and the diode; The RF-DC circuit is formed in bulk CMOS; the diode, the second diode and the third diode are formed in a channel region on a silicon substrate; The RF-DC circuit of claim 1.

5. outputs of the second diode and the third diode are connected to the overvoltage protection element and the power supply voltage supply terminal; The RF-DC circuit of claim 4.

6. The RF-DC circuit includes: a fourth diode provided between the capacitor and the power supply voltage supply terminal; a fifth diode provided between the capacitor and the GND output; Equipped with the fourth diode and the fifth diode are configured as NMOS transistors; The RF-DC circuit of claim 4.

7. The RF-DC circuit is formed by an SOI process; The diode is formed in a silicon layer on an insulating layer. The RF-DC circuit of claim 1.

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