Exposure equipment and systems

Abstract

To transfer a mask pattern on a substrate with precision, while improving a throughput, in a projection exposure apparatus.SOLUTION: Positions of alignment marks of chips arranged in a matrix on a substrate W are measured in advance by a measuring device independent of a projection exposure apparatus (S101), and an amount of positional deviation specific to each chip is determined (S102). The projection exposure apparatus measures GA alignment mark and calculates an amount of positional deviation of each chip with linearity (S103). Then, based on the inherent positional deviation amount (S104) and the linear positional deviation amount, the position of the alignment mark of each chip is calculated in a situation where the substrate W is mounted on the exposure apparatus.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an exposure apparatus that forms a pattern on a substrate, and more particularly to alignment with respect to the substrate. [Background technology]

[0002] Exposure tools require high-precision alignment as patterns become finer. For this reason, alignment marks formed on a substrate are not only marks provided at the four corners of the substrate to measure deformation of the entire substrate, but also alignment marks are formed to match the one-shot exposure area.

[0003] Detecting the positions of such a large number of alignment marks provided on a substrate takes a lot of time and reduces throughput. For this reason, a configuration is known in which a measurement device that measures the positions of the alignment marks is provided independently of the exposure device (see Patent Document 1).

[0004] In this system, the position of the alignment mark in a given exposure area is detected by a measurement device prior to alignment adjustment by the exposure tool itself.Then, the exposure tool detects only the position of the alignment mark on the entire substrate using a GA method or the like, and performs alignment using the position information of the alignment mark detected earlier. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 10-64804 Summary of the Invention [Problem to be solved by the invention]

[0006] For example, in the case of a fan-out wafer-level package (FO-WLP) substrate that mounts a silicon chip on a carrier, random chip alignment errors occur due to the chip mounting accuracy. On the other hand, the expansion and contraction and deformation of the substrate occur with each process, and the degree of expansion and contraction and deformation varies.

[0007] Therefore, the position of the alignment mark measured prior to the exposure tool may be different when the alignment is measured later by the exposure tool, and a registration error occurs during the alignment of the exposure step. The registration error becomes particularly noticeable in a process in which the exposure step is repeated to transfer a pattern onto multiple layers.

[0008] Therefore, when measuring the position of an alignment mark prior to alignment by an exposure apparatus, it is required to achieve highly accurate alignment. [Means for solving the problem]

[0009] The exposure apparatus of the present invention is capable of exposing a plurality of chips arranged in a matrix on a substrate, aligning the substrate, and communicating with a data server, and includes a measurement unit that measures the position of a GA (global alignment) alignment mark provided on the substrate on which the plurality of chips are arranged in a matrix when the substrate is mounted on a stage during the exposure process, a calculation unit that calculates the die shift amount of each chip by removing the linear component deformation amount related to the entire substrate from the difference between the exposure position of each chip in the substrate design and the alignment mark position information of each chip of the substrate measured in advance by an independent measurement device and stored in the data server, and a calculation means that calculates the exposure position of each chip during the exposure process by adding the die shift amount and the linear positional deviation amount obtained from the positional information of the GA alignment mark measured by the measurement unit during the exposure process to the exposure position of each chip in the substrate design. Here, the die shift amount (intrinsic positional deviation amount) is an error component inherent to each chip, not an error that has linearity such as deformation or expansion / contraction of the entire substrate and can be considered to be common between chips.

[0010] Another aspect of the present invention is an exposure apparatus capable of exposing a plurality of chips arranged in a matrix on a substrate, aligning with the substrate, and communicating with a data server, and is equipped with a measurement unit that measures the position of a GA (global alignment) alignment mark provided on the substrate on which the plurality of chips are arranged in a matrix when the substrate is mounted on the stage during the exposure process, and a calculation means that calculates the exposure position of each chip during the exposure process by taking into account the die shift amount of each chip on the substrate stored in the data server and the linear positional deviation amount obtained from the position information of the GA alignment mark measured by the measurement unit during the exposure process, relative to the exposure position of each chip in the substrate design.

[0011] Another aspect of the present invention is an exposure apparatus that is capable of exposing multiple chips arranged in a matrix on a substrate, is capable of aligning with the substrate, and is capable of communicating with an independent measuring device that measures position information of alignment marks formed for each chip.The exposure apparatus is equipped with a measurement unit that measures the position of a GA (global alignment) alignment mark provided on the substrate on which multiple chips are arranged in a matrix when the substrate is mounted on a stage during the exposure process, and a calculation means that calculates the exposure position of each chip during the exposure process by taking into account the die shift amount of each chip on the substrate determined by the measurement device and sent from the measurement device, and the linear positional deviation amount obtained from the position information of the GA alignment mark measured by the measurement unit during the exposure process, relative to the exposure position of each chip in the substrate design.

[0012] Another aspect of the present invention is a system that includes an exposure device capable of exposing a plurality of chips arranged in a matrix on a substrate and aligning the substrate, an independent measurement device that measures position information of an alignment mark formed for each chip, and a data server that can store position information of the alignment mark for each measured chip and can communicate with the exposure device. The system includes a measurement unit that is provided in the exposure device and measures the position of a GA (global alignment) alignment mark provided on the substrate on which the plurality of chips are arranged in a matrix when the substrate is mounted on a stage during the exposure process. The system includes an arithmetic unit provided in the exposure apparatus, measurement apparatus, or data server, which calculates the die shift amount of each chip on the substrate by removing the linear component of deformation amount related to the entire substrate from the difference between the exposure position of each chip on the substrate in the design and the alignment mark position information of each chip on the substrate measured by the measurement apparatus, and a calculation means provided in the exposure apparatus, which calculates the exposure position of each chip during the exposure process by taking into account the die shift amount of each chip on the substrate and the linear positional deviation amount obtained from the position information of the GA alignment mark measured by the measurement unit during the exposure process, relative to the exposure position of each chip on the substrate in the design. Effect of the Invention

[0013] According to the present invention, in a projection exposure apparatus, it is possible to transfer a mask pattern onto a substrate with high accuracy while improving throughput. [Brief description of the drawings]

[0014] [Figure 1] 1 is a schematic block diagram of a projection exposure apparatus according to an embodiment of the present invention. [Diagram 2] 1 is a diagram showing a shot arrangement formed on a substrate W. FIG. [Diagram 3]FIG. 13 is a diagram showing shot arrangement error divided into components. [Figure 4] 13 is a flowchart showing a chip-specific arrangement error calculation process executed by the measurement device 15. FIG. [Diagram 5] 1 is a diagram showing an exposure process including alignment performed in a projection exposure apparatus 10. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0016] 1 is a schematic block diagram of a projection exposure apparatus according to the present embodiment, in which an exposure process is performed to form patterns in a plurality of layers in an overlapping manner.

[0017] The projection exposure apparatus 10 is an exposure apparatus that transfers a mask pattern formed on a reticle R as a photomask onto a substrate (work substrate) W in accordance with a step-and-repeat method, and is equipped with a light source 20 such as a discharge lamp, and a projection optical system 34. The reticle R is made of a quartz material or the like, and has a mask pattern having a light-shielding region formed thereon. The substrate W used here is a substrate made of silicon, ceramics, glass, or resin (e.g., an interposer substrate), or the like.

[0018] The illumination light emitted from the light source 20 is incident on an integrator 24 via a mirror 22, and the amount of illumination light is made uniform. The uniform illumination light is incident on a collimator lens 28 via a mirror 26. As a result, parallel light is incident on the reticle R. The light source 20 is driven and controlled by a lamp driver 21.

[0019] The reticle R is mounted on a reticle stage 30 so that the mask pattern is at the light source side focal position of the projection optical system 34. Three-axis coordinate systems of XY-Z, which are orthogonal to each other, are defined for the stage 30 on which the reticle R is mounted and the stage 40 on which the substrate W is mounted. The stage 30 is movable in the XY directions so as to move the reticle R along the focal plane, and is driven by a stage drive unit 32. The stage 30 is also capable of rotating on the XY coordinate plane. The position coordinates of the stage 30 are measured here by a laser interferometer or a linear encoder (not shown).

[0020] The light transmitted through the area of ​​the reticle R where the mask pattern is formed is projected as pattern light onto the substrate W by the projection optical system 34. The substrate W is mounted on a substrate stage 40 so that the exposure surface of the substrate W coincides with the image-side focal position of the projection optical system 34.

[0021] The stage 40 is movable in the XY directions so as to move the substrate W along the focal plane, and is driven by a stage driver 42. The stage 40 is also movable in the Z-axis direction (the optical axis direction of the projection optical system 34) perpendicular to the focal plane (XY directions), and can also rotate on the XY coordinate plane. The position coordinates of the stage 40 are measured by a laser interferometer or a linear encoder (not shown).

[0022] The control unit 50 controls the stage driving units 32, 42 to position the reticle R and the substrate W, and also controls the lamp driving unit 21. Then, an exposure operation based on the step and repeat method is performed. A memory (not shown) provided in the control unit 50 stores the mask pattern position coordinates of the reticle R, the designed position coordinates of the shot area formed on the substrate W, the step movement amount, etc.

[0023] The alignment mark imaging unit 36 ​​is a camera or microscope that images the alignment marks formed on the substrate W, and before exposure, images the alignment marks provided on the substrate W by driving the stage driving unit 42 to move the stage 40. The image processing unit 38 detects the position coordinates of the alignment marks based on the image signal sent from the alignment mark imaging unit 36. Here, the positions of the alignment marks for GA (global alignment) provided at the four corners of the substrate W are detected.

[0024] According to the step-and-repeat method, the control unit 50 sequentially transfers the mask pattern of the reticle R to each shot area formed on the substrate W. That is, the control unit 50 intermittently moves the stage 40 according to the shot area intervals, and when the shot area to be exposed is positioned at the projection position of the mask pattern, the control unit 50 drives the light source 20 to project the pattern light onto the shot area.

[0025] The measuring device 15 is a device for measuring an alignment mark provided on the substrate W, and includes an alignment mark measuring unit 15A, and is connected to the projection exposure device 10 so as to be capable of mutual data communication. The substrate W is constituted here by a FO-WLP substrate, and a large number of silicon chips (for example, 10,000 pieces) are arranged in a matrix on a carrier substrate. The substrate is not limited to the FO-WLP substrate, and may be a normal wafer substrate or a printed wiring board. The chips do not have to be of the same type, and a plurality of types of chips may be arranged. In addition, the substrate may be a substrate on which a large number of circuit patterns (referred to as units) having an area smaller than the substrate are arranged in a matrix, and may be exposed by aligning the units as a reference. There may be one or a plurality of chips inside the unit. The measuring device 15 measures the position of an alignment mark provided on each chip at a stage before patterning by the exposure device 10.

[0026] The measuring device 15 comprises a substrate stage on which the substrate W is placed, a camera that images the alignment mark, a scanning mechanism that moves the substrate relative to the camera, a measurement unit that measures the amount of relative movement of the substrate, an image processing unit that measures the position of the alignment mark from the image obtained by imaging with the camera, a data management unit that records the measured position information of the alignment mark in a file, and a controller that controls them (none of which are shown here).

[0027] The measuring device 15 transmits a file relating to the positional information of the alignment marks of each chip to the data server 60. The data server 60 records and manages the file by linking it to the ID of the substrate W that is the measurement target.

[0028] The projection exposure apparatus 10 performs alignment when transferring (exposing) a mask pattern onto each layer. That is, it detects a positioning error, which is an arrangement error of the shot areas, and performs alignment in advance between the shot areas of the substrate W and the projection area of ​​the mask pattern.

[0029] In this embodiment, the projection exposure apparatus 10 calculates the amount of positional deviation specific to each chip from the position of the alignment mark of each chip measured by the measurement device 15, and determines the exposure position of each chip during the exposure process using this amount of positional deviation and the position of the GA alignment mark measured by the alignment mark imaging unit 36. The projection exposure apparatus 10 performs alignment exposure by the die-by-die (hereinafter, D / D) method according to the determined exposure position of each chip. This will be described in detail below.

[0030] Fig. 2 is a diagram showing a shot arrangement formed on a substrate W. Fig. 3 is a diagram showing distortion of the shot arrangement caused by deformation of the substrate W or the like.

[0031] As shown in Fig. 2, a lower layer pattern is formed on the substrate W in which chips CP are arranged at regular intervals in a matrix shape in accordance with a grid defined by an XY coordinate system. Here, each chip CP corresponds to a shot area, and a mask pattern formed on the reticle R is formed by superimposing it on the chip CP (hereinafter also referred to as a shot area). In addition, alignment marks AM for positioning are formed at arbitrary positions (center positions at the left and right ends in Fig. 2) along the arrangement of the shot areas CP. The alignment marks AM for positioning may be provided in the vicinity of the shot areas CP (for example, on the scribe line). In addition, some of the alignment marks AM for positioning may also be used as alignment marks for GA.

[0032] 3 shows a state in which the alignment of the shot areas CP is disrupted due to deformation of the substrate W. When the substrate W is a wafer, the amount of deformation is not so large, but it is not negligible compared to the allowable error range in overlay with the lower layer pattern. Furthermore, when the substrate W is a printed circuit board or an interposer substrate, the deformation of the substrate W becomes even larger. As a result, the positions of the chips CP deviate from their designed positions.

[0033] When the substrate W is an FO-WLP substrate, random chip arrangement errors (called die shift) occur due to chip mounting accuracy. Meanwhile, the substrate W expands, contracts, and deforms with each process (collectively called substrate deformation). Therefore, the position of the alignment mark AM of each chip CP during exposure differs from the position of the alignment mark AM when measured by the measurement device 15.

[0034] In particular, when patterning multiple layers, the degree of expansion / contraction and deformation of the substrate W changes each time exposure and the processes before and after it (exposure, etching, heat treatment, etc.) are repeated, and the positional deviation from the alignment mark AM measured by the measuring device 15 becomes larger.

[0035] FIG. 3 is a diagram showing shot arrangement error divided into its components. The chip arrangement error component due to die shift (defined as the die shift amount) has no correlation or regularity in the error amount between chip CPs. This arrangement error with no correlation or regularity is defined as the inherent positional deviation amount. The inherent positional deviation amount can be considered to be a non-linear (non-linear) error component regardless of the deformation or expansion / contraction of the entire substrate W. On the other hand, the chip arrangement error component due to deformation, expansion, etc. of the substrate W is an arrangement error that occurs with a common regularity between chip CPs depending on the degree of deformation relative to the entire substrate W, and therefore can be considered to be a linear error component.

[0036] Therefore, first, the linear arrangement error amount is removed from the chip arrangement error amount between the position of the alignment mark AM of each chip CP measured by the measuring device 15 and the designed position, and the inherent positional deviation amount of each chip is extracted. Then, the exposure device 10 obtains the linear chip arrangement error amount obtained from the GA alignment mark, and combines the inherent positional deviation amount of each chip to estimate the exposure position of each chip during the exposure process.

[0037] FIG. 4 is a flowchart showing the chip-specific arrangement error calculation process executed by the measurement device 15. As shown in FIG.

[0038] When the position of the alignment mark provided on each chip of the substrate W is measured (S101), the difference (X, Y, θ) between the position information of the alignment mark on each chip and the design position information is calculated (S102). Then, from the obtained chip arrangement error amount, a linear component is extracted using the least squares method or the like (S103), and by removing this, the X, Y, θ components that are the inherent positional deviation amount of each chip are obtained (S104).

[0039] FIG. 5 is a diagram showing an exposure process including alignment performed in the projection exposure apparatus 10. As shown in FIG.

[0040] The positions of GA alignment marks provided on the substrate W (for example, the positions of alignment marks provided at the four corners of the substrate) are measured, and the difference from the designed position is calculated separately for the X component, the Y component, and the θ component (S201). Meanwhile, data on the inherent positional deviation amount of each chip obtained by the measuring device 15 is read from the data server 60 (S202).

[0041] Since the amount of misalignment of the GA alignment marks measured by the exposure apparatus 10 can be regarded as a linear amount of misalignment (i.e., the sum of the amounts of misalignment in X, Y, and θ when the substrate is placed on the exposure apparatus, and the amount of deformation such as the expansion / contraction of the substrate and changes in orthogonality), the amount of deformation of the entire substrate W in the exposure process can be calculated from this. Then, by using the GA alignment technique, the amount of misalignment of the X, Y, and θ components at the exposure position of each chip calculated from the amount of deformation of the entire substrate W can be calculated (the amount of misalignment at the exposure position of each chip calculated from the amount of deformation of the entire substrate W is defined as a linear amount of misalignment). However, it is assumed that the deformation and expansion of the substrate W occurs approximately uniformly over the entire substrate or over the area to be exposed.

[0042] Then, based on the linear positional deviation amount and the inherent positional deviation amount of each chip, the exposure position of each chip is calculated (S203). That is, the exposure position (exposure map) of each chip during the exposure process is calculated by taking into account the linear positional deviation amount and the inherent positional deviation amount with respect to the designed exposure position. Although the projection exposure apparatus 10 does not measure the alignment marks of each chip, the exposure position of each chip is estimated by this calculation, and exposure is performed by the die-by-die method (S204).

[0043] Thus, according to this embodiment, the positions of the alignment marks of the chips arranged in a matrix on the substrate W are measured in advance by the measuring device 15 independent of the projection exposure apparatus 10, and an inherent positional deviation amount specific to each chip is obtained. Then, the projection exposure apparatus 10 measures the GA alignment marks and calculates a linear positional deviation amount for each chip. Then, based on the inherent positional deviation amount and the linear positional deviation amount, the exposure position of each chip is calculated and exposure is performed when the substrate W is mounted on the exposure apparatus 10.

[0044] In this way, by calculating the linear misalignment amount that changes with the process during the exposure process, while calculating the intrinsic misalignment amount that occurs when the first chip is mounted and does not change through the process before using the exposure tool, appropriate alignment can be performed. In particular, appropriate alignment can be performed even when repeated patterns are superimposed on the substrate W. This can also be applied to substrates on which elements other than chips are two-dimensionally arranged.

[0045] Instead of the measuring device 15 calculating the chip-specific misalignment amount and outputting it to the projection exposure device 10, the chip-specific misalignment amount may be calculated by the data server 60 or the projection exposure device 10. Also, the GA alignment mark is not limited to one formed at a specific location on the substrate W, and a predetermined alignment mark may be selected to obtain a linear misalignment amount. Also, it is possible to apply this to a maskless exposure device instead of a projection exposure device. In this case, the exposure data may be corrected based on the position of the alignment mark-specific misalignment amount of each chip that has been obtained.

[0046] In addition, when exposing a predetermined layer of the substrate W, the measuring device 15 may calculate the chip-specific positional deviation amount and output it to the projection exposure device 10, and when exposing a layer above that layer, alignment may be performed using the chip-specific positional deviation amount that has already been calculated. [Explanation of symbols]

[0047] 10 Projection exposure equipment 40 Stages 42 Stage drive unit 50 Control section W substrate AM alignment mark R Reticle

Claims

1. An exposure apparatus that projects a mask pattern and is capable of exposing a plurality of chips arranged in a matrix on a substrate, aligning the substrate, and communicating with a data server, comprising: a measurement unit that measures the position of a GA (global alignment) mark provided on a substrate on which a plurality of chips are arranged in a matrix when the substrate is mounted on a stage during an exposure process; a calculation unit that calculates a die shift amount for each chip by removing a linear component deformation amount related to the entire substrate from a difference between an exposure position of each chip on the substrate in terms of design and alignment mark position information for each chip on the substrate that is measured in advance by an independent measuring device and stored in the data server; a calculation means for calculating an exposure position of each chip during an exposure process by taking into account the die shift amount and a linear positional deviation amount obtained from position information of a GA alignment mark measured by the measurement unit during an exposure process, with respect to an exposure position of each chip on the substrate in terms of design; The exposure apparatus is characterized in that the substrate is a FO-WLP (Fan out Wafer Level Package) substrate.

2. For a plurality of chips arranged in a matrix on a substrate, position information of an alignment mark formed for each chip is measured by a measuring device independent of an exposure device capable of alignment; in the measuring apparatus or in a data server capable of communicating with the measuring apparatus and the exposure apparatus, determining a die shift amount for each chip by removing a linear component deformation amount related to the entire substrate from a difference between an exposure position of each chip in the design of the substrate and alignment mark position information of each chip of the substrate that has been measured, and storing the amount of die shift in the data server; In the exposure apparatus, a position of a GA (global alignment) alignment mark provided on a substrate on which a plurality of chips are arranged in a matrix is ​​measured when the substrate is mounted on a stage during an exposure process; an alignment method for calculating and aligning an exposure position of each chip during an exposure process by taking into account a die shift amount of each chip of the substrate stored in the data server and a linear position deviation amount obtained from position information of a GA alignment mark measured during an exposure process, with respect to an exposure position of each chip on the substrate in terms of design, the method comprising: In the exposure step for a predetermined layer of the substrate, a die shift amount of each chip is obtained in the measuring device, and alignment is performed based on an exposure position of each chip calculated from the obtained die shift amount of each chip; In the exposure process of the upper layer, the exposure position of each chip is calculated from the die shift amount of each chip obtained during the exposure process of the specified layer, and alignment is performed based on the calculated exposure position.

3. For a plurality of chips arranged in a matrix on a substrate, position information of an alignment mark formed for each chip is measured by a measuring device independent of an exposure device capable of alignment; in the measuring device, a die shift amount of each chip is obtained by removing a linear component deformation amount related to the entire substrate from a difference between an exposure position of each chip on the substrate in terms of design and alignment mark position information of each chip on the substrate; Transmitting the determined die shift amount of each chip to the exposure device; In the exposure apparatus, a position of a GA (global alignment) alignment mark provided on a substrate on which a plurality of chips are arranged in a matrix is ​​measured when the substrate is mounted on a stage during an exposure process; an alignment method in which, in the exposure apparatus, an exposure position of each chip in the design of the substrate is calculated and aligned by taking into account a die shift amount of each chip of the substrate determined by the measurement apparatus and transmitted from the measurement apparatus, and a linear positional deviation amount obtained from positional information of a GA alignment mark measured by the measurement unit during an exposure process, In the exposure step for a predetermined layer of the substrate, a die shift amount of each chip is obtained in the measuring device, and alignment is performed based on an exposure position of each chip calculated from the obtained die shift amount of each chip; In the exposure process of the upper layer, the exposure position of each chip is calculated from the die shift amount of each chip obtained during the exposure process of the specified layer, and alignment is performed based on the calculated exposure position.

4. an exposure apparatus capable of exposing a plurality of chips arranged in a matrix on a substrate and aligning the substrate, and projecting a mask pattern onto the substrate; An independent measuring device for measuring the position information of an alignment mark formed for each chip; a data server capable of storing position information of the alignment mark for each measured chip and capable of communicating with the measurement apparatus and the exposure apparatus; A system comprising: a measurement unit that is provided in the exposure apparatus and that measures the position of a GA (global alignment) alignment mark provided on a substrate on which a plurality of chips are arranged in a matrix when the substrate is mounted on a stage during an exposure process; a calculation unit that is provided in the exposure apparatus, the measurement apparatus, or the data server, and that calculates a die shift amount for each chip on the substrate by removing a linear component deformation amount related to the entire substrate from a difference between an exposure position of each chip on the substrate in terms of design and alignment mark position information for each chip on the substrate measured by the measurement apparatus; a calculation unit that is provided in the exposure apparatus and calculates an exposure position of each chip during an exposure process by taking into account a die shift amount of each chip of the substrate and a linear positional deviation amount obtained from position information of a GA alignment mark measured by the measurement unit during an exposure process, with respect to an exposure position of each chip on the substrate in terms of design; The system is characterized in that the substrate is a FO-WLP (Fan out Wafer Level Package) substrate.

5. A maskless exposure apparatus capable of exposing a plurality of chips arranged in a matrix on a substrate, capable of aligning with the substrate, and capable of communicating with a data server, comprising: a measurement unit that measures the position of a GA (global alignment) mark provided on a substrate on which a plurality of chips are arranged in a matrix when the substrate is mounted on a stage during an exposure process; a calculation unit that calculates a die shift amount for each chip by removing a linear component deformation amount related to the entire substrate from a difference between an exposure position of each chip on the substrate in terms of design and alignment mark position information for each chip on the substrate that is measured in advance by an independent measuring device and stored in the data server; a calculation means for calculating an exposure position of each chip during an exposure process by taking into account the die shift amount and a linear positional deviation amount obtained from position information of a GA alignment mark measured by the measurement unit during an exposure process, with respect to an exposure position of each chip on the substrate in terms of design; The exposure apparatus is characterized in that the substrate is a FO-WLP (Fan out Wafer Level Package) substrate.

6. A maskless exposure apparatus capable of exposing a plurality of chips arranged in a matrix on a substrate and aligning the same with respect to the substrate; An independent measuring device for measuring the position information of an alignment mark formed for each chip; a data server capable of storing position information of the alignment mark for each measured chip and capable of communicating with the measurement apparatus and the exposure apparatus; A system comprising: a measurement unit that is provided in the exposure apparatus and that measures the position of a GA (global alignment) alignment mark provided on a substrate on which a plurality of chips are arranged in a matrix when the substrate is mounted on a stage during an exposure process; a calculation unit that is provided in the exposure apparatus, the measurement apparatus, or the data server, and that calculates a die shift amount for each chip on the substrate by removing a linear component deformation amount related to the entire substrate from a difference between an exposure position of each chip on the substrate in terms of design and alignment mark position information for each chip on the substrate measured by the measurement apparatus; a calculation unit that is provided in the exposure apparatus and calculates an exposure position of each chip during an exposure process by taking into account a die shift amount of each chip of the substrate and a linear positional deviation amount obtained from position information of a GA alignment mark measured by the measurement unit during an exposure process, with respect to an exposure position of each chip on the substrate in terms of design; The system is characterized in that the substrate is a FO-WLP (Fan out Wafer Level Package) substrate.

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