Method and apparatus for processing a substrate - Patents.com
By using silicon-based hard masks and specific gas etching techniques in high-density metal lines, the problems of chrome line shape control and side wall smoothness are solved, and the line etching effect with low line impedance and good compatibility is achieved.
Patent Information
- Application Number
- JP2023567869
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-05-04
- Filing Date
- 2022-04-26
- Publication Date
- 2025-04-02
- Estimated Expiration
- 2042-04-26
AI Technical Summary
In high-density metal lines, it is difficult to achieve effective management of chromium (ruthenium) lines, side wall smoothness and line edge roughness, especially when the line pitch is reduced (such as <30nm).
The SiO layer covering hard mask is formed by using a silicon-based hard mask on the chromium (ruthenium) base layer and using oxygen (O2) or chlorine (Cl2) as the etchant during plasma etching, and smooth treatment of the chromium side wall is achieved by assisting etching with nitrogen (N2).
In high-density lines, the shape control of the chrome line and the improvement of the side wall smoothness are achieved, ensuring the low line impedance of the line and compatibility with subsequent dielectric filling.
Smart Images

Figure 0007656082000001 
Figure 0007656082000002 
Figure 0007656082000003
Abstract
Description
[Technical field]
[0001] Embodiments of the present disclosure relate generally to methods and apparatus for processing a substrate, and more particularly, to methods and apparatus for etching one or more metal layers using a silicon-based hard mask. [Background technology]
[0002] As device scaling continues to decrease, front-end-of-line (FEOL) transistors are becoming smaller in size, increasing the number of transistors per unit area. Back-end-of-line (BEOL) metal interconnect line pitches are correspondingly decreasing (e.g., <30 nm pitch). Subtractive interconnects (e.g., chemically etched) of one or more metals (e.g., tungsten, ruthenium, molybdenum, etc.) may be used to achieve lower resistance versus copper or cobalt damascene. For example, ruthenium is widely used for scaling interconnects in advanced logic nodes because of ruthenium's low resistivity and compatibility for integration with dielectric fills. However, ruthenium lines may need to be patterned at a tight pitch, and control of shape, sidewall smoothness, and line edge roughness during patterning is often difficult to achieve. Summary of the Invention
[0003] Provided herein is a method and apparatus for processing a substrate.In some embodiments, the method for processing a substrate includes: supplying oxygen (O2) into the processing volume of an etch chamber to react with a silicon-based hard mask layer on a base layer of ruthenium to form a coating of a material such as SiO covering the silicon-based hard mask layer; and supplying nitrogen (N2) to etch the base layer of ruthenium with at least one of O2 or chlorine (Cl2) and sputter a portion of the material such as SiO onto the exposed ruthenium sidewall created during etching.
[0004] According to at least some embodiments, a non-transitory computer readable storage medium has stored thereon instructions that, when executed by a processor, perform a method of processing a substrate, the method including: supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon based hardmask layer on a ruthenium base layer to form a coating of material such as SiO over the silicon based hardmask layer, and supplying nitrogen (N2) to etch the ruthenium base layer with at least one of O2 or chlorine (Cl2) and sputter a portion of the material such as SiO onto exposed ruthenium sidewalls created during the etch.
[0005] According to at least some embodiments, the etch chamber includes a gas panel configured to supply an etchant into a processing volume of the etch chamber, and a controller configured to supply oxygen (O) into the processing volume of the etch chamber to react with a silicon based hardmask layer on the ruthenium base layer to form a coating of a material such as SiO over the silicon based hardmask layer, etch the ruthenium base layer with at least one of O or chlorine (Cl), and supply nitrogen (N) to sputter a portion of a material such as SiO onto exposed ruthenium sidewalls created during the etch.
[0006] Other and further embodiments of the present disclosure are described below.
[0007] Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, will be understood by reference to the exemplary embodiments of the present disclosure, which are illustrated in the accompanying drawings, which, however, depict only typical embodiments of the present disclosure and are therefore not to be considered limiting in scope, as the present disclosure may admit of other equally effective embodiments. [Brief description of the drawings]
[0008] [Figure 1] 1 is a schematic cross-sectional view of a processing chamber according to at least some embodiments of the present disclosure. [Diagram 2] 1 is a flowchart of a method for processing a substrate according to at least some embodiments of the present disclosure. [Diagram 3] FIG. 3 is a flow chart corresponding to the flow chart of FIG. 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements that are common to multiple figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further elaboration.
[0010] Provided herein are embodiments of treating a substrate. For example, in at least some embodiments, the methods described herein include treating a hard mask (e.g., silicon-based, such as silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), etc.) disposed on a metal layer with one or more process gases (e.g., oxygen (O2)) to form a coating such as SiO over the hard mask. The metal layer is then etched, for example, with O2 and / or chlorine (Cl2). Nitrogen (N2) can be provided during the etch to aid in sputtering of the treated hard mask onto the exposed metal sidewalls (e.g., passivation layer), thus resulting in smooth sidewalls. The methods and apparatus described herein are configured to achieve smooth and controllable sidewall profiles with pitches from about 14 nm to about 28 nm. Smooth ruthenium sidewalls provide low line resistance (e.g., minimal surface scattering) and compatibility with subsequent dielectric fills (e.g., adhesion, reliability, etc.).
[0011] 1 is a schematic cross-sectional view of a processing chamber 100 according to at least some embodiments of the present disclosure. The processing chamber 100 includes a chamber body 101 and a lid 102 disposed on the chamber body 101, the chamber body 101 and the lid 102 together defining an interior volume (processing volume 113). The chamber body 101 is typically coupled to an electrical ground 103.
[0012] The processing chamber 100 can be one of an inductively coupled plasma (ICP) chamber and / or a capacitively coupled plasma (CCP) chamber. For example, in at least some embodiments, the processing chamber 100 is a chamber that includes a CCP device 107 at the top. In at least some embodiments, the top of the processing chamber 100 can be grounded. The CCP device 107 generates reactive species of the plasma in the processing chamber 100, and a system controller 108 is adapted to control the systems and subsystems of the processing chamber 100 as described above.
[0013] A substrate support assembly 104 is disposed within the interior volume for supporting a substrate 105 from below during processing. An edge ring 106 is positioned on the substrate support assembly 104 around the outer periphery of the substrate 105. The edge ring 106 is disposed on and surrounds a substrate support surface of the electrostatic chuck (e.g., the substrate support assembly 104). The substrate support assembly 104 includes one or more electrodes, such as a first electrode 109 and a second electrode, such as a ring electrode 111, surrounding the first electrode 109. The first electrode 109 and the ring electrode 111 are each coupled to a number of RF power sources 110 providing different frequencies via a matching network 112 and an edge adjustment circuit 155 (e.g., hereinafter simply referred to as edge adjustment circuit 155) including a variable capacitor and a variable inductor. The matching network 112 ensures that the output of the RF power source 110 is efficiently coupled to the plasma to maximize the energy coupled to the plasma. Matching network 112 typically matches the complex impedance of the plasma to 50 Ohms. To facilitate dynamic matching as plasma properties change during processing, matching network 112 can be continuously adjusted to ensure that the match is maintained throughout the process.
[0014] The edge adjustment circuit 155 is an RF circuit that can adjust the voltage higher or lower than the source voltage and operates near resonance, as described in more detail below. The RF power supply 110 is utilized to bias the substrate 105 disposed on the upper surface 160 of the substrate support assembly 104. The RF power supply 110 may illustratively be a source of RF energy up to (but not limited to) about 10,000 W, which may be provided at one or multiple frequencies, such as 400 kHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, or 60 MHz. The RF power supply 110 may include two or more independent RF power supplies configured to provide RF energy at two or more corresponding frequencies. For example, in at least some embodiments, RF power source 110 may include RF power source 110a and RF power source 110b, each configured to provide RF energy at corresponding frequencies, e.g., 400 kHz and 2 MHz, and optional RF power source 110c may be provided and configured to provide RF energy at frequencies of 400 kHz, 2 MHz, and / or 40 MHz. RF power source 110 may be capable of producing either or both continuous or pulsed power. First electrode 109 is coupled to a chuck power source 114 to facilitate chucking substrate 105 to top surface 160 during processing.
[0015] The CCP device 107 is disposed above the lid 102 and is configured to capacitively couple RF power into the processing chamber 100 to generate a plasma 116 therein. The CCP device 107 may be adjusted as desired to control the shape or density of the plasma 116 formed. The CCP device 107 is coupled to an RF power supply 121 via an RF feed structure 124 through a matching network 122 (similar to matching network 112). The RF power supply 121 may illustratively be capable of producing up to about 60,000 W (but is not limited to about 60,000 W) at an adjustable frequency ranging from 50 kHz to 150 MHz, although other frequencies and powers may be utilized as desired for a particular application.
[0016] In some examples, a power divider (not shown), such as a splitting capacitor, may be provided between the RF delivery structure 124 and the RF power supply 121 to control the relative amount of RF power provided. For example, a power divider may be used in embodiments where the processing chamber 100 includes an ICP device. In such embodiments, the power divider may be incorporated into the matching network 122.
[0017] A heater element 128 may be disposed on the lid 102 to facilitate heating the interior of the processing chamber 100. The heater element 128 may be disposed between the lid 102 and a plasma device, such as the CCP device 107. In some examples, the heater element 128 may include a resistive heating element and may be coupled to a power supply 130, such as an AC power supply, configured to provide sufficient energy to control the temperature of the heater element 128 within a desired range.
[0018] In operation, a substrate 105, such as a semiconductor wafer or other substrate suitable for plasma processing, is disposed on the substrate support assembly 104. Substrate lift pins 146 are movably disposed on the substrate support assembly 104 to assist in moving the substrate 105 onto the substrate support assembly 104. After positioning the substrate 105, a process gas (e.g., an etchant) is supplied from the gas panel 132 into the interior volume of the chamber body 101 through the inlet port 134. The process gas is ignited into a plasma 116 in the processing chamber 100 by applying power from the RF power supply 121 to the CCP device 107. In some examples, power from the RF power source 110 may also be provided to the first electrode 109 and / or the edge ring 106 in the substrate support assembly 104 through a matching network 112. Alternatively or additionally, power from the RF power sources 110, e.g., two or more of the RF power sources 110a-110c, may also be provided to the base plate and / or other electrodes in the substrate support assembly 104 via the matching network 112. In at least some embodiments, a DC power source 131 may be connected to the substrate support assembly 104 (e.g., to the ring electrode 111) and may be configured to provide a clamping force to clamp the edge ring 106 to a substrate support (e.g., a ceramic ring 250 disposed on a substrate support as described below) during operation, e.g., to improve thermal control of the edge ring 106.
[0019] The pressure within the interior of the processing chamber 100 may be controlled using a valve 136 and a vacuum pump 138. The temperature of the chamber body 101 may be controlled using a fluid-containing conduit (not shown) that passes through the chamber body 101.
[0020] The processing chamber 100 includes a system controller 108 for controlling the operation of the processing chamber 100 during processing. The system controller 108 comprises a central processing unit 140, a memory 142 (e.g., a non-transitory computer readable storage medium), and support circuits 144 for the central processing unit 140 to facilitate control of the components of the processing chamber 100. The system controller 108 may be one of any form of general-purpose computer processor that may be used in an industrial setting to control various chambers and sub-processors. The memory 142 stores instructions (e.g., software (source or object code)) that may be executed or invoked to control the operation of the processing chamber 100 in the manner described herein.
[0021] FIG. 2 is a flow chart of a method 200 for processing a substrate (eg, substrate 105), and FIG. 3 is a flow chart corresponding to the flow chart of FIG.
[0022] For example, the method 200 includes a two-step etch process (e.g., ruthenium etch) to achieve smooth sidewalls and controllable topography for a ruthenium etch with a pitch of less than about 28 nm. For example, the method 200 includes, at 202, supplying oxygen (O2) to a process volume (e.g., process volume 113) of an etch chamber (e.g., process chamber 100) to react with a silicon-based hard mask layer 300 on top of a base layer 302 of ruthenium to form a coating of material 304 such as SiO over the silicon-based hard mask layer 300 (FIG. 3). For example, the system controller 108 can be configured to supply oxygen (O2) into the process volume via the gas panel 132. At 202, the process parameters can include a source power (e.g., RF power supply 121) of about 1500 W at an operating frequency of about 50 kHz to about 150 MHz and a bias power (e.g., RF power supply 110) of about 40 W at an operating frequency of about 400 kHz to about 60 MHz. In at least some embodiments, the operating power and the bias power may be provided at the same frequency. Further, in 202, the substrate support assembly temperature (e.g., chuck temperature) may be about 50° C., the inside pressure of the etch chamber may be about 10 mTorr, and O2 may be provided at about 200 sccm. In at least some embodiments, the silicon-based hard mask layer 300 comprises at least one of silicon (Si), silicon oxide (SiO), silicon nitride (SiN), or silicon carbide (SiC).
[0023] Next, the method 200 includes, at 204, etching the ruthenium base layer 302 with at least one of O2 or chlorine (Cl2) and providing nitrogen (N2) to sputter a portion of a material 304 such as SiO (illustrated by directional arrows) onto one or both of the exposed ruthenium sidewalls 306 created during the etch (e.g., the sputtered material 304 such as SiO provides a passivation layer to one or both of the exposed ruthenium sidewalls 306). At 204, the process parameters may comprise a source power (e.g., RF power supply 121) of about 500 W at an operating frequency of about 50 kHz to about 150 MHz, and a bias power (e.g., RF power supply 110) of about 200 W at an operating frequency of about 400 kHz to about 60 MHz. In at least some embodiments, the operating power and the bias power may be provided at the same frequency with a bias pulse ratio of about 30%. Further at 204, the chuck temperature may be about 50° C., the inside pressure of the etch chamber may be about 10 mTorr, O2 (if used) may be provided at about 200 sccm, Cl2 (if used) may be provided at about 40 sccm, and N2 may be provided at about 20 sccm to about 200 sccm (e.g., 50 sccm). For illustrative purposes, only one of the exposed ruthenium sidewalls 306 is shown to have a material 304 such as SiO sputtered onto it. In the illustrated embodiment, the ruthenium base layer 302 is shown to have been etched down to the substrate 105 (e.g., an etch stop layer). Alternatively, the etch process may include etching through the substrate 105. The sputtered material 304 such as SiO protects the exposed ruthenium sidewalls 306 from lateral etching, resulting in a smooth sidewall.
[0024] The ruthenium line shape can be controlled. For example, in at least some embodiments, the method 200 can include adjusting the line shape of the exposed ruthenium sidewall 306 by adjusting the amount (flow rate) of N2 supplied to sputter the material 304, such as SiO. For example, in at least some embodiments, N2 can be provided (adjusted) between 20 and 200 sccm (e.g., to about 50 sccm). For example, the more N2 supplied to sputter the material 304, such as SiO, the slower the etching of the ruthenium sidewall 306 (e.g., due to greater passivation of the ruthenium sidewall 306), which results in a more tapered sidewall shape.
[0025] In at least some embodiments, the method 200 may include etching the ruthenium base layer 302 to form a plurality of interconnect lines. For example, in at least some embodiments, the plurality of interconnect lines may have a pitch of about 14 nm to about 28 nm (e.g., about 24 nm).
[0026] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.
Claims
1. 1. A method for processing a substrate, comprising: oxygen (O 2 ) into a processing volume of an etch chamber; O 2 or chlorine (Cl 2 ) to etch the ruthenium base layer and nitrogen (N) to sputter a portion of the SiO onto exposed ruthenium sidewalls created during the etch. 2 ) and A method for processing a substrate, comprising:
2. The nitrogen (N) supplied to sputter the SiO is used to control the amount of the ruthenium base layer that is etched. 2 2. The method of claim 1, further comprising adjusting the line shape of the exposed ruthenium sidewall by adjusting the flow rate of
3. 10. The method of claim 1 further comprising etching said ruthenium base layer to form a plurality of interconnect lines.
4. The method of claim 3 , wherein the plurality of interconnect lines has a pitch of from about 14 nm to about 28 nm.
5. The method of claim 3 , wherein the plurality of interconnect lines have a pitch of about 24 nm.
6. 10. The method of claim 1, wherein the silicon based hardmask layer comprises at least one of silicon (Si), silicon oxide (SiO), silicon nitride (SiN), or silicon carbide (SiC).
7. Oxygen (O 2 ) into said processing volume; about 1500 W source power at an operating frequency of about 50 kHz to about 150 MHz; A bias power of about 40 W at an operating frequency of about 400 kHz to about 60 MHz; A chuck temperature of about 50° C. an internal pressure of the etch chamber of about 10 mTorr; About 200 sccm of the oxygen (O 2 )and The method of claim 1 , further comprising providing:
8. Etching the ruthenium base layer about 500 W source power at an operating frequency of about 50 kHz to about 150 MHz; A bias power of about 200 W at an operating frequency of about 400 kHz to about 60 MHz; A chuck temperature of about 50° C. an internal pressure of the etch chamber of about 10 mTorr; When used, about 200 sccm of the oxygen (O 2 )and, When used, about 40 sccm of the chlorine (Cl 2 )and, About 20 sccm to about 200 sccm of the nitrogen (N 2 )and 8. The method of claim 1 , further comprising providing:
9. A non-transitory computer readable storage medium having instructions stored thereon, the instructions, when executed by a processor, perform a method of processing a substrate, the method comprising: oxygen (O 2 ) into a processing volume of an etch chamber; O 2 or chlorine (Cl 2 ) to etch the ruthenium base layer and nitrogen (N) to sputter a portion of the SiO onto exposed ruthenium sidewalls created during the etch. 2 ) and 1. A non-transitory computer readable storage medium comprising:
10. The nitrogen (N) supplied to sputter the SiO is used to control the amount of the ruthenium base layer that is etched. 2 10. The non-transitory computer readable storage medium of claim 9, further comprising adjusting a line shape of the exposed ruthenium sidewall by adjusting a flow rate of
11. 10. The non-transitory computer-readable storage medium of claim 9, further comprising etching the base layer of ruthenium to form a plurality of interconnect lines.
12. 12. The non-transitory computer-readable storage medium of claim 11, wherein the plurality of interconnect lines has a pitch of from about 14 nm to about 28 nm.
13. 12. The non-transitory computer-readable storage medium of claim 11, wherein the plurality of interconnect lines have a pitch of about 24 nm.
14. 10. The non-transitory computer-readable storage medium of claim 9, wherein the silicon-based hardmask layer comprises at least one of silicon (Si), silicon oxide (SiO), silicon nitride (SiN), or silicon carbide (SiC).
15. Oxygen (O 2 ) into said processing volume; about 1500 W source power at an operating frequency of about 50 kHz to about 150 MHz; A bias power of about 40 W at an operating frequency of about 400 kHz to about 60 MHz; A chuck temperature of about 50° C. an internal pressure of the etch chamber of about 10 mTorr; About 200 sccm of the oxygen (O 2 )and 10. The non-transitory computer-readable storage medium of claim 9, further comprising:
16. Etching the ruthenium base layer about 500 W source power at an operating frequency of about 50 kHz to about 150 MHz; A bias power of about 200 W at an operating frequency of about 400 kHz to about 60 MHz; an internal pressure of the etch chamber of about 10 mTorr; When used, about 200 sccm of the oxygen (O 2 )and, When used, about 40 sccm of the chlorine (Cl 2 )and, About 20 sccm to about 200 sccm of the nitrogen (N 2 )and 16. The non-transitory computer-readable storage medium of claim 9, further comprising:
17. 1. An etch chamber comprising: a gas panel configured to supply an etchant into a processing volume of the etch chamber; and reacting with the silicon-based hardmask layer on top of the ruthenium base layer to form a silicon oxide (SiO) coating over the silicon-based hardmask layer. 2 ) into the processing volume of the etch chamber; O 2 or chloride (Cl 2 ) to etch the ruthenium base layer and nitrogen (N) to sputter a portion of the SiO onto exposed ruthenium sidewalls created during the etch. 2 ) The controller is configured as follows: An etch chamber comprising:
18. The controller controls the amount of the ruthenium base layer that is etched by controlling the nitrogen (N 2 20. The etch chamber of claim 17, further configured to adjust a line shape of the exposed ruthenium sidewall by adjusting a flow rate of
19. 20. The etch chamber of claim 17, wherein the controller is further configured to etch the ruthenium base layer to form a plurality of interconnect lines.
20. 20. The etch chamber of claim 19, wherein the plurality of interconnect lines has a pitch of from about 14 nm to about 28 nm.
Citation Information
Patent Citations
Method for processing workpiece
JP2019186322A
Plasma heating of a substrate with subsequent high temperature etching
US20020139774A1
Selective Removal Process To Create High Aspect Ratio Fully Self-Aligned Via
US20190348322A1