Programmable logic circuit device and method for constructing same

Abstract

To solve a problem in which conventional eFPGAs had two challenges: the first was to reduce the size of logic cells and improve the density of implemented logic, and the second was to minimize the speed difference with ASICs.SOLUTION: A method according to an embodiment is provided for configuring a programmable logic circuit represented by a gate-level netlist by allocating the gate-level netlist to a 4-input 3-output combinational logic cell that combines three 2-input (m-input) basic logic cells that cover three (n) nodes that constitute the netlist graph.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a programmable logic circuit device suitable for incorporation into an application specific integrated circuit (ASIC) such as an SoC, and a method for configuring the same. [Background technology]

[0002] There is an IC product called ASIC (Application Specific Integrated Circuit) that is custom designed, manufactured and provided for a specific application. ASIC is a semiconductor integrated circuit that is designed and manufactured by combining the necessary logic functions for a specific device or application, but it is not possible to change the logic functions installed after manufacturing.

[0003] However, in recent years, as ASICs have become larger and more expensive, there have been an increasing number of cases where logic needs to be modified due to defects discovered after manufacturing, or new functions need to be added. Therefore, a method has been adopted in which programmable logic circuit blocks such as FPGA (Field Programmable Gate Array) devices are installed in ASICs, making it possible to fix defects or add functions. Here, the FPGA part installed in ASICs is called "embedded FPGA (eFPGA)".

[0004] Conventional eFPGA logic cells use LUTs (Look-Up Tables), which are a direct representation of a truth table. Standard FPGAs that are not designed to incorporate ASICs use SRAM as the memory used for the LUT, whereas it is not easy to design an ASIC to use a large amount of small SRAM memory. For this reason, eFPGAs in ASICs use FFs (Flip-Flops). However, FFs generally require several times (e.g. 6 to 10 times) the area of ​​SRAM, so in eFPGAs, the area of ​​a logic cell capable of implementing the same amount of logic is several times larger than in standard FPGAs. This creates certain problems in terms of implementation logic density.

[0005] Furthermore, logic cells that use LUTs can implement logic functions up to the number of inputs. For example, a four-input LUT can implement logic functions up to four variables. The amount of memory required to configure an LUT is two to the power of the number of inputs, and as the number of inputs increases, the amount of memory increases exponentially. Meanwhile, the speed of the implemented logic circuit is proportional to the number of stages (number of logic stages) that pass through the LUT. Generally, there is a trade-off between increasing the number of inputs to the LUT and decreasing the number of logic stages; the number of logic stages decreases, and vice versa.

[0006] Therefore, by reducing the number of LUT inputs used in the logic cells of eFPGA, the amount of memory used can be reduced, making it possible to achieve miniaturization, but there is a concern that the speed will decrease due to the increased number of logic stages. Since eFPGAs mounted on ASICs are difficult to control if there is a speed difference with other parts of the ASIC, it is desirable not to slow down the speed of the circuits on the eFPGA. Summary of the Invention [Problem to be solved by the invention]

[0007] As explained above, conventional eFPGAs have two challenges: the first is to miniaturize the logic cells (improve the implementation logic density), and the second is to minimize the speed difference with ASICs. There is a demand for a programmable logic circuit that can solve both challenges simultaneously.

[0008] The present invention has been made in view of the above circumstances, and has as its object to provide a programmable logic circuit having a novel structure capable of solving the above-mentioned problems. [Means for solving the problem]

[0009] In order to solve the above problems, the inventor of the present invention came up with the idea that by focusing on the structure of the netlist, which is the representation format of the logic circuit to be implemented, it is possible to realize a logic cell structure that differs from conventional LUTs, and completed the present invention.

[0010] According to the present invention, the following inventions are provided.

[0011] (1) A programmable logic circuit, having basic logic cells which constitute nodes of a gate-level netlist; This basic logic cell is a programmable circuit configured by adding a programmable NOT circuit to a basic logic operation element, The input / output of the basic logic cell is programmable in accordance with the connection relationship of the nodes in the netlist. 1. A programmable logic circuit comprising:

[0012] (2) In the programmable logic circuit according to (1), a combinational logic cell formed by combining a plurality of the basic logic cells; The combinational logic cell has a plurality of basic logic cells that cover a plurality of nodes that constitute the graph of the netlist. 1. A programmable logic circuit comprising:

[0013] (3) In the programmable logic circuit according to (2), The combinational logic cell comprises: It is an (m-1) x n+1 input, n output logic cell in which n basic m-input logic cells are connected in a switchable combination of input signals to represent two or more patterns of node connections. 1. A programmable logic circuit comprising:

[0014] (4) In the programmable logic circuit according to (3), The combinational logic cell comprises: In order to realize two or more patterns of node connection relationships, a switching circuit is provided to switch the connection relationships of basic logic nodes. 1. A programmable logic circuit comprising:

[0015] (5) The programmable logic circuit according to (4), The switching circuit is a multiplexer. 1. A programmable logic circuit comprising:

[0016] (6) The programmable circuit according to (3), A memory for storing switching information of the switching circuit, The switching information is information for programming basic logic cells in accordance with the connection relationships of the nodes that constitute the netlist. 1. A programmable logic circuit comprising:

[0017] (7) A method for configuring a programmable logic circuit, comprising the steps of: The nodes that make up the gate-level netlist are assigned to programmable logic cells. A method for configuring a programmable logic circuit, comprising the steps of: programming the logic cells so that input / output is switched in accordance with the connection relationship of the nodes;

[0018] (8) The method for configuring a programmable logic circuit according to (7) above, mapping the gate-level netlist into combinational logic cells that combine n m-input basic logic cells covering the n nodes of the netlist graph; configuring the combinational logic cell as an (m-1)×n+1-input, n-output logic cell in which n m-input basic logic cells are connected in a switchable combination with input signals in order to express two or more patterns of connection relationships between the covered nodes; 1. A method for configuring a programmable logic circuit comprising the steps of:

[0019] (9) In the method according to (8) above, The method further comprises assigning the basic logic cells to nodes of a gate-level netlist; This basic logic cell is a programmable circuit configured by adding a programmable NOT circuit to a basic logic operation element, The input / output of the basic logic cell is programmable in accordance with the connection relationship of the nodes in the netlist. A method comprising:

[0020] (10) In the method according to (8) above, This method is A step of disposing a switching circuit between basic logic nodes in the combinational logic cell to switch between the connection relationships of the basic logic nodes in order to realize two or more patterns of node connection relationships. The method of claim 1, further comprising:

[0021] (11) In the method according to (9) above, This method is The method further comprises a step of programming the switching information of the connection relationship into a basic logic cell in accordance with the connection relationship of the nodes constituting the netlist. A method comprising:

[0022] According to the present invention, the number of memories constituting the logic can be suppressed to a number proportional to the number of inputs. Therefore, compared to the case where the logic is configured with a conventional SRAM-based LUT, the logic can be configured with a much smaller number of memories. In addition, since the speed of the implemented logic circuit depends on the netlist, the impact of the increase in speed due to the number of logic cell stages is small, unlike the case where the logic is configured with a conventional LUT.

[0023] Other aspects of the present invention and other configurations will be described in the following embodiments and drawings. [Brief description of the drawings]

[0024] [Figure 1] Figure 1 is a schematic diagram showing gate-level technology mapping for a conventional LUT assignment.

[0025] [Diagram 2] FIG. 2 is a schematic diagram showing the configuration of a conventional LUT.

[0026] [Diagram 3] FIG. 3 is an explanatory diagram for explaining the concept of the present invention.

[0027] [Figure 4] FIG. 4 is an explanatory diagram for explaining a node connection pattern in one embodiment of the present invention.

[0028] [Diagram 5] FIG. 5 is a schematic diagram showing the configuration of a two-node, four-input combinational logic cell.

[0029] [Figure 6] FIG. 6 is an explanatory diagram for explaining technology mapping of a gate-level netlist.

[0030] [Figure 7] FIG. 7 is a table showing a comparison of performance between a conventional LUT and the logic cell of this embodiment.

[0031] [Figure 8] FIG. 8 is a schematic diagram showing the configuration of a PA circuit.

[0032] [Figure 9] FIG. 9 is a schematic diagram showing an example of the configuration of a PX circuit according to different basic logical operation elements.

[0033] [Figure 10] FIG. 10 is a schematic diagram showing an example of the configuration of a PX circuit according to different basic logical operation elements.

[0034] [Figure 11] FIG. 11 is an explanatory diagram for explaining a node connection pattern realized by a combinational logic cell.

[0035] [Figure 12] FIG. 12 is a schematic diagram showing a combinational logic cell.

[0036] [Figure 13] FIG. 13 is an explanatory diagram showing a connection pattern of four nodes.

[0037] [Figure 14] FIG. 14 is a schematic diagram showing a combinational logic cell.

[0038] [Figure 15] FIG. 15 is a schematic diagram showing a combinational logic cell.

[0039] [Figure 16] FIG. 16 is a schematic diagram showing a combinational logic cell.

[0040] [Figure 17] FIG. 17 is a schematic diagram showing a combinational logic cell.

[0041] [Figure 18] FIG. 15 is an explanatory diagram showing four node connection patterns and combination patterns of basic logic cells.

[0042] [Figure 19] FIG. 19 is a schematic diagram showing a combinational logic cell.

[0043] [Figure 20] FIG. 20 is an explanatory diagram showing a gate-level netlist.

[0044] [Figure 21] FIG. 21 is an explanatory diagram of how a gate-level netlist is allocated to a conventional LUT.

[0045] [Figure 22] FIG. 22 is an explanatory diagram of how a gate-level netlist is allocated to a conventional LUT.

[0046] [Figure 23]FIG. 23 is an explanatory diagram of how a gate-level netlist is allocated to a conventional LUT.

[0047] [Figure 24] FIG. 24 is an explanatory diagram of how a gate-level netlist is allocated to a conventional LUT.

[0048] [Diagram 25] FIG. 25 is an explanatory diagram for explaining a process of allocating a gate-level netlist to a logic cell according to an embodiment of the present invention.

[0049] [Figure 26] FIG. 26 is an explanatory diagram for explaining a process of allocating a gate-level netlist to a logic cell according to an embodiment of the present invention.

[0050] [Figure 27] FIG. 27 is an explanatory diagram for explaining a process of allocating a gate-level netlist to a logic cell according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0051] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0052] 1.Basic concept In general, the performance of logic cells used in FPGAs is measured by how little logic can be used to cover the circuit to be implemented, i.e., the gate-level netlist, and the operating speed of the logic cell-level netlist after covering it.

[0053] Here, covering the gate-level netlist with logic cells is called technology mapping. Also, the gate-level netlist is represented by a graph of NAND gates (NAND graph) or a graph of AND gates and NOT gates (AIG (AND-Inverter graph)).

[0054] Figure 1(a) shows the technology mapping of the gate-level netlist for implementing a conventional LUT. In the case of a 3-input LUT (3-LUT) shown in Figure 2(a), a conventional LUT is structured as shown in Figure 2(b) in which an SRAM is used as the configuration memory (M) and a truth value stored there is selected by the input values ​​(X, Y, X) and output (f). Such an LUT realizes a logic function by storing a truth table in the configuration memory.

[0055] In the example of technology mapping using the conventional LUT described above (the example shown in FIG. 2(a)), the logic functions of the outputs S and CO in FIG. 1(a) are converted into truth tables, and each is implemented in a different LUT (two 4-LUTs) as shown in FIG. 1(b).

[0056] In contrast to this, the logic cell of this embodiment is a logic that focuses on the structure of the gate netlist itself.

[0057] That is, in one embodiment of the present invention, as shown in Fig. 3(a), an AIG (And Inverter Gate), which is a gate-level netlist, is regarded as a combination of AND gates (circles) and NOT gates (dotted parts of edges) as nodes, and wiring between the nodes as edges. The above nodes are then implemented as basic logic cells (PA circuits: programmable AND circuits) as shown in Fig. 3(b). Fig. 3(c) is a conceptual diagram showing combinations of memory values ​​and outputs f stored in memories M0 and M1 for programming the PA circuit.

[0058] The number of connection patterns between the above nodes (basic logic cells) is three, as shown in Fig. 4(a) to (c), assuming that the number of nodes (basic logic cells) included in the combinational logic cell is three (four inputs). That is, Fig. 4(a) is a pattern in which one PA circuit is on the first layer and two PA circuits are on the second layer, Fig. 4(b) is a pattern in which three PA circuits are arranged in series across the first to third layers, and Fig. 4(c) is a pattern in which two PA circuits are on the first layer and one PA circuit is on the second layer. Considering the configuration of a four-input, three-output combinational logic cell (PAE circuit) (Fig. 5(a)) that realizes all three patterns, it is one in which three PA circuits (basic logic cells) are switchably connected, as shown in Fig. 5(b).

[0059] In this way, the "basic logic cells" and the "combinational logic cells" (hereinafter sometimes referred to as "PAE circuits") formed by combining these basic logic cells form the basis of the present invention.

[0060] If the same gate-level netlist as the above-mentioned conventional LUT example (FIG. 1(a)) is realized by the above-mentioned PAE circuit, it will look like the one shown in FIGS. 6(a) and 6(b).

[0061] 2.Performance comparison FIG. 7 shows a performance comparison between a logic cell using a conventional LUT and the logic cell according to the above-described embodiment.

[0062] In the comparative example shown in FIG. 7(a), a comparison is made between logic cells having the same four inputs.

[0063] First, regarding the number of memories used, in the case of a conventional 4-input LUT (4LUT), the number of memories used is 16 bits, whereas the 4-input PAE circuit of this embodiment uses 8 bits, which is half the number.

[0064] Furthermore, the average coverage rate of the netlist in this embodiment is 2.52 nodes, which exceeds the 2.43 nodes of the LUT. As a result, in an evaluation using 29 types of benchmark circuits in this embodiment, the average configuration memory reduction rate reaches 51.6%, which means that the configuration memory can be halved. In addition, the maximum configuration memory reduction rate is 66.5%, and the minimum configuration memory reduction rate is 23.0%, which means that the memory can be reduced more than in the conventional LUT.

[0065] It should be noted that the number of inputs of the logic cell and PAE of this embodiment is not limited to four as described above. For example, when the number of inputs is increased (corresponding to increasing the number of PA nodes in the logic cell), in this embodiment, the number of configuration memories of the logic cell is proportional to the number of PA nodes. On the other hand, the number of configuration memories of the LUT is proportional to the power of the number of inputs, so the performance difference between them will increase.

[0066] 7(b) shows a comparison of performance between this embodiment and the conventional logic cell when the number of inputs is 5. According to this, the configuration memory reduction rate of this embodiment is 75.7% on average, 82.3% at maximum, and 68.1% at minimum, showing an increasing performance difference.

[0067] The basic logic cells, combinational logic cells, and netlist mapping of this embodiment will be described in detail below.

[0068] 3. Basic logic cells First, the basic logic cell will be described.

[0069] The basic logic cell (PA circuit) described above in the section on the basic concept of the present invention was an example of realizing an AND gate and a NOT gate in an AIG, but the basic logic cell of the present invention is not limited to a PA circuit as long as it is configured as a "Px circuit" (where "X" means that it is not limited to an AND gate) in which a programmable NOT circuit is added to a basic logic operation element.

[0070] That is, as described above, a netlist representing a logic circuit is a graph showing a logic circuit in which basic logical operation elements such as AND gates, OR gates, and NOT gates are treated as nodes and the elements are connected as edges. A netlist created with NAND gates as nodes is called a NAND graph, and a netlist created with AND gates and NOT gates as nodes is called an AIG (AND-Inverter graph). However, a netlist can also be created using NOR gates or OR gates and NOT gates as nodes. That is, in this embodiment, if the nodes are a universal logic function set, all logic circuits can be expressed.

[0071] Therefore, the programmable NOT circuit of the PA circuit shown in Fig. 3(b) may be realized by a NOT gate and a multiplexer as shown in Fig. 8(a), or by an XOR gate as shown in Fig. 8(b). In addition, except when the original netlist uses AND gates and NOT gates as basic logic elements, the Px circuit may be configured using other logic elements. Fig. 9(a) shows an example of a Px circuit when the basic logic operation element is a NAND gate, (b) a NOR gate, and (c) an OR gate.

[0072] Also, as shown in Fig. 10(a), programmable NOT circuits may be placed at all inputs of the Px circuit. Also, Fig. 10(b) shows an example in which an AND gate with three inputs to the basic logic cell is used. In this way, the number of inputs to the basic logic cell is not limited to two.

[0073] 4. Combinational Logic Cells The combinational logic cell described above in the section on the basic concept of the present invention has four inputs and three outputs, but it is not limited to this, just as the number of inputs to a basic logic cell is not limited to two.

[0074] That is, according to this embodiment, when a combinational logic cell is configured by combining two or more types of graphs in which n basic logic cells with m inputs are connected, the number of inputs is (m-1)×n+1 inputs and the number of outputs is n. m and n may be any number equal to or greater than 2.

[0075] 12 shows a combinational logic cell 1 in which the number of inputs m of the basic logic cell (Px) is 2 and the number of connected cells n is 3. The number of inputs to this combinational logic cell 1 is (m-1) x n + 1 = (2-1) x 3 + 1 = 4, and the number of outputs is n, or 3.

[0076] Moreover, the number of inputs of the basic logic cell is m=2, and the graph with n=3 inputs connected will have three patterns of connections as shown in Figures 11(a)-(c) (circles indicate basic logic cells). In order to realize such multiple node connection relationships, the present combinational logic cell 1 has a function (indicated by reference symbol 2 in Figure 12) of switching the connection relationships of the internal logic nodes with a multiplexer or an equivalent circuit. The present combinational logic cell 1 also has a memory (reference symbol 3 in Figure 12) that holds switching information for the multiplexer etc. for switching the connections, and it is possible to set the internal memory of the logic cell according to the connection shape of the nodes that make up the netlist.

[0077] The basic logic cell (Px circuit) is not limited to the Px circuit including the programmable NOT circuit described above, but may be a single NAND gate or NOR gate.

[0078] Other embodiments of the combinational logic cell that are realized depending on the values ​​of m and n will be described below.

[0079] Example of connecting n=4 basic logic cells with m=2 inputs If the number of inputs to the basic logic cell is m=2, and n=4 of them are connected, the graph will have seven patterns as shown in Figure 13 (the circles indicate the basic logic cells (PX circuits)).

[0080] Of these seven patterns, a (2-1)×4+1=5-input, 4-output combinatorial logic cell can be created by combining the two patterns shown in Figures 13(b) and 13(c), for example as shown by reference numeral 5 in Figure 14. Here, the basic logic cell Px may be a single NAND gate or NOR gate, as described above.

[0081] FIG. 15 shows an embodiment of a 5-input 4-output logic cell created by combining two of the seven patterns shown in FIGS. 13(a) and 13(c).

[0082] Similarly, Fig. 16 shows an embodiment of the combinational logic cell of Fig. 13(c) and (d). Fig. 17 shows an embodiment of the combinational logic cell of Fig. 13(c) and (f). As above, the basic logic cell (Px circuit) may be a single NAND gate or NOR gate.

[0083] Example of a logic cell consisting of a combination of three or more basic logic types In the above example, the connection relationship between two types of basic logic cells (nodes) is realized by one combinational logic cell, but it is possible to realize connection relationships between more than two types of nodes by one combinational logic cell.

[0084] Fig. 18 shows an example of a connection of logic cells that realizes the four patterns of node connection relationships shown in Fig. 13(a), (c), (d), and (f). And Fig. 19 shows an example of a configuration of a combinational logic cell that realizes these four patterns of node connection relationships.

[0085] Although the above example shows a case where the number of contained basic logic cells is four, the number n contained therein is also arbitrary.

[0086] 5. Technology mapping method of the present embodiment Next, a technology mapping method using the above combinational logic cell in this embodiment will be described.

[0087] When a netlist (AIG) as shown in FIG. 20 is given, the procedure of technology mapping using a general LUT is as follows.

[0088] (1) Based on graph theory, we decompose the Directed Acyclic Graph (DAG) of the AIG into trees. (2) Mapping the tree to the LUT, (3) Select the next Tree and go to (2) above. (4) Once all trees have been mapped, you are done.

[0089] Here, when mapping a tree to an LUT in (2) above, a minimum cover is searched for, but since the tree is decomposed, multiple nodes overlap, and these overlapping nodes are mapped to different LUTs. Therefore, the number of LUTs after mapping increases according to the degree of overlap.

[0090] That is, the DAG of the AIG shown in Fig. 20 can be decomposed into trees with the input signal PO as a vertex, as shown in Figs. 21 to 24. Since each tree is independently mapped to the LUT, multiple nodes are common to two trees and are mapped to the LUT multiple times. As a result, a total of 14 LUTs are required. As a result, the required configuration memory amount is 16 bits x 14 = 224 bits.

[0091] On the other hand, the procedure for technology mapping using the logic cell of this embodiment is as follows.

[0092] (1) Matching with one of the node graphs (a), (b), or (c) in Figure 25 from the AIG, (2) Mapping to logical cells, (3) Go back to (1) until all nodes are covered. (4) When all nodes have been mapped, the process is complete.

[0093] When the netlist shown in Fig. 20, which is the same as the conventional mapping method described above, is mapped with the 4-input 3-output combinational logic cell shown in Fig. 26, the result is as shown in Fig. 27. When mapping to the logic cell of this embodiment, the output from the nodes within the covered range can be used, so there is no possibility of covering the target node redundantly. As a result, in this example, eight 4-input 3-output combinational logic cells (configuration memory number 8 bits) can be mapped, and the configuration memory amount is 8 bits x 8, or 64 bits. This is less than one-third of the amount when a 4-LUT is used.

[0094] According to the configuration described above, there is provided a programmable logic circuit (PAE and combinations thereof) which is a logic cell for an embedded FPGA mounted on an ASIC, the programmable logic circuit having a basic logic cell (PX circuit) constituting a node of a gate-level netlist, the basic logic cell being a programmable circuit configured by adding a programmable NOT circuit to a basic logic operation element, and which is programmable to switch the input / output of the basic logic cell depending on the connection relationship of the nodes in the netlist.

[0095] With this configuration, the number of memories that make up the logic can be kept to a number proportional to the number of inputs. Therefore, compared to when logic is configured with a conventional SRAM-based LUT, the logic can be configured with a much smaller number of memories. In addition, since the speed of the implemented logic circuit depends on the netlist, the impact of the number of logic cell stages on the speed increase is small, unlike when it is configured with a conventional LUT.

[0096] It should be noted that the present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0097] 1. Combinational logic cell 2. Multiplexer 3. Memory 5. Combinational logic cells PA···Basic logic cell PX: Basic logic cell

Claims

1. A programmable logic circuit, having basic logic cells which constitute nodes of a gate-level netlist; The basic logic cell is a programmable circuit configured by adding a programmable NOT circuit to a basic logic operation element, The input / output of the basic logic cell is programmable in accordance with the connection relationship of the nodes in the netlist.

1. A programmable logic circuit comprising:

2. 2. The programmable logic circuit of claim 1, a combinational logic cell formed by combining a plurality of the basic logic cells; The combinational logic cell includes a plurality of basic logic cells that cover a plurality of nodes that constitute a graph of a netlist.

1. A programmable logic circuit comprising:

3. 3. The programmable logic circuit of claim 2, If the number of basic logic cells to be combined is n, an integer equal to or greater than 2, and the number of inputs to each basic logic cell is m, an integer equal to or greater than 2, then: The combinational logic cell comprises: It is an (m-1) x n+1 input, n output logic cell in which n basic logic cells are connected in a switchable combination of input signals to express two or more patterns of node connections.

1. A programmable logic circuit comprising:

4. 4. The programmable logic circuit of claim 3, The combinational logic cell comprises: A switching circuit is provided for switching the connection relationship of the basic logic cells in order to realize two or more patterns of node connection relationship.

1. A programmable logic circuit comprising:

5. 5. The programmable logic circuit of claim 4, The switching circuit is a multiplexer.

1. A programmable logic circuit comprising:

6. 5. The programmable logic circuit of claim 4, A memory for storing switching information for switching the switching circuit, The switching information is information for programming basic logic cells in accordance with the connection relationships of the nodes that constitute the netlist.

1. A programmable logic circuit comprising:

7. A method for configuring a programmable logic circuit, comprising: The nodes that make up the gate-level netlist are assigned to programmable basic logic cells. A method for configuring a programmable logic circuit, comprising the steps of: programming the basic logic cells so that input / output is switched in accordance with the connection relationship of the nodes;

8. 8. The method of claim 7, further comprising the steps of: If the number of basic logic cells to be combined is n, an integer equal to or greater than 2, and the number of inputs to each basic logic cell is m, an integer equal to or greater than 2, then: Allocating the gate-level netlist to combinational logic cells that combine n basic logic cells and that can cover n nodes that constitute the netlist graph; configuring the combinational logic cell as an (m-1) x n+1 input, n output logic cell in which input signals are switchably combined and connected to express two or more patterns of connection relationships between a plurality of nodes covered by the n basic logic cells; 1. A method for configuring a programmable logic circuit comprising the steps of:

9. 9. The method of claim 8, further comprising assigning the basic logic cells to nodes of a gate-level netlist; The basic logic cell is a programmable circuit configured by adding a programmable NOT circuit to a basic logic operation element, The input / output of the basic logic cell is programmable in accordance with the connection relationship of the nodes in the netlist. A method comprising:

10. 9. The method of claim 8, A step of disposing a switching circuit in the combinational logic cell for switching the connection relationship of the basic logic cells in order to realize two or more patterns of node connection relationships. The method of claim 1, further comprising:

11. 10. The method of claim 9, A step of programming switching information for switching the connection relationships into the basic logic cells in accordance with the connection relationships of the nodes constituting the netlist. The method of claim 1, further comprising:

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