CONTROLLER, CONTROLLER OPERATION METHOD, AND STORAGE DEVICE INCLUDING THE SAME

Abstract

To provide a controller, and a controller action method that can improve a reading performance, and to provide a storage device including the controller.SOLUTION: A controller according to an embodiment of the present invention is configured so as to control an action of a non-volatile memory, and the controller is configured to: analyze a pattern of a command to be queuing at a command que in a first unit of time, and determine a writing command processing schedule, in which the command to be queuing at the command que during the first unit of time includes a first writing command or a first reading command, or both; and process a second writing command to be queuing at the command que during a second unit of time subsequent to the first unit of time in accordance with the determined writing command processing schedule.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to electronic devices, and more particularly to a controller, a method of operating the controller, and a storage device including the same. [Background technology]

[0002] Recently, the paradigm for computer environments has been shifting to ubiquitous computing, which allows computer systems to be used anywhere, anytime. This has led to a rapid increase in the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers. Such portable electronic devices generally use data storage devices that use memory devices. Data storage devices are used to store data used in the portable electronic devices.

[0003] Data storage devices using memory devices have the advantages of being safe and durable because they do not have mechanical driving parts, and have very fast information access speeds and low power consumption. Data storage devices with such advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, Universal Flash Storage (UFS) devices, and Solid State Drives (SSDs). Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE DISCLOSURE The present invention provides a controller capable of improving read performance, a method of operating the controller, and a storage device including the same.

[0005] Furthermore, the embodiments of the present invention provide a controller, a method of operating the controller, and a storage device including the same, which can improve data reliability. [Means for solving the problem]

[0006] A controller according to an embodiment of the present invention is configured to control the operation of a non-volatile memory, and determines a write command processing schedule by analyzing a pattern of commands queued in a command queue during a first unit of time, where the commands queued in the command queue during the first unit of time include a first write command, a first read command, or both; and processes a second write command queued in the command queue during a second unit of time subsequent to the first unit of time according to the determined write command processing schedule.

[0007] A method of operating a controller according to an embodiment of the present invention includes the steps of: analyzing a pattern of commands queued in a command queue during a first unit of time, where the commands queued in the command queue during the first unit of time include a first write command, a first read command, or both; determining a write command processing schedule based on the pattern of commands; and processing a second write command queued in the command queue during a second unit of time subsequent to the first unit of time according to the determined write command processing schedule.

[0008] A storage device according to an embodiment of the present invention includes a non-volatile memory; and a controller that controls an operation of the non-volatile memory at a request of a host. The controller determines a write command processing schedule by analyzing a pattern of commands queued in a command queuing area during a first unit time, the commands queued in the command queue during the first unit time including a first write command, a first read command, or both; and processes a second write command queued in the command queuing area during a second unit time subsequent to the first unit time according to the determined write command processing schedule. Effect of the Invention

[0009] According to this embodiment, based on the queuing pattern of commands queued in the command queue during the previous unit time, write commands queued in the command queue during the current unit time are processed immediately after being queued, or processed after a certain time delay, or processed after priority is given to processing read commands, thereby processing read requests received from the host without delay to improve read performance and preventing write operations from being frequently suspended to improve data reliability. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 illustrates a storage device according to an embodiment of the present invention. [Diagram 2] FIG. 2 illustrates a controller of FIG. 1. [Diagram 3] FIG. 2 illustrates the controller and non-volatile memory of FIG. 1. [Figure 4] FIG. 3 illustrates the memory of FIG. 2. [Diagram 5] FIG. 5 illustrates a command queuing area in FIG. 4. [Figure 6] FIG. 11 is a diagram illustrating an example of dynamically changing a command processing schedule according to an embodiment of the present invention. [Figure 7] FIG. 11 is a diagram showing an example of dynamically changing a command processing schedule according to another embodiment of the present invention. [Figure 8] 4 is a flowchart illustrating a method of operation of a controller according to an embodiment of the present invention. [Figure 9] FIG. 1 illustrates a data processing system including a solid-state drive (SSD) according to an embodiment of the present invention. [Figure 10] 10 is a diagram illustrating an example of the configuration of a controller in FIG. 9. [Figure 11] 1 illustrates a data processing system including a data storage device according to an embodiment of the present invention. [Figure 12]1 illustrates a data processing system including a data storage device according to an embodiment of the present invention. [Figure 13] 1 is a diagram illustrating a network system including a data storage device according to an embodiment of the present invention. [Figure 14] 2 is a block diagram illustrating a non-volatile memory device included in a data storage device according to an embodiment of the inventive concept; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0012] FIG. 1 is a diagram illustrating a storage device 10 according to an embodiment of the present invention.

[0013] 1, a storage device 10 according to an embodiment of the present invention can store data to be accessed by a host 20 such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, an in-vehicle infotainment system, etc. The storage device 10 is also called a memory system.

[0014] The storage device 10 may be any one of various types of storage devices depending on an interface protocol connected to the host 20. For example, the storage device 10 may be any one of various types of storage devices such as a solid state drive (SSD), a multimedia card (MMC), embedded MMC (eMMC), RS-MMC, or micro-MMC type multimedia card, a secure digital card (SD), mini-SD, or micro-SD type secure digital card, a universal storage bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI-e (PCI-express) card type storage device, a compact flash (CF) card, a smart media card, or a memory stick.

[0015] The storage device 10 may be manufactured in any one of a variety of package forms, such as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabricated package (WFP), and wafer-level stack package (WSP).

[0016] The storage device 10 may include a non-volatile memory 100 and a controller 200 .

[0017] The non-volatile memory 100 can operate as a data storage medium of the storage device 10. The non-volatile memory 100 can be any one of various types of non-volatile memory, such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) film, a phase change random access memory (PRAM) using chalcogenide alloys, and a resistive random access memory (ReRAM) using a transition metal oxide, depending on the memory cell.

[0018] The non-volatile memory 100 may include a memory cell array (not shown) having a plurality of memory cells each arranged at an intersection of a plurality of bit lines (not shown) and a plurality of word lines (not shown). The memory cell array may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of pages.

[0019] For example, each memory cell of the memory cell array may be a single level cell (SLC) that stores one bit, a multi-level cell (MLC) that stores two bits of data, a triple level cell (TLC) that stores three bits of data, or a quad level cell (QLC) that stores four bits of data. The memory cell array may include at least one of a single level cell, a multi-level cell, a triple level cell, and a quad level cell. For example, the memory cell array may include memory cells having a two-dimensional horizontal structure, or may include memory cells having a three-dimensional vertical structure.

[0020] 3, the non-volatile memory 100 may include a plurality of memory chips. The plurality of memory chips transmit and receive signals (or data) to and from the controller 200 via corresponding channels CH1 to CHm. Referring to FIG. 3, at least one or more memory chips Memory Chip1 to Memory Chipn may be connected to each of the plurality of channels CH1 to CHm.

[0021] The controller 200 may control all operations of the storage device 10. The controller 200 may control the non-volatile memory 100 to perform an operation corresponding to a request received from the host 20. For example, the controller 200 may generate a control signal for controlling an operation of the non-volatile memory 100 based on the request received from the host 20, and provide the generated control signal to the non-volatile memory 100. The control signal may include, but is not limited to, a command, an address, and an operation control signal.

[0022] FIG. 2 is a diagram illustrating the controller 200 of FIG.

[0023] 2, the controller 200 may include a first core (HIL Core) 210, a second core (FTL Core) 220, a third core (FIL Core) 230, a memory 240, and a command searcher 250. FIG 2 illustrates the controller 200 having separate (or independent) first, second, and third cores 210, 220, 230 and a separate (or independent) command searcher 250, but is not limited thereto. For example, in one embodiment, the second core 220 may perform some or all of the functions attributed to the first core 210, the third core 230, and / or the command searcher 250.

[0024] The first core 210 can be configured to interface between the host 20 and the storage device 10 according to the protocol of the host 20. Thus, the first core 210 is also called a protocol core or a host interface layer core (HIL Core). For example, the first core 210 can communicate with the host 20 by any one of universal serial bus (USB), universal flash storage (UFS), multimedia card (MMC), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), and PCI express (PCI-e) protocols.

[0025] The first core 210 may include a micro control unit (MCU) or a central processing unit (CPU). The first core 210 may analyze a request received from the host 20 and provide request information to the second core 220 for generating a command corresponding to the received request. For example, the request information may include, but is not limited to, an operation type, address information, and data size information.

[0026] In addition, the first core 210 may store data (e.g., write data) received from the host 20 in a write buffer (not shown) of the memory 240. To this end, the controller 200 may further include a separate data transfer block (not shown) for transferring the data received from the host 20 to the write buffer of the memory 240. For example, the data transfer block may receive data from the host 20 in response to a control signal received from the first core 210 and store the data in the write buffer of the memory 240.

[0027] In addition, the first core 210 can transfer data (e.g., read data) stored in a read buffer (not shown) of the memory 240 to the host 20. For example, the data transfer block can read the data stored in the read buffer of the memory 240 and transfer it to the host 20 according to a control signal received from the first core 210.

[0028] The second core 220 can control all operations of the storage device 10 by executing firmware or software loaded in the memory 240. The second core 220 can analyze and execute instructions or algorithms in the form of code, such as firmware or software. The second core 220 is also called a flash translation layer core (FTL Core).

[0029] The second core 220 may include a microcontroller unit (MCU) and a central processing unit (CPU).

[0030] The second core 220 may generate a command corresponding to a request received from the host 20 based on the request information provided by the first core 210. The second core 220 may also queue the generated command in a command queuing area 243 (see FIG. 4) of the memory 240. The second core 220 may also generate a command corresponding to an operation performed in the storage device 10 without the involvement of the host 20, i.e., a background operation, and queue the command in the command queuing area 243 of the memory 240. The background operation may include, but is not limited to, garbage collection.

[0031] The third core 230 can dequeue commands queued in the command queuing area 243 of the memory 240 from the command queuing area 243 and provide the dequeued commands to the non-volatile memory 100. The third core 230 is also called a flash interface layer core (FIL Core).

[0032] The third core 230 may include a microcontroller unit (MCU) and a central processing unit (CPU).

[0033] The third core 230 can provide write data stored in the write buffer of the memory 240 to the non-volatile memory 100, or can store read data received from the non-volatile memory 100 in the read buffer of the memory 240. To this end, the controller 200 can further include a separate data transfer block (not shown) for transferring write data stored in the write buffer of the memory 240 to the non-volatile memory 100, or transferring read data received from the non-volatile memory 100 to the read buffer of the memory 240, in response to a control signal received from the third core 230.

[0034] The memory 240 may be comprised of a random access memory, such as, but not limited to, a static random access memory (SRAM) or a dynamic random access memory (DRAM). Although the memory 240 is shown in FIG. 3 as being contained within the controller 200, the memory 240 may also be located external to the controller 200.

[0035] The memory 240 may be physically and electrically connected to the first core 210, the second core 220, and the third core 230. The memory 240 may store firmware executed by the second core 220. The memory 240 may also store data, such as metadata, required for the execution of the firmware. That is, the memory 240 may operate as a working memory for the second core 220.

[0036] In addition, the memory 240 can temporarily store write data transferred from the host 20 to the non-volatile memory 100 and read data transferred from the non-volatile memory 100 to the host 20. That is, the memory 240 can operate as a buffer memory. The internal configuration of the memory 240 will be described below with reference to FIG. 4.

[0037] The command searcher 250 monitors whether a new command is queued in the command queuing area 243 of the memory 240, and when a new command is queued in the command queuing area 243, the command searcher 250 may provide a signal indicating that a new command has been queued to the third core 230. The command searcher 250 may periodically monitor the command queuing area 243 using a polling method, but the method of the command searcher 250 monitoring the command queuing area 243 is not limited thereto.

[0038] Upon receiving a signal from the command retriever 250 , the third core 230 can fetch the new command from the command queuing area 243 of the memory 240 and provide the new command to the non-volatile memory 100 .

[0039] FIG. 4 is a diagram illustrating the memory 240 of FIG.

[0040] 4, the memory 240 according to the present embodiment may include, but is not limited to, a first region 241, a second region 242, and a third region 243. For example, the first region 241 of the memory 240 may store firmware (FW) (or software) that is analyzed and executed by the second core 220. Also, the second region 242 of the memory 240 may store metadata, etc., required for executing the firmware (FW) (or software). Also, the third region 243 of the memory 240 may store commands generated by the second core 220.

[0041] For example, the firmware stored in the first area 241 of the memory 240 may be a flash translation layer (FTL). In this embodiment, firmware and flash translation layer are used as terms indicating the same configuration. The flash translation layer (FTL) may be executed by the second core 220, which executes the flash translation layer (FTL) to control specific operations of the non-volatile memory 100 and provide device compatibility to the host 20. By executing the flash translation layer (FTL), the host 20 recognizes and uses the storage device 10 as a general storage device such as a hard disk.

[0042] The flash translation hierarchy (FTL) can be stored in a system area (not shown) of the non-volatile memory 100, and when the storage device 10 is powered on, it can be read from the system area of ​​the non-volatile memory 100 and loaded into the first area 241 of the memory 240. On the other hand, the flash translation hierarchy (FTL) can also be loaded into a dedicated memory (not shown) of the second core 220 that is not the first area 241 of the memory 240.

[0043] 4, the firmware (FW) in this embodiment may include a command processing scheduler 245. However, the modules included in the firmware (FW) are not limited thereto, and may include various modules such as a write module, a read module, a garbage collection module, a wear leveling module, a bad block management module, a power management module, and a map module. Each module included in the firmware (FW) is made up of a collection of source codes, etc. for performing a specific operation (or function).

[0044] In this embodiment, the command processing scheduler 245 is described as a collection of source code for performing a specific operation (or function), but is not limited to this, and the command processing scheduler 245 can also be embodied as hardware.

[0045] The command processing scheduler 245 can dynamically change the processing schedule for write commands and read commands depending on the pattern of commands queued in the command queuing area 243 of the memory 240. For example, the command processing scheduler 245 can analyze the command queuing pattern corresponding to each of the multiple memory chips included in the non-volatile memory 100, and dynamically change the command processing schedule for each of the multiple memory chips depending on the analyzed command queuing pattern.

[0046] In this embodiment, the command queuing pattern may include a command type pattern indicating whether or not command types to be queued in the command queuing area 243 are mixed, and a queuing time pattern indicating a time from when a write command is queued to when a read command is queued when a write command is queued in the command queuing area 243 and then a read command is queued. The command type pattern may include a first command type pattern in which write commands and read commands are mixed and queued in the command queuing area 243, and a second command type pattern in which write commands and read commands are not mixed and are queued in the command queuing area 243.

[0047] FIG. 5 is a diagram showing the command queuing area 243 of FIG.

[0048] 5, the command queuing area 243 may include a plurality of command queues CMDQ1 to CMDQk. In this embodiment, the number of command queues CMDQ1 to CMDQk may be the same as the number of memory chips included in the non-volatile memory 100, but is not limited thereto. That is, the command queuing area 243 may include a plurality of command queues corresponding to each of the plurality of memory chips included in the non-volatile memory 100.

[0049] Each of the multiple command queues CMDQ1 to CMDQk may include a normal command queue NQ in which normal commands are queued, and a high command queue HQ in which high commands are queued. In this embodiment, the normal command may indicate a command with a relatively lower priority than the high command, and the high command may indicate a command with a relatively higher priority than the normal command.

[0050] In this embodiment, the normal command may include, but is not limited to, a host write command Write_H CMD, an erase command Erase CMD, a background read command Read_B CMD for background operation, and a background write command Write_B CMD received from the host 20. Also, the high command may include, but is not limited to, a host read command Read_H CMD received from the host 20.

[0051] In general, the performance of the storage device 10 may be determined by the response speed to a host read command received from the host 20. The second core 220 may queue the host read command received from the host 20 in a high command queue HQ that queues high priority commands, and may queue the remaining commands in a normal command queue NQ that queues low priority commands.

[0052] For example, when a host read command is queued in a high command queue of a command queue corresponding to a first memory chip included in the non-volatile memory 100, an operation (e.g., a write operation) performed in the first memory chip may be suspended, and the suspended write operation may be resumed after the read operation corresponding to the queued host read command is performed. The write operation may include a data transfer operation in which data to be written is transferred from the controller 200 to the first memory chip of the non-volatile memory 100, and a write execute operation in which data is stored in a memory cell in the first memory chip. In one embodiment, the data transfer operation may not be suspended, and only the write execute operation may be suspended.

[0053] As a result, when a host read command is queued in the high command queue of the command queue corresponding to the first memory chip, if a data transfer operation related to the first memory chip is being performed, the host read command is processed after the data transfer operation is completed, which may delay the response speed to the host read command.

[0054] Furthermore, if a write operation is suspended, the retention characteristic of the memory cell in which the write operation is being performed, which causes charge to leak, may deteriorate, and the reliability of the data may decrease.

[0055] In this embodiment, in order to prevent delays in the response speed to host read commands and improve data reliability, a command queuing pattern corresponding to each of the multiple memory chips included in the non-volatile memory 100 is analyzed, and the processing schedule of write commands for each of the multiple memory chips is dynamically changed based on the analyzed command queuing pattern.

[0056] The command processing scheduler 245 can periodically analyze the command queuing pattern for each of the command queues CMDQ1 to CMDQk by a predetermined unit time. For example, the command processing scheduler 245 can monitor commands queued in each of the command queues CMDQ1 to CMDQk during a predetermined unit time, and analyze the command queuing pattern for each of the command queues CMDQ1 to CMDQk, i.e., the command type pattern and the queuing time pattern, based on the monitoring result. The command type pattern and the queuing time pattern have been described above, so they will not be described here.

[0057] The period from when the storage device 10 is powered on to when it is powered off may include a number of unit times, and the command processing scheduler 245 analyzes a command queuing pattern for each of the command queues CMDQ1 to CMDQk for each unit time, and dynamically changes the processing schedule of commands queued during the following unit time according to the command queuing pattern analyzed during the current unit time, as will be described in detail below with reference to FIGS.

[0058] 6 is a diagram illustrating an example of dynamically changing a command processing schedule according to an embodiment of the present invention. FIG. 6 illustrates an example in which commands are queued in one command queue, but it will be obvious to one skilled in the art that the same can be applied to each of a plurality of command queues. In FIG. 6, 'W1 to W4' indicate write commands, and 'R1 to R3' indicate read commands. In this case, the write command may be one of a host write command received from the host 20 and a background write command for a background operation. Also, the read command may be a host read command received from the host 20.

[0059] The command processing scheduler 245 can monitor whether a command is queued in the command queue during the first unit time. As shown in Fig. 6, when the first write command W1 is queued in the command queue, since there is no unit time immediately before the first unit time, the command processing scheduler 245 can instruct the third core 230 to dequeue the first write command W1 from the command queue and provide it to the corresponding memory chip of the non-volatile memory 100 in order to process the queued first write command W1 without delay.

[0060] Then, when the first read command R1 is queued in the command queue, the command processing scheduler 245 may analyze a command type pattern for the command queue based on the first read command R1 being queued after the first write command W1 is queued. For example, the command processing scheduler 245 may determine that the commands queued in the command queue have a first command type pattern. As described above, the first command type pattern indicates a pattern in which write commands and read commands are mixed and queued. In this case, the read command may be a command corresponding to a read request received from the host 20.

[0061] In addition, the command processing scheduler 245 can analyze a queuing time pattern from the time when the first write command W1 is queued to the time when the first read command R1 is queued, based on whether the commands queued in the command queue have a first command type pattern. In FIG. 6, this is shown as a first delay time TD1, and the first delay time TD1 in this embodiment can be used as the same term as the queuing time pattern.

[0062] The command processing scheduler 245 can change the processing schedule of the write commands queued during the second unit time following the first unit time based on the queuing time pattern in the first unit time, i.e., the first delay time TD1.

[0063] The command processing scheduler 245 can determine whether the first delay time TD1 exceeds a predetermined critical delay time. In this embodiment, the critical delay time can be set as the time required to process a write command, i.e., the sum of the data transfer time and the write execution time, but is not limited thereto. In another embodiment, the critical delay time can be set as the data transfer time.

[0064] If the first delay time TD1 exceeds the critical delay time, the command processing scheduler 245 may instruct the third core 230 to immediately process the second write command W2 queued in the command queue during the second unit time. In this case, if a read command is queued in the command queue while the second write command W2 is being processed, in some cases, the processing of the second write command W2 may be suspended and the read command may be preferentially processed. On the other hand, if the first delay time TD1 is equal to or less than the critical delay time, the command processing scheduler 245 may instruct the third core 230 to process the second write command W2 queued in the command queue during the second unit time after a time of about the first delay time TD1 has elapsed since the command was queued. At this time, if the second read command R2 is queued in the command queue within the first delay time TD1 from the time when the second write command W2 is queued in the command queue, the command processing scheduler 245 can instruct the third core 230 to prioritize processing of the second read command R2 over the second write command W2. The second write command W2 can be processed after processing of the second read command R2.

[0065] In addition, the command processing scheduler 245 can monitor commands queued in the command queue during the second unit time. As shown in Fig. 6, when a second write command W2 and a second read command R2 are successively queued in the command queue during the second unit time, the command processing scheduler 245 can analyze a queuing time pattern from the time when the second write command W2 is queued to the time when the second read command R2 is queued, that is, a second delay time TD2. The command processing scheduler 245 can change the processing schedule of the write commands queued during a third unit time following the second unit time based on the second delay time TD2.

[0066] As shown in FIG. 6, if, during the third unit time, after the third write command W3 is queued in the command queue, the third read command R3 is not queued within the second delay time TD2, the command processing scheduler 245 can instruct the third core 230 to process the third write command W3 after a time period of approximately the second delay time TD2 has elapsed from the time the third write command W3 is queued.

[0067] In addition, the command processing scheduler 245 can monitor commands queued in the command queue during the third unit time. As shown in Fig. 6, when a third write command W3 and a third read command R3 are successively queued in the command queue during the third unit time, the command processing scheduler 245 can analyze a queuing time pattern from the time when the third write command W3 is queued to the time when the third read command R3 is queued, that is, a third delay time TD3. The command processing scheduler 245 can change the processing schedule of the write commands queued during the fourth unit time following the third unit time based on the third delay time TD3.

[0068] In this manner, the command processing scheduler 245 according to the present embodiment can process write commands queued in the command queue during the current unit time immediately after queuing, or process them after a delay determined by the queuing pattern in the previous unit time, or process them preferentially after processing a read command, based on the queuing pattern of commands queued in the command queue during the previous unit time. This allows read requests received from the host 20 to be processed without delay, improving read performance, and preventing write operations from being frequently suspended, improving data reliability.

[0069] Fig. 7 is a diagram showing an example of dynamically changing a command processing schedule according to another embodiment of the present invention. Fig. 7 shows an example in which a plurality of write commands and a plurality of read commands are mixed and queued during one unit time. In this embodiment, the contents that overlap with the above description will be omitted, and the differences will be described later.

[0070] 7, a first write command W1, a first read command R1, a second read command R2, a second write command W2, a third read command R3, a third write command W3, a fourth read command R4, and a fifth read command R5 can be queued in sequence in a command queue during a first unit time. The command processing scheduler 245 can analyze a first delay time TD1 from the time when the first write command W1 is queued to the time when the first read command R1 is queued, a second delay time TD2 from the time when the second write command W2 is queued to the time when the third read command R3 is queued, and a third delay time TD3 from the time when the third write command W3 is queued to the time when the fourth read command R4 is queued. That is, the command processing scheduler 245 can analyze the delay time from the time when each write command is queued to the time when the read command immediately following each write command is queued.

[0071] The command processing scheduler 245 calculates an average delay time TDa of the first delay time TD1, the second delay time TD2, and the third delay time TD3, and based on the calculated average delay time TDa, can change the processing schedule of the write command queued during the second unit time following the first unit time.

[0072] In this manner, when multiple write commands and multiple read commands are mixed and queued during one unit of time, the command processing scheduler 245 can process the write commands queued during the subsequent unit of time immediately, after a certain delay, or after processing the read commands, based on the average time between the time the multiple write commands are queued and the time the multiple read commands queued following each write command are queued.

[0073] 8 is a flowchart showing an operation method of a controller according to an embodiment of the present invention. When describing the operation method of a controller according to the present embodiment with reference to FIG. 8, at least one of FIGS.

[0074] In step S810, the controller 200 of the storage device 10 may analyze a pattern of commands queued in the command queuing area 243 during a first unit time. For example, the controller 200 may analyze the pattern of commands by determining whether the types of commands queued in the command queuing area 243 are mixed, and measuring the time from when a write command is queued in the command queuing area 243 to when a read command is subsequently queued.

[0075] In step S820, the controller 200 may determine a write command processing schedule based on the command pattern analyzed in step S810. For example, the controller 200 may determine whether the measured time is equal to or less than a predetermined critical time, and may determine when to process the write commands queued in the command queue during the second unit time based on the result of the determination.

[0076] In step S830, the controller 200 can process the write commands queued in the command queuing area 243 during a second unit time subsequent to the first unit time, according to the write command processing schedule determined in step S820.

[0077] For example, if the measured time is equal to or less than the critical time, the controller 200 may process a write command queued in the command queuing area 243 during the second unit time after the measured time has elapsed. In this case, if a read command is queued in the command queuing area 243 within the measured time, the write command may be processed after completing the processing of the read command. In one embodiment, if the measured time is equal to or less than the critical time and a write command is queued in the command queuing area 243 that holds a previously queued command, the controller 200 may process the write command after the write command reaches the head of the command queuing area 243 and the measured time has elapsed.

[0078] Also, if the measured time exceeds the critical time, the controller 200 may immediately process, without delay, any write commands queued in the command queuing area 243 during the second unit time. In one embodiment, if the measured time exceeds the critical time and a write command is queued in the command queuing area 243 that holds previously queued commands, the controller 200 may immediately process the write command once it reaches the head of the command queuing area 243.

[0079] 9 is a diagram illustrating a data processing system including a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 9, a data processing system 2000 may include a host device 2100 and a solid state drive (SSD) 2200.

[0080] The SSD (2200) may include a controller 2210, a buffer memory device 2220, non-volatile memory devices 2231 to 223n, a power supply 2240, a signal connector 2250, and a power connector 2260.

[0081] The controller 2210 can control all operations of the SSD 2200. The controller 2210 can perform the functions performed by the controller 200 of FIGS.

[0082] The buffer memory device 2220 can temporarily store data to be stored in the nonvolatile memory devices 2231-223n. Also, the buffer memory device 2220 can temporarily store data read from the nonvolatile memory devices 2231-223n. The data temporarily stored in the buffer memory device 2220 can be transferred to the host device 2100 or the nonvolatile memory devices 2231-223n under the control of the controller 2210.

[0083] The non-volatile memory devices 2231 to 223n are used as storage media for the SSD 2200. Each of the non-volatile memory devices 2231 to 223n can be connected to the controller 2210 via a plurality of channels CH1 to CHn. One or more non-volatile memory devices can be connected to one channel. The non-volatile memory devices connected to one channel can be connected to the same signal bus and data bus.

[0084] The power supply 2240 can provide the power PWR inputted through the power connector 2260 to the SSD 2200. The power supply 2240 can include an auxiliary power supply 2241. The auxiliary power supply 2241 can supply power so that the SSD 2200 can be normally shut down when a sudden power off occurs. The auxiliary power supply 2241 can include large-capacitors that can be charged by the power PWR.

[0085] The controller 2210 can exchange signals SGL with the host device 2100 through a signal connector 2250. Here, the signal SGL can include commands, addresses, data, etc. The signal connector 2250 can be configured as various types of connectors depending on the interface method between the host device 2100 and the SSD (2200).

[0086] Fig. 10 is a diagram illustrating a configuration of the controller of Fig. 9. Referring to Fig. 10, the controller 2210 may include a host interface unit 2211, a control unit 2212, a random access memory 2213, an error correction code (ECC) unit 2214, and a memory interface unit 2215.

[0087] The host interface unit 2211 can interface with the host device 2100 and the SSD (2200) according to the protocol of the host device 2100. For example, the host interface unit 2211 can communicate with the host device 2100 via any one of secure digital (SD), universal serial bus (USB), multi-media card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI Express (PCI-E), and universal flash storage (UFS) protocols. In addition, the host interface unit 2211 may perform a disk emulation function that allows the host device 2100 to recognize the SSD 2200 as a general-purpose data storage device, for example, a hard disk drive (HDD).

[0088] The control unit 2212 can analyze and process the signal SGL input from the host device 2100. The control unit 2212 can control the operation of the internal functional blocks by firmware or software for driving the SSD (2200). The random access memory 2213 is used as an operating memory for driving such firmware or software.

[0089] The error correction code (ECC) unit 2214 may generate parity data for data to be transferred to the non-volatile memory devices 2231-223n. The generated parity data may be stored in the non-volatile memory devices 2231-223n together with the data. The error correction code (ECC) unit 2214 may detect errors in the data read from the non-volatile memory devices 2231-223n based on the parity data. If the detected error is within a correction range, the error correction code (ECC) unit 2214 may correct the detected error.

[0090] The memory interface unit 2215 can provide control signals such as commands and addresses to the non-volatile memory devices 2231-223n under the control of the control unit 2212. The memory interface unit 2215 can also exchange data with the non-volatile memory devices 2231-223n under the control of the control unit 2212. For example, the memory interface unit 2215 can provide data stored in the buffer memory device 2220 to the non-volatile memory devices 2231-223n, or provide data read from the non-volatile memory devices 2231-223n to the buffer memory device 2220.

[0091] 11 is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present invention. Referring to FIG. 11, a data processing system 3000 may include a host device 3100 and a data storage device 3200.

[0092] The host device 3100 may be formed in the form of a substrate such as a printed circuit board. Although not shown, the host device 3100 may include an internal functional block for performing the functions of the host device.

[0093] The host device 3100 may include a connection terminal 3110, such as a socket, a slot, or a connector. The data storage device 3200 may be mounted on the connection terminal 3110.

[0094] The data storage device 3200 may be in the form of a substrate such as a printed circuit board. The data storage device 3200 may also be called a memory module or a memory card. The data storage device 3200 may include a controller 3210, a buffer memory device 3220, non-volatile memory devices 3231-3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

[0095] The controller 3210 can control all operations of the data storage device 3200. The controller 3210 can be configured similarly to the controller 2210 shown in FIG.

[0096] The buffer memory device 3220 can temporarily store data to be stored in the nonvolatile memory devices 3231-3232. In addition, the buffer memory device 3220 can temporarily store data read from the nonvolatile memory devices 3231-3232. The data temporarily stored in the buffer memory device 3220 can be transferred to the host device 3100 or the nonvolatile memory devices 3231-3232 under the control of the controller 3210.

[0097] The non-volatile memory devices 3231 to 3232 are used as storage media for the data storage device 3200.

[0098] The PMIC 3240 can provide power input via a connection terminal 3250 to the data storage device 3200. The PMIC 3240 can manage the power of the data storage device 3200 under the control of the controller 3210.

[0099] The connection terminal 3250 may be connected to the connection terminal 3110 of the host device. Signals such as commands, addresses, data, and power may be transmitted between the host device 3100 and the data storage device 3200 via the connection terminal 3250. The connection terminal 3250 may be configured in various forms depending on the interface method between the host device 3100 and the data storage device 3200. The connection terminal 3250 may be disposed on any side of the data storage device 3200.

[0100] 12 is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present invention. Referring to FIG. 12, a data processing system 4000 may include a host device 4100 and a data storage device 4200.

[0101] The host device 4100 may be formed in the form of a board such as a printed circuit board. Although not shown, the host device 4100 may include an internal function block for performing the functions of the host device.

[0102] The data storage device 4200 may be in the form of a surface mount package. The data storage device 4200 may be mounted on the host device 4100 via solder balls 4250. The data storage device 4200 may include a controller 4210, a buffer memory device 4220, and a non-volatile memory device 4230.

[0103] The controller 4210 can control all operations of the data storage device 4200. The controller 4210 can be configured similarly to the controller 2210 shown in FIG.

[0104] The buffer memory device 4220 may temporarily store data to be stored in the nonvolatile memory device 4230. In addition, the buffer memory device 4220 may temporarily store data read from the nonvolatile memory device 4230. The data temporarily stored in the buffer memory device 4220 may be transferred to the host device 4100 or the nonvolatile memory device 4230 under the control of the controller 4210.

[0105] The non-volatile memory device 4230 is used as a storage medium for the data storage device 4200 .

[0106] 13 is a diagram illustrating a network system 5000 including a data storage device according to an embodiment of the present invention. Referring to FIG 13, the network system 5000 may include a server system 5300 and a plurality of client systems 5410 to 5430 connected via a network 5500.

[0107] The server system 5300 can provide data services in response to requests from the multiple client systems 5410 to 5430. For example, the server system 5300 can store data provided from the multiple client systems 5410 to 5430. As another example, the server system 5300 can provide data to the multiple client systems 5410 to 5430.

[0108] The server system 5300 may include a host device 5100 and a data storage device 5200. The data storage device 5200 may be configured as the storage device 10 in FIG. 1, the SSD (2200) in FIG. 9, the data storage device 3200 in FIG. 11, or the data storage device 4200 in FIG.

[0109] 14 is a block diagram illustrating a non-volatile memory device included in a data storage device according to an embodiment of the present invention. Referring to FIG. 14, the non-volatile memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 140, a data read / write block 130, a voltage generator 150, and a control logic 160.

[0110] The memory cell array 110 may include memory cells MC arranged in regions where word lines WL1 to WLm and bit lines BL1 to BLn intersect with each other.

[0111] The row decoder 120 may be connected to the memory cell array 110 via word lines WL1 to WLm. The row decoder 120 may be operated under the control of a control logic 160. The row decoder 120 may decode an address provided from an external device (not shown). The row decoder 120 may select and drive the word lines WL1 to WLm based on a result of the decoding. For example, the row decoder 120 may provide a word line voltage provided from a voltage generator 150 to the word lines WL1 to WLm.

[0112] The data read / write block 130 may be connected to the memory cell array 110 via bit lines BL1 to BLn. The data read / write block 130 may include read / write circuits RW1 to RWn corresponding to the bit lines BL1 to BLn, respectively. The data read / write block 130 may be operated under the control of the control logic 160. The data read / write block 130 may operate as a write driver or a sense amplifier depending on the operation mode. For example, the data read / write block 130 may operate as a write driver that stores data provided from an external device in the memory cell array 110 during a write operation. As another example, the data read / write block 130 may operate as a sense amplifier that reads data from the memory cell array 110 during a read operation.

[0113] The column decoder 140 may be operated under the control of the control logic 160. The column decoder 140 may decode an address provided from an external device. The column decoder 140 may connect the read / write circuits RW1-RWn of the data read / write block 130 corresponding to each of the bit lines BL1-BLn to a data input / output line (or a data input / output buffer) based on a decoding result.

[0114] The voltage generator 150 may generate voltages used for internal operations of the non-volatile memory device 100. The voltages generated by the voltage generator 150 may be applied to memory cells of the memory cell array 110. For example, a program voltage generated during a program operation may be applied to a word line of a memory cell in which the program operation is performed. As another example, an erase voltage generated during an erase operation may be applied to a well region of a memory cell in which the erase operation is performed. As yet another example, a read voltage generated during a read operation may be applied to a word line of a memory cell in which the read operation is performed.

[0115] The control logic 160 may control all operations of the non-volatile memory device 100 based on control signals provided from an external device, such as read, write, and erase operations of the non-volatile memory device 100.

[0116] Those skilled in the art to which the present invention pertains should understand that the present invention can be embodied in other specific forms without departing from the technical spirit and essential features thereof, and that the above-described embodiments are illustrative and not limiting in all respects. The scope of the present invention is defined by the claims rather than the above detailed description, and all modifications and variations derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0117] 10 Storage device 100 Non-volatile Memory 200 Controller 210 First Core 220 Second Core 230 Third Core 240 Memory 245 Command Processing Scheduler

Claims

1. A controller configured to control operation of a non-volatile memory, comprising: The controller: determining a write command processing schedule by analyzing a pattern of commands queued in a command queue during a first unit of time, where the commands queued in the command queue during the first unit of time include a first write command, a first read command, or both; processing a second write command queued in the command queue during a second unit time subsequent to the first unit time according to the determined write command processing schedule; The pattern of commands includes a queuing time pattern indicating the time from when a previous command is queued to when a subsequent command is queued.

2. 2. The controller of claim 1, wherein the controller analyzes a pattern of the commands queued in the command queue based on whether the types of commands queued in the command queue are mixed and the time from when the first write command is queued in the command queue to when the first read command is subsequently queued.

3. 3. The controller of claim 2, wherein the controller determines whether the time is equal to or less than a critical time, and if the time is equal to or less than the critical time, processes the second write command after the time has elapsed from the time the second write command is queued.

4. 4. The controller according to claim 3, wherein if a second read command is queued in the command queue within the time period, the controller processes the queued second read command as a priority and then processes the second write command.

5. The controller of claim 3 , wherein the controller immediately processes the second write command queued in the command queue if the time exceeds the critical time.

6. The controller of claim 3 , wherein the critical time corresponds to a time required to process the second write command.

7. The operation of processing the second write command includes: a data transfer operation of transferring write data corresponding to the second write command to the non-volatile memory; and The controller of claim 3 further comprising a write perform operation that stores the write data in a region of the non-volatile memory corresponding to the second write command.

8. The controller of claim 7 , wherein the critical time corresponds to a time required for the data transfer operation.

9. 8. The controller of claim 7, wherein the critical time corresponds to a sum of a first time required for the data transfer operation and a second time required for the write performance operation.

10. the first write command includes a host write command generated by a host write request or a background write command generated by the controller without the host's involvement; The controller of claim 2 , wherein the first read command comprises a host read command generated by a read request of the host.

11. 1. A method of operating a controller configured to control operation of a non-volatile memory, comprising: analyzing a pattern of commands queued in a command queue during a first unit of time, where the commands queued in the command queue during the first unit of time include a first write command, a first read command, or both; determining a write command processing schedule based on the pattern of commands; and processing a second write command queued in the command queue during a second unit time subsequent to the first unit time according to the determined write command processing schedule; A method of operating a controller, wherein the pattern of commands includes a queuing time pattern indicating the time from when a previous command is queued to when a subsequent command is queued.

12. The step of analyzing a pattern of the command includes: determining whether the types of commands queued in the command queue are mixed; and 12. The method of claim 11, further comprising measuring a time from when the first write command is queued in the command queue to when the first read command is subsequently queued in the command queue.

13. The step of determining a write command processing schedule includes: determining whether the measured time is less than or equal to a critical time; and 13. The method of claim 12, further comprising: determining, based on a result of the determination, when to process the second write command queued in the command queue during the second unit time.

14. The step of processing the second write command according to the write command processing schedule includes:

14. The method of claim 13, further comprising: if the measured time is less than or equal to the critical time, processing the second write command after the measured time has elapsed from when the second write command is queued.

15. 15. The method of claim 14, further comprising: if a second read command is queued in the command queue within the measured time, processing the second read command and then processing the second write command.

16. The step of processing the second write command according to the write command processing schedule includes:

14. The method of claim 13, further comprising: if the measured time exceeds the critical time, processing the second write command as soon as the second write command was queued in the command queue during the second unit time.

17. A non-volatile memory; and a controller for controlling an operation of the non-volatile memory at a request of a host; The controller: determining a write command processing schedule by analyzing a pattern of commands queued in a command queuing area during a first unit of time, where the commands queued in the command queuing area during the first unit of time include a first write command, a first read command, or both; processing a second write command queued in the command queuing area during a second unit time subsequent to the first unit time according to the determined write command processing schedule; The pattern of commands includes a queuing time pattern indicating the time from when a previous command is queued to when a subsequent command is queued.

18. the non-volatile memory includes a plurality of memory chips; 20. The storage device of claim 17, wherein the command queuing area includes a plurality of command queues corresponding to each of the plurality of memory chips.

19. 20. The storage device of claim 18, wherein the controller analyzes a pattern of commands queued in each of the plurality of command queues during the first unit time to determine the write command processing schedule for each of the plurality of memory chips.

20. 20. The storage device of claim 18, wherein each of the plurality of command queues includes a normal command queue in which relatively low priority commands are queued, and a high command queue in which relatively high priority commands are queued.

21. the normal command queue is configured to queue host write commands corresponding to write requests received from the host, background write commands relating to background operations performed in the storage device without the involvement of the host, and background read commands; 21. The storage device of claim 20, wherein the high command queue is configured to queue host read commands corresponding to read requests received from the host.

22. 22. The storage device of claim 21, wherein the controller analyzes a pattern of the commands based on whether at least one type of command is mixed and queued in each of the plurality of command queues, and based on the time from when the host write command or the background write command is queued in the normal command queue to when the host read command is subsequently queued in the high command queue.

23. 23. The storage device of claim 22, wherein the controller determines whether the time is equal to or less than a critical time, and if the time is equal to or less than the critical time, processes the second write command queued in each of the plurality of command queues during the second unit time after the time has elapsed.

24. 24. The storage device according to claim 23, wherein, if the host read command is queued within the period of time, the controller processes the queued host read command with priority, and then processes the second write command.

25. 24. The storage device of claim 23, wherein the controller processes the second write command queued in each of the plurality of command queues as soon as the second write command is queued if the time exceeds the critical time.

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