Vibration Device

Abstract

To provide a vibration device that can prevent the occurrence of a deterioration in oscillation characteristic due to capacitive coupling.SOLUTION: A vibration device 1 includes: a base 2 that includes: a semiconductor substrate 20, and a through electrode 40 penetrating between a first surface 21 and a second surface of the semiconductor substrate 20; a vibration element 5 that is arranged on the first surface 21; and an external connection terminal 91 that is provided on the second surface 22 with an insulating layer 80 therebetween. An oscillation circuit 11 that is electrically connected with the vibration element 5 through the through electrode 40 and causes the vibration element 5 to oscillate to generate an oscillation signal, and an output buffer circuit 12 that outputs a clock signal based on the oscillation signal are arranged on the second surface 22. A clock signal from the output buffer circuit 12 is output from the external connection terminal 91. The through electrode 40 and the external connection terminal 91 are arranged not to overlap each other in plan view from a direction orthogonal to the first surface 21.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a vibration device and the like. [Background technology]

[0002] Conventionally, vibration devices such as oscillators have been known as devices using vibration elements. For example, Patent Document 1 discloses an oscillator in which a piezoelectric vibrating piece is mounted as a vibration element on a semiconductor substrate such as a silicon substrate on which a circuit pattern of an integrated circuit is formed, and the piezoelectric vibrating piece is sealed by the semiconductor substrate and a lid. The oscillator of Patent Document 1 has a through hole that is a through hole that connects the piezoelectric vibrating piece and the circuit pattern, and a mount electrode that serves as an external connection terminal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-214787 A Summary of the Invention [Problem to be solved by the invention]

[0004] It has been found that in vibration devices such as oscillators, problems occur such as a deterioration in the accuracy of the oscillation frequency and an increase in the noise components contained in the oscillation signal due to capacitive coupling between the through hole, which serves as the wiring electrically connecting the oscillation circuit of the integrated circuit and the vibration element, and the external connection terminal for outputting a clock signal based on the oscillation signal. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a vibration device including a semiconductor substrate having a first surface and a second surface that is opposite to the first surface, a base including a through electrode that penetrates between the first surface and the second surface, a vibration element arranged on the first surface side, and an external connection terminal provided on the second surface side via an insulating layer, wherein an oscillation circuit electrically connected to the vibration element via the through electrode and configured to oscillate the vibration element to generate an oscillation signal, and an output buffer circuit that outputs a clock signal based on the oscillation signal are arranged on the second surface, the clock signal from the output buffer circuit being output from the external connection terminal, and the through electrode and the external connection terminal are arranged so as not to overlap when viewed in a planar view from a direction perpendicular to the first surface. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a cross-sectional view showing an example of the configuration of a vibration device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view showing a specific configuration example of the vibration device according to the embodiment. [Diagram 3] FIG. 2 is a plan view showing an example of a vibration element of the vibration device. [Figure 4] FIG. 1 is a diagram showing a configuration example of an integrated circuit. [Diagram 5] FIG. 2 is a diagram showing a detailed configuration example of an integrated circuit. [Figure 6] FIG. 2 is a diagram showing a configuration example of an oscillator circuit. [Figure 7] FIG. 4 is a diagram showing a configuration example of an output buffer circuit. [Figure 8] 5A to 5C are manufacturing process diagrams showing an example of a method for manufacturing a vibration device. [Figure 9] FIG. 2 is a plan view showing an example of the arrangement of through electrodes, external connection terminals, integrated circuits, etc. [Figure 10] FIG. 4 is a plan view showing an example of the arrangement of external connection terminals. [Figure 11] FIG. 11 is a cross-sectional view showing another example of the through electrode. [Figure 12] FIG. 13 is a diagram showing another example of the configuration of an output driver of the output buffer circuit. [Figure 13] FIG. 13 is a diagram showing another example of the configuration of an output driver of the output buffer circuit. [Figure 14] FIG. 11 is a plan view showing another example of the arrangement of the external connection terminals. [Figure 15] FIG. 13 is a diagram showing another example of the configuration of the integrated circuit. [Figure 16] FIG. 11 is a plan view showing another example of the arrangement of the external connection terminals. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the contents of the claims. Not all of the configurations described in the present embodiment are essential components. In addition, in the following drawings, some components may be omitted for convenience of explanation. In addition, in each drawing, the dimensional ratio of each component is different from the actual one for ease of understanding.

[0008] 1. Vibration Device FIG. 1 is a cross-sectional view showing a configuration example of a vibration device 1 of the present embodiment. As shown in FIG. 1, the vibration device 1 of the present embodiment includes a base 2, a vibration element 5, and external connection terminals 91 and 92. The vibration device 1 may also include a lid 7 and a relocation wiring layer 8. The base 2 includes a semiconductor substrate 20 and a through electrode 40. The semiconductor substrate 20 has a first surface 21 and a second surface 22 that is opposite to the first surface 21. The first surface 21 is, for example, the upper surface of the semiconductor substrate 20, and the second surface 22 is, for example, the lower surface of the semiconductor substrate 20. The through electrode 40 is an electrode that penetrates the first surface 21 and the second surface 22 of the semiconductor substrate 20. The vibration element 5 is disposed on the first surface 21 side of the semiconductor substrate 20. For example, the vibration element 5 is disposed at a position spaced apart from the first surface 21 of the semiconductor substrate 20 by a given distance. Specifically, the vibration element 5 is fixed to the first surface 21 of the semiconductor substrate 20 via, for example, a conductive bonding member 60. The external connection terminals 91, 92 are provided via an insulating layer 80 or the like on the second surface 22 side of the semiconductor substrate 20. The insulating layer 80 is an insulating layer that constitutes the rearrangement wiring layer 8, for example.

[0009] In each figure described in this embodiment, the X-axis, Y-axis, and Z-axis are illustrated as three mutually orthogonal axes. The direction along the X-axis is called the "X-axis direction", the direction along the Y-axis is called the "Y-axis direction", and the direction along the Z-axis is called the "Z-axis direction". The tip side of the arrow in each axis direction is also called the "plus side", the base side is called the "minus side", the plus side of the Z-axis direction is called the "upper", and the minus side of the Z-axis direction is called the "lower". For example, the Z-axis direction is along the vertical direction, and the XY plane is along the horizontal plane. FIG. 1 is a cross-sectional view of the vibration device 1 as viewed from the Y-axis direction. The first surface 21 and the second surface 22 of the semiconductor substrate 20 are surfaces along the XY plane and perpendicular to the Z-axis. Note that "perpendicular" includes not only cases where the surfaces intersect at 90°, but also cases where the surfaces intersect at an angle slightly inclined from 90°.

[0010] The vibration device 1 is, for example, an oscillator. Specifically, the vibration device 1 is an oscillator such as a simple package crystal oscillator (SPXO), a voltage-controlled crystal oscillator (VCXO), a temperature-compensated crystal oscillator (TCXO), an oven-controlled crystal oscillator (OCXO), a surface acoustic wave (SAW) oscillator, a voltage-controlled SAW oscillator, or a micro electro mechanical systems (MEMS) oscillator. A MEMS oscillator can be realized by a MEMS vibration element in which a piezoelectric film and electrodes are arranged on a substrate such as a silicon substrate. However, the vibration device 1 may also be an inertial sensor such as an acceleration sensor or an angular velocity sensor, or a force sensor such as an inclination sensor.

[0011] The base 2 is composed of a semiconductor substrate 20. The semiconductor substrate 20 is, for example, a silicon substrate. However, the semiconductor substrate 20 is not limited to a silicon substrate, and may be a semiconductor substrate such as Ge, GaP, GaAs, or InP.

[0012] The base 2 also includes an integrated circuit 10. The integrated circuit 10, which is a semiconductor circuit, is formed on the second surface 22 of the semiconductor substrate 20. The integrated circuit 10 is composed of a plurality of circuit elements. The circuit elements are, for example, active elements such as transistors, or passive elements such as capacitors and resistors. Specifically, the integrated circuit 10 is composed of a plurality of circuit blocks, each of which includes a plurality of circuit elements. The integrated circuit 10 is also formed of a diffusion region, which is an impurity region formed by doping impurities into the semiconductor substrate 20, and a wiring layer in which a metal layer and an insulating layer are laminated. The diffusion region forms a source region and a drain region of a transistor, which is a circuit element of the integrated circuit 10, and the wiring region forms wiring that connects the circuit elements.

[0013] The base 2 also includes a through electrode 40. The through electrode 40 is made of a conductive material that penetrates the first surface 21 and the second surface 22 of the semiconductor substrate 20. For example, a through hole is formed in the semiconductor substrate 20, and the through hole is filled with a conductive material to form the through electrode 40. The conductive material may be a metal such as copper, or may be conductive polysilicon. Conductive polysilicon refers to polysilicon that is doped with impurities such as phosphorus (P), boron (B), and arsenic (As) to give it conductivity. If polysilicon is used as the conductive material, it is possible to realize a through electrode 40 that has sufficient resistance to heat applied in the process of forming the integrated circuit 10.

[0014] One end of the through electrode 40 is electrically connected to the vibration element 5 via a conductive bonding member 60. In FIG. 1, the conductive bonding member 60 is realized by a bump 62 having one end electrically connected to the vibration element 5 and the other end electrically connected to the through electrode 40. Specifically, the other end of the bump 62 is connected to the through electrode 40 via a terminal 64. The bump 62 is a conductive bump, specifically a metal bump. The conductive bonding member 60 may be realized by a conductive adhesive or the like.

[0015] The other end of the through electrode 40 is electrically connected to the integrated circuit 10. Specifically, the other end of the through electrode 40 is connected to a circuit element of the integrated circuit 10 via a contact pad 36 formed on the integrated circuit 10. In this manner, the vibration element 5 and the integrated circuit 10 can be electrically connected via the through electrode 40.

[0016] The lid 7 is joined to the base 2 via joining members 71 and 72. The base 2 and the lid 7, which is a cover body, form an airtight storage space SP, and the vibration element 5 is accommodated in this storage space SP. The storage space SP is hermetically sealed, and the inside of the storage space SP is, for example, in a reduced pressure state. This allows the vibration element 5 to be driven stably. Note that the state in the storage space SP is not limited to a reduced pressure state, and the inside of the storage space SP may be, for example, an inert gas atmosphere.

[0017] The relocation wiring layer 8 is provided on the second surface 22 side of the semiconductor substrate 20, and includes an insulating layer 80 and wiring 82 for relocation wiring. The insulating layer 80 is realized by a resin layer such as polyimide, and the wiring 82 is realized by a metal wiring such as copper foil. The insulating layer 80 needs to have heat resistance that can withstand soldering when mounting the resonator device 1, and it is preferable to use polyimide. The material of the wiring 82 may be a metal material such as silver other than copper. The thickness of the wiring layer and terminals in the relocation wiring layer 8 is, for example, about 50 μm. By providing the relocation wiring layer 8, it becomes possible to electrically connect the contact pads 38 and 39 formed on the integrated circuit 10 to the external connection terminals 91 and 92. Then, by mounting the external connection terminals 91 and 92 of the resonator device 1 to terminals and wiring of a circuit board or the like on which the resonator device 1 is mounted, it becomes possible to incorporate the resonator device 1 into an electronic device. Furthermore, by providing such a relocation wiring layer 8, it is possible to mechanically protect the integrated circuit 10 and thermally protect the integrated circuit 10 etc. from heat in the soldering process when mounting the resonator device 1.

[0018] Fig. 2 is a cross-sectional view showing a specific configuration example of the vibration device 1, and Fig. 3 is a plan view showing an example of a vibration element 5 of the vibration device 1. First, the vibration element 5 will be described in detail with reference to Fig. 3.

[0019] The vibration element 5 is an element that generates mechanical vibration by an electrical signal. For example, as shown in FIG. 3, the vibration element 5 has a vibration substrate 50 and an electrode arranged on the surface of the vibration substrate 50. The vibration substrate 50 has a thickness-shear vibration mode, and is formed of an AT-cut quartz substrate in this embodiment. The AT-cut quartz substrate has a third-order frequency-temperature characteristic, and therefore the vibration element 5 has excellent temperature characteristics. The electrodes include an excitation electrode 52 arranged on the upper surface of the vibration substrate 50 and an excitation electrode 53 arranged on the lower surface opposite the excitation electrode 52. The upper surface is the surface on the positive side in the Z-axis direction, and the lower surface is the surface on the negative side in the Z-axis direction. One of the excitation electrodes 52 and 53 is a first excitation electrode, and the other of the excitation electrodes 52 and 53 is a second excitation electrode. The electrodes also have a pair of terminals 56, 57 arranged on the underside of the vibration substrate 50, a wiring 54 electrically connecting the terminal 56 and the excitation electrode 52, and a wiring 55 electrically connecting the terminal 57 and the excitation electrode 53.

[0020] The configuration of the vibration element 5 is not limited to the above configuration. For example, the vibration element 5 may be a mesa type in which the vibration region sandwiched between the excitation electrodes 52 and 53 protrudes from its surroundings, or conversely, may be an inverted mesa type in which the vibration region is recessed from its surroundings. In addition, the vibration substrate 50 may be subjected to bevel processing for grinding the periphery, or convex processing for making the upper and lower surfaces convex curved. In addition, the vibration element 5 is not limited to one that vibrates in a thickness-shear vibration mode. For example, the vibration element 5 may be a tuning fork type vibration element in which multiple vibration arms flexurally vibrate in an in-plane direction, a tuning fork type vibration element in which multiple vibration arms flexurally vibrate in an out-of-plane direction, a gyro sensor element that includes a driving arm that vibrates for driving and a detection arm that vibrates for detection and detects angular velocity, or an acceleration sensor element that includes a detection unit that detects acceleration. In addition, the vibration substrate 50 is not limited to one formed from an AT-cut quartz substrate, and may be formed from a quartz substrate other than an AT-cut quartz substrate, for example, an X-cut quartz substrate, a Y-cut quartz substrate, a Z-cut quartz substrate, a BT-cut quartz substrate, an SC-cut quartz substrate, an ST-cut quartz substrate, or the like. In the present embodiment, the vibration substrate 50 is made of quartz, but is not limited thereto, and may be made of, for example, a piezoelectric single crystal such as lithium niobate, lithium tantalate, lithium tetraborate, potassium niobate, gallium phosphate, or other piezoelectric single crystal. The vibration element 5 is not limited to a piezoelectric drive type vibration element, and may be an electrostatic drive type vibration element using electrostatic force.

[0021] As shown in FIG. 2 and FIG. 3, the vibration element 5 is fixed to the first surface 21, which is the upper surface of the semiconductor substrate 20, via conductive bonding members 60 and 61. Although not shown in FIG. 2, as shown in FIG. 3, for example, two bonding members 60 and 61 are provided along the Y-axis direction. As shown in FIG. 9 described later, the semiconductor substrate 20 is provided with two through electrodes 40 and 41 along the Y-axis direction, and these through electrodes 40 and 41 are electrically connected to the vibration element 5 via conductive bonding members 60 and 61. One of the through electrodes 40 and 41 is a first through electrode, and the other of the through electrodes 40 and 41 is a second through electrode. Specifically, one end of the through electrode 40 is electrically connected to the excitation electrode 52 of the vibration element 5 via the bonding member 60, the terminal 56 of the vibration element 5, and the wiring 54. One end of the through electrode 41 is electrically connected to the excitation electrode 53 of the vibration element 5 via the bonding member 61, the terminal 57 of the vibration element 5, and the wiring 55. The other ends of the through electrodes 40, 41 are electrically connected to the integrated circuit 10. This allows the vibration element 5 and the integrated circuit 10 to be electrically connected via the through electrodes 40, 41. Specifically, the other ends of the through electrodes 40, 41 are electrically connected to the oscillation circuit 11 of the integrated circuit 10 via the contact pads 36, 37 shown in Figures 2 and 9. This allows the vibration element 5 and the oscillation circuit 11 to be electrically connected via the through electrodes 40, 41.

[0022] The bonding members 60 and 61 are not particularly limited as long as they have both electrical conductivity and bonding properties, and can be realized by various conductive bumps 62 such as gold bumps, silver bumps, copper bumps, solder bumps, and resin core bumps. Alternatively, the bonding members 60 and 61 may be conductive adhesives in which conductive fillers such as silver fillers are dispersed in various adhesives such as polyimide, epoxy, silicone, and acrylic adhesives. If the conductive bumps 62 are used as the bonding members 60 and 61, gas generation from the bonding members 60 and 61 can be suppressed, and environmental changes in the accommodation space SP, particularly an increase in pressure, can be effectively suppressed. On the other hand, if a conductive adhesive is used as the bonding members 60 and 61, the bonding members 60 and 61 are softer than the conductive bumps 62, and stress is less likely to be transmitted to the vibration element 5.

[0023] In addition, the semiconductor substrate 20 is thermally oxidized after the through holes are formed, so that an insulating layer 44, which is an insulating film made of, for example, silicon oxide (SiO2), is formed on the first surface 21 of the semiconductor substrate 20 and the inner surface of the through holes. By forming the insulating layer 44 by thermal oxidation, a dense and homogeneous insulating layer 44 can be formed on the surface of the semiconductor substrate 20. In addition, the difference in linear expansion coefficient between the insulating layer 44 and the semiconductor substrate 20 can also be reduced. Therefore, thermal stress is less likely to occur, and a resonator device 1 having excellent oscillation characteristics can be realized. The constituent material of the insulating layer 44 is not particularly limited, and may be made of, for example, silicon nitride (SiN) or resin. In addition, the method of forming the insulating layer 44 is not limited to thermal oxidation, and may be formed by, for example, CVD (Chemical Vapor Deposition).

[0024] Then, the through-holes are filled with a conductive material such as copper or conductive polysilicon inside the insulating layer 44 to form the through-holes 40, 41. That is, the through-holes are filled with a conductive material to form the through-holes 40, 41. One end of the through-holes 40, 41 is electrically connected to the vibration element 5. Specifically, one end of the through-holes 40, 41 is electrically connected to the excitation electrodes 52, 53 of the vibration element 5. Meanwhile, the other end of the through-holes 40, 41 is electrically connected to the integrated circuit 10. Specifically, the other end of the through-holes 40, 41 is electrically connected to the oscillation circuit 11 of the integrated circuit 10 via the contact pads 36, 37.

[0025] As shown in FIG. 2, the integrated circuit 10 is composed of, for example, an N-type transistor 23 and a P-type transistor 24. These transistors 23 and 24 are composed of a source region and a drain region, which are diffusion regions formed in a semiconductor substrate 20, a gate electrode, and a gate oxide film. The transistors 23 and 24 are isolated by an element isolation film 25 called LOCOS (LOCal Oxidation of Silicon). The integrated circuit 10 also includes a wiring layer 30 that realizes connection wiring between a plurality of circuit elements such as the transistors 23 and 24. For example, the wiring layer 30 in FIG. 2 includes metal layers 31 and 32 and insulating layers 33, 34, and 35. The metal layers 31 and 32 are a first metal layer and a second metal layer, respectively, and the insulating layers 33, 34, and 35 are a first insulating layer, a second insulating layer, and a third insulating layer, respectively. The metal layer 31 is formed between the insulating layer 33 and the insulating layer 34, and the metal layer 32 is formed between the insulating layer 34 and the insulating layer 35. These metal layers 31 and 32 are realized by a metal such as aluminum. A passivation film is formed by the insulating layer 35 of the top layer. The metal layers 31 and 32 are electrically connected by contacts called via contacts, and the metal layer 31 is electrically connected to the source regions and drain regions of the transistors 23 and 24 by the contacts. As shown in FIG. 2, a contact pad 36 electrically connected to the other end of the through electrodes 40 and 41 is formed by the lower metal layer 31. The contact pads 38 and 39 electrically connected to the external connection terminals 91 and 92 are formed by the upper metal layer 32. In the wiring layer 30, the layer closer to the transistors 23 and 24 in the integrated circuit 10 is the lower layer, and the layer farther from the transistors 23 and 24 is the upper layer. FIG. 2 shows a case where the wiring layer 30 has two metal layers 31 and 32, but this embodiment is not limited to this, and the wiring layer 30 may have three or more metal layers. In this case, the contact pads 36, 37 are formed from the lowest metal layer among the multiple metal layers, and the contact pads 38, 39 are formed from the highest metal layer. Also, a passivation film is formed from the highest insulating layer.

[0026] The rearrangement wiring layer 8 includes an insulating layer 80 realized by a resin layer such as polyimide, and wiring 82 realized by copper foil or the like. The contact pad 38 is electrically connected to an external connection terminal 91, and the contact pad 39 is electrically connected to the external connection terminal 92 via the wiring 82.

[0027] 2, each of the external connection terminals 91, 92 has a two-layer structure having a first metal layer 101 and a second metal layer 102. For example, a titanium tungsten layer is used as the first metal layer 101 on the polyimide insulating layer 80 side in order to improve adhesion with the polyimide. For example, a metal layer such as copper or gold is used as the second metal layer 102, which is easy to solder to external terminals and wiring.

[0028] 4 shows an example of the configuration of the integrated circuit 10. The integrated circuit 10 includes an oscillator circuit 11 and an output buffer circuit 12. The integrated circuit 10 may also include a logic circuit 13 and a power supply circuit 14.

[0029] The oscillator circuit 11 is a circuit that oscillates the vibration element 5. For example, the oscillator circuit 11 is electrically connected to the terminals TXA and TXB, and generates an oscillation signal OSC. Specifically, the oscillator circuit 11 is electrically connected to the vibration element 5 via the wiring LA, LB, and the terminals TXA and TXB, and generates the oscillation signal OSC by oscillating the vibration element 5. One of the terminals TXA and TXB is a first terminal, and the other of the terminals TXA and TXB is a second terminal. For example, the oscillator circuit 11 can be realized by a drive circuit for oscillation provided between the terminals TXA and TXB, and passive elements such as a capacitor and a resistor. The drive circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The drive circuit is a core circuit of the oscillator circuit 11, and the drive circuit drives the vibration element 5 with a voltage or current to oscillate the vibration element 5. As the oscillator circuit 11, various types of oscillation circuits such as an inverter type, a Pierce type, a Colpitts type, or a Hartley type can be used. The oscillator circuit 11 is also provided with a variable capacitance circuit, and the oscillation frequency can be adjusted by adjusting the capacitance of the variable capacitance circuit. The variable capacitance circuit can be realized by a variable capacitance element such as a varactor. Alternatively, the variable capacitance circuit may be realized by a capacitor array and a switch array connected to the capacitor array. For example, the variable capacitance circuit may be configured by a capacitor array having a plurality of capacitors whose capacitance values ​​are weighted in binary, and a switch array having a plurality of switches, each of which turns on and off the connection between each capacitor of the capacitor array and the terminal TXA or TXB. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that allows information to be transmitted by an electrical signal. The electrical connection may be a connection via an active element or the like.

[0030] The output buffer circuit 12 outputs a clock signal CK based on the oscillation signal OSC. For example, the output buffer circuit 12 buffers the oscillation signal OSC and outputs it to the terminal TCK as a clock signal CK. Then, this clock signal CK is output to the outside via the external connection terminal 91 of the vibration device 1. For example, the output buffer circuit 12 outputs the clock signal CK in a single-ended CMOS signal format. For example, when the output enable signal OE from the terminal TOE is active, the enable signal from the logic circuit 13 becomes active, and the output buffer circuit 12 outputs the clock signal CK obtained by buffering the oscillation signal OSC. On the other hand, when the output enable signal OE is inactive, the output buffer circuit 12 sets the clock signal CK to a fixed voltage level, such as a low level. This sets the voltage level of the terminal TCK to a fixed voltage level. Note that an active signal is, for example, a high level in the case of positive logic, and a low level in the case of negative logic. Also, an inactive signal is, for example, a low level in the case of positive logic, and a high level in the case of negative logic. The output buffer circuit 12 may output the clock signal CK in a signal format other than CMOS.

[0031] The logic circuit 13 is a control circuit and performs various control processes. For example, the logic circuit 13 performs overall control of the integrated circuit 10 and controls the operation sequence of the integrated circuit 10. The logic circuit 13 may also perform various processes for controlling the oscillator circuit 11 and control the power supply circuit 14. The logic circuit 13 can be realized by an ASIC (Application Specific Integrated Circuit) circuit that is automatically placed and wired, such as a gate array.

[0032] The power supply circuit 14 is supplied with a power supply voltage VDD from a terminal TVDD and with a ground voltage GND from a terminal TGND. The power supply circuit 14 supplies the power supply voltage for each internal circuit of the integrated circuit 10 to each internal circuit. The power supply circuit 14 may generate a reference voltage, a reference current, and the like used in the integrated circuit 10. For example, the power supply circuit 14 has a regulator and supplies a regulated voltage generated by the regulator to the oscillation circuit 11, the output buffer circuit 12, and the logic circuit 13. In this case, the power supply circuit 14 may have a regulator that generates a regulated voltage supplied to the oscillation circuit 11, and a regulator that generates a regulated voltage supplied to the output buffer circuit 12 and the logic circuit 13.

[0033] Fig. 5 shows a detailed configuration example of the integrated circuit 10. In Fig. 5, a temperature compensation circuit 15, a temperature sensor circuit 16, and a memory 17 are further provided.

[0034] The temperature compensation circuit 15 performs temperature compensation of the oscillation signal OSC of the oscillation circuit 11. The temperature compensation of the oscillation signal OSC is temperature compensation of the oscillation frequency of the oscillation circuit 11. The output buffer circuit 12 outputs a clock signal CK based on the temperature-compensated oscillation signal OSC. Specifically, the temperature compensation circuit 15 performs temperature compensation based on temperature detection information from the temperature sensor circuit 16. For example, the temperature compensation circuit 15 performs temperature compensation of the oscillation signal OSC of the oscillation circuit 11 by generating a temperature compensation voltage based on a temperature detection voltage from the temperature sensor circuit 16 and outputting the generated temperature compensation voltage to the oscillation circuit 11. For example, the temperature compensation circuit 15 performs temperature compensation by outputting a temperature compensation voltage to the variable capacitance circuit of the oscillation circuit 11, which becomes a capacitance control voltage of the variable capacitance circuit. In this case, the variable capacitance circuit of the oscillation circuit 11 is realized by a variable capacitance element such as a varactor. The temperature compensation is a process of suppressing and compensating for fluctuations in the oscillation frequency due to temperature fluctuations. For example, the temperature compensation circuit 15 performs analog temperature compensation by polynomial approximation. For example, when a temperature compensation voltage for compensating for the frequency-temperature characteristic of the vibration element 5 is approximated by a polynomial, the temperature compensation circuit 15 performs analog-type temperature compensation based on coefficient information of the polynomial. Analog-type temperature compensation is temperature compensation realized by, for example, adding current signals and voltage signals, which are analog signals. Specifically, the memory 17 stores coefficient information of a polynomial for temperature compensation, and the logic circuit 13 reads out this coefficient information from the memory 17 and sets it, for example, in a register of the temperature compensation circuit 15. The temperature compensation circuit 15 then performs analog-type temperature compensation based on the coefficient information set in the register.

[0035] The temperature compensation circuit 15 may perform digital temperature compensation. In this case, the temperature compensation circuit 15 is realized by, for example, a logic circuit. Specifically, the temperature compensation circuit 15 performs digital temperature compensation processing based on temperature detection data, which is temperature detection information from the temperature sensor circuit 16. For example, the temperature compensation circuit 15 obtains frequency adjustment data based on the temperature detection data. Then, the capacitance value of the variable capacitance circuit of the oscillation circuit 11 is adjusted based on the obtained frequency adjustment data, thereby achieving temperature compensation processing of the oscillation frequency of the oscillation circuit 11. In this case, the variable capacitance circuit of the oscillation circuit 11 is realized by a capacitor array having a plurality of binary-weighted capacitors and a switch array. The memory 17 also stores a lookup table indicating the correspondence between the temperature detection data and the frequency adjustment data, and the temperature compensation circuit 15 performs temperature compensation processing to obtain the frequency adjustment data from the temperature data using the lookup table read from the memory 17 by the logic circuit 13.

[0036] The temperature sensor circuit 16 is a sensor circuit that detects temperature. Specifically, the temperature sensor circuit 16 outputs a temperature-dependent voltage that changes according to the environmental temperature as a temperature detection voltage. For example, the temperature sensor circuit 16 generates the temperature detection voltage by using a circuit element having temperature dependency. Specifically, the temperature sensor circuit 16 uses the temperature dependency of the forward voltage of a PN junction to output a temperature detection voltage whose voltage value changes depending on temperature. For example, the base-emitter voltage of a bipolar transistor can be used as the forward voltage of the PN junction.

[0037] When performing digital temperature compensation processing, the temperature sensor circuit 16 measures a temperature such as an environmental temperature, and outputs the result as temperature detection data. The temperature detection data is, for example, data that monotonically increases or decreases with respect to temperature. In this case, a temperature sensor circuit that utilizes the temperature dependency of the oscillation frequency of a ring oscillator can be used as the temperature sensor circuit 16. Specifically, the temperature sensor circuit 16 includes a ring oscillator and a counter circuit. The counter circuit counts the output pulse signal, which is the oscillation signal of the ring oscillator, during a count period defined by a clock signal based on the oscillation signal OSC from the oscillation circuit 11, and outputs the count value as temperature detection data.

[0038] The memory 17 stores various information used in the integrated circuit 10. The memory 17 can be realized by, for example, a nonvolatile memory. The nonvolatile memory is an EEPROM such as a Floating gate Avalanche injection MOS (FAMOS) memory or a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) memory, but is not limited thereto and may be an OTP (One Time Programmable) memory or a fuse-type ROM. Alternatively, the memory 17 may be realized by a volatile memory such as a RAM.

[0039] The terminals TXA and TXB in FIG. 4 and FIG. 5 are realized by the contact pads 36 and 37 in FIG. 2 and FIG. 9. That is, the oscillator circuit 11 is electrically connected to the vibration element 5 through the terminals TXA and TXB realized by the contact pads 36 and 37. The terminal TCK is realized by the contact pad 38. That is, the clock signal CK from the output buffer circuit 12 is output to the outside from the external connection terminal 91 through the terminal TCK realized by the contact pad 38. The terminals TVDD and TGND are realized by the contact pads 39 and 68 in FIG. 2 and FIG. 9. That is, the power supply voltages VDD and GND are supplied to the integrated circuit 10 through the terminals TVDD and TGND realized by the contact pads 39 and 68. Specifically, VDD and GND are supplied to the power supply circuit 14. The terminal TOE is realized by the contact pad 69. That is, the output enable signal OE is input to the integrated circuit 10 through the terminal TOE realized by the contact pad 69. For example, it is input to the logic circuit 13.

[0040] FIG. 6 shows a configuration example of the oscillator circuit 11. As shown in FIG. 6, the oscillator circuit 11 includes inverter circuits DV1 and DV2 and variable capacitance circuits CV1 and CV2. The inverter circuit DV1 is a drive circuit for the vibration element 5, and an input node is connected to one end of the vibration element 5 and an output node is connected to the other end of the vibration element 5. The inverter circuit DV2 buffers the output signal of the inverter circuit DV1 and outputs it as an oscillation signal OSC. The inverter circuits DV1 and DV2 are operated by being supplied with a regulated power supply voltage VREG1 and GND. The regulated power supply voltage VREG1 is generated by a regulator included in the power supply circuit 14.

[0041] The variable capacitance circuit CV1 has one end connected to one end of the vibration element 5 and the other end connected to the GND node. The variable capacitance circuit CV2 has one end connected to the other end of the vibration element 5 and the other end connected to GND. As described above, these variable capacitance circuits CV1 and CV2 may be realized by a variable capacitance element such as a varactor whose capacitance is controlled by a capacitance control voltage that is a temperature compensation voltage, or may be realized by a circuit having a capacitor array and a switch array, whose capacitance value is controlled by frequency control data.

[0042] FIG. 7 shows a configuration example of the output buffer circuit 12. As shown in FIG. 7, the output buffer circuit 12 includes a NAND circuit NA and inverter circuits IV1, IV2, and IV3. In this way, the output buffer circuit 12 is composed of buffer circuits such as a plurality of signal inversion circuits. An oscillation signal OSC, which is an oscillation clock signal from the oscillation circuit 11, is input to a first input node of the NAND circuit NA, and an enable signal EN from the logic circuit 13 is input to a second input node. For example, when the output enable signal OE input from the terminal TOE becomes a high level, which is an active level, the enable signal EN becomes a high level, and the oscillation signal OSC is buffered by the NAND circuit NA and the inverter circuits IV1, IV2, and IV3 and output as a clock signal CK. On the other hand, when the output enable signal OE input from the terminal TOE becomes a low level, which is an inactive level, the enable signal EN becomes a low level, and the output of the output buffer circuit 12 is fixed to a low level.

[0043] Next, a method for manufacturing the vibration device 1 of this embodiment will be described below. Fig. 8 is a manufacturing process diagram showing an example of a method for manufacturing the vibration device 1.

[0044] In the integrated circuit formation process (S11), a semiconductor substrate 20 is prepared, and an integrated circuit 10 is formed on the second surface 22, which is the lower surface of the semiconductor substrate 20, as shown in Figs. 1 and 2. In the rearrangement wiring layer formation process (S12), a rearrangement wiring layer 8 having, for example, an insulating layer 80, wiring 82, external connection terminals 91, 92, etc. is formed, and contact pads 38, 39, etc. of the integrated circuit 10 are electrically connected to the external connection terminals 91, 92, etc. In the base thinning process (S13), the first surface 21, which is the mounting surface side of the vibration element 5 of the semiconductor substrate 20, is polished to thin the base 2. That is, the base 2 is thinned.

[0045] In the hole forming process (S14), a through hole is formed. Specifically, a hole is formed in the semiconductor substrate 20 by dry etching, and a hole is further formed by wet etching up to the metal layer 31, which is the first metal layer of the wiring layer 30 in FIG. 2. In the insulating layer forming process (S15), the semiconductor substrate 20 is thermally oxidized to form an insulating layer 44, which is an insulating film made of silicon oxide (SiO2) or a resin layer, on the surface of the semiconductor substrate 20, particularly on the inner surface of the through hole. In the through electrode forming process (S16), the through hole is filled with a conductive material such as copper to form the through electrodes 40, 41. In the vibration element arrangement process (S17), the vibration element 5 is prepared, and the vibration element 5 is bonded to the first surface 21 of the semiconductor substrate 20 via the bonding members 60, 61. In the lid bonding process (S18), the lid 7 is prepared, and the lid 7 is bonded to the base 2 via the bonding members 71, 72 in a reduced pressure environment. In the singulation process (S19), the vibration device 1 is singulated by a dicing saw or the like. In this manner, the vibration device 1 is obtained.

[0046] As described above, in this embodiment, a first semiconductor wafer having a plurality of bases 2 each having a vibration element 5 and an integrated circuit 10 is attached to a second semiconductor wafer having a plurality of lids 7, thereby bonding the plurality of bases 2 and the plurality of lids 7. Then, the vibration devices 1 are individually separated to manufacture a large number of vibration devices 1. For example, a small vibration device 1 having a length and width of about 1 mm to several mm and a thickness of less than 1 mm is manufactured. In this way, it is possible to realize a wafer-level package (WLP) vibration device 1, and it is possible to manufacture the vibration device 1 at a high throughput and low cost. In other words, it is possible to collectively manufacture the vibration devices 1 having the vibration elements 5 and the integrated circuits 10 by wafer-level batch processing.

[0047] 2. Positional relationship between through electrodes and external connection terminals FIG. 9 is a plan view showing an example of the arrangement of the through electrodes 40, 41, the external connection terminals 91, 92, 93, 94, the integrated circuit 10, and the like in the vibration device 1 of this embodiment. FIG. 9 shows the relationship between the arrangement positions of each circuit of the integrated circuit 10 and the arrangement positions of the through electrodes 40, 41, and the external connection terminals 91, 92, 93, 94. FIG. 9 is a plan view in a plan view of the base 2 seen from the negative side in the Z axis direction, and the outer shapes of the through electrodes 40, 41 located on the positive side of the Z axis direction with respect to the base 2 on which the integrated circuit 10 is formed and the outer shapes of the external connection terminals 91, 92, 93, 94 located on the negative side of the Z axis direction with respect to the base 2 are shown by dotted lines. FIG. 10 shows the arrangement positions of the external connection terminals 91, 92, 93, 94 on the bottom surface of the vibration device 1, and is a plan view in a plan view of the bottom surface of the vibration device 1 seen from the negative side in the Z axis direction. 9 and 10, external connection terminals 91, 92, 93, and 94 are rectangular, but these terminals do not have to be strictly rectangular, and may be shaped such that corners are chamfered, or may be shaped in a way other than rectangular. Also, Fig. 9 shows a layout in which integrated circuit 10 includes temperature compensation circuit 15, temperature sensor circuit 16, etc., but as described in Fig. 4, integrated circuit 10 may not include temperature compensation circuit 15, temperature sensor circuit 16, etc. In this case, the layout in Fig. 9 may be such that temperature compensation circuit 15, temperature sensor circuit 16, etc. are not included, and the free space is filled up.

[0048] As described above, the vibration device 1 of this embodiment includes the semiconductor substrate 20, the base 2 including the through electrodes 40 and 41 penetrating between the first surface 21 and the second surface 22 of the semiconductor substrate 20, the vibration element 5 disposed on the first surface 21 side of the semiconductor substrate 20, and the external connection terminals 91, 92, 93, and 94 provided on the second surface 22 side of the semiconductor substrate 20 via the insulating layer 80. As shown in FIG. 9, the second surface 22 of the semiconductor substrate 20 includes an oscillation circuit 11 electrically connected to the vibration element 5 via the through electrodes 40 and 41, which oscillates the vibration element 5 to generate an oscillation signal OSC, and an output buffer circuit 12 which outputs a clock signal CK based on the oscillation signal OSC. For example, the oscillation circuit 11 oscillates the vibration element 5 to generate an oscillation signal OSC, and the oscillation signal OSC is buffered by the output buffer circuit 12 and output as a clock signal CK. The clock signal CK from the output buffer circuit 12 is output from the external connection terminal 91. 4 and 5 is output from a terminal TCK realized by the contact pad 38. Since the contact pad 38 is electrically connected to the external connection terminal 91 as shown in FIGS. 1 and 2, the clock signal CK from the output buffer circuit 12 is output from the external connection terminal 91 to the outside of the resonator device 1.

[0049] 9, in the resonator device 1 of this embodiment, the through electrodes 40, 41 and the external connection terminal 91 are arranged so as not to overlap in a plan view from a direction perpendicular to the first surface 21. For example, the through electrodes 40, 41 electrically connecting the resonator element 5 and the integrated circuit 10 and the external connection terminal 91 to which the clock signal CK is output are arranged so as not to overlap in a plan view from the Z-axis direction. Thus, in this embodiment, in a WLP (Wafer Level Package) resonator device 1 including the integrated circuit 10 having the oscillation circuit 11 and the output buffer circuit 12 and the resonator element 5, the through electrodes 40, 41 electrically connecting the resonator element 5 and the oscillation circuit 11 of the integrated circuit 10 and the external connection terminal 91 for outputting the clock signal CK are arranged so as not to overlap in a plan view. In other words, the through electrodes 40, 41, which are part of the wiring electrically connected to the vibration element 5, and the external connection terminal through which an AC signal flows, such as the external connection terminal 91 for outputting the clock signal CK based on the oscillation signal OSC, are arranged so as not to overlap in a planar view, thereby reducing the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91.

[0050] For example, in this embodiment, unlike the conventional ceramic package, the vibration element 5 is directly mounted on the semiconductor substrate 20 to configure the vibration device 1, which causes the following unique problems. In the package of the small vibration device 1 by WLP, the integrated circuit 10 is formed on the second surface 22, which is the lower surface of the semiconductor substrate 20 constituting a part of the airtight package, and the through electrodes 40, 41, which are called conductive vias or through holes and are electrically connected to the vibration element 5, are formed on the semiconductor substrate 20. The through electrodes 40, 41 to which the vibration element 5 is electrically connected will have a negative effect on the oscillation characteristics such as the oscillation frequency if a terminal or electrode of an AC signal, which is an alternating current signal, is arranged nearby and capacitively coupled. Then, on the second surface 22 side of the semiconductor substrate 20 such as a silicon substrate, a thin insulating layer 80 formed of a resin layer such as polyimide is formed, and further, for example, four external connection terminals 91 to 94 are formed on the lower surface of the insulating layer 80. Here, the thickness of the insulating layer 80 is thinner than that of the semiconductor substrate 20, for example, 0.1 mm or less. As shown in FIG. 2, a thin insulating layer 44 is also formed around the through electrodes 40, 41. Unlike conventional ceramic packages, a semiconductor substrate 20 that can be a dielectric or a conductor is interposed between the through electrodes 40, 41 and the external connection terminals 91 to 94. For this reason, if the through electrodes 40, 41 and the external connection terminal 91 for outputting the clock signal CK, which is an AC signal, are arranged to overlap each other in a plan view, the capacitance coupling becomes large because they are arranged through the thin insulating layers 80, 44, etc., and this adversely affects the oscillation characteristics. That is, since the capacitance value is inversely proportional to the distance between the electrodes, the capacitance due to the thin insulating layers 80, 44 becomes large. If the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91 becomes large, the signal component of the clock signal CK at the external connection terminal 91 is transmitted as noise to the vibration element 5 or the oscillation circuit 11 through the through electrodes 40, 41, causing problems such as deterioration of the oscillation characteristics.

[0051] 9, in this embodiment, the through electrodes 40, 41 electrically connected to the vibration element 5 and the external connection terminal 91 to which the clock signal CK, which is an AC signal, are arranged so as not to overlap in a plan view. By arranging the through electrodes 40, 41 and the external connection terminal 91 so as not to overlap in a plan view in this manner, it is possible to increase the distance between the through electrodes 40, 41 and the external connection terminal 91 compared to a case in which the through electrodes 40, 41 and the external connection terminal 91 are arranged so as to overlap in a plan view. This makes it possible to reduce the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91, and effectively suppress situations such as deterioration of the oscillation characteristics of the vibration element 5.

[0052] The external connection terminals 91 to 94 of the resonator device 1 are mounted by connecting them to terminals or wiring of a circuit board or the like on which the resonator device 1 is mounted by soldering or the like. Therefore, it is preferable that the external connection terminals 91 to 94 are terminals suitable for mounting by soldering or the like, and are also required to have heat resistance and strength so as not to be damaged during mounting.

[0053] In this regard, in the above-mentioned Patent Document 1, the pads of the integrated circuit are used as the external connection terminals. For example, pads formed of the topmost metal layer of the wiring layer are used as the external connection terminals. However, the pads of the integrated circuit are not suitable for mounting by soldering or the like, and have a small area and low heat resistance and strength, so there is a risk of problems such as breakage during mounting.

[0054] In contrast, in the resonator device 1 of the present embodiment, external connection terminals 91-94 are provided on the second surface 22 side of the semiconductor substrate 20 via an insulating layer 80. That is, instead of the contact pads 38, 39, 68, and 69 of the integrated circuit 10, the external connection terminals 91-94 are provided separately from these pads and formed, for example, in the manufacturing process of the relocation wiring layer 8. Therefore, it becomes possible to use terminals suitable for mounting by soldering or the like as the external connection terminals 91-94. For example, the external connection terminals 91-94 can be made larger in area and thicker in thickness than the contact pads 38, 39, 68, and 69, and strength can be maintained. Therefore, the external connection terminals 91-94 can be easily connected to external terminals and wiring for mounting, and the occurrence of damage during mounting can be suppressed.

[0055] On the other hand, when the external connection terminals 91 to 94 have a large area, there is a risk that the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91 may become large. In this regard, in the present embodiment, the through electrodes 40, 41 and the external connection terminal 91 are arranged so as not to overlap in a plan view, so that even if the external connection terminal 91 has a large area, the deterioration of the oscillation characteristics caused by the capacitive coupling can be suppressed. Therefore, according to the present embodiment, it is possible to provide the external connection terminals 91 to 94 that are easy to mount by connecting to external terminals and wiring, have high heat resistance and strength, and are not easily damaged, while simultaneously suppressing the deterioration of the oscillation characteristics caused by the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91.

[0056] In this embodiment, as shown in Fig. 9, the base 2 has a side SD1 and a side SD2 opposite to the side SD1. The side SD1 is the first side, and the side SD2 is the second side. The base 2 also has a side SD3 and a side SD4 opposite to the side SD3. The side SD3 is the third side, and the side SD4 is the fourth side. For example, the base 2 has a rectangular shape having sides SD1, SD2, SD3, and SD4 in a plan view. Note that the rectangular shape does not need to be a strict rectangular shape, and may be a shape in which the corners are chamfered, for example.

[0057] As shown in FIG. 9, the through electrodes 40 and 41 are disposed in a position closer to the side SD1, which is the first side, than the side SD2, which is the second side, in a plan view. On the other hand, the external connection terminal 91, to which the clock signal CK is output, is disposed in a position closer to the side SD2 than the side SD1, in a plan view. For example, the center line between the side SD1 and the side SD2 is defined as CL. For example, the distance between the side SD1 and the center line CL is equal to the distance between the side SD2 and the center line CL. In this case, the through electrodes 40 and 41 are disposed in a first region, which is, for example, a region between the side SD1 and the center line CL. On the other hand, the external connection terminal 91 is disposed in a second region, which is, for example, a region between the side SD2 and the center line CL. In this way, the through electrodes 40 and 41 are disposed closer to the side SD1, and the external connection terminal 91 is disposed closer to the side SD2. Therefore, it is possible to increase the distance between the through electrodes 40 and 41 and the external connection terminal 91. This makes it possible to reduce the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91, and makes it possible to suppress the occurrence of deterioration of the oscillation characteristics of the vibration element 5, etc.

[0058] As shown in FIG. 1, FIG. 2, and FIG. 9, in this embodiment, the contact pads 36, 37 for the through electrodes electrically connected to the through electrodes 40, 41 are arranged on the second surface 22 of the semiconductor substrate 20. For example, the contact pads 36, 37 for the through electrodes are formed by the metal layer 31 of the wiring layer 30 formed by the semiconductor manufacturing process. For example, the metal layer 31 is patterned at the locations corresponding to the lower ends of the through electrodes 40, 41 to form the contact pads 36, 37 for the through electrodes. As shown in FIG. 9, the contact pads 36, 37 for the through electrodes are arranged at positions closer to the side SD1 than to the side SD2 in a plan view. For example, the contact pads 36, 37 are arranged in a first region between the side SD1 and the center line CL and electrically connected to the through electrodes 40, 41. In this way, it is possible to increase not only the distance between the through electrodes 40, 41 and the external connection terminal 91 but also the distance between the contact pads 36, 37 for the through electrodes and the external connection terminal 91. This makes it possible to reduce not only the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91, but also the capacitance of the capacitive coupling between the contact pads 36, 37 and the external connection terminal 91, thereby making it possible to suppress deterioration of the oscillation characteristics of the vibration element 5, etc.

[0059] In addition, on the second surface 22 of the semiconductor substrate 20, wirings LA and LB are arranged to electrically connect the contact pads 36 and 37 for the through electrodes and the oscillation circuit 11. As shown in FIG. 4 and FIG. 5, the wirings LA and LB are wirings that connect the oscillation circuit 11 and the terminals TXA and TXB realized by the contact pads 36 and 37. For example, the wiring LA is connected to one of the input node and the output node of the oscillation circuit 11, and the wiring LB is connected to the other node. In addition, the wirings LA and LB are formed by at least one of the metal layers 31 and 32 of the wiring layer 30 in FIG. 2. As shown in FIG. 9, the wirings LA and LB are arranged in a position closer to the side SD1 than the side SD2 in a plan view. For example, at least one of the wirings LA and LB is arranged in a position closer to the side SD1 than the side SD2. For example, the wirings LA and LB are arranged in a first region between the side SD1 and the center line CL to connect the oscillation circuit 11 and the terminals TXA and TXB realized by the contact pads 36 and 37. In this way, it is possible to increase the distance not only between the through electrodes 40, 41 and the external connection terminal 91, but also between the wirings LA, LB and the external connection terminal 91. This makes it possible to reduce not only the capacitance of the capacitive coupling between the through electrodes 40, 41 and the external connection terminal 91, but also the capacitance of the capacitive coupling between the wirings LA, LB and the external connection terminal 91, and makes it possible to suppress the occurrence of deterioration of the oscillation characteristics of the vibration element 5.

[0060] As shown in FIGS. 1 and 2, a contact pad 38 for outputting a clock signal CK is disposed on the second surface 22 of the semiconductor substrate 20. For example, as shown in FIGS. 4 and 5, the output buffer circuit 12 outputs a clock signal CK to a terminal TCK realized by the contact pad 38, and this contact pad 38 is disposed on the second surface 22 of the semiconductor substrate 20. For example, the contact pad 38 for outputting a clock signal is formed by a metal layer 32, which is, for example, the uppermost metal layer of the wiring layer 30 formed in the semiconductor manufacturing process. For example, the contact pad 38 for outputting a clock signal is formed by patterning the metal layer 32. At this time, it is desirable to expose the contact pad 38 from the passivation film, which is the uppermost insulating layer 35.

[0061] The contact pad 38 for outputting the clock signal and the external connection terminal 91 are electrically connected via an insulating layer 80. For example, an insulating layer 80 is provided between the contact pad 38 and the external connection terminal 91, and the contact pad 38 and the external connection terminal 91 are electrically connected via the insulating layer 80. Specifically, the contact pad 38 and the external connection terminal 91 are electrically connected via the insulating layer 80 constituting the relocation wiring layer 8. That is, they are electrically connected via the insulating layer 80 realized by a resin layer such as polyimide. In this way, the vibration device 1 can be connected to an external terminal or wiring using the external connection terminal 91 provided via the contact pad 38 and the insulating layer 80, rather than the contact pad 38 formed on the second surface 22 of the semiconductor substrate 20. For example, with the contact pad 38, it is difficult to realize an external connection terminal that is suitable for mounting by soldering or the like, has a large area, and is not easily damaged. For this reason, if the contact pad 38 is used as an external connection terminal, problems such as difficulty in mounting the vibration device 1 and damage to the external connection terminal may occur. In this regard, in the present embodiment, the occurrence of the above-mentioned problems can be suppressed by using the external connection terminal 91 provided separately from the contact pad 38. In addition, the distance between the external connection terminal 91 and the through electrodes 40, 41 can be increased, so that the deterioration of the oscillation characteristics can be prevented.

[0062] In this embodiment, as shown in FIGS. 1, 2, and 9, the area of ​​the external connection terminal 91 is larger than the area of ​​the contact pad 38 for outputting a clock signal. Similarly, the areas of the external connection terminals 92, 93, and 94 are also larger. The contact pad 38 has an area of, for example, about 70 μm to 100 μm on one side. The external connection terminals 91, 92, 93, and 94 have an area of, for example, about 0.19 mm or more on one side. By providing such a large-area external connection terminal 91, etc. on the bottom surface of the resonation device 1 as shown in FIG. 10, it becomes possible to facilitate the connection between the external connection terminals 91, etc. and external terminals and wiring when mounting the resonation device 1.

[0063] 1, 2, and 9, in this embodiment, the contact pad 38 for outputting a clock signal and the external connection terminal 91 are arranged to overlap in a plan view. For example, as shown in Figures 1 and 2, the external connection terminal 91 is arranged below the contact pad 38 via an insulating layer 80. The contact pad 38 and the external connection terminal 91 arranged below it are electrically connected via a via contact of the rearrangement wiring layer 8, for example.

[0064] 4 and 5 can be output to the outside via a short path through the contact pad 38 and the external connection terminal 91. This makes it possible to reduce the parasitic capacitance and parasitic resistance in the output path of the clock signal CK, and makes it possible to output a clock signal CK with good signal characteristics to the outside.

[0065] In this embodiment, as shown in FIG. 9, the oscillation circuit 11 is disposed in a position closer to the side SD1 than to the side SD2 in a plan view. For example, the oscillation circuit 11 is disposed in a first region between the side SD1 and the center line CL. Specifically, the oscillation circuit 11 is disposed between the side SD1 and the through electrodes 40 and 41 in a plan view. That is, the oscillation circuit 11 is disposed in a region between the side SD1 and a line connecting the through electrodes 40 and 41. For example, the oscillation circuit 11 is disposed along the side SD1, and disposed such that its longitudinal direction is along the side SD1. The oscillation circuit 11 is electrically connected to the vibration element 5 via the terminals TXA and TXB realized by the wirings LA and LB and the contact pads 36 and 37 disposed in the first region like the oscillation circuit 11, and causes the vibration element 5 to oscillate.

[0066] For example, circuit elements such as transistors, capacitors, and resistors constituting the oscillation circuit 11 have conductive layers such as metal layers and diffusion layers having an area in a plan view. Therefore, due to capacitive coupling between the conductive layers in the oscillation circuit 11 and the external connection terminal 91, the signal components of the clock signal CK output from the external connection terminal 91 may be transmitted to the oscillation circuit 11 as noise, which may adversely affect the oscillation characteristics. In this regard, in the present embodiment, the oscillation circuit 11 is disposed at a position close to the side SD1 in a plan view, so that it is possible to increase the distance between the oscillation circuit 11 and the external connection terminal 91 disposed at a position close to the side SD2 in a plan view. Therefore, the capacitance of the capacitive coupling between the oscillation circuit 11 and the external connection terminal 91 can be reduced, so that the occurrence of deterioration of the oscillation characteristics of the oscillation circuit 11 can be suppressed.

[0067] 9, the output buffer circuit 12 is disposed at a position closer to the side SD2 than to the side SD1 in a plan view. For example, the output buffer circuit 12 is disposed in a second region between the side SD2 and the center line CL. Specifically, the output buffer circuit 12 is disposed near a corner where the side SD2 and the side SD3 intersect.

[0068] For example, a circuit element such as a transistor constituting the output buffer circuit 12 has a conductive layer such as a metal layer or a diffusion layer having an area in a plan view. Therefore, due to capacitive coupling between the conductive layer in the output buffer circuit 12 and the through electrodes 40 and 41, the signal component of the clock signal CK in the output buffer circuit 12 may be transmitted as noise to the vibration element 5 or the oscillation circuit 11 through the through electrodes 40 and 41, which may adversely affect the oscillation characteristics. In this respect, in the present embodiment, the output buffer circuit 12 is disposed at a position close to the side SD2 in a plan view, so that it is possible to increase the distance between the output buffer circuit 12 and the through electrodes 40 and 41 disposed at a position close to the side SD1 in a plan view. Therefore, the capacitance of the capacitive coupling between the output buffer circuit 12 and the through electrodes 40 and 41 can be reduced, so that the occurrence of deterioration of the oscillation characteristics can be suppressed.

[0069] In this embodiment, the semiconductor substrate 20 includes external connection terminals 92 and 94 for constant potential signals provided on the second surface 22 side via the insulating layer 80. Here, the constant potential signal is a signal that is not an AC signal, for example, a signal whose potential does not change dynamically. The constant potential signal may be a power supply signal. For example, the external connection terminal 92 is a terminal to which a power supply voltage VDD, which is a constant potential power supply signal, is supplied. The external connection terminal 94 is a terminal to which an output enable signal OE, which is a constant potential signal fixed to a low level or a high level when the resonator device 1 is in operation, is input. As shown in FIG. 9, the through electrode 40 is arranged so as to overlap the external connection terminal 92 for the power supply voltage VDD in a plan view. The through electrode 41 is arranged so as to overlap the external connection terminal 94 for the output enable signal OE in a plan view. The external connection terminal for the constant potential signal is not limited to the external connection terminal for the power supply voltage VDD or the output enable signal OE, and may be, for example, an external connection terminal for GND.

[0070] For example, as shown in FIG. 10, the external connection terminals 91 to 94 are terminals having a large area, so that most of the area of ​​the bottom surface of the resonating device 1 is occupied by the external connection terminals 91 to 94. Therefore, if the external connection terminals 91 to 94 are arranged without any ingenuity, the through electrodes 40 and 41 and the external connection terminal 91 for outputting a clock signal may overlap in a plan view, which may cause a situation such as deterioration of oscillation characteristics. In this regard, in this embodiment, the external connection terminals 92 and 94 for a constant potential signal are arranged so as to overlap the through electrodes 40 and 41 in a plan view. If the external connection terminals 92 and 94 are arranged so as to overlap the through electrodes 40 and 41 in this way, the external connection terminal 91 for outputting a clock signal can be arranged in the remaining area of ​​the arrangement area of ​​the external connection terminals 92 and 94 among the area of ​​the bottom surface of the resonating device 1. This makes it easy to arrange the through electrodes 40 and 41 so as not to overlap with the external connection terminal 91 for outputting a clock signal in a plan view, which makes it possible to suppress the occurrence of deterioration of oscillation characteristics.

[0071] 1, in this embodiment, the vibration device 1 includes a lid 7 joined to the base 2 so as to house the vibration element 5. For example, the lid 7 is joined to the base 2 by joining members 71 and 72. By providing such a lid 7, it becomes possible to arrange the vibration element 5 in the housing space SP formed by joining the base 2 and the lid 7. For example, it becomes possible to arrange the vibration element 5 in the hermetically sealed housing space SP, and it becomes possible to suitably protect the vibration element 5 and the like from impact, dust, heat, moisture, and the like.

[0072] Here, the lid 7 can be realized by a silicon substrate, like the base 2. This makes the linear expansion coefficients of the base 2 and the lid 7 equal, suppressing the occurrence of thermal stress caused by thermal expansion, and realizing a resonator device 1 with excellent vibration characteristics. In addition, both the base 2 and the lid 7 can be formed by a semiconductor manufacturing process. Therefore, it is possible to manufacture the resonator device 1 with high precision and to reduce its size. However, the lid 7 is not limited to a silicon substrate, and may be realized by a semiconductor substrate such as Ge, GaP, GaAs, or InP.

[0073] The resonator device 1 may have a configuration that does not include the lid 7 bonded to the base 2. For example, the base 2 in which the resonator element 5 is arranged on the first surface 21 side and the integrated circuit 10 is formed on the second surface 22 may be housed in a separate package or in a container that serves as a thermostatic oven in an oven-controlled crystal oscillator (OCXO).

[0074] In FIG. 9, the direction from side SD1 to side SD2 is the first direction, and the direction from side SD3 to side SD4 is the second direction. The first direction is along the X-axis, and the second direction is along the Y-axis. The opposite direction to the first direction is the third direction, and the opposite direction to the second direction is the fourth direction. At this time, the oscillation circuit 11 is arranged on the first direction side of the side SD1, and the through electrodes 40 and 41 are arranged on the first direction side of the oscillation circuit 11. The temperature sensor circuit 16 is arranged on the second direction side of the oscillation circuit 11. The output buffer circuit 12, the logic circuit 13, the power supply circuit 14, the temperature compensation circuit 15, and the memory 17 are arranged on the first direction side of the through electrodes 40 and 41. That is, the output buffer circuit 12, the logic circuit 13, the power supply circuit 14, the temperature compensation circuit 15, and the memory 17 are arranged in the area between the through electrodes 40 and 41 and the side SD2. A temperature compensation circuit 15 is arranged on the second direction side of the output buffer circuit 12, a logic circuit 13 and a power supply circuit 14 are arranged on the second direction side of the temperature compensation circuit 15, and a memory 17 is arranged on the second direction side of the logic circuit 13.

[0075] In this embodiment, the vibration element 5 is fixed to the semiconductor substrate 20 via conductive bonding members 60 and 61, and the distance between the temperature sensor circuit 16 and, for example, the through electrode 41 is smaller than the distance between the output buffer circuit 12 and the through electrode 41. In this manner, in this embodiment, the vibration element 5 is directly fixed to the semiconductor substrate 20 via the bonding members 60 and 61, so that heat generated in the output buffer circuit 12 is more easily transmitted to the vibration element 5 than in a conventional oscillator using a ceramic package. That is, the temperature of the vibration element 5 also rises immediately due to heat generated in the output buffer circuit 12. In addition, since there is no ceramic with low thermal conductivity between the output buffer circuit 12 and the vibration element 5, heat generated in the output buffer circuit 12 is also more easily transmitted to the vibration element 5 as radiant heat. For example, since the output buffer circuit 12 is a circuit that drives an external load of the vibration device 1, a current of, for example, 10 mA or more may flow when the external load is driven, and the amount of heat generated is very large. On the other hand, since the distance between the temperature sensor circuit 16 and the through electrode 41 is small, the temperature sensor circuit 16 can immediately detect the actual temperature of the vibration element 5 that has risen due to heat generation in the output buffer circuit 12. That is, the actual temperature of the vibration element 5 is transmitted to the integrated circuit 10 via the through electrode 41 or the like, which has a high thermal conductivity, and this actual temperature can be immediately detected by the temperature sensor circuit 16, which is disposed at a short distance from the through electrode 41. For example, when the vibration device 1 is started up, the heat generated in the output buffer circuit 12 is immediately transmitted to the vibration element 5 via a short thermal conduction path, so that the actual temperature of the vibration element 5 increases, and the actual temperature of the vibration element 5 is detected by the temperature sensor circuit 16, which is disposed near the through electrode 41, via the through electrode 41 or the like. Then, the temperature compensation circuit 15 performs a temperature compensation process based on the detected temperature of the temperature sensor circuit 16, so that temperature compensation of an appropriate oscillation frequency according to the actual temperature of the vibration element 5 is performed. Therefore, it is possible to effectively suppress the occurrence of deterioration in the oscillation characteristics caused by an error between the temperature detected by the temperature sensor circuit 16 and the actual temperature of the vibration element 5.

[0076] 3. Variations Next, various modified examples of this embodiment will be described. For example, FIG. 11 shows another example of the through electrode 40. The through electrode 41 is similar, so its description will be omitted. In FIG. 11, an insulating layer 44 is formed on the inner wall of the through hole of the base 2, and a resin layer 45 is formed further inside the insulating layer 44. The through electrode 40 is formed by a metal layer formed inside the resin layer 45. Such a through electrode 40 allows the vibration element 5 and the oscillation circuit 11 of the integrated circuit 10 to be electrically connected. That is, the vibration element 5 and the contact pad 36 of the integrated circuit 10 are electrically connected by the bonding member 60 composed of the bump 62 and the through electrode 40, and the contact pad 36 is electrically connected to the oscillation circuit 11 as the terminals TXA and TXB in FIG. 4 and FIG. 5, so that the vibration element 5 and the oscillation circuit 11 are electrically connected.

[0077] The output buffer circuit 12 may output differential clock signals CK and CKX to the outside in a signal format such as LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed ​​Current Steering Logic), or differential CMOS (Complementary MOS). That is, the output buffer circuit 12 may have an output driver for LVDS, PECL, HCSL, or differential CMOS. For example, FIG. 12 shows an example of the configuration of an output driver for LVDS. This output driver has a P-type transistor for a current source that flows a drive current of 3.5 mA, P-type and N-type transistors that constitute a differential section that receives differential input signals IN and INX and outputs differential clock signals CK and CKX, and an N-type transistor provided on the VSS side. A bias voltage BSP is applied to the gate of the P-type transistor that serves as a current source. This causes a drive current of 3.5 mA to flow. FIG. 13 shows an example of the configuration of an output driver for PECL. This output driver has a P-type transistor that passes a drive current of 15.25 mA, two P-type transistors that form a differential section, and two P-type transistors that form a bias current circuit that passes a bias current of 5.7 mA to the nodes of the clock signals CK and CKX.

[0078] FIG. 14 is an example of an external connection terminal arrangement when differential clock signals CK and CKX are output as in FIG. 12 and FIG. 13. In FIG. 14, the resonator device 1 has six external connection terminals, namely, external connection terminals 91a, 91b, 92, 93, 94, and 95. The external connection terminals 91a and 91b are terminals to which the differential clock signals CK and CKX are output. The external connection terminals 92 and 93 are terminals for VDD and GND, and the external connection terminal 94 is a terminal for an output enable signal OE. The external connection terminal 95 is an NC (Non Connection) terminal. The external connection terminals 91a, 91b, 92, 93, 94, and 95 in FIG. 14 are also provided on the second surface 22 side of the semiconductor substrate 20 of the base 2 in the resonator device 1 via the insulating layer 80. The through electrodes 40 and 41 and the external connection terminals 91a and 91b for outputting the differential clock signals CK and CKX are arranged so as not to overlap each other in a plan view.

[0079] FIG. 15 shows another example of the configuration of the integrated circuit 10, which is used in, for example, a programmable voltage-controlled crystal oscillator (VCXO). In FIG. 15, a PLL circuit 18 is provided. For example, by providing a fractional-N type PLL circuit 18, clock signals CK and CKX of any frequency obtained by multiplying the frequency of the oscillation signal of the oscillation circuit 11 can be output. Also, in FIG. 15, a terminal TVC for inputting a frequency control voltage VC is provided. Furthermore, in FIG. 15, a digital interface circuit 19 is also provided. The interface circuit 19 is a circuit that performs interface processing between the vibration device 1 and an external device, and this interface circuit 19 can realize serial data transfer using a data signal SDA and a clock signal SCL. As the interface circuit 19, for example, a circuit that performs interface processing such as I2C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface) can be used. By setting the register of the logic circuit 13 using this interface circuit 19, for example, it becomes possible to set the frequencies of the clock signals CK and CKX. In FIG. 15, a temperature compensation circuit 15 for performing digital temperature compensation processing is provided in the logic circuit 13.

[0080] FIG. 16 is an example of an arrangement of external connection terminals of a resonator device 1 using the integrated circuit 10 of FIG. 15. In FIG. 16, similarly to FIG. 14, external connection terminals 91a, 91b, 92, 93, and 94 for CK, CKX, VDD, GND, and OE are provided. In FIG. 16, an external connection terminal 96 for a frequency control voltage VC, an external connection terminal 97 for a data signal SDA, and an external connection terminal 98 for a clock signal SCL are further provided, resulting in a resonator device 1 having eight external connection terminals. In this case, for example, it is desirable to arrange the external connection terminals for digital signals, such as the external connection terminal 98 for the clock signal SCL and the external connection terminal 97 for the data signal SDA, so that they do not overlap with the through electrodes 40 and 41 in a plan view. That is, the external connection terminals for digital signals, which are AC signals, and the through electrodes 40 and 41 are not overlapped with each other in a plan view. Digital signals contain many signals that are close to square waves, and square waves contain various frequency components. Therefore, if the external connection terminal to which such a digital signal is applied is placed near wiring such as the through electrodes 40 and 41 connected to the vibration element 5, it will have an adverse effect on the oscillation characteristics. For example, problems such as a shift in the oscillation frequency and a noise signal caused by the digital signal being superimposed on the oscillation signal will occur. In this regard, if the external connection terminal for the digital signal and the through electrodes 40 and 41 are not overlapped in a plan view, it is possible to prevent such problems from occurring.

[0081] As described above, the vibration device of this embodiment includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a base including a through electrode penetrating between the first surface and the second surface, a vibration element disposed on the first surface side, and an external connection terminal disposed on the second surface side via an insulating layer. Also, on the second surface, an oscillation circuit electrically connected to the vibration element via the through electrode and configured to oscillate the vibration element to generate an oscillation signal, and an output buffer circuit outputting a clock signal based on the oscillation signal are disposed. A clock signal from the output buffer circuit is output from the external connection terminal, and the through electrode and the external connection terminal are disposed so as not to overlap when viewed in a plan view perpendicular to the first surface.

[0082] Thus, the vibration device of this embodiment includes a semiconductor substrate, a base having a through electrode penetrating the semiconductor substrate, a vibration element disposed on the first surface side of the semiconductor substrate, and an external connection terminal provided on the second surface side of the semiconductor substrate via an insulating layer. An oscillation circuit and an output buffer circuit are also disposed on the second surface of the semiconductor substrate. The through electrode and the external connection terminal from which a clock signal is output are disposed so as not to overlap in a planar view. If the through electrode and the external connection terminal for outputting a clock signal are disposed so as not to overlap in a planar view in this way, it is possible to increase the distance between the through electrode and the external connection terminal compared to when they are disposed so as to overlap in a planar view. This makes it possible to reduce the capacitance of the capacitive coupling between the through electrode and the external connection terminal, and effectively suppress situations such as deterioration of the oscillation characteristics of the vibration element.

[0083] In addition, in this embodiment, the base has a first side and a second side opposite to the first side, the through electrode is positioned at a position closer to the first side than the second side in a planar view, and the external connection terminal is positioned at a position closer to the second side than the first side in a planar view.

[0084] In this way, the through electrode is positioned closer to the first side and the external connection terminal is positioned closer to the second side, making it possible to increase the distance between the through electrode and the external connection terminal and reducing the capacitance of the capacitive coupling between the through electrode and the external connection terminal.

[0085] In addition, in this embodiment, a contact pad for the through electrode electrically connected to the through electrode is arranged on the second surface, and the contact pad for the through electrode may be arranged at a position closer to the first side than the second side in a planar view.

[0086] In this way, it is possible to increase the distance between the contact pad for the through electrode and the external connection terminal, and it is also possible to reduce the capacitance of the capacitive coupling between the contact pad for the through electrode and the external connection terminal.

[0087] In this embodiment, wiring is arranged on the second surface to electrically connect the contact pad for the through electrode and the oscillator circuit, and the wiring may be arranged in a position closer to the first side than to the second side in a planar view.

[0088] In this way, it is possible to increase the distance between the wiring electrically connecting the contact pad for the through electrode and the oscillator circuit and the external connection terminal, and it is also possible to reduce the capacitance of the capacitive coupling between the wiring and the external connection terminal.

[0089] In addition, in this embodiment, a contact pad for outputting a clock signal, from which a clock signal is output, is arranged on the second surface, and the contact pad for outputting the clock signal and the external connection terminal may be electrically connected via an insulating layer.

[0090] In this way, rather than using a contact pad for outputting a clock signal formed on the second surface of the semiconductor substrate, the vibration device can be connected to an external terminal or wiring using an external connection terminal provided between the contact pad and an insulating layer.

[0091] In this embodiment, the area of ​​the external connection terminal may be larger than the area of ​​the contact pad for outputting the clock signal.

[0092] By providing the resonator device with such a large-area external connection terminal, it becomes possible to facilitate connection between the external connection terminal and external terminals or wiring when mounting the resonator device.

[0093] In this embodiment, the contact pads for outputting clock signals and the external connection terminals may be arranged to overlap each other in a plan view.

[0094] In this way, the clock signal from the output buffer circuit can be output to the outside via a short path, the contact pad, and the external connection terminal, making it possible to output a clock signal with good signal characteristics to the outside.

[0095] In this embodiment, the oscillator circuit may be disposed at a position closer to the first side than to the second side in a plan view.

[0096] In this way, by arranging the oscillator circuit close to the first side, it is possible to increase the distance between the oscillator circuit and the external connection terminal located close to the second side, thereby reducing the capacitance of the capacitive coupling between the oscillator circuit and the external connection terminal.

[0097] In this embodiment, the output buffer circuit may be disposed at a position closer to the second side than to the first side in a plan view.

[0098] In this way, by arranging the output buffer circuit close to the second side, it is possible to increase the distance between the output buffer circuit and the through electrode arranged close to the first side, thereby reducing the capacitance of the capacitive coupling between the output buffer circuit and the through electrode.

[0099] In addition, in this embodiment, the second surface side may include an external connection terminal for a constant potential signal provided via an insulating layer, and the through electrode may be arranged to overlap the external connection terminal for a constant potential signal in a planar view.

[0100] In this way, the external connection terminal for outputting a clock signal can be arranged in the remaining area of ​​the arrangement area of ​​the external connection terminal for the constant potential signal, which makes it easier to arrange the through electrodes and the external connection terminal for outputting a clock signal so that they do not overlap, thereby making it possible to suppress the occurrence of deterioration of the oscillation characteristics, etc.

[0101] This embodiment may also include a lid joined to the base to house the vibration element.

[0102] In this way, the vibration element can be disposed in the accommodation space formed by the base and the lid, so that the vibration element can be suitably protected from impact, dust, heat, moisture, and the like.

[0103] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term at any point in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configuration and operation of the vibration device are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0104] 1...vibration device, 2...base, 5...vibration element, 7...lid, 8...relocation wiring layer, 10...integrated circuit, 11...oscillating circuit, 12...output buffer circuit, 13...logic circuit, 14...power supply circuit, 15...temperature compensation circuit, 16...temperature sensor circuit, 17...memory, 18...PLL circuit, 19...interface circuit, 20...semiconductor substrate, 21...first surface, 22...second surface, 23, 24...transistor, 25...element isolation film, 30...wiring layer, 31, 32...metal layer, 33, 34, 35...insulator Edge layer, 36, 37, 38, 39...contact pads, 40, 41...through electrodes, 44...insulating layer, 45...resin layer, 50...vibration substrate, 52, 53...excitation electrodes, 54, 55...wiring, 56, 57...terminals, 60, 61...joint members, 62...bumps, 64...terminals, 68, 69...contact pads, 71, 72...joint members, 80...insulating layer, 82...wiring, 91, 91a, 91b, 92, 93, 94, 95, 96, 97, 98, 99...external connection terminals, 101...first metal layer, 102...second metal layer, CK, CKX...clock signal, CL...center line, CV1, CV2...variable capacitance circuit, DV1, DV2...inverter circuit, IV1, IV2, IV3...inverter circuit, LA, LB...wiring, NA...NAND circuit, OE...output enable signal, OSC...oscillation signal, SCL...clock signal, SD1, SD2, SD3, SD4...side, SDA...data signal, SP...accommodation space, TCK, TGND, TOE, TVC, TVDD, TXA, TXB...terminal

Claims

1. A base including a semiconductor substrate having a first surface and a second surface opposite to the first surface, and two through electrodes penetrating between the first surface and the second surface; A vibration element disposed on the first surface side; a clock signal output external connection terminal and a constant potential signal external connection terminal provided on the second surface side via an insulating layer; Including, The second surface has an oscillation circuit electrically connected to the vibration element via the two through electrodes and oscillating the vibration element to generate an oscillation signal; an output buffer circuit that outputs a clock signal based on the oscillation signal; is placed, the clock signal from the output buffer circuit is output from the clock signal output external connection terminal; In a plan view from a direction perpendicular to the first surface, the two through electrodes and the clock signal output external connection terminal are arranged so as not to overlap each other; A vibration device, characterized in that the two through electrodes and the external connection terminal for a constant potential signal are arranged to overlap each other.

2. 2. The vibrating device according to claim 1, The base is A first side and a second side opposite to the first side, The two through electrodes are In the plan view, the first side is closer to the second side, The clock signal output external connection terminal is A vibration device characterized in that, when viewed in a plan view, the vibration device is positioned closer to the second side than to the first side.

3. The vibration device according to claim 2 , The second surface has a contact pad for a through electrode electrically connected to the two through electrodes is disposed; The contact pad for the through electrode is A vibration device characterized in that, when viewed in a plan view, the vibration device is positioned closer to the first side than to the second side.

4. The vibrating device according to claim 3 , The second surface has Wiring is disposed to electrically connect the contact pad for the through electrode and the oscillation circuit, The wiring is A vibration device characterized in that, when viewed in a plan view, the vibration device is positioned closer to the first side than to the second side.

5. The vibration device according to claim 2 , The second surface has a contact pad for outputting the clock signal is disposed, A vibration device characterized in that the contact pad for outputting a clock signal and the external connection terminal for outputting a clock signal are electrically connected via the insulating layer.

6. The vibration device according to claim 5 , A vibration device, characterized in that an area of ​​the external connection terminal for outputting a clock signal is larger than an area of ​​the contact pad for outputting a clock signal.

7. 7. The vibration device according to claim 5, A vibration device characterized in that the contact pad for outputting a clock signal and the external connection terminal for outputting a clock signal are arranged so as to overlap when viewed in a plane.

8. The vibration device according to claim 2 , The oscillator circuit includes: A vibration device characterized in that, when viewed in a plan view, the vibration device is positioned closer to the first side than to the second side.

9. The vibration device according to any one of claims 2 to 8, The output buffer circuit includes: A vibration device characterized in that, when viewed in a plan view, the vibration device is positioned closer to the second side than to the first side.

10. 10. The vibration device according to claim 1 , A vibration device comprising a lid joined to the base so as to house the vibration element.

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