Electric motor control method and electric motor control device

Abstract

To maintain a dead time that is designed in motor control using a complementary PWM signal in which the dead time is inserted by software.SOLUTION: A first PWM signal that is based on a torque command value and a second PWM signal that is an inversion signal of the first PWM signal are generated as complementary PWM signals. A timer cycle that is equal to one part in an integer multiple of a carrier cycle of the complementary PWM signals is set. Raising control and falling control on the PWM signals are performed by different timer cycles. In a case where falling of the second PWM signal is set in a position within a following-stage timer cycle and a time from falling of the first PWM signal of a preceding-stage timer cycle to the end of a preceding-stage carrier cycle is shorter than a prescribed dead time, the time is subtracted from the prescribed dead time, thereby a differential time is calculated. The differential time is set as a time for the second PWM signal to rise in the following-stage timer cycle.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to an electric motor control method and an electric motor control device. [Background technology]

[0002] A technique is known in which a complementary PWM signal is generated based on a torque command value, and the output voltage of an inverter via the complementary PWM signal is used to control the drive of an electric motor (see Patent Document 1). In this case, a short-circuit prevention period (dead time) is set between the positive-phase PWM signal and the negative-phase PWM signal constituting the complementary PWM signal, to prevent short-circuiting of each phase of the inverter. This dead time can be set by hardware such as a CR circuit, but it is difficult to optimize the dead time because only a fixed value can be set for the switching element. Furthermore, it is difficult to perform high-precision control because the PWM signal has a waveform with a time constant and there is variation in parts. Therefore, it has been proposed to generate a complementary PWM signal with a dead time by a microcomputer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4509535 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, when a microcomputer generates complementary PWM signals without using hardware that provides dead time, the timing of inversion of the complementary PWM signals is calculated by software. In this case, the cycle of the timer in the microcomputer is synchronized with the carrier cycle, and two compare match registers that the timer usually has are used to execute a compare match between the voltage command value and the carrier wave twice during one cycle of the timer, thereby inverting the complementary PWM signals twice during the carrier cycle. However, when the torque command value changes suddenly between the adjacent front and rear carrier cycles, the dead time given to the complementary PWM signals in the front carrier cycle may be shorter than the dead time that is determined by design for the semiconductor element to which the complementary PWM signals are input. In this case, it is necessary to set the missing dead time in the rear carrier cycle, but it is not possible to execute a separate compare match for the missing dead time in the rear carrier cycle, i.e., to execute the inversion of the complementary PWM signals three times. This causes a problem that the desired PWM signal cannot be generated and the motor cannot be controlled.

[0005] The present invention aims to provide a motor control method and a motor control device that are capable of maintaining a dead time determined by design when controlling a motor using complementary PWM signals to which dead time is added by software. [Means for solving the problem]

[0006] According to the electric motor control method of the present invention, a complementary PWM signal is generated based on a torque command value, and a drive control of an electric motor is performed by the voltage generated based on the complementary PWM signal. In this control method, a first PWM signal based on a torque command value is generated as the complementary PWM signal, and a second PWM signal is generated that falls before a predetermined dead time from when the first PWM signal rises and rises after the predetermined dead time from when the first PWM signal falls. Also, a timer period that is an integer multiple of the carrier period of the complementary PWM signal is set, and the rising and falling of the first PWM signal are executed in mutually different timer periods, while the falling and rising of the second PWM signal are executed in mutually different timer periods. Then, in the case where an upstream timer period and a downstream timer period are adjacent to each other, where the upstream timer period is included in the upstream carrier period of a pair of adjacent carrier periods and the downstream timer period is included in the downstream carrier period of the pair of carrier periods, if the falling edge of the second PWM signal is set at a midpoint in the downstream timer period and the time from the falling edge of the first PWM signal in the upstream timer period to the end of the upstream carrier period is shorter than a predetermined dead time, the differential time is calculated by subtracting that time from the predetermined dead time, and the differential time is set as the time at which the second PWM signal rises in the downstream timer period. Effect of the Invention

[0007] According to the present invention, the timer period is repeated multiple times within the carrier period. Therefore, even if the timer of the microcomputer has two compare match registers, it is possible to perform twice as many compare matches as the number of repetitions of the timer period within the carrier period, i.e., to invert the PWM signal. Therefore, since the PWM signal can be inverted three or more times within the carrier period, it is possible to form a complementary PWM signal based on a torque command value in the latter carrier period, while adding an inversion of a second PWM signal for forming a dead time required by the complementary PWM signal in the latter carrier period. Therefore, it is possible to maintain the dead time determined by design in the control of the motor using complementary PWM signals to which dead time is added by software without the intervention of hardware. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a basic configuration of an electric motor control device for executing an electric motor control method according to the present embodiment. [Diagram 2] FIG. 2 is a circuit diagram of an inverter constituting the motor control device of the present embodiment. [Diagram 3] FIG. 3 is a block diagram of a PWM converter constituting the motor control device of this embodiment. [Figure 4] FIG. 4 is a diagram showing the relationship between the carrier period of the PWM control, the timer period, and the output waveforms of PWM1 and PWM2. [Diagram 5] FIG. 5 is a diagram showing the definition of modes of complementary PWM signals. [Figure 6] FIG. 6 is a diagram showing output patterns of complementary PWM signals at the time of mode transition. [Figure 7] FIG. 7 is a diagram showing output waveforms of normal scenes and special scenes of complementary PWM signals in each mode. [Figure 8] FIG. 8 is a control flow diagram of the PWM converter. [Figure 9] FIG. 9 is a diagram showing a first example of a mode transition of complementary PWM signals, illustrating a PWM output when transitioning from mode 5 to mode 3. In FIG. [Figure 10] FIG. 10 is a diagram showing a second example of the mode transition of the complementary PWM signals, illustrating the PWM output when transitioning from mode 1 to mode 5. In FIG. [Figure 11] FIG. 11 is a diagram showing a third example of mode transition of complementary PWM signals, illustrating PWM outputs when transitioning from mode 1 to mode 4. In FIG. [Figure 12] FIG. 12 is a diagram showing a fourth example of the mode transition of the complementary PWM signals, which illustrates a PWM output when transitioning from mode 5 to mode 1. In FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0010] [Basic configuration of motor control device] FIG. 1 is a diagram showing a basic configuration of an electric motor control device for executing an electric motor control method according to the present embodiment.

[0011] The motor control device according to the present invention is applicable to an electric vehicle having an electric motor (motor 009) that functions as a part or the whole of the drive source of the vehicle. Electric vehicles include not only electric vehicles, but also hybrid vehicles and fuel cell vehicles.

[0012] The current command value generating unit 001 generates a torque command value T * , and the d-axis current command value Id * , and the q-axis current command value Iq * Calculate.

[0013] The current vector controller 002 determines the d-axis current command value Id * , q-axis current command value Iq * , and the d-axis voltage command value Vd based on the d-axis current value Id and the q-axis current value Iq calculated by the two-phase converter 011. * , q-axis voltage command value Vq * Calculate.

[0014] The two-phase converter 011 calculates a d-axis current value Id and a q-axis current value Iq based on the output currents iu, iv, and iw from the inverter 005 detected by the current sensor 008 .

[0015] The three-phase converter 003 outputs the d-axis voltage command value Vd * , q-axis voltage command value Vq * , and the three-phase voltage command value (Vu * ,Vv * ,Vw * )

[0016] The PWM converter 004 outputs the voltage command value (Vu * ,Vv * ,Vw * ) to a PWM signal (Duu * ,Dul * ,Dvu * ,Dvl * ,Dwu * ,Dwl * )

[0017] Inverter 005 generates a PWM signal (Duu * ,Dul * ,Dvu * ,Dvl * ,Dwu * ,Dwl * ) is used to convert the output voltage Vdc of the battery 006 into three-phase AC voltages Vu, Vv, and Vw, which are output to the motor 009. The motor control device performs current feedback control of the motor 009 with the above configuration.

[0018] [Inverter] 2 is a circuit diagram of an inverter 005 constituting the motor control device of this embodiment. The inverter 005 includes a series circuit 51U in which a parallel circuit of a semiconductor element 5UU (upper arm) such as an IGBT (Insulated Gate Bipolar Transistor) and a feedback diode 52A is connected in series with a parallel circuit of a semiconductor element 5UL (lower arm) and a feedback diode 52B, and an internal circuit in which three series circuits 51V and 51W having the same configuration are connected in parallel. A smoothing capacitor 53 and a battery 006 are further connected in parallel to the inverter 005.

[0019] The connection midpoint 5MU of series circuit 51U is connected to the U-phase coil of the stator of motor 009, the connection midpoint 5MV of series circuit 51V is connected to the V-phase coil of the stator of motor 009, and the connection midpoint 5MW of series circuit 51W is connected to the W-phase coil of the stator of motor 009.

[0020] Here, when the series circuits 51U, 51V, 51W receive a PWM signal from the three-phase converter 3, they convert the direct current supplied from the battery 006 into a three-phase alternating current and output it to the motor 009.

[0021] In addition, when the motor 009 generates a regenerative current, the inverter 005 receives a PWM signal for extracting the regenerative current from the three-phase converter 3, and converts the regenerative current into a single-phase DC current and outputs it to the smoothing capacitor 53 and the battery 006.

[0022] The semiconductor element 5UU of the series circuit 51U is supplied with a PWM signal (Duu * ) is input to the semiconductor element 5UL, and a PWM signal (Dul * ) is input to the semiconductor element 5VU of the series circuit 51V. * ) is input, and the semiconductor element 5VL receives a PWM signal (Dvl * ) is input to the semiconductor element 5WU of the series circuit 51W. * ) is input to the semiconductor element 5WL, and a PWM signal (Dwl * ) is entered.

[0023] Here, when a high (e.g., 5 [V]) (high level) PWM signal is applied to the gate of each semiconductor element, the semiconductor element becomes conductive (short-circuited), and when a low (e.g., 0 [V]) (low level) PWM signal is applied, the semiconductor element becomes non-conductive.

[0024] For example, in series circuit 51U (similar to series circuit 51V and series circuit 51W), the PWM signal is output controlled so that when semiconductor element 5UU of the upper arm is in a conductive state, semiconductor element 5UL of the lower arm is in a non-conductive state, and when semiconductor element 5UL of the lower arm is in a conductive state, semiconductor element 5UU of the upper arm is in a non-conductive state, thereby avoiding the risk of semiconductor element 5UU and semiconductor element 5UL being simultaneously in a conductive state and causing a malfunction.

[0025] However, in semiconductor element 5UU and semiconductor element 5UL, the transition between the conductive state and the non-conductive state takes a certain amount of time.

[0026] Therefore, as a PWM signal, for example, the PWM signal (Duu * A PWM signal (Dul) (described later, PWM1) is input to the semiconductor element 5UL of the lower arm a predetermined time (dead time) before the time when the PWM signal (Dul) (described later, PWM2) rises from low to high. * ) (PWM2 described later) falls from high to low, and the PWM signal (Duu * The PWM signal (Dul) is generated after a certain period of time (dead time) has elapsed since the time when the PWM signal (Dul * ) is used to create a complementary PWM signal that goes from low to high (see Figure 4).

[0027] The complementary PWM signals input to the series circuits 51V and 51W are similar to those described above, although they are different in phase. * ,Dvu * ,Dwu *) is PWM1 (first PWM signal), and the PWM signal (Dul * ,Dvul * ,Dwl * ) is treated as PWM2 (the second PWM signal).

[0028] The complementary PWM signals (PWM1, PWM2) are generated in the PWM converter 004 as described above, and the inversion control (rising edge control, falling edge control) of the complementary PWM signals is also performed by the PWM converter 004.

[0029] When generating complementary PWM signals (PWM1, PWM2) using a microcontroller, the input voltage command value (Vu * ,Vv * ,Vw * ) with a carrier wave generated by a microcontroller or the like, and at that time, a dead time is added to PWM2, for example.

[0030] By the way, when generating complementary PWM signals by a microcontroller without using hardware that adds dead time, the inversion timing of the complementary PWM signals is calculated by software. In this case, the period of the timer in the microcontroller is synchronized with the carrier period, and the voltage command value (Vu * ,Vv * ,Vw * ) and the carrier wave twice, the complementary PWM signal can be inverted twice during the carrier period. However, the torque command value T *In cases such as when the voltage level suddenly changes, the dead time given to the PWM signal in the preceding carrier cycle may become shorter than the dead time (predetermined dead time (Td), for example 5 ms) that is determined by design for the semiconductor element to which the complementary PWM signal is input. In this case, it is necessary to set the missing dead time in the subsequent carrier cycle, but it is not possible to execute a separate compare match for the missing dead time in the subsequent carrier cycle, i.e., to execute the inversion of the PWM signal three times. This causes a problem in that the desired PWM signal cannot be generated, making it impossible to control the motor.

[0031] However, in this embodiment, the PWM converter 004 that generates the PWM signal has the following configuration, thereby maintaining the dead time determined by design and executing appropriate PWM control.

[0032] [PWM converter] As shown in FIG. 3, the PWM converter 004 includes a duty ratio command value calculation unit 41, a first PWM signal generation unit 42, a second PWM signal generation unit 43, and a determination unit 44.

[0033] The duty ratio command value calculation means 41 calculates the torque command value T * The voltage command value (Vu * ,Vv * ,Vw * ) with a carrier wave, which is a high-frequency triangular wave, to calculate a duty ratio command value for the PWM signal, and output the duty ratio command value to the first PWM signal generating unit 42 (first compare match value calculating means 421). Note that the duty ratio command value calculating means 41 may be integrated with the determining means 44.

[0034] The first PWM signal generating unit 42 includes a first compare match value calculating means 421 , a first timer 422 , a first compare match value setting means 423 , a first compare match register 424 , a second compare match register 425 , and a first PWM signal output means 426 .

[0035] The first timer 422 counts up, for example, with zero as an initial value, and when the count value reaches a full count (upper limit count value) (TMmax described later), the count value is reset and counts up again. The timer period of the first timer 422 is set to half the period of the carrier wave (carrier period) (it may be an integer multiple of the period). That is, the first timer 422 counts up (or down) in the first and second timer periods in the same carrier period. Note that the first PWM signal generating unit 42 and the second PWM signal generating unit 43 are configured to recognize negative values ​​and count values ​​higher than the upper limit count value as the count value.

[0036] The first timer 422 outputs the count value to the first compare match register 424 and the second compare match register 425, and outputs a carry signal indicating that a full count has been reached (or a signal indicating that the count value has been reset) to the first compare match value setting means 423.

[0037] The first compare match value calculation means 421 calculates or sets a first compare match value A which is the count number of the rising timing of PWM1 in the first timer cycle, a second compare match value A which is the count number of the falling timing of PWM1 in the first timer cycle, and a first compare match value B which is the count number of the rising timing of PWM1 in the second timer cycle, and a second compare match value B which is the count number of the falling timing of PWM1, based on the first command signal input from the judgment means 44, and outputs these compare match values ​​to the first compare match value setting means 423.

[0038] The first compare match value calculation means 421 calculates the first compare match value A and the second compare match value B based on the duty ratio command value input from the duty ratio command value calculation means 41, and sets the second compare match value A and the first compare match value B to a value that is the upper limit count value of the first timer 422 + 1 (a count value outside the count range of the first timer 422, same below).

[0039] However, when the first command signal includes a second count value, which will be described later, the first compare match value calculation means 421 sets the second count value as the first compare match value A.

[0040] Furthermore, when the first command signal includes a differential count value described below, the first compare match value calculation means 421 calculates the second compare match value B by adding a count value representing the timing at which PWM1 falls, which is calculated based on the duty ratio command value, to a count value obtained by subtracting the differential count value from a predetermined count value corresponding to a predetermined dead time.

[0041] In addition, when the calculated or set first compare match value B becomes the upper limit count number of the first timer 422 and the second compare match value A in the next timer period becomes zero (PWM1 rises and falls like a delta function), or when the first compare match value A in the next timer period becomes zero (a signal to rise PWM1 is output twice in a row), the first compare match value calculation means 421 sets the first compare match value B to a value that becomes the upper limit count number + 1 (a count value outside the count range of the first timer 422, same below).

[0042] Similarly, the first compare match value calculation means 421 sets the second compare match value B to a value that is the upper limit count number + 1 when the calculated or set second compare match value B becomes the upper limit count number of the first timer 422 and the first compare match value A in the next timer period becomes zero (PWM1 falls and rises in a delta function manner) or when the second compare match value A in the next timer period becomes zero (a signal that falls PWM1 is output two consecutive times).

[0043] The first compare match value setting means 423 receives the first compare match value A, the second compare match value A, the first compare match value B, and the second compare match value B from the first compare match value calculation means 421 .

[0044] When a carry signal is input from the first timer 422 at the end of the previous (previous) carrier period, the first compare match value setting means 423 outputs the first compare match value A to the first compare match register 424 and outputs the second compare match value A to the second compare match register 425.

[0045] In addition, when a carry signal is input from the first timer 422 in the current (later) carrier period, the first compare match value setting means 423 outputs the first compare match value B to the first compare match register 424 and outputs the second compare match value B to the second compare match register 425.

[0046] The first compare match value A and the first compare match value B are alternately input to the first compare match register 424, and the later input compare match value overwrites the earlier input compare match value.

[0047] The first compare match register 424 outputs a first signal to the first PWM signal output means 426 when the count value input from the first timer 422 matches the first compare match value (first compare match value A, first compare match value B).

[0048] In addition, if the first compare match value is a count value outside the count range of the first timer 422, for example a negative value or a value higher than the upper limit count value, the first compare match register 424 will not output the first signal because the count number and the first compare match value will not match, and the second compare match register 425, third compare match register 434, and fourth compare match register 435 described below also operate in a similar manner.

[0049] The second compare match value A and the second compare match value B are alternately input to the second compare match register 425, and the later input compare match value overwrites the earlier input second compare match value.

[0050] The second compare match register 425 outputs a second signal to the first PWM signal output means 426 when the count value input from the first timer 422 matches the second compare match value (second compare match value A, second compare match value B).

[0051] The first PWM signal output means 426 raises PWM1 when the first signal is input, i.e., sets the output of PWM1 from low to high. Also, the first PWM signal output means 426 lowers PWM1 when the second signal is input, i.e., sets the output of PWM1 from high to low.

[0052] The second PWM signal generating unit 43 includes a second compare match value calculating means 431 , a second timer 432 , a second compare match value setting means 433 , a third compare match register 434 , a fourth compare match register 435 , and a second PWM signal output means 436 .

[0053] The second timer 432 has the same timer period as the first timer 422, and is reset and reaches a full count at the same timing.

[0054] The second timer 432 outputs the count value to the third compare match register 434 and the fourth compare match register 435, and outputs a carry signal indicating that a full count has been reached (or a signal indicating that the count value has been reset) to the second compare match value setting means 433.

[0055] The second compare match value calculation means 431 calculates a third compare match value A which is the count number of the falling timing of PWM2 in the first timer cycle, a fourth compare match value A which is the count number of the rising timing of PWM2 in the first timer cycle, a third compare match value B which is the count number of the falling timing of PWM2 in the second timer cycle, and a fourth compare match value B which is the count number of the rising timing of PWM2 in the second timer cycle, and outputs these compare match values ​​to the second compare match value setting means 433.

[0056] The second compare match value calculation means 431 calculates a third compare match value A by subtracting a predetermined count value corresponding to a predetermined dead time (Td) from the first compare match value A input from the first compare match value calculation means 421.

[0057] In addition, the second compare match value calculation means 431 calculates a fourth compare match value B by adding a predetermined count value corresponding to a predetermined dead time (Td) to the second compare match value B input from the first compare match value calculation means 421.

[0058] Furthermore, the fourth compare match value A and the third compare match value B are set to a value that is the upper limit count value of the second timer 432+1 (a count value outside the count range of the second timer 432, the same applies below).

[0059] However, when the second command signal includes a first count value, which will be described later, the second compare match value calculation means 431 sets the first count value as the fourth compare match value A.

[0060] In addition, when the calculated or set fourth compare match value B becomes the upper limit count number of the second timer 432 and the third compare match value A in the next timer period becomes zero (PWM2 rises and falls like a delta function), or when the fourth compare match value A in the next timer period becomes zero (a signal to rise PWM2 is output twice in a row), the second compare match value calculation means 431 sets the fourth compare match value B to a value that becomes the upper limit count number + 1 (a count value outside the count range of the second timer 432, same below).

[0061] Similarly, the second compare match value calculation means 431 sets the third compare match value B to a value that is the upper limit count number + 1 when the calculated or set third compare match value B becomes the upper limit count number of the second timer 432 and the fourth compare match value A in the next timer period becomes zero (PWM2 falls and rises in a delta function manner) or when the third compare match value A in the next timer period becomes zero (a signal that falls PWM2 is output twice in a row).

[0062] The second compare match value setting means 433 receives the third compare match value A, the fourth compare match value A, the third compare match value B, and the fourth compare match value B from the second compare match value calculation means 431.

[0063] When a carry signal is input from the second timer 432 at the end of the previous (previous) carrier period, the second compare match value setting means 433 outputs a third compare match value A to the third compare match register 434 and outputs a fourth compare match value A to the fourth compare match register 435.

[0064] In addition, when a carry signal is input from the second timer 432 in the current (later) carrier period, the second compare match value setting means 433 outputs a third compare match value B to the third compare match register 434, and outputs a fourth compare match value B to the fourth compare match register 435.

[0065] The third compare match value A and the third compare match value B are alternately input to the third compare match register 434, and the later input compare match value overwrites the earlier input compare match value.

[0066] The third compare match register 434 outputs a third signal to the second PWM signal output means 436 when the count value input from the second timer 432 matches the third compare match value (third compare match value A, third compare match value B).

[0067] The fourth compare match value A and the fourth compare match value B are alternately input to the fourth compare match register 435, and the later input compare match value overwrites the earlier input compare match value.

[0068] The fourth compare match register 435 outputs a fourth signal to the second PWM signal output means 436 when the count value input from the second timer 432 matches the fourth compare match value (fourth compare match value A, fourth compare match value B).

[0069] The second PWM signal output means 436, when the third signal is input, causes PWM2 to fall, i.e., sets the output of PWM2 from high to low, and when the fourth signal is input, causes PWM2 to rise, i.e., sets the output of PWM2 from low to high.

[0070] The determination means 44 outputs a first command signal to the first compare match value calculation means 421 to cause the first compare match value calculation means 421 to calculate and set the first compare match value and the second compare match value. In addition, the determination means 44 outputs a second command signal to the second compare match value calculation means 431 to cause the second compare match value calculation means 431 to calculate and set the third compare match value and the fourth compare match value.

[0071] In addition, the determination means 44 compares the mode of the complementary PWM signal in the preceding carrier cycle with the mode of the complementary PWM signal in the following carrier cycle in a pair of adjacent carrier cycles, as described below, and executes control via the first command signal and the second command signal to maintain a dead time determined by design in the complementary PWM signals, as described below.

[0072] [Relationship between the carrier period, timer period, and output waveforms of PWM1 and PWM2] FIG. 4 is a diagram showing the relationship between the carrier period of the PWM control, the timer period, and the output waveforms of PWM1 and PWM2.

[0073] As shown in FIG. 4, the duty ratio command value calculation means 41 (DUTY) calculates the duty ratio command value D by comparing the voltage command value with the carrier wave of the carrier period T0. * [%] is calculated.

[0074] The first timer 422 (TIMER1) and the second timer 432 (TIMER2) each have an upper limit count value TMmax, and a timer period of T0 / 2.

[0075] When the value of the specified dead time (Td) converted into Duty is Dd [%], in the first timer period of the carrier cycle, the first compare match value A (UCM1a), second compare match value A (UCM0a), third compare match value A (LCM0a), and fourth compare match value A (LCM1a) are calculated as follows.

number

[0076] In the second timer period of the carrier period, the first compare match value B (UCM1b), the second compare match value B (UCM0b), the third compare match value B (LCM0b), and the fourth compare match value B (LCM1b) are calculated as follows.

number

[0077] TMmax+1 in Equation 1 means that the compare match is not performed, that is, the output level of PWM1 is maintained. Similarly, TMmax+1 in Equation 2 means that the compare match is not performed, that is, the output level of PWM2 is maintained.

[0078] Therefore, as shown in Figure 4, PWM1 rises from low to high (inverts) due to the first compare match value A (UCM1a) set in the first timer period, and falls from high to low (inverts) due to the second compare match value B (UCM0b) set in the second timer period.

[0079] Similarly, PWM2 falls from high to low (inverts) due to the third compare match value A (LCM0a) set in the first timer period, and rises from low to high (inverts) due to the fourth compare match value B (LCM1b) set in the second timer period.

[0080] Here, the carrier period T0 is 200 [μs], the timer frequency is 100 [MHz], the predetermined dead time (Td) is 5 [μs], and the duty ratio command value is 50 [%]. In this case, the values ​​of TMmax, Dd, and formula 1 and formula 2 are as follows.

number

[0081] As described above, the timer period can be set to an integer multiple of the carry period. In this case, the above compare match is executed in the timer period that includes the timing at which PWM1 and PWM2 are inverted, and each compare match value is set to, for example, TMmax+1 in the timer period that does not include the timing, that is, the compare match is not executed.

[0082] [Complementary PWM signal mode] Fig. 5 is a diagram showing the definition of the modes of the complementary PWM signals. Fig. 6 is a diagram showing the output pattern at the time of the transition of the mode of the complementary PWM signals. Fig. 7 is a diagram showing the output waveform of the normal scene and the output waveform of the special scene of each mode of the complementary PWM signals. As shown in Fig. 5, in this embodiment, the modes of the complementary PWM signals are classified into five types.

[0083] In mode 1, the duty ratio command values ​​of PWM1 and PWM2 are both 0%. The output of PWM1 is set low and the output of PWM2 is set high throughout the entire carrier period (T0) (see the normal scene of mode 1 in FIG. 7).

[0084] In mode 2, the duty ratio command value of PWM1 is 0[%], and the duty ratio command value of PWM2 is (Td / T0)×100[%] or less based on the specified dead time (Td). PWM1 is set to low throughout the entire carrier period, and PWM2 is set to low only in the center for a width of Td×2 or less, but is set to high in other parts (see the normal scene of mode 2 in Figure 7).

[0085] In mode 3, the duty ratio command value of PWM1 is higher than 0[%] and lower than ((100-Td) / T0)×100[%], and the duty ratio command value of PWM2 is higher than (Td / T0)×100[%] and lower than 100[%]. PWM1 is set high in the center of the carrier cycle for a width based on the duty ratio command value, and is set low in the other parts. PWM2 is set low in the center of the carrier cycle for a width wider than the width of the high part of PWM1 by Td×2, and is set high in the other parts (see the normal scene of mode 3 in FIG. 7).

[0086] In mode 4, the duty ratio command value of PWM1 is equal to or greater than ((100-Td) / T0)×100[%] and less than 100[%], and the duty ratio command value of PWM2 is 100[%]. PWM1 is set to low within the width of Td at both ends of the carrier period, and is set to high in other parts. PWM2 is set to low for the entire carrier period (normal scene of mode 4 in Figure 7).

[0087] In mode 5, the duty ratio command values ​​of PWM1 and PWM2 are both 100% and the output of PWM1 is set high and the output of PWM2 is set low throughout the entire carrier period (normal scene of mode 5 in FIG. 7).

[0088] As shown in FIG. 6, in a pair of adjacent carrier periods, a dead time shortage may occur when a complementary PWM mode transition occurs between the preceding carrier period and the following carrier period.

[0089] Consider a case where the complementary PWM mode in the previous carrier cycle is mode 5, and the complementary PWM mode in the next carrier cycle transitions to mode 1, mode 2, or mode 3. In this case, at the boundary between the previous carrier cycle and the next carrier cycle, PWM1 falls from high to low, and PWM2 rises from low to high. Therefore, there is insufficient dead time for PWM2 after PWM1 inverts to low.

[0090] For this reason, in this embodiment, a predetermined dead time (Td) is set as the time when PWM2 rises in the first timer cycle of the subsequent carrier cycle.

[0091] Specifically, when the judgment means 44 judges the above-mentioned mode transition, it outputs a predetermined count value related to a predetermined dead time (Td) to the second compare match value calculation means 431, and the second compare match value calculation means 431 sets the predetermined count value as the fourth compare match value A.

[0092] This allows the output of PWM2 to be kept low until a predetermined dead time (Td) has elapsed since the start of the first timer cycle in the subsequent carrier cycle (see the special scenes of Modes 1, 2, and 3 in Figure 7).

[0093] Consider a case where the complementary PWM mode in the preceding carrier cycle is mode 4, and the complementary PWM mode in the following carrier cycle transitions to mode 1, mode 2, or mode 3. In this case, PWM2 rises in the first timer cycle of the following carrier cycle before a predetermined dead time (Td) has elapsed since PWM1 fell in the second timer cycle of the preceding carrier cycle, resulting in insufficient dead time for PWM2.

[0094] For this reason, this embodiment (determination means 44) controls PWM2 of the first timer cycle of the subsequent carrier cycle to rise a predetermined dead time (Td) after PWM1 of the second timer cycle of the previous carrier cycle falls.

[0095] Specifically, when the determination means 44 determines the above-mentioned mode transition, it calculates the time from when PWM1 of the previous carrier cycle falls to when the previous carrier cycle ends based on the duty ratio command value related to the previous carrier cycle, and subtracts this time from a predetermined dead time (Td) to calculate a first differential time.

[0096] Then, the determination means 44 outputs a first count value corresponding to the first difference time to the second compare match value calculation means 431, and the second compare match value calculation means 431 sets the first count value as the fourth compare match value A.

[0097] This allows the output of PWM2 to be kept low until the first differential time has elapsed since the start of the first timer cycle in the latter carrier cycle (see the special scenes of modes 1, 2, and 3 in FIG. 7). Note that the maximum value of the first count value is the above-mentioned predetermined count value, and mode 5 can be regarded as a part of mode 4.

[0098] In particular, when the complementary PWM mode of the preceding carrier cycle is mode 4 or mode 5 and the complementary PWM mode of the following carrier cycle transitions to mode 2 or mode 3, PWM2 will invert three times during the carrier cycle. For example, when the timer cycle and the carrier cycle are the same and there are two compare match registers for one PWM signal, the number of compare matches that can be executed during the carrier cycle is two, so PWM control corresponding to the special scenes of modes 2 and 3 in FIG. 7 cannot be realized.

[0099] However, in this embodiment, by setting the timer period to half the carrier period, two timer periods are set during the carrier period, and different compare match values ​​are set in the first timer period and the second timer period to execute the compare match respectively. Therefore, one PWM signal can be inverted up to four times during the carrier period, thereby realizing PWM control that can respond to special scenes such as those described above.

[0100] Consider a case where the complementary PWM mode of the previous carrier cycle is mode 1, mode 2, or mode 3, and the complementary PWM mode of the next carrier cycle transitions to mode 5. In this case, at the boundary between the previous carrier cycle and the next carrier cycle, PWM1 rises from low to high, and PWM2 falls from high to low. Therefore, there is a shortage of dead time required for PWM1 after PWM2 inverts to low.

[0101] For this reason, in this embodiment, a predetermined dead time (Td) is set as the time when PWM1 rises in the first timer cycle of the subsequent carrier cycle.

[0102] Specifically, when the judgment means 44 judges the above-mentioned mode transition, it outputs a predetermined count value corresponding to a predetermined dead time (Td) to the first compare match value calculation means 421, and the first compare match value calculation means 421 sets the predetermined count value (second count value) as the first compare match value A.

[0103] This makes it possible to maintain the output of PWM1 low until a predetermined dead time (Td) has elapsed since the start of the first timer cycle in the latter carrier cycle (see the special scene of mode 5 in FIG. 7).

[0104] Consider a case where the complementary PWM mode in the preceding carrier cycle is mode 1, mode 2, or mode 3, and the complementary PWM mode in the following carrier cycle transitions to mode 4. In this case, PWM1 rises in the first timer cycle of the following carrier cycle before a predetermined dead time (Td) has elapsed since PWM2 fell in the second timer cycle of the preceding carrier cycle, resulting in insufficient dead time for PWM1.

[0105] For this reason, in this embodiment, a predetermined dead time (Td) during which PWM1 remains low in the first timer cycle in the latter carrier cycle is set, and the falling time of PWM1 is delayed by the amount of the shift in the rising time of PWM1.

[0106] Specifically, when the judgment means 44 judges the above-mentioned mode transition, it outputs a predetermined count value corresponding to a predetermined dead time (Td) to the first compare match value calculation means 421, and the first compare match value calculation means 421 sets the predetermined count value as the first compare match value A.

[0107] In addition, the first compare match value calculation means 421 calculates a second differential time by subtracting the time from the start of the subsequent carrier cycle to the rise of PWM1 in the first timer cycle from a predetermined dead time (Td) based on the duty ratio setting value of the subsequent carrier cycle, and calculates a third count value equivalent to the second differential time.

[0108] Then, the first compare match value calculation means 421 calculates a second compare match value B by adding the third count value to a count value corresponding to the time when PWM1 falls, which is calculated based on the duty ratio command value, and outputs the second compare match value B to the first compare match register 424 (special scene of mode 4 in Figure 7).

[0109] This makes it possible to secure the dead time without changing the duty ratio of PWM1, thereby ensuring the accuracy of PWM control.

[0110] On the other hand, if the mode of the complementary PWM in the preceding carrier cycle is mode 1, mode 2, or mode 3, and the mode of the complementary PWM in the following carrier cycle transitions to mode 1, mode 2, or mode 3, no shortage of dead time occurs (see normal 1 in FIG. 6). Similarly, if the mode of the complementary PWM in the preceding carrier cycle is mode 4 or mode 5, and the mode of the complementary PWM in the following carrier cycle transitions to mode 4 or mode 5, no shortage of dead time occurs (see normal 2 in FIG. 6).

[0111] [Control Flow] 8 is a control flow diagram of the PWM converter 004. The control flow of the PWM converter 004 (particularly the determination means 44) of this embodiment will be described.

[0112] In step S101 , the determination means 44 determines the complementary PWM mode of the subsequent carrier cycle based on the duty ratio command value input from the duty ratio command value calculation means 41 .

[0113] In step S102, the judgment means 44 compares the complementary PWM mode of the previous carrier cycle with the complementary PWM mode of the next carrier cycle to judge whether the transition from the complementary PWM of the previous carrier cycle to the complementary PWM of the next carrier cycle is normal (no state of insufficient dead time occurs) (see FIG. 6). If the answer is YES, the process proceeds to step S103, and if the answer is NO, the process proceeds to step S104.

[0114] In step S103, the determination means 44 outputs a first command signal (no second count value, no difference count value) to the first compare match value calculation means 421, and outputs a second command signal (no first count value) to the second compare match value calculation means 431. As a result, the first compare match value calculation means 421 and the second compare match value calculation means 431 calculate and output normal complementary PWM signals according to the above formulas 1 and 2.

[0115] In step S104, the decision means 44 decides whether or not the output of the PWM (PWM2) needs to be inverted three times (see FIG. 6), and if YES, the process proceeds to step S105, and if NO, the process proceeds to step S106.

[0116] In step S105, the determination means 44 determines that the mode of the complementary PWM signals in the preceding carrier cycle is mode 4 or mode 5, and that the mode of the complementary PWM signals in the following carrier cycle is mode 2 or mode 3. Therefore, the determination means 44 outputs a first command signal (no second count value, no difference count value) to the first compare match value calculation means 421, and outputs a second command signal (with first count value) to the second compare match value calculation means 431. As a result, the second compare match value calculation means 431 sets the first count value as the fourth compare match value A, thereby calculating and outputting three-times inversion complementary PWM signals.

[0117] Here, the fourth compare match value A and the third compare match value A are compared and matched in the first timer period of the latter carrier period, and the fourth compare match value B is compared and matched in the second timer period, causing PWM2 to invert three times.

[0118] If the time (difference time) from when PWM1 falls in the second timer period of the previous carrier period to when the previous carrier period ends is converted into a duty factor of Dd_z1, the first compare match value A (UCM1a), second compare match value A (UCM0a), third compare match value A (LCM0a), and fourth compare match value A (LCM1a) in the first timer period of the subsequent carrier period will be as follows:

number

[0119] Here, 0≦Dd_z1≦Dd, and when the mode of the complementary PWM of the preceding carrier cycle is mode 5, Dd_z1 becomes zero.

[0120] Also, when LCM1a=TMmax+1, a compare match using the fourth compare match value (LCM1a) is not executed. This is the case when, after PWM1 falls in the second timer cycle of the previous carrier cycle, PWM2 is kept low for a predetermined dead time (Td), and the time to request the rise of PWM2 in the first timer cycle of the subsequent carrier cycle is later than the time when PWM2 falls in the first timer cycle of the subsequent carrier cycle.

[0121] In step S105, if the fourth compare match value B of the second timer cycle of the previous carrier cycle is TMmax, the decision means 44 adds one count to it and sets it to TMmax+1. This makes it possible to avoid a state in which PWM2 rises at the same time as the end of the previous carrier cycle, resulting in insufficient dead time.

[0122] The first compare match value B (UCM1b), second compare match value B (UCM0b), third compare match value B (LCM0b), and fourth compare match value B (LCM1b) in the second timer period of the latter carrier period are as follows:

number

[0123] In step S106, the decision means 44 decides whether or not the dead time is insufficient when PWM2 in the subsequent timer cycle is started (see FIG. 6), and if YES, the process proceeds to step S107, and if NO, the process proceeds to step S108.

[0124] In step S107, the determination means 44 determines that the dead time is insufficient at the start of PWM2 in the subsequent timer cycle. That is, the determination means 44 determines that the mode of the complementary PWM signals in the preceding carrier cycle is mode 4 or mode 5, and that the mode of the complementary PWM signals in the subsequent carrier cycle is mode 1.

[0125] Therefore, the judgment means 44 calculates a first count value (TMmax*(Dd-Dd_z1)*(1 / 100)) by subtracting the difference obtained by subtracting the second compare match value B set in the previous timer period from the upper limit counter value from a predetermined count value corresponding to the predetermined dead time, and outputs a second command signal including the first count value to the second compare match value calculation means 431, and the second compare match value calculation means 431 sets the first count value as the fourth compare match value A.

[0126] At this time, the first compare match value A (UCM1a), second compare match value A (UCM0a), third compare match value A (LCM0a), and fourth compare match value A (LCM1a) in the first timer period of the subsequent carrier period are as follows, and the dead time required until the start-up of PWM2 in the subsequent carrier period is calculated and set.

number

[0127] When the complementary PWM mode of the subsequent carrier cycle is mode 1, the third compare match value (LCM0a) of the first timer cycle of the subsequent timer cycle is set to TMmax+1.

[0128] In addition, the first compare match value B (UCM1b), second compare match value B (UCM0b), third compare match value B (LCM0b), and fourth compare match value B (LCM1b) in the second timer period of the latter carrier period are as follows.

number

[0129] When the mode of the complementary PWM signal in the subsequent carrier cycle is mode 1, mode 4, or mode 5, the fourth compare match value (LCM1b) in the second timer cycle in the subsequent carrier cycle is TMmax+1.

[0130] In step S108, the determination means 44 determines that there is insufficient dead time when PWM1 rises in the subsequent timer cycle. That is, the determination means 44 determines that the mode of the complementary PWM signals in the preceding carrier cycle is either mode 1, mode 2, or mode 3, and that the mode of the complementary PWM signals in the subsequent carrier cycle is mode 4 or mode 5. In this case, PWM1 is low and PWM2 is high at the end of the second timer cycle in the preceding carrier cycle. Then, PWM1 rises before the dead time (Td) has elapsed since the start of the first timer cycle in the subsequent carrier cycle.

[0131] Therefore, if the time from when PWM2 in the previous carrier cycle falls to when the previous carrier cycle ends is converted into a duty ratio Dd_z2, the determination means 44 calculates a difference count value equivalent to Dd-Dd_z2.

[0132] Then, the determination means 44 outputs a first command signal including the difference count value to the first compare match value calculation means 421.

[0133] The first compare match value calculation means 421 sets the difference count value as the first compare match value A. The first compare match value calculation means 421 also subtracts a count value calculated based on the duty ratio command value of the subsequent carrier cycle at the timing when PWM1 rises in the first timer cycle of the subsequent carrier cycle from the difference count value to obtain a third count value TMmax*((Dd-Dd_z2)-(100-D * Calculate 1 / 100 (1 / 2).

[0134] Then, the first compare match value calculation means 421 sets as the second compare match value B the count value calculated based on the duty ratio command value of the subsequent carrier cycle at the timing when PWM1 falls in the second timer cycle of the subsequent carrier cycle, plus the third count value.

[0135] At this time, the first compare match value A (UCM1a), second compare match value A (UCM0a), third compare match value A (LCM0a), and fourth compare match value A (LCM1a) in the first timer period of the subsequent carrier period are as follows, and the dead time required until the start-up of PWM1 in the subsequent carrier period is calculated and set.

number

[0136] When the mode of the complementary PWM signal in the preceding carrier cycle is mode 4 or mode 5, Dd_z2 becomes zero.

[0137] The first compare match value B (UCM1b), second compare match value B (UCM0b), third compare match value B (LCM0b), and fourth compare match value B (LCM1b) in the 12th timer period of the latter carrier period are as follows, and the third compare match value B is corrected based on the third count value.

number

[0138] Regarding Equation 9 (UCM0b), when the mode of the complementary PWM signal of the subsequent carrier cycle is mode 5, the value is equal to or greater than TMmax+1, but is set to TMmax+1.

[0139] In addition, when the mode of the complementary PWM signal of the subsequent carrier cycle is mode 4 and the value of Equation 9 (UCM0b) is equal to or less than TMmax, the rising time and falling time of PWM1 are set to TMmax*((Dd-Dd_z2)-((100-D * ) / 2))(1 / 100) of the time will be delayed.

[0140] [Example of complementary PWM signal transitions] FIG. 9 is a diagram showing a first example of a mode transition of complementary PWM signals, illustrating a PWM output when transitioning from mode 5 to mode 3. In FIG.

[0141] As shown in FIG. 9, each compare match value in the first timer period of the previous carrier period is expressed as D * =100[%]. That is, the first compare match value A (UCM1a) is set to zero, the second compare match value A (UCM0a) is set to TMmax+1, the third compare match value A (LCM0a) is set to zero, and the fourth compare match value A (LCM1a) is set to TMmax+1. Note that the third compare match value A (LCM0a) is a negative value according to Equation 1, but is set to zero for convenience.

[0142] Each compare match value in the second timer period of the previous carrier period is D * = 100. That is, the first compare match value B (UCM1b) is set to TMmax+1, the second compare match value B (UCM0b) is set to TMmax+1, the third compare match value B (LCM0b) is set to TMmax+1, and the fourth compare match value B (LCM1b) is set to TMmax(+1).

[0143] Here, the fourth compare match value B (LCM1b) is originally TMmax, but in step S104 of Fig. 8, it is determined that it will invert three times (there is insufficient dead time when PWM2 rises in the subsequent carrier cycle), so one count is added and it is set to TMmax+1. The second compare match value B (LCM1b) is also originally TMmax, but since the second compare match value A (UCM0a) of the first timer cycle of the subsequent carrier cycle is set to zero, and a signal to fall PWM1 is output two times in succession, it is set to TMmax+1. Note that similar settings may be made in the following content as well, but explanations will be omitted unless necessary.

[0144] Each compare match value in the first timer cycle of the subsequent carrier cycle is calculated and set based on Equation 4. That is, the first compare match value A(UCM1a) is set based on Equation 4(UCM1a), the second compare match value A(UCM0a) is set to zero, the third compare match value A(LCM0a) is set based on Equation 4(LCM0a), and the fourth compare match value A(LCM1a) is set based on Equation 4(LCM1a=LCM1a_temp) and Equation 4(LCM1a_temp, Dd_z1=0).

[0145] Each compare match value in the second timer cycle of the latter carrier cycle is calculated and set based on Formula 5. That is, the first compare match value B(UCM1b) is set to TMmax+1, the second compare match value B(UCM0b) is set based on Formula 5(UCM0b), the third compare match value B(LCM0b) is set to TMmax+1, and the fourth compare match value B(LCM1b) is set based on Formula 5(LCM1b).

[0146] According to the first example shown in FIG. 9, when the complementary PWM signals transition from the previous carrier cycle to the next carrier cycle, PWM1 inverts from high to low, but PWM2 does not invert from low to high immediately, but inverts from low to high after a predetermined dead time (Td) has elapsed, so that a dead time can be secured between when PWM1 falls and when PWM2 rises.

[0147] In the latter carrier cycle, PWM2 needs to be inverted three times. However, in this embodiment, the timer cycle is set to half the carrier cycle, and count-up can be performed twice in the carrier cycle. Therefore, even when the first compare match register 424 and the second compare match register 425 are assigned to the first timer 422 as described above, PWM2 can be inverted up to four times, and different compare match values ​​can be set in the first timer cycle and the second timer cycle to perform compare matches. Therefore, even in the special case shown in FIG. 9, even without implementing hardware for setting the dead time, it is possible to reliably set a predetermined dead time (Td) from when PWM1 falls to when PWM2 rises, and it is possible to form a complementary PWM signal in the latter carrier cycle. When LCM1a (LCM1a_temp) shown in FIG. 9 is calculated under the same conditions as in Equation 3, it becomes 500 [count] because Dd=5 [%].

[0148] FIG. 10 is a diagram showing a second example of the mode transition of the complementary PWM signals, illustrating the PWM output when transitioning from mode 1 to mode 5. In FIG.

[0149] As shown in FIG. 10, each compare match value in the first timer period of the previous carrier period is expressed as D * = 0. That is, the first compare match value A (UCM1a) is set to TMmax+1, the second compare match value A (UCM0a) is set to zero, the third compare match value A (LCM0a) is set to TMmax+1 zero, and the fourth compare match value A (LCM1a) is set to zero.

[0150] Each compare match value in the second timer period of the previous carrier period is D *= 0. That is, the first compare match value B (UCM1b) is set to TMmax(+1), the second compare match value B (UCM0b) is set to TMmax+1, the third compare match value B (LCM0b) is set to TMmax(+1), and the fourth compare match value B (LCM1b) is set to TMmax+1.

[0151] Here, the first compare match value B (UCM1b) is originally TMmax, but in steps S106 and S108 of FIG. 8, it is determined that there is insufficient dead time at the start-up of PWM1 in the subsequent carrier cycle, so one count is added and the value is set to TMmax+1.

[0152] Each compare match value in the first timer period of the subsequent carrier period is calculated by Equation 8. That is, the first compare match value A(UCM1a) is set based on Equation 8(UCM1a), the second compare match value A(UCM0a) is set to TMmax+1, the third compare match value A(LCM0a) is set to zero, and the fourth compare match value A(LCM1a) is set to TMmax+1.

[0153] The compare match value in the second timer period of the latter carrier period is expressed as D in Equation 9. * = 100. That is, the first compare match value B (UCM1b) is set to TMmax+1, the second compare match value B (UCM0b) is set to TMmax (one count may be added), the third compare match value B (LCM0b) is set to TMmax+1, and the fourth compare match value B (LCM1b) is set to TMmax+1.

[0154] According to the second example shown in Fig. 10, PWM1 is set to low and PWM2 is set to high in the previous carrier cycle. Also, PWM2 is inverted from high to low at the boundary between the previous carrier cycle and the next carrier cycle. However, by setting as above, PWM1 does not rise immediately at the boundary, but is inverted to rise to high after a predetermined dead time (Td) has elapsed, so that the dead time from when PWM2 falls to when PWM1 rises can be secured.

[0155] 11 is a diagram showing a third example of the mode transition of complementary PWM signals, which illustrates the PWM output when transitioning from mode 1 to mode 4. Each compare match value of the preceding carrier cycle is the same as that shown in FIG.

[0156] The compare match value in the first timer period of the subsequent carrier period is expressed as Dd_z2=0, 95[%]≦D * <100[%]. That is, the first compare match value A (UCM1a) is set based on Equation 8 (UCM1a), the second compare match value A (UCM0a) is set to TMmax+1, the third compare match value A (LCM0a) is set to zero, and the fourth compare match value A (LCM1a) is set to TMmax+1.

[0157] The compare match value in the second timer period of the latter carrier period is expressed as Dd_z2=0, 95[%]≦D in Equation 9. * <100[%]. That is, the first compare match value B (UCM1b) is set to TMmax+1, the second compare match value B (UCM0b) is set based on Equation 9 (UCM0b), the third compare match value B (LCM0b) is set to TMmax+1, and the fourth compare match value B (LCM1b) is set to TMmax+1.

[0158] For example, as in Equation 3, the carrier period is 200 [μm], the timer frequency is 100 [MHz], and Dd = 5 [%].* = 96[%], the first compare match value A is 500[count] (the value determined by the duty ratio is 400[count]), the second compare match value A is 10001[count], the third compare match value A is 10001[count], and the fourth compare match value A is 10001[count]. The first compare match value B is 10001[count], the third compare match value is 10001[count], and the fourth compare match value B is 10001[count]. The second compare match value B is 9600 (value determined by the duty ratio command value) + 100 (third count value) = 9700[count].

[0159] The third example shown in FIG. 11 has the same effect as the second example. Furthermore, according to the third example, the first compare match value (UCM1a) of the first timer period of the latter carrier period is set to a value smaller than the third count value (TMmax*((Dd-Dd_z2)-((100-D * ) / 2))*(1 / 100)) has been added (time delayed). Therefore, the second compare match value B of the second timer cycle of the latter carrier cycle is set to the count value calculated based on the duty ratio command value plus the third count value. This maintains the duty ratio of PWM1, ensuring the accuracy of PWM control.

[0160] In addition, the control of adding the third count value to the count value calculated based on the duty ratio command value may be omitted for the second compare match value B of the second timer cycle of the latter carrier cycle. In addition, in the case where the third count value is omitted, Dd_z2 is set to 3[%], and D * = 99[%], the first compare match value A is 500 (count number determined by Dd) - 300 (count number determined by Dd_z2) = 200 [count] (the value determined by the duty ratio is 100 [count]), and the second compare match value B is 9900 [count].

[0161] 12 is a diagram showing a fourth example of the mode transition of complementary PWM signals, which illustrates the PWM output when transitioning from mode 5 to mode 1. Each compare match value in the preceding carrier cycle is the same as in the case shown in FIG.

[0162] As shown in FIG. 12, each compare match value in the first timer cycle of the latter carrier cycle is Dd_z1=0, D * = 0. That is, the first compare match value A (UCM1a) is set to TMmax+1, the second compare match value A (UCM0a) is set to zero, the third compare match value A (LCM0a) is set to, for example, TMmax+1, and the fourth compare match value A (LCM1a) is set based on Equation 6 (LCM1a).

[0163] Each compare match value in the second timer period of the latter carrier period is D * = 0. That is, the first compare match value B (UCM1b) is set to TMmax+1, the second compare match value B (UCM0b) is set to zero, the third compare match value B (LCM0b) is set to TMmax+1, and the fourth compare match value B (LCM1b) is set to TMmax+1.

[0164] According to the fourth example shown in FIG. 12, when the complementary PWM signals transition from the previous carrier cycle to the next carrier cycle, PWM1 inverts from high to low, but PWM2 does not invert from low to high immediately, but inverts from low to high after a predetermined dead time (Td) has elapsed, so that a dead time can be secured between when PWM1 falls and when PWM2 rises.

[0165] [Effects of this embodiment] According to the motor control method of the present embodiment, the torque command value (T * In a motor control method, a complementary PWM signal is generated based on a torque command value (T *a first PWM signal (PWM1) based on a first PWM signal (PWM1) and a second PWM signal (PWM2) that falls before a predetermined dead time (Td) from when the first PWM signal (PWM1) rises and rises after the predetermined dead time (Td) from when the first PWM signal (PWM1) falls; a timer period that is an integer multiple of a carrier period (T0) of the complementary PWM signals is set; the rising of the first PWM signal (PWM1) and the falling of the first PWM signal (PWM1) are executed in mutually different timer periods, while the falling of the second PWM signal (PWM2) and the rising of the second PWM signal (PWM2) are executed in mutually different timer periods; ), and the latter timer period is included in the latter carrier period (T0) of the pair of carrier periods (T0), if the falling edge of the second PWM signal (PWM2) is set in the middle of the latter timer period and the time (Dd_z1) from the falling edge of the first PWM signal (PWM1) in the former timer period to the end of the former carrier period (T0) is shorter than a predetermined dead time (Td(Dd)), then the differential time (first count value: TMmax*(Dd-Dd_z1)(1 / 100)) is calculated by subtracting that time from the predetermined dead time (T0), and the differential time (first count value: TMmax*(Dd-Dd_z1)(1 / 100)) is set as the time at which the second PWM signal (PWM2) rises in the latter timer period.

[0166] According to the motor control device of this embodiment, the torque command value (T * In a motor control device, a complementary PWM signal is generated based on a torque command value (T *a first PWM signal generating unit 42 that generates a first PWM signal (PWM1) which is one of the complementary PWM signals based on the first PWM signal (PWM2), a second PWM signal generating unit 43 that generates a second PWM signal (PWM2) which is the other of the complementary PWM signals and falls before a predetermined dead time (Td) from when the first PWM signal (PWM1) rises and rises after a predetermined dead time (Td) from when the first PWM signal (PWM2) falls, and a determination means 44 that determines the states of the first PWM signal (PWM1) and the second PWM signal (PWM2). The first PWM signal generating unit 42 includes a first timer 422 having a timer period set to an integer multiple of the carrier period (T0) of the complementary PWM signal, and executes the rising edge of the first PWM signal (PWM1) and the falling edge of the first PWM signal (PWM1) in mutually different timer periods. The determining means 44 determines whether a timer period of a previous stage and a timer period of a subsequent stage adjacent to each other is included in the previous carrier period (T0) of a pair of adjacent carrier periods (T0) and whether the timer period of the subsequent stage is included in the pair of carrier periods (T0). When the second PWM signal generation unit 43 calculates the difference time (first count value: TMmax*(Dd-Dd_z1)(1 / 100)) by subtracting the time from the falling edge of the first PWM signal (PWM1) in the previous timer cycle to the end of the previous carrier cycle (T0), if the falling edge of the second PWM signal (PWM2) is set in the middle of the previous timer cycle and the time from the falling edge of the first PWM signal (PWM1) in the previous timer cycle to the end of the previous carrier cycle (T0) is shorter than the predetermined dead time (Td), the second PWM signal generation unit 43 calculates the difference time (first count value: TMmax*(Dd-Dd_z1)(1 / 100)) by subtracting the time from the predetermined dead time (Td). The timer 422 includes a second timer 432 having a timer period set in synchronization with the timer 422, and the falling edge of the second PWM signal (PWM2) and the rising edge of the second PWM signal (PWM2) are executed in different timer periods. When the determination means 44 calculates the differential time (first count value: TMmax*(Dd-Dd_z1)(1 / 100)), the differential time (first count value: TMmax*(Dd-Dd_z1)(1 / 100)) is set as the time at which the second PWM signal (PWM2) rises in the subsequent timer period.

[0167] According to the motor control method or motor control device of this embodiment, the timer period is repeated multiple times within the carrier period. Therefore, even if the timer of the microcomputer has two compare match registers, it is possible to perform compare matches twice as many times as the number of timer period repetitions within the carrier period, i.e., to invert the PWM signal. Therefore, since the PWM signal can be inverted three or more times within the carrier period, the torque command value (T * ), while forming a complementary PWM signal based on the first carrier cycle, it is possible to add an inversion of a second PWM signal (PWM2) for forming a dead time required by the complementary PWM signal of the subsequent carrier cycle. Therefore, in the control of an electric motor using complementary PWM signals to which dead time is added by software without the intervention of hardware, it is possible to maintain the dead time determined by design (predetermined dead time (Td)).

[0168] In the electric motor control method of the present embodiment, a first compare match is executed using a first timer 422 that counts in a first timer period and a second timer period in the carrier period (T0) by synchronizing with the carrier period (T0) with a timer period that is half the carrier period (T0), and a second compare match is executed using a second timer 432 that counts in a first timer period and a second timer period in the carrier period (T0) by synchronizing with the first timer 422, and a torque command value (T *), a first compare match value which is a count value at the timing when the first PWM signal (PWM1) rises and a second compare match value which is a count value at the timing when the first PWM signal falls are calculated based on the first compare match value, and when the count value of the first timer 422 matches the first compare match value, the first PWM signal (PWM1) is set to a high level, and when the count value of the first timer 422 matches the second compare match value, the first PWM signal (PWM1) is set to a low level whose voltage is lower than the high level, and A compare match is executed using a first compare match value in a timer period, a compare match is executed using a second compare match value in a second timer period of a carrier period, and in the second compare match, a value obtained by subtracting a count value (predetermined count value) related to a predetermined dead time (Td) from the first compare match value is calculated as a third compare match value, and a value obtained by adding a count value (predetermined count value) related to the predetermined dead time (Td) to the second compare match value is calculated as a fourth compare match value. a second PWM signal (PWM2) set to a low level when the count value of the second timer 432 matches a third compare match value, a second PWM signal (PWM2) set to a high level when the count value of the second timer 432 matches a fourth compare match value, a compare match is executed based on the third compare match value in a first timer period of the carrier period, and a compare match is executed based on the fourth compare match value in a second timer period of the carrier period, and a timer period of a preceding stage and a timer period of a succeeding stage adjacent to each other, When the second timer period is included in the previous carrier period (T0) of a pair of adjacent carrier periods (T0), and the latter timer period is included in the latter carrier period (T0) of the pair of carrier periods (T0), if a compare match based on the third compare match value is set in the middle of the latter timer period, and the difference obtained by subtracting the second compare match value set in the previous timer period from the upper limit count value of the first timer 422 and the second timer 432 is lower than the count value (predetermined count value) related to the predetermined dead time (Td),The difference is subtracted from the count value (predetermined count value) related to the predetermined dead time (Td) to calculate a difference count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)), and when the difference count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)) is calculated in the second compare match, a compare match is executed in the subsequent timer period with the difference count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)) as the fourth compare match value.

[0169] In the electric motor control device of this embodiment, the first PWM signal generating unit 42 includes a first timer 422 that counts in a first timer period and a second timer period in the carrier period (T0) by synchronizing with the carrier period (T0) with a timer period that is half the carrier period (T0), a first compare match register 424 that generates a first signal when the count value of the first timer 422 matches a first compare match value, a second compare match register 425 that generates a second signal when the count value of the first timer 422 matches a second compare match value, a first PWM signal output means 426 that sets a first PWM signal (PWM1) to a high level when receiving the first signal and sets the first PWM signal (PWM1) to a low level that is lower in voltage than the high level when receiving the second signal, and a torque command value (T *a first compare match value calculation means 421 for calculating a first compare match value which is a count value at a timing when the first PWM signal (PWM1) rises and a second compare match value which is a count value at a timing when the first PWM signal (PWM1) falls based on the carrier period (T0); and a first compare match value setting means for setting a first compare match value A in a first compare match register 424 in a first timer period of a carrier period (T0) and setting a second compare match value B in a second compare match register 425 in a second timer period of the carrier period (T0). The second PWM signal generating unit 43 includes a second timer 432 that is synchronized with the first timer 422 to count in a first timer period and a second timer period in a carrier period, a third compare match register 434 that generates a third signal when the count value of the second timer 432 matches a third compare match value, a fourth compare match register 435 that generates a fourth signal when the count value of the second timer 432 matches a fourth compare match value, and a fourth compare match register 435 that sets the second PWM signal (PWM2) to a low level when the third signal is received and generates a fourth signal when the fourth compare match value is received. a second PWM signal output means 436 for setting a second PWM signal (PWM2) to a high level when the second PWM signal is received; a second compare match value calculation means 431 for calculating a third compare match value by subtracting a count value (predetermined count value) relating to a predetermined dead time (Td) from the first compare match value and for calculating a fourth compare match value by adding the count value (predetermined count value) relating to the predetermined dead time to the second compare match value; and a third compare match register 434 for setting the third compare match value in a first timer period of a carrier period (T0) and calculating a fourth compare match value. and a second compare match value setting means 433 for setting a fourth compare match value in a fourth compare match register 435 in a second timer period of a first carrier period (T0), and a determination means 44 for determining whether a first timer period is included in the first carrier period (T0) of a pair of adjacent carrier periods (T0) and whether a second timer period is included in the second carrier period (T0) of the pair of adjacent carrier periods (T0), and a third compare match value A is set in a middle position of the second timer period;Furthermore, if the difference obtained by subtracting the second compare match value B set in the previous timer period from the upper limit count value (TMmax) of the first timer 422 and the second timer 432 is lower than the count value (predetermined count value) related to the predetermined dead time (Td), the difference is subtracted from the count value (predetermined count value) related to the predetermined dead time (Td) to calculate a difference count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)), and if the determination means 44 calculates the difference count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)), the second compare match value setting means 433 sets the difference count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)) as the fourth compare match value A in the fourth compare match register 435 in the subsequent timer period.

[0170] The above method and configuration make it possible to invert the PWM signal three times in the carrier period by using two timers with a timer period that is half the carrier period and two compare match registers assigned to each timer, and to maintain the dead time determined by design (predetermined dead time (Td)) in control of an electric motor using complementary PWM signals to which dead time has been added by software without the use of hardware.

[0171] In the motor control method of this embodiment, when a compare match using a first compare match value is executed in the first timer period of a carrier period (T0), a compare match using a second compare match value is not executed in that timer period, and when a compare match using a second compare match value is executed in the second timer period of a carrier period (T0), a compare match using the first compare match value is not executed in that timer period.

[0172] In the motor control device of this embodiment, when the first compare match value setting means 423 sets the first compare match value A in the first compare match register 424 in the first timer period of the carrier period (T0), it sets a count value (e.g., TMmax+1) outside the count range of the first timer 422 in the second compare match register 425 in that timer period, and when the first compare match value B in the second compare match register 425 in the second timer period of the carrier period (T0), it sets a count value (e.g., TMmax+1) outside the count range of the first timer 422 in the first compare match register 424 in that timer period.

[0173] With the above method and configuration, it is possible to reliably execute only a compare match based on the first compare match value in the first timer period within a carrier period, and to reliably execute only a compare match based on the second compare match value in the second timer period within the carrier period.

[0174] In the motor control method of this embodiment, if a compare match using the third compare match value is executed in the first timer period of the carrier period (T0), a compare match using the fourth compare match value is not executed in that timer period, and if a compare match using the fourth compare match value is executed in the second timer period of the carrier period (T0), a compare match using the third compare match value is not executed, and when the differential count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)) is calculated, a compare match is executed in the first timer period of the carrier period (T0) with the differential count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)) as the fourth compare match value.

[0175] In the motor control device of this embodiment, when the third compare match value A is set in the third compare match register 434 in the first timer period of the carrier period (T0), the second compare match value setting means 433 sets a count value (for example, TMmax+1) outside the count range of the second timer 432 in the fourth compare match register 435 in that timer period, and when the fourth compare match value B is set in the fourth compare match register 435 in the second timer period of the carrier period (T0), the second compare match value setting means 433 sets a count value (for example, TMmax+1) outside the count range of the second timer 432 in that timer period. A count value (e.g., TMmax+1) outside the count range of the second timer 432 is set in the third compare match register 434 during a period, and when the judgment means 44 calculates the difference count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)), the difference count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)) is set in the fourth compare match register 435 as the fourth compare match value A during the first timer period of the carrier period (T0).

[0176] With the above method and configuration, it is possible to reliably execute only a compare match based on the third compare match value in the first timer period within a carrier period, and to reliably execute only a compare match based on the fourth compare match value in the second timer period within the carrier period. Even in the first timer period within a carrier period, if the difference count value (first count value: TMmax*(Dd-Dd_z1)*(1 / 100)) is calculated, the compare match based on the fourth compare match value is not canceled, and a compare match based on the difference count value can be executed.

[0177] Although the embodiments of the present invention have been described above, the above-mentioned embodiments merely show some of the application examples of the present invention, and the technical scope of the present invention is not limited to the specific configurations of the above-mentioned embodiments. In addition, the above-mentioned embodiments can be appropriately combined. [Explanation of symbols]

[0178] 42 first PWM signal generating unit, 421 first compare match value calculating means, 422 first timer, 423 first compare match value setting means, 424 first compare match register, 425 second compare match register, 43 second PWM signal generating unit, 431 second compare match value calculating means, 432 second timer, 433 second compare match value setting means, 434 third compare match register, 435 fourth compare match register, 44 determination means

Claims

1. 1. A motor control method for generating complementary PWM signals based on a torque command value and controlling a drive of a motor using voltages generated based on the complementary PWM signals, comprising: generating, as the complementary PWM signals, a first PWM signal based on the torque command value, and generating a second PWM signal that falls before a predetermined dead time from when the first PWM signal rises and rises after the predetermined dead time from when the first PWM signal falls; a timer period is set to an integer multiple of a carrier period of the complementary PWM signals, and the rising edge of the first PWM signal and the falling edge of the first PWM signal are executed in the timer periods different from each other, while the falling edge of the second PWM signal and the rising edge of the second PWM signal are executed in the timer periods different from each other, a first timer period and a second timer period that are adjacent to each other, the first timer period being included in the first carrier period of a pair of adjacent carrier periods and the second timer period being included in the second carrier period of the pair of carrier periods, and when a falling edge of the second PWM signal is set at a midpoint of the second timer period and a time from when the first PWM signal in the first timer period falls to when the carrier period of the first carrier period ends is shorter than a predetermined dead time, the method for controlling an electric motor calculates a difference time by subtracting the time from the predetermined dead time and sets the difference time as a time when the second PWM signal rises in the second timer period.

2. a first compare match using a first timer that is synchronized with the carrier cycle with the timer cycle being half the carrier cycle, thereby counting in a first timer cycle and a second timer cycle in the carrier cycle; a second compare match is executed using a second timer that is synchronized with the first timer to count in a first timer period and a second timer period in the carrier period, In the first compare match, calculating a first compare match value that is a count value at a timing when the first PWM signal rises and a second compare match value that is a count value at a timing when the first PWM signal falls based on the torque command value; When the count value of the first timer matches the first compare match value, the first PWM signal is set to a high level. setting the first PWM signal to a low level that is lower in voltage than the high level when the count value of the first timer matches the second compare match value; executing a compare match using the first compare match value in a first timer period of the carrier period, and executing a compare match using the second compare match value in a second timer period of the carrier period; In the second compare match, calculating a third compare match value by subtracting the count value related to the predetermined dead time from the first compare match value, and calculating a fourth compare match value by adding the count value related to the predetermined dead time to the second compare match value; setting the second PWM signal to the low level when the count value of the second timer matches the third compare match value; setting the second PWM signal to the high level when the count value of the second timer matches the fourth compare match value; executing a compare match using the third compare match value in a first timer period of the carrier period, and executing a compare match using the fourth compare match value in a second timer period of the carrier period; when the timer period of an earlier stage and the timer period of a later stage are adjacent to each other, the timer period of the earlier stage being included in the carrier period of an earlier stage of a pair of carrier periods adjacent to each other, and the timer period of the later stage being included in the carrier period of the later stage of the pair of carrier periods, if a compare match is set in the middle of the timer period of the later stage using the third compare match value, and if a difference obtained by subtracting the second compare match value set in the timer period of the earlier stage from the upper limit count values ​​of the first timer and the second timer is lower than a count value related to the specified dead time, a difference count value is calculated by subtracting the difference from the count value related to the specified dead time, 2. The motor control method according to claim 1, wherein when the difference count value is calculated in the second compare match, a compare match is executed in a subsequent timer period in which the difference count value is set as the fourth compare match value.

3. 3. The motor control method of claim 2, wherein when a compare match using the first compare match value is executed in the first timer period of the carrier period, a compare match using the second compare match value is not executed in that timer period, and when a compare match using the second compare match value is executed in the second timer period of the carrier period, a compare match using the first compare match value is not executed in that timer period.

4. 4. The motor control method of claim 3, wherein when a compare match using the third compare match value is executed in the first timer period of the carrier cycle, a compare match using the fourth compare match value is not executed in that timer period, and when a compare match using the fourth compare match value is executed in the second timer period of the carrier cycle, a compare match using the third compare match value is not executed, and when the difference count value is calculated, a compare match is executed in the first timer period of the carrier cycle with the difference count value as the fourth compare match value.

5. 1. An electric motor control device that generates complementary PWM signals based on a torque command value and controls a drive of an electric motor using voltages generated based on the complementary PWM signals, a first PWM signal generating unit that generates a first PWM signal, which is one of the complementary PWM signals, based on the torque command value; a second PWM signal generating unit configured to generate a second PWM signal, the second PWM signal being the other of the complementary PWM signals, the second PWM signal falling before a predetermined dead time from when the first PWM signal rises and rising after the predetermined dead time from when the first PWM signal falls; A determination means for determining a state of the first PWM signal and the second PWM signal, The first PWM signal generating unit is a first timer having a timer period set to an integer multiple of a carrier period of the complementary PWM signals, and the first PWM signal is raised and the first PWM signal is lowered in the timer periods different from each other; the determination means, in a case where the timer period of the previous stage and the timer period of the next stage are adjacent to each other, the timer period of the previous stage being included in the carrier period of the previous stage of a pair of carrier periods adjacent to each other, and the timer period of the next stage being included in the carrier period of the next stage of the pair of carrier periods, if a falling edge of the second PWM signal is set at a midpoint of the timer period of the next stage and a time from the falling edge of the first PWM signal in the timer period of the previous stage to the end of the carrier period of the previous stage is shorter than a predetermined dead time, calculates a differential time by subtracting the time from the predetermined dead time; The second PWM signal generating unit is a second timer having a timer period set in synchronization with the first timer, and executing the falling edge of the second PWM signal and the rising edge of the second PWM signal in different timer periods, and when the determination means has calculated the difference time, the motor control device sets the difference time as the time at which the second PWM signal rises in a subsequent timer period.

6. The first PWM signal generating unit is the first timer is synchronized with the carrier cycle with a timer period that is half the carrier cycle, thereby counting in a first timer period and a second timer period in the carrier cycle; a first compare match register that generates a first signal when a count value of the first timer matches a first compare match value; a second compare match register that generates a second signal when the count value of the first timer matches a second compare match value; a first PWM signal output means for setting the first PWM signal to a high level when the first signal is received, and for setting the first PWM signal to a low level having a voltage lower than the high level when the second signal is received; a first compare match value calculation means for calculating the first compare match value, which is a count value at a timing when the first PWM signal rises, and the second compare match value, which is a count value at a timing when the first PWM signal falls, based on the torque command value; a first compare match value setting means for setting the first compare match value in the first timer period of the carrier period and setting the second compare match value in the second compare match register in the second timer period of the carrier period, The second PWM signal generating unit is the second timer being synchronized with the first timer to count in a first timer period and a second timer period in the carrier period; a third compare match register that generates a third signal when the count value of the second timer matches a third compare match value; a fourth compare match register that generates a fourth signal when the count value of the second timer matches a fourth compare match value; a second PWM signal output means for setting the second PWM signal to the low level when the third signal is received, and for setting the second PWM signal to the high level when the fourth signal is received; a second compare match value calculation means for calculating a third compare match value by subtracting a count value related to the predetermined dead time from the first compare match value, and for calculating a fourth compare match value by adding the count value related to the predetermined dead time to the second compare match value; a second compare match value setting means for setting the third compare match value in the third compare match register in a first timer period of the carrier period, and setting the fourth compare match value in the fourth compare match register in a second timer period of the carrier period, The determination means is when the timer period of the previous stage and the timer period of the next stage are adjacent to each other, the timer period of the previous stage being included in the carrier period of the previous stage of a pair of carrier periods adjacent to each other, and the timer period of the next stage being included in the carrier period of the next stage of the pair of carrier periods, and when the third compare match value is set at a midpoint of the timer period of the next stage and a difference obtained by subtracting the second compare match value set in the timer period of the previous stage from the upper limit count values ​​of the first timer and the second timer is lower than a count value related to the specified dead time, a difference count value is calculated by subtracting the difference from the count value related to the specified dead time, 6. The motor control device according to claim 5, wherein when the determination means calculates the difference count value, the second compare match value setting means sets the difference count value in the fourth compare match register as the fourth compare match value in a subsequent timer period.

7. 7. The motor control device of claim 6, wherein when the first compare match value is set in the first compare match register in the first timer period of the carrier cycle, the first compare match value setting means sets a count value outside the count range of the first timer in the second compare match register in the second timer period of the carrier cycle, and when the second compare match value is set in the second compare match register in the second timer period of the carrier cycle, the first compare match value setting means sets a count value outside the count range of the first timer in the first compare match register in the second timer period of the carrier cycle.

8. 7. The motor control device of claim 6, wherein when the second compare match value setting means sets the third compare match value in the third compare match register in the first timer period of the carrier cycle, it sets a count value outside the count range of the second timer in the fourth compare match register in that timer period, and when the fourth compare match value is set in the fourth compare match register in the second timer period of the carrier cycle, it sets a count value outside the count range of the second timer in the third compare match register in that timer period, and when the determination means calculates the difference count value, it sets the difference count value in the fourth compare match register as the fourth compare match value in the first timer period of the carrier cycle.

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