FeFET Unit Cell for Neuromorphic Computing

Abstract

The circuit structure includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode, and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is connected to a word line, and the first source electrode and the second source electrode are connected to a bit line. The first drain electrode is connected to the second gate electrode, and the second drain electrode is connected to a bias line. A weight synapse structure is constructed by combining the two circuit structures. Multiple weight synapse structures are incorporated into a crossbar array.

Description

[Technical field]

[0001] The present invention relates generally to semiconductor devices, and more specifically to ferroelectric field effect transistor (FeFET) unit cells for neuromorphic computing. [Background technology]

[0002] The FeFET is a new device that incorporates a ferroelectric layer (FE) in the gate stack of a transistor on top of a dielectric (DE). Any metal can also be used between the FE and DE layers. The polarization of the FE couples with the polarization of the underlying FET, resulting in unique properties (since it retains P in the absence of external E), e.g., non-volatile transistor behavior. Experimental studies have demonstrated analog computing or non-volatile (memory) properties for FeFETs, e.g., by changing the composition of the gate stack and using design-time optimization / static device optimization. Summary of the Invention [Means for solving the problem]

[0003] According to one embodiment, a circuit structure is provided that includes a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode, and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode, where the first gate electrode is connected to a word line, and the first source electrode and the second source electrode are connected to a bit line.

[0004] According to another embodiment, a weight synapse structure is provided comprising a first circuit structure integrated between a first word line and a first bit line, the first circuit structure comprising a first ferroelectric field effect transistor (FeFET) and a second FeFET, and a second circuit structure integrated between a second word line and a second bit line, the second circuit structure comprising a third FeFET and a fourth FeFET, the first circuit structure being electrically connected to the second circuit structure by electrically connecting the first word line to the second word line to define a single synapse.

[0005] According to yet another embodiment, a method is provided that includes constructing a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode, constructing a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode, combining the first FeFET and the second FeFET to form a first circuit structure, connecting the first gate electrode to a first word line, and connecting the first source electrode and the second source electrode to a first bit line.

[0006] It should be noted that the exemplary embodiments are described with reference to different subject matter. In particular, some embodiments are described with reference to method type claims, while other embodiments are described with reference to apparatus type claims. However, those skilled in the art will understand from the above and following description that, unless otherwise specified, in addition to any combination of features belonging to one type of subject matter, any combination between features relating to different subject matters, in particular between features of method type claims, between features of apparatus type claims, is also considered to be described herein.

[0007] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0008] The invention is provided in more detail in the following description of preferred embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 shows the ferroelectric field effect transistor (FeFET) structure. [Diagram 2] FIG. 2 is a unit cell comprising two FeFETs according to one embodiment of the present invention. [Diagram 3] FIG. 3 is a synaptic weight with four FeFETs according to one embodiment of the present invention. [Figure 4] FIG. 4 is a block / flow diagram for training or setting synaptic weights according to one embodiment of the present invention. [Diagram 5] FIG. 5 is a block / flow diagram for resetting synaptic weights according to one embodiment of the present invention. [Figure 6] FIG. 6 is a block / flow diagram for resetting pass transistors and reading synaptic weights according to one embodiment of the present invention. [Figure 7] FIG. 7 is a schematic diagram of an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET) under a first set of bias conditions in accordance with one embodiment of the present invention. [Figure 8] FIG. 8 is a schematic diagram of an nFET and a pFET under a second set of bias conditions according to one embodiment of the present invention. [Figure 9] FIG. 9 is an exemplary neuromorphic and synaptronic network comprising a crossbar of electronic synapses interconnecting electronic neurons and axons, in accordance with one embodiment of the present invention. [Figure 10] FIG. 10 is a block diagram of components of a computing system including a computing device and a neuromorphic chip that can use unit cells or synaptic weights or a combination thereof, according to one embodiment of the invention. [Figure 11] FIG. 11 is a block / flow diagram of a method for illustrating unit cell connections (two FeFETs) according to one embodiment of the present invention. [Figure 12] FIG. 12 is a block / flow diagram of a method for illustrating synaptic weight connections (4 FeFETs) according to one embodiment of the present invention.

[0010] Throughout the drawings, the same or similar reference numbers represent the same or similar elements. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] An embodiment according to the present invention provides a method and device for using unit cells to improve linearity for neuromorphic computing. The unit cell comprises two ferroelectric field effect transistors (FeFETs). In the unit cell, one FeFET functions as an access (i.e., pass) transistor, and the other FeFET is used to store information proportional to the conductance (G). A weight is represented by two unit cells, i.e., four FeFETs. The weight is expressed as proportional to the difference between (G+, G-). The FeFETs can be either n-type field effect transistors (nFETs) or p-type field effect transistors (pFETs) or a combination thereof.

[0012] Linearity is an important factor for analog memory elements for weight updates. For online training purposes, the pulses need to have the same amplitude and duration. However, it remains a challenge to obtain the required linearity when using existing FeFETs under voltage pulses. As one methodology, the gate voltage of an FeFET synapse can be adjusted to improve the linear response. This can be achieved by using an FeFET as a pass transistor such that the voltage applied to the synapse is modulated.

[0013] An embodiment in accordance with the present invention provides a method and apparatus for a structure with two FeFETs, one used as a pass transistor and the other used for analog computing to improve the linearity of the weight updates. One FeFET is used for potentiation and the other FeFET is used for depression. As a result, an exemplary embodiment of the present invention focuses on a two FeFET unit cell structure to improve linearity for neuromorphic computing, where two ferroelectric memories are used for training purposes.

[0014] Examples of semiconductor materials that can be used in forming such FeFETs include silicon (Si), germanium (Ge), silicon germanium alloy (SiGe), silicon carbide (SiC), germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors, or combinations thereof. III-V compound semiconductors are materials that include at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. II-VI compound semiconductors are materials that include at least one element from Group II of the Periodic Table of Elements and at least one element from Group VI of the Periodic Table of Elements.

[0015] Although the present invention is described in terms of a given example architecture, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks may vary within the scope of the present invention. It should be noted that for clarity, certain features may not be shown in every figure. This is not intended to be construed as a limitation of the particular embodiment, or illustration, or the scope of the claims.

[0016] FIG. 1 shows the ferroelectric field effect transistor (FeFET) structure.

[0017] The FeFET device 5 includes a source region 12 and a drain region 14 formed on a portion of a substrate 10. An interfacial layer (IL) 16 is formed in direct contact with the top surface of the substrate 10, the source region 12, and the drain region 14. A ferroelectric oxide layer 18 is formed on the IL 16. A top electrode 20 is then formed on the ferroelectric oxide layer 18. A gate voltage 22 (VGS) can be applied via the top electrode 20.

[0018] The substrate 10 can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 10 can essentially (e.g., except for contaminants) comprise a single element (e.g., silicon), predominantly comprise a single element (e.g., with doping), e.g., silicon (Si) or germanium (Ge), or the substrate 10 can comprise a compound, e.g., GaAs, SiC, or SiGe. The substrate 10 can also have multiple layers of material. In some embodiments, the substrate 10 comprises a semiconductor, including but not necessarily limited to silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon germanium carbide (SiGeC), carbon-doped silicon germanium (SiGe:C), III-V compound semiconductors (e.g., GaAs, AlGaAs, InAs, InP, etc.), II-V compound semiconductors (e.g., ZnSe, ZnTe, ZnCdSe, etc.), or other similar semiconductors. In addition, multiple layers of semiconductor material can be used as the semiconductor material of the substrate 10. In some embodiments, the substrate 10 includes both semiconductor and dielectric materials. The semiconductor substrate 10 can also include organic semiconductors or layered semiconductors, such as Si / SiGe, silicon-on-insulator, or SiGe-on-insulator. Part or all of the semiconductor substrate 10 can be amorphous, polycrystalline, or single crystalline. In addition to the types of semiconductor substrates described above, the semiconductor substrate 10 used in the present invention can also include hybrid oriented (HOT) semiconductor substrates, where the HOT substrate has surface regions with different crystal orientations.

[0019] The terms "epitaxial growth" and "epitaxial deposition" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, where the grown semiconductor material has substantially the same crystalline properties as the semiconductor material on the deposition surface. The term "epitaxial material" refers to a material formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters are set correctly, the deposited atoms move around on the deposition surface and arrive at the deposition surface with enough energy to orient the deposited atoms in the crystalline arrangement of the atoms on the deposition surface. Thus, in some instances, an epitaxial film deposited on a {100} crystalline surface will adopt a {100} orientation.

[0020] The top electrode 20 can include a conductive material, such as Cu, Al, Ag, Au, Pt, W, Ta, Ru, etc. In some embodiments, the top electrode 20 can include a nitride, such as TiN, TaN.

[0021] The ferroelectric oxide layer 18 can include a hafnium oxide (HfO2) layer or HfO2 with dopants, such as Si, Al, Zr, N, etc. The ferroelectric oxide layer 18 can include, for example, HfO2 in the orthorhombic phase (the ferroelectric phase).

[0022] FIG. 2 is a unit cell comprising two FeFETs according to one embodiment of the present invention.

[0023] The unit cell 30 includes two FeFETs, a first FeFET 40 and a second FeFET 42. The first FeFET 40 functions as a pass transistor, and the second FeFET 42 functions as a non-volatile memory (NVM) for analog computing.

[0024] In various exemplary embodiments, the unit cells 30 are embedded between bit lines 34 and word lines 32. Thus, an array can be obtained with perpendicular conductive word lines (rows) 32 and bit lines (columns) 34, where a unit cell structure 30 resides at the intersection between each row and each column. The cell structures 30 can be accessed for reading and writing by biasing the corresponding word lines 32 and bit lines 34. The unit cells 30 exhibit a conductance (G) value 36.

[0025] FIG. 3 is a synaptic weight with four FeFETs according to one embodiment of the present invention.

[0026] The weight synapse structure 50 includes two unit cells and four FeFETs. In particular, the G+ (66) or unit cell 60 includes two FeFETs 62 and 64, and the G- (76) or unit cell 70 includes two FeFETs 72 and 74. The FeFET 62 of the unit cell 60 is a pass transistor, and the FeFET 64 of the unit cell 60 is an NVM for analog computing. Similarly, the FeFET 72 of the unit cell 70 is a pass transistor, and the FeFET 74 of the unit cell 70 is an NVM for analog computing. Each unit cell includes a word line and a bit line. For example, the unit cell 60 includes a word line 52 and a bit line 54, while the unit cell 70 includes a word line 56 and a bit line 58.

[0027] Therefore, according to Figures 1-3, the FeFET device 5 comprises a single transistor structure (source region 12, drain gate region 14, substrate 10) with a ferroelectric oxide layer 18 acting as the gate dielectric. Two FeFETs (one acting as a pass transistor and one acting as an NVM for analog computing) represent a unit cell structure 30 that represents a conductance (G) value used for analog computing. G+ (two FeFETs) and G- (two additional FeFETs) together represent a synaptic weight 50 where W is proportional to the difference between G+ and G-. The two-unit-cell-represent-one-synapse concept is used in phase-change memory (PCM) based synapse applications where two PCM devices represent one weight (G+-G-). According to an exemplary embodiment of the present invention, two unit cells are required to represent a synapse, and for each unit cell, two FeFETs (one pass transistor, and one NVM for analog computing) are required.

[0028] FIG. 4 is a block / flow diagram for training or setting synaptic weights according to one embodiment of the present invention.

[0029] For training 80, for word line 82, Vp can gradually change the Vt of the FeFET (pass transistor) when the synapse is set. For bit line 84, Vb-Vt can modulate the channel conductance of the synapse. Therefore, to program an FeFET device, a positive voltage pulse must be applied that exceeds the threshold voltage Vt. In this way, a sufficient electric field is generated on the ferroelectric layer to induce polarization reversal. Therefore, every time a positive voltage pulse Vp is input, the FeFET is turned on.

[0030] FIG. 5 is a block / flow diagram for resetting synaptic weights according to one embodiment of the present invention.

[0031] In the case of synapse reset 90, with respect to word line 92, V w_rst is large and turns on the pass transistor. For bit line 94, V b_rst is negative and its absolute value is large enough to reset the synaptic device.

[0032] FIG. 6 is a block / flow diagram for resetting pass transistors and reading synaptic weights according to one embodiment of the present invention.

[0033] For a read of synapse 100, for word line 102, V p_full is large and completely programs the polarization to the initial state. b_read is small and does not disturb the FeFET.

[0034] FIG. 7 is a schematic diagram of an nFET and a pFET under a first set of bias conditions according to one embodiment of the present invention.

[0035] In a first configuration 110, two nFETs 112 and 114 are connected together in a unit cell. In a first set of conditions 116, V バイアス <V bl , and V GS(シナプス) =V bl -V t -V バイアス where the synapse is V t It decreases as V increases. バイアス If is chosen to be zero, then the configuration becomes equivalent to that described with respect to FIG.

[0036] In the second configuration 120, one nFET 122 and one pFET 124 are connected together in a unit cell. In the first set of conditions 126, V バイアス <V bl , and -V GS(シナプス) =V t where the synapse is Vt increases as increases.

[0037] In a third configuration 130, one pFET 132 and one nFET 134 are connected together in a unit cell. In a first set of conditions 136, V バイアス >V bl , and V GS(シナプス) =V t , where the synapse is -V t decreases as increases.

[0038] In a fourth configuration 140, two pFETs 142 and 144 are connected together in a unit cell. In a first set of conditions 146, V バイアス >V bl , and -V GS(シナプス) =V バイアス -V bl -V t , where the synapse is -V t increases as increases.

[0039] FIG. 8 is a schematic diagram of an nFET and a pFET under a second set of bias conditions according to one embodiment of the present invention.

[0040] In the first configuration 110, two nFETs 112 and 114 are connected together in a unit cell. In the second set of conditions 118, V バイアス >V bl , and V GS(シナプス) =-V t where the synapse is V t decreases as increases.

[0041] In the second configuration 120, one nFET 122 and one pFET 124 are connected together in a unit cell. In the second set of conditions 128, V バイアス >V bl , and -V GS(シナプス) =V バイアス -(V bl -V t ), where the synapse is V tincreases as increases.

[0042] In a third configuration 130, one pFET 132 and one nFET 134 are connected together in a unit cell. In a first set of conditions 138, V バイアス <V bl , and V GS(シナプス) =(V bl +V t )-V バイアス where the synapse is -V t decreases as increases.

[0043] In the fourth configuration 140, two pFETs 142 and 144 are connected together in a unit cell. In the first set of conditions 148, V バイアス <V bl , and -V GS(シナプス) =-V t where the synapse is -V t increases as increases.

[0044] In one non-limiting example of a pulse train of equal amplitude (V) and duration, n is the number of pulses applied after resetting the FeFET, which reduces the channel conductance and hence V t is assumed to factor V and n based on the empirical FeFET formula: ΔV t,PASS =V t,PASS -V t0,PASS =α1V[1-exp(-λ1n)] Here, α1 and λ1 are empirical parameters.

[0045] Therefore, the ΔV of the synapse t can be expressed as:

[0046] ΔV t,シナプス =α2(C+ΔV t,PASS )[1-exp(-λ2n)] where C is V t0,PASS , and V バイアス And V blis a constant that depends on

[0047] As a result, V 有効,シナプス =C+α1V[1-exp(-λ1n)] increases as a function of n, thus improving linearity.

[0048] Quantitatively, without the pass transistor FeFET, the synapse linearity at n ≈ 1 / λ2 is (1-exp(-1)) × 100 ≈ 64%.

[0049] With the addition of the pass transistor FeFET, the linearity of the synapse increases by a factor of [1+α1(V / C).(1-exp(-λ1 / λ2)], which is approximately [1+0.64α1(V / C)] for λ1≒λ2.

[0050] FIG. 9 is an exemplary neuromorphic and synaptronic network comprising a crossbar of electronic synapses interconnecting electronic neurons and axons, in accordance with one embodiment of the present invention.

[0051] The exemplary tile circuit 200 includes a crossbar 212 in accordance with one embodiment of the present invention. In one example, the entire circuit can include an "ultra-dense crossbar array" that can have a pitch of about 10 nm to about 500 nm. However, smaller and larger pitches can also be contemplated by one skilled in the art. The neuromorphic and synaptronic circuit 200 includes a crossbar 212 that interconnects a plurality of digital neurons 211, including neurons 214, 216, 218, and 220. These neurons 211 are also referred to herein as "electronic neurons." For illustrative purposes, the exemplary circuit 200 provides symmetrical connections between two pairs of neurons (e.g., N1 and N3). However, one embodiment of the present invention is useful not only with such symmetrical connections of neurons, but also with asymmetrical connections of neurons (neurons N1 and N3 need not be connected with the same connections). The crossbars in the tiles accommodate the appropriate ratio of synapses to neurons and therefore need not be square.

[0052] In the exemplary tile circuit 200, neuron 211 is connected to crossbar 212 via dendritic pathways / wires (dendrites) 213, e.g., dendrites 226 and 228. Neuron 211 is also connected to crossbar 212 via axonal pathways / wires (axons) 215, e.g., axons 234 and 236. Neurons 214 and 216 are dendritic neurons, and neurons 218 and 220 are axonal neurons connected to axon 213. Specifically, neurons 214 and 216 are shown with outputs 222 and 224 connected to dendrites (e.g., bit lines) 226 and 228, respectively. Axonal neurons 218 and 220 are shown with outputs 230 and 232 connected to axons (e.g., word lines or access lines) 234 and 236, respectively.

[0053] When any of the neurons 214, 216, 218, 220 fire, it sends out a pulse to the connection between their axon and their dendrites. Each synapse provides contact between the axon of a neuron and a dendrite on another neuron, and with respect to a synapse, the two neurons are called the presynaptic and postsynaptic, respectively.

[0054] Each connection between the dendrites 226 and 228 and the axons 234 and 236 is made through a digital synaptic device 231 (synapse). The junctions at which the synaptic devices are located may be referred to herein as "cross-point junctions." Generally, according to one embodiment of the present invention, the neurons 214 and 216 "fire" (send a pulse) in response to the input they receive from their axonal input connections (not shown) exceeding a threshold. Each single synapse 231 may comprise a first circuit structure and a second circuit structure electrically connected to each other, either directly or indirectly via surrounding circuitry. The first circuit structure may be referred to as a first unit cell, and the second circuit structure may be referred to as a second unit cell. Each single synapse 231 comprises four FeFETs, as shown in FIG. 3. Thus, in one example, one or more of the weight synapse structures of FIG. 3 are incorporated into the neuromorphic and synaptronic network of FIG.

[0055] Neurons 218 and 220 "fire" (send a pulse) in response to the input they receive from an external input connection (not shown), typically another neuron, exceeding a threshold. In one embodiment, as neurons 214 and 216 fire, they maintain a decaying postsynaptic spike-timing-dependent plasticity (STDP) (post-STDP) variable. For example, in one embodiment, the decay period can be 50 μs (which corresponds to a 1000 times shorter and 1000 times higher operating speed than that of a real biological system). The post-STDP variable is used to achieve STDP by encoding the time since the last firing of the associated neuron. Such STDP is used to control long-term potentiation, or "potentiation," which in this context is defined as increasing synaptic conductance. As neurons 218 and 220 fire, they maintain a presynaptic-STDP parameter that decays in a manner similar to that of neurons 214 and 216 .

[0056] The pre-STDP and post-STDP variables can decay, for example, according to an exponential, linear, polynomial, or quadratic function. In another embodiment of the invention, the variables can increase instead of decreasing over time. In any case, the variables can be used to achieve STDP by encoding the time since the last firing of the associated neuron. STDP is used to control long-term depression or "depression", which in this context is defined as decreasing synaptic conductance. It should be noted that the roles of the pre-STDP and post-STDP variables can also be reversed, with pre-STDP enhancement and post-STDP inhibition.

[0057] An external bidirectional communication environment can provide sensory input and consume motor output. Digital neurons 211 implemented with complementary metal oxide semiconductor (CMOS) logic gates receive the spike inputs and integrate them. In one embodiment, neurons 211 include a comparator circuit that generates a spike when the integrated input exceeds a threshold. In one embodiment, the synapses are implemented with flash memory cells, where each neuron 211 can be an excitatory neuron or an inhibitory neuron (or both). Each learning rule on the axon and dendrites of each neuron is reconfigurable as described below. This assumes transposable access to the crossbar memory array. Spiking neurons are selected one at a time and send spike events to the corresponding axon, where the axon can be on the core or can be elsewhere in a larger system with many cores.

[0058] As used herein, the term "electronic neuron" refers to an architecture configured to simulate a biological neuron. An electronic neuron creates connections between processing elements that are approximately functionally equivalent to neurons in a biological brain. Thus, neuromorphic and synaptronic systems comprising electronic neurons according to an embodiment of the present invention can, in many useful embodiments, comprise various electronic circuits that model biological neurons, where the neuromorphic and synaptronic systems can operate on faster time scales (e.g., 1000X) than their biological counterparts. Furthermore, neuromorphic and synaptronic systems comprising electronic neurons according to an embodiment of the present invention can comprise various processing elements (including computer simulations) that model biological neurons. Although certain exemplary embodiments of the present invention are described herein using electronic neurons, e.g., the electronic neurons that include electronic circuits, the present invention is not limited to electronic circuits. Neuromorphic and synaptronic systems according to an embodiment of the present invention can be implemented as neuromorphic and synaptronic architectures, e.g., the neuromorphic and synaptronic architectures that include circuits, and also as computer simulations. Indeed, an embodiment of the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements.

[0059] FIG. 10 is a block diagram of components of a computing system including a computing device and a neuromorphic chip that can use unit cells or synaptic weights or a combination thereof, according to one embodiment of the invention.

[0060] 10 illustrates a block diagram of components of a system 300 including a computing device 305. It should be understood that FIG. 10 is only intended to provide an illustration of one implementation and is not intended to imply any limitation with respect to the environments in which different embodiments may be implemented. Many modifications to the illustrated environment may be made.

[0061] Computing device 305 includes a communications fabric 302 that provides communication between one or more computer processors 304, memory 306, persistent storage 308, communications units 310, and one or more input / output (I / O) interfaces 312. Communications fabric 302 can be implemented with any architecture designed to pass data or control information, or a combination thereof, between a processor (e.g., a microprocessor, communications and network processors), system memory, peripheral devices, and any other hardware components in the system. For example, communications fabric 302 can be implemented using one or more buses.

[0062] Memory 306, cache memory 316, and persistent storage 308 are computer-readable storage media. In this embodiment, memory 306 includes random access memory (RAM) 314. In another embodiment, memory 306 can be flash memory. In general, memory 306 can include any suitable volatile or non-volatile computer-readable storage medium.

[0063] In some embodiments of the present invention, the deep learning program 325 is provided as a component of the computing device 305 and is operated by the neuromorphic chip 322. In other embodiments, the deep learning program 325 is stored in the persistent storage 308 for execution by the neuromorphic chip 322 in cooperation with one or more of the respective computer processors 304 via one or more of the memories of the memory 306. In this embodiment, the persistent storage 308 includes a magnetic hard disk drive. Alternatively or in addition to the magnetic hard disk drive, the persistent storage 308 may include a solid-state hard drive, a semiconductor storage device, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0064] The media used by persistent storage 308 may also be removable. For example, a removable hard drive may be used for persistent storage 308. Other examples include optical and magnetic disks, thumb drives, and smart cards that are inserted into a drive for transfer onto another computer-readable storage medium that is also part of persistent storage 308.

[0065] The communication unit 310, in these examples, provides communication with other data processing systems or devices, such as other data processing systems or devices that include resources of a distributed data processing environment. In these examples, the communication unit 310 includes one or more network interface cards. The communication unit 310 can provide communication through the use of either or both physical and wireless communication links. The deep learning program 325 can be downloaded to the persistent storage 308 through the communication unit 310.

[0066] One or more I / O interfaces 312 allow for input and output of data with other devices that may be connected to computing system 300. For example, I / O interface 312 may provide connection to external devices 318, such as a keyboard, a keypad, a touch screen, or some other suitable input device or combination thereof. External devices 318 may include portable computer-readable storage media, such as thumb drives, portable optical or magnetic disks, and memory cards.

[0067] Display 320 provides a mechanism for displaying data to a user and can be, for example, a computer monitor.

[0068] FIG. 11 is a block / flow diagram of a method for illustrating unit cell connections (two FeFETs) according to one embodiment of the present invention.

[0069] In block 410, a first FeFET is provided having a first gate electrode, a first source electrode, and a first drain electrode.

[0070] In block 420, a second FeFET is used having a second gate electrode, a second source electrode, and a second drain electrode.

[0071] In block 430, the first gate electrode is connected to a word line.

[0072] In block 440, the first source electrode and the second source electrode are connected to a bit line.

[0073] In block 450, the first drain electrode is connected to the second gate electrode.

[0074] In block 460, the second drain electrode is connected to a bias line.

[0075] FIG. 12 is a block / flow diagram of a method for illustrating synaptic weight connections (4 FeFETs) according to one embodiment of the present invention.

[0076] In block 510, a first unit cell is defined using the first FeFET and the second FeFET.

[0077] In block 520, a second unit cell is defined using the third FeFET and the fourth FeFET.

[0078] In block 530, the first unit cell is connected to the second unit cell to represent a synaptic weight in neuromorphic computing.

[0079] In block 540, the synaptic weights are trained, read, and reset.

[0080] It is understood that the present invention is described in terms of certain exemplary architectures, however, other architectures, structures, substrate materials, and process features and steps / blocks may be varied within the scope of the present invention.

[0081] When an element, e.g., a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that it can be directly on the other element, or that intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that it is directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0082] This embodiment may include a design for an integrated circuit chip that may be created in a graphical computer programming language and stored in a computer storage medium (e.g., a disk, a tape, a physical hard drive, or a virtual hard drive, such as a virtual hard drive in a storage access network). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer may transmit the resulting design to such an entity, directly or indirectly, by a physical mechanism (e.g., by providing a copy of a storage medium that stores the design) or electronically (e.g., via the Internet). The stored design is then converted into a format (e.g., GDSII) appropriate for the manufacture of a photolithography mask that typically contains multiple copies of the chip design in question to be formed on a wafer. The photolithography mask is used to define the areas of the wafer (or layers thereon, or a combination thereof) to be etched or otherwise processed.

[0083] The methods described herein can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in a single-chip package (e.g., a plastic carrier with leads that are attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with either surface interconnects or buried interconnects or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or combinations thereof, as part of either (a) an intermediate product, such as a motherboard, or (b) a final product. The final product can be any product that includes the integrated circuit chip, from toys or other low-end applications to sophisticated computer products with displays, keyboards, other input devices, and a central processor.

[0084] It should also be understood that the material compounds are described in terms of the elements listed, e.g., SiGe. These compounds may contain different ratios of elements within the compound, e.g., SiGe is Si x Ge 1-x where x is, for example, 1 or less. In addition, other elements can be included in the compound and still function according to this embodiment. Compounds that include additional elements will be referred to herein as alloys.

[0085] In this specification, references to "one embodiment" or "an embodiment" of the present invention, as well as other variations thereof, mean that the particular features, structures, characteristics, etc. described in connection with the embodiment are included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification, as well as other variations, do not necessarily all refer to the same embodiment.

[0086] It should be understood that the use of any of " / ", "and / or", "at least one of", e.g., "A / B", "A and / or B", "at least one of A and B" is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of both alternatives (A and B). As a further example, "A, B and / or C" and "at least one of A, B and C" are intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first and second alternatives (A and B), the selection of only the first and third alternatives (A and C), the selection of only the second and third alternatives (B and C), or the selection of all three alternatives (A and B and C). This may be expanded as many times as there are items listed.

[0087] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that as used herein, the words "comprises", "comprising", "includes" or "including" or combinations thereof specify the presence of stated features, integers, steps, operations, elements, or components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof, or combinations thereof.

[0088] Spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of an element or feature to one or more other elements or features, as illustrated in the drawings for ease of description. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if a device in the drawings is turned over, an element described as "below" or "below" another element or feature would then be "above" the other element or feature. Thus, the term "below" can encompass both an above and below orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, when a layer is referred to as being "between" two layers, it will be understood that it can be the only layer between the two layers or that one or more intervening layers can also be present.

[0089] In this specification, the terms "first" and "second" etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another element. Thus, a first element described below can be referred to as a second element without departing from the scope of the present concepts.

[0090] Having described a preferred embodiment of a method and system for improving linearity in neuromorphic computing by using two FeFET unit cell structures, which are illustrative and not intended to be limiting, it is noted that modifications and variations may be made by one of ordinary skill in the art in light of the above teachings. It is therefore understood that changes may be made in the specific embodiments described which are within the scope of the invention as outlined by the appended claims. Thus, having described the aspects of the invention with the detail and particularity required by the patent laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.

Claims

1. 1. A circuit structure comprising a unit cell, the unit cell comprising: a first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode; and a second FeFET having a second gate electrode, a second source electrode, and a second drain electrode; Equipped with wherein the first gate electrode is connected to a word line; and wherein the first source electrode and the second source electrode are connected to the same bit line. The circuit structure.

2. 2. The circuit structure of claim 1, wherein the first drain electrode is connected to the second gate electrode.

3. The circuit structure of claim 1 , wherein the second drain electrode is connected to a bias line.

4. A weight synapse structure, the weight synapse structure comprising: a first circuit structure comprising a circuit structure according to any one of claims 1 to 3 integrated between a first word line and a first bit line; and A second circuit structure comprising a circuit structure according to any one of claims 1 to 3, incorporated between a second word line and a second bit line. Equipped with wherein the first circuit structure is electrically connected with the second circuit structure to define a single synapse. The weight synapse structure.

5. 5. The weight synapse structure of claim 4, wherein a voltage pulse is applied to the first word line and a bias voltage is applied to the first bit line to train the single synapse.

6. 6. The weight synapse structure of claim 5, wherein the voltage pulse gradually changes a threshold voltage of the first FeFET of the first circuit structure.

7. The weight synapse structure of claim 6 , wherein the bias voltage modulates a channel conductance of the single synapse.

8. 5. The weighted synapse structure of claim 4, wherein a word line reset voltage is applied to said first word line to reset said single synapse.

9. 5. The weighted synapse structure of claim 4, wherein a bit line reset voltage is applied to said first bit line to reset said single synapse.

10. 5. The weighted synapse structure of claim 4, wherein a bit line read voltage is applied to the first bit line to read out the single synapse.

11. constructing a first ferroelectric field effect transistor (FeFET) in a first unit cell, the first ferroelectric field effect transistor (FeFET) having a first gate electrode, a first source electrode, and a first drain electrode; constructing a second FeFET in the first unit cell, the second FeFET having a second gate electrode, a second source electrode, and a second drain electrode, and combining the first FeFET and the second FeFET to form a first circuit structure; connecting the first gate electrode to a first word line; and connecting the first source electrode and the second source electrode to a same first bit line; The method includes:

12. The method of claim 11 , further comprising connecting the first drain electrode to the second gate electrode.

13. The method of claim 12 , further comprising connecting the second drain electrode to a first bias line.

14. constructing a third FeFET in the second unit cell, the third FeFET comprising a third gate electrode, a third source electrode, and a third drain electrode; constructing a fourth FeFET in the second unit cell, the fourth FeFET having a fourth gate electrode, a fourth source electrode, and a fourth drain electrode, and combining the third FeFET and the fourth FeFET to form a second circuit structure; connecting the third gate electrode to a second word line; and connecting the third source electrode and the second source electrode to the same second bit line; The method of claim 13 further comprising:

15. The method of claim 14 , further comprising connecting the third drain electrode to the fourth gate electrode.

16. The method of claim 15 further comprising connecting the fourth drain electrode to a second bias line.

17. 17. The method of claim 16, further comprising electrically connecting the first circuit structure to the second circuit structure for differential reading of channel conductance values ​​of the second and fourth FeFETs to define a single synapse.

18. 20. The method of claim 17, further comprising applying a voltage pulse to the first word line and a bias voltage to the first bit line to train the single synapse.

19. 20. The method of claim 18, further comprising gradually changing a threshold voltage of the first FeFET of the first circuit structure and the third FeFET of the second circuit structure via the voltage pulse.

20. 20. The method of claim 19, further comprising modulating a channel conductance of the single synapse via the bias voltage.

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