Imaging device and electronic device

Abstract

To provide an imaging apparatus capable of suppressing a decrease in a dynamic range of the entire imaging apparatus due to an input transistor of a comparator inserted between a signal line and a load current source in an analog-to-digital converter.SOLUTION: An imaging apparatus according to the present disclosure includes a load current source, a comparator including an input transistor connected between a signal line that transmits a signal read from a pixel and a load current source, and a reference signal supply unit that supplies a predetermined reference signal to a charge-voltage conversion unit of the pixel.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to an imaging device and an electronic device. [Background technology]

[0002] The imaging device is equipped with an analog-to-digital conversion unit that digitizes analog pixel signals read from the pixels. The analog-to-digital conversion unit equipped in the imaging device is a so-called column-parallel type analog-to-digital conversion unit that is made up of a plurality of analog-to-digital converters arranged corresponding to pixel columns.

[0003] As an analog-to-digital converter constituting a column-parallel analog-to-digital conversion unit, for example, a so-called single-slope analog-to-digital converter is known, which digitizes an analog pixel signal read out from a pixel by comparing the analog pixel signal with a predetermined reference signal.

[0004] The single-slope analog-digital converter is composed of, for example, a comparator that compares an analog pixel signal with a predetermined reference signal, and a counter that counts based on the comparison result of the comparator. As an imaging device having a single-slope analog-digital converter, for example, an imaging device has been proposed in which an input transistor of a comparator that compares an analog pixel signal with a predetermined reference signal is inserted between a signal line that transmits a signal read from a pixel and a load current source (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] WO 2020 / 170518 A1 Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, in the imaging device described in Patent Document 1, the input transistor of the comparator of the analog-digital converter is inserted between the signal line that transmits the signal read out from the pixel and the load current source. In this way, by inserting the input transistor between the signal line and the load current source, the drain-source voltage V ds As a result, the lower limit of the signal line potential at which linearity is guaranteed increases, and the dynamic range of the entire image pickup device decreases.

[0007] The present disclosure aims to provide an imaging device that can suppress a reduction in the dynamic range of the entire imaging device caused by an input transistor of a comparator inserted between a signal line and a load current source in an analog-to-digital converter, and an electronic device that has the imaging device. [Means for solving the problem]

[0008] In order to achieve the above object, the imaging device of the present disclosure comprises: load current source, a comparator having an input transistor connected between a signal line transmitting a signal read out from a pixel and a load current source; a reference signal supplying unit that supplies a predetermined reference signal to the charge-voltage conversion unit of the pixel; Equipped with.

[0009] In order to achieve the above object, the electronic device of the present disclosure comprises: load current source, a comparator having an input transistor connected between a signal line transmitting a signal read out from a pixel and a load current source; a reference signal supplying unit that supplies a predetermined reference signal to the charge-voltage conversion unit of the pixel; Equipped with It has an imaging device. [Brief description of the drawings]

[0010] [Figure 1]FIG. 1 is a block diagram showing a schematic overview of the system configuration of a CMOS image sensor, which is an example of an imaging device to which the technology according to the present disclosure is applied. [Diagram 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a pixel. [Diagram 3] FIG. 3A is a perspective view that typically shows a flat-type chip structure, and FIG. 3B is an exploded perspective view that typically shows a stacked-type semiconductor chip structure. [Figure 4] FIG. 4 is a block diagram illustrating an example of the configuration of the analog-to-digital conversion unit. [Diagram 5] FIG. 5 is a circuit diagram showing an example of a circuit configuration of a comparator according to the conventional technology. [Figure 6] FIG. 6 is a circuit diagram showing an example of a circuit configuration for one pixel column including a comparator in the CMOS image sensor according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a timing chart for explaining the operation of the CMOS image sensor according to the first embodiment of the present disclosure. [Figure 8] FIG. 8A is a diagram showing how a ramp wave reference signal is superimposed on the potential of the floating diffusion FD, and FIG. 8B is a diagram for explaining the comparison operation of the comparator. [Figure 9] FIG. 9 is a circuit diagram showing an example of a circuit configuration for one pixel column including a comparator in a CMOS image sensor according to the second embodiment of the present disclosure. [Figure 10] FIG. 10 is a timing chart for explaining the operation of the CMOS image sensor according to the second embodiment of the present disclosure. [Figure 11] FIG. 11 is a circuit diagram showing an example of a circuit configuration for one pixel column including a comparator in a CMOS image sensor according to the third embodiment of the present disclosure. [Figure 12] FIG. 12 is a circuit diagram illustrating an example of a configuration of a reference signal supply unit according to the first embodiment. [Figure 13] FIG. 13 is a circuit diagram illustrating an example of a configuration of a reference signal supply unit according to the second embodiment. [Figure 14]FIG. 14 is a circuit diagram illustrating an example of a configuration of a reference signal supply unit according to the third embodiment. [Figure 15] FIG. 15 is a circuit diagram of an example of a configuration of a reference signal supply unit according to the fourth embodiment. [Figure 16] FIG. 16 is a circuit diagram of an example of a configuration of a reference signal supply unit according to the fifth embodiment. [Figure 17] FIG. 17 is a circuit diagram illustrating an example of a configuration of a reference signal supply unit according to the sixth embodiment. [Figure 18] FIG. 18 is a circuit diagram of an example of a configuration of a reference signal supply unit according to the seventh embodiment. [Figure 19] FIG. 19 is a circuit diagram of an example of a configuration of a reference signal supply unit according to the eighth embodiment. [Figure 20] FIG. 20 is a circuit diagram of an example of a configuration of a reference signal supply unit according to the ninth embodiment. [Figure 21] FIG. 21 is a circuit diagram of an example of a configuration of a reference signal supply unit according to a tenth embodiment. [Figure 22] FIG. 22 is a circuit diagram of an example of a configuration of a reference signal supply unit according to the eleventh embodiment. [Figure 23] FIG. 23 is a circuit diagram showing a pixel circuit according to the first circuit configuration example. [Figure 24] FIG. 24 is a circuit diagram showing a pixel circuit according to the second circuit configuration example. [Diagram 25] FIG. 25 is a circuit diagram showing a pixel circuit according to the third circuit configuration example. [Figure 26] FIG. 26 is a diagram illustrating an inter-chip wiring structure according to the first wiring structure example. [Figure 27] FIG. 27 is a diagram illustrating an interchip wiring structure according to the second wiring structure example. [Figure 28] FIG. 28 is a diagram illustrating an interchip wiring structure according to the third wiring structure example. [Figure 29] FIG. 29 is a diagram illustrating an interchip wiring structure according to the fourth wiring structure example. [Diagram 30] FIG. 30 is a diagram illustrating an interchip wiring structure according to wiring structure example 5. In FIG. [Diagram 31] FIG. 31 is a diagram illustrating an interchip wiring structure according to wiring structure example 6. In FIG. [Diagram 32] FIG. 32 is a diagram showing an application example of the technology disclosed herein. [Diagram 33] FIG. 33 is a block diagram illustrating an outline of an example configuration of an imaging system that is an example of an electronic device according to the present disclosure. [Diagram 34] FIG. 34 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied. [Diagram 35] FIG. 35 is a diagram showing an example of an installation position of an imaging unit in a mobile object control system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, a form for carrying out the technology according to the present disclosure (hereinafter, referred to as "embodiment") will be described in detail with reference to the drawings. The technology according to the present disclosure is not limited to the embodiment. In the following description, the same reference numerals will be used for the same elements or elements having the same functions, and duplicated description will be omitted. The description will be given in the following order. 1. General Description of the Imaging Device and Electronic Device of the Present Disclosure 2. Imaging device to which the technology disclosed herein is applied 2-1.Example of CMOS image sensor configuration 2-2. Example of pixel circuit configuration 2-3.Semiconductor chip structure 2-3-1.Flat-type semiconductor chip structure 2-3-2.Stacked semiconductor chip structure 2-4. Example of analog-to-digital conversion section 2-5.About the comparator in an analog-to-digital converter 2-6. Comparator according to the reference example 2-6-1. Example of a circuit configuration of a comparator according to the prior art 2-6-2. Problems with comparators related to conventional technology 3. First embodiment of the present disclosure (example in which a ramp wave reference signal is applied to a floating diffusion FD) 3-1. Example of circuit configuration for one pixel column including comparator 4. Second embodiment of the present disclosure (example of ramp wave reference signal in which offset portion is separated from ramp waveform, inverted upside down, and input to comparator) 4-1. Example of circuit configuration for one pixel column including comparator 5. Third embodiment of the present disclosure (example of pixel sharing) 5-1. Example of circuit configuration for one pixel column including comparator 6. Example of the reference signal supply unit configuration 6-1. Example 1 (Example of supplying ramp wave reference signals along the column direction) 6-2. Example 2 (Modification of Example 1: Example in which a reference signal generating unit is commonly arranged for all pixel columns) 6-3. Third embodiment (Modification of the second embodiment: Example in which the reference signal generated by the reference signal generating unit is directly supplied to each pixel column) 6-4. Example 4 (Modification of Example 3: Example of driving from both top and bottom of matrix pixel array) 6-5. Example 5 (Example of supplying a ramp wave reference signal along the row direction) 6-6. Example 6 (Modification of Example 5: Example of driving from both left and right sides of a matrix pixel array) 6-7. Seventh embodiment (modification of the fifth embodiment: an example in which a reference signal generating unit is commonly arranged for all pixel rows) 6-8. Example 8 (Modification of Example 7: Example of driving from both left and right sides of a matrix pixel array) 6-9. Example 9 (Example of supplying reference signals in a mesh pattern on a pixel-by-pixel basis) 6-10. Example 10 (Modification of Example 9: Example in which a buffer is interposed between the wiring of the reference signal and the reference signal generating unit) 6-11. Example 11 (Example of supplying ramp wave reference signals in the column direction from the center of a pixel array in a matrix) 7. Example of pixel circuit configuration 7-1. Circuit configuration example 1 (Example of providing a buffer before the input capacitance element) 7-2. Circuit configuration example 2 (an example in which the constant current source transistor of the buffer is provided on a chip separate from the pixel) 7-3. Circuit configuration example 3 (example of providing a reference signal generating unit within a pixel) 8. Example of inter-chip wiring structure in stacked semiconductor chip structure 8-1. Wiring structure example 1 (Example of wiring structure between chips in a two-layer stacked chip structure) 8-2. Wiring structure example 2 (example of electrical connection between chips at the output part of the reference signal generating part in a two-layer stacked chip structure) 8-3. Wiring structure example 3 (example of providing a reference signal generating unit for each pixel in a two-layer stacked chip structure) 8-4. Wiring structure example 4 (Example of wiring structure between chips in a three-layer stacked chip structure) 8-5. Wiring structure example 5 (example of electrical connection between chips at the output part of the reference signal generating part in a three-layer stacked chip structure) 8-6. Wiring Structure Example 6 (Example of Providing a Reference Signal Generator for Each Pixel in a Three-Layer Stacked Chip Structure) 9. Variations 10. Application Examples 11. Application Examples of the Technology Disclosed Herein 11-1. Electronic Device of the Present Disclosure (Example of Imaging Device) 11-2. Application examples for mobile devices 12. Configurations that the present disclosure can take

[0012] <General Description of Imaging Device and Electronic Device of the Present Disclosure> In the imaging device and electronic device of the present disclosure, a predetermined reference signal may be a voltage having a slope waveform that changes linearly with a predetermined slope, and a comparator may be configured to compare a signal voltage on which a slope waveform voltage is superimposed and which is supplied through a signal line with a predetermined reference voltage.

[0013] In the imaging device and electronic device of the present disclosure including the preferred configuration described above, when the voltage of the sloping waveform is composed of a slope portion and an offset portion, the slope portion of the voltage of the sloping waveform can be input to the charge-voltage conversion section via a capacitive element, and the offset portion of the voltage of the sloping waveform can be configured to have its polarity inverted with respect to the slope portion and to be input to the comparator as a predetermined reference voltage.

[0014] In the imaging device and electronic device disclosed herein including the above-mentioned preferred configuration, the reference signal supply unit may be configured to supply a predetermined reference signal to a charge-voltage conversion unit shared among a plurality of pixels, and may be configured to include a reference signal generation unit that generates the predetermined reference signal, and an input capacitance element that applies the reference signal generated by the reference signal generation unit to the charge-voltage conversion unit of the pixel.

[0015] Furthermore, in the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, the reference signal supplying section may be configured to supply a reference signal to the charge-voltage conversion section of the pixel along the column direction of the pixel array in which the pixels are two-dimensionally arranged in a matrix. Furthermore, the reference signal generating section may be configured to be commonly arranged for all pixel columns of the pixel array in which the pixels are two-dimensionally arranged in a matrix. Furthermore, the reference signal generating section may be configured to be arranged on both sides in the column direction of the pixel array.

[0016] In addition, in the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, the reference signal supplying section may be configured to supply a reference signal to the charge-voltage conversion section of the pixel along the row direction of a pixel array in which pixels are arranged two-dimensionally in a matrix. Furthermore, the reference signal generating section may be configured to be commonly arranged for all pixel rows of the pixel array. Furthermore, the reference signal generating section may be configured to be arranged on both sides of the pixel array in the row direction.

[0017] In the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, the reference signal generation unit may be configured to supply a reference signal to the pixel's charge-voltage conversion unit on a pixel-by-pixel basis to each pixel in a pixel array in which the pixels are arranged two-dimensionally in a matrix. Also, the reference signal generation unit may be configured to supply a reference signal to the pixel's charge-voltage conversion unit along the column direction from the center of the pixel array.

[0018] In the imaging device and electronic device according to the present disclosure including the above-described preferred configuration, a buffer may be provided in front of the input capacitance element of the pixel, or the reference signal generating unit may be provided within the pixel.

[0019] In addition, in the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, when the imaging device and electronic device have a stacked semiconductor chip structure in which at least two semiconductor chips are stacked, the pixels and the comparator may be formed in different semiconductor chips. In addition, in a two-layer stacked chip structure in which a first-layer semiconductor chip and a second-layer semiconductor chip are stacked, the pixels may be formed in the first-layer semiconductor chip, and the comparator and the reference signal generating unit may be formed in the second-layer semiconductor chip. Alternatively, in a three-layer stacked chip structure in which a first-layer semiconductor chip, a second-layer semiconductor chip, and a third-layer semiconductor chip are stacked, the photoelectric conversion element may be formed in the first-layer semiconductor chip, the pixel components except the photoelectric conversion element may be formed in the second-layer semiconductor chip, and the comparator and the reference signal generating unit may be formed in the third-layer semiconductor chip.

[0020] <Imaging device to which the technology according to the present disclosure is applied> As an example of an imaging device to which the technology according to the present disclosure is applied, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a type of imaging device using an XY address method, will be described. A CMOS image sensor is an image sensor that is manufactured by applying or partially using a CMOS process.

[0021] [Example of CMOS image sensor configuration] FIG. 1 is a block diagram showing a schematic overview of the system configuration of a CMOS image sensor, which is an example of an imaging device to which the technology according to the present disclosure is applied.

[0022] The CMOS image sensor 1 according to this application example has a configuration including a pixel array section 11 and a peripheral circuit section of the pixel array section 11. The pixel array section 11 has pixels (pixel circuits) 20 including light receiving elements arranged two-dimensionally in row and column directions, that is, in a matrix. Here, the row direction refers to the arrangement direction of the pixels 20 in a pixel row, and the column direction refers to the arrangement direction of the pixels 20 in a pixel column. The pixels 20 generate and accumulate photocharges according to the amount of light received by performing photoelectric conversion.

[0023] The peripheral circuit section of the pixel array section 11 is made up of, for example, a row selection section 12, an analog-digital conversion section 13, a logic circuit section 14 as a signal processing section, a timing control section 15, and the like.

[0024] In the pixel array section 11, pixel control lines 31 (311 to 31 m ) are wired in the row direction. Also, signal lines 32 (321 to 322) are wired for each pixel column. n ) are wired in the column direction. The pixel control line 31 transmits a drive signal for driving the pixel 20 when reading out a signal. In FIG. 1, the pixel control line 31 is illustrated as a single wire, but the number of wires is not limited to one. One end of the pixel control line 31 is connected to an output terminal of the row selection section 12 corresponding to each row.

[0025] The components of the peripheral circuitry of the pixel array section 11, that is, the row selection section 12, the analog-digital conversion section 13, the logic circuit section 14, and the timing control section 15, will be described below.

[0026] The row selection unit 12 is composed of a shift register, an address decoder, etc., and controls scanning of pixel rows and addresses of pixel rows when selecting each pixel 20 in the pixel array unit 11. Although the specific configuration of the row selection unit 12 is not shown in the figure, the row selection unit 12 is generally configured to have two scanning systems, a read scanning system and a sweep scanning system.

[0027] The readout scanning system sequentially selects and scans the pixels 20 in the pixel array unit 11 row by row to read out pixel signals from the pixels 20. The pixel signals read out from the pixels 20 are analog signals. The sweep scanning system performs sweep scanning on the readout row to be read out scanned by the readout scanning system, prior to the readout scanning by the shutter speed.

[0028] The sweep-out scanning by this sweep-out scanning system sweeps out unnecessary charges from the photoelectric conversion elements of the pixels 20 in the readout row, thereby resetting the photoelectric conversion elements. Then, by sweeping out (resetting) the unnecessary charges by this sweep-out scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the operation of discarding the photoelectric charge in the photoelectric conversion element and starting a new exposure (starting the accumulation of photoelectric charge).

[0029] The analog-to-digital conversion unit 13 is made up of a set of multiple analog-to-digital converters (ADCs) provided in correspondence with (for example, for each pixel column) the pixel columns of the pixel array unit 11. The analog-to-digital conversion unit 13 connects signal lines 321 to 32 for each pixel column. n The column-parallel analog-to-digital converter converts the analog pixel signals output through each of the columns into digital signals.

[0030] As the analog-digital converter in the analog-digital conversion unit 13, for example, a single-slope analog-digital converter, which is an example of a reference signal comparison type analog-digital converter, can be used.

[0031] The logic circuit unit 14, which is a signal processing unit, reads out the pixel signals digitized by the analog-digital conversion unit 13 and performs predetermined signal processing. Specifically, the logic circuit unit 14 performs predetermined signal processing, such as correction of vertical line defects and point defects, or signal clamping, and further digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The logic circuit unit 14 outputs the generated image data to a downstream device as an output signal OUT of the CMOS image sensor 1.

[0032] The timing control unit 15 generates various timing signals, clock signals, control signals, etc. based on a synchronization signal provided from the outside. Then, the timing control unit 15 performs drive control of the row selection unit 12, the analog-digital conversion unit 13, the logic circuit unit 14, etc. based on these generated signals.

[0033] [Pixel circuit configuration example] 2 is a circuit diagram showing an example of a circuit configuration of the pixel 20. The pixel 20 has, for example, a photodiode 21 as a photoelectric conversion element. In addition to the photodiode 21, the pixel 20 has a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25.

[0034] For example, N-channel MOS field effect transistors are used as the four transistors, namely, the transfer transistor 22, the reset transistor 23, the amplifying transistor 24, and the selection transistor 25. However, the combinations of the conductivity types of the four transistors 22 to 25 illustrated here are merely examples, and are not limited to these combinations.

[0035] The pixel 20 is connected to the pixel control lines 31 (311 to 31 m), a plurality of pixel control lines are commonly wired to each pixel 20 in the same pixel row. These pixel control lines are connected to output terminals of the row selection unit 12 corresponding to each pixel row on a pixel row basis. The row selection unit 12 outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of pixel control lines as appropriate.

[0036] The photodiode 21 has an anode electrode connected to a low potential power supply (for example, ground), and photoelectrically converts received light into photocharges (here, photoelectrons) with an amount of charge corresponding to the amount of light, and accumulates the photocharges. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. Here, the region electrically connected to the gate electrode of the amplification transistor 24 is a floating diffusion (floating diffusion region / impurity diffusion region) FD. The floating diffusion FD is a charge-voltage converter that converts charge into voltage.

[0037] A high level (e.g., V DD A transfer signal TRG in which a signal level (signal level) becomes active is provided from the row selection unit 12. The transfer transistor 22 becomes conductive in response to the transfer signal TRG, and transfers the photoelectric charge that is photoelectrically converted by the photodiode 21 and accumulated in the photodiode 21 to the floating diffusion FD.

[0038] The reset transistor 23 is connected to the high-potential power supply voltage V DD A reset signal RST, which is active at a high level, is applied to the gate electrode of the reset transistor 23 from the row selection unit 12. In response to the reset signal RST, the reset transistor 23 becomes conductive and transfers the charge of the floating diffusion FD to a voltage V DD Reset the floating diffusion FD by dumping it into the node.

[0039] The gate electrode of the amplifier transistor 24 is connected to the floating diffusion FD, and the drain electrode is connected to the high-potential power supply voltage V DD The amplification transistor 24 serves as an input section of a source follower that reads out a signal obtained by photoelectric conversion in the photodiode 21. That is, the source electrode of the amplification transistor 24 is connected to a signal line 32 via a selection transistor 25.

[0040] The selection transistor 25 has a drain electrode connected to the source electrode of the amplification transistor 24, and a source electrode connected to a signal line 32. A selection signal SEL that becomes active at a high level is provided to a gate electrode of the selection transistor 25 from the row selection unit 12. The selection transistor 25 becomes conductive in response to the selection signal SEL, thereby selecting the pixel 20 and transmitting a signal output from the amplification transistor 24 to the signal line 32.

[0041] In the above circuit example, the pixel 20 is configured with a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25, i.e., a 4Tr configuration with four transistors (Tr), but the present invention is not limited to this. For example, the selection transistor 25 can be omitted and the amplification transistor 24 can have the function of the selection transistor 25, resulting in a 3Tr configuration, or the number of transistors can be increased to 5Tr or more, as necessary.

[0042] A reset signal (so-called P-phase signal) which is a reset level when the floating diffusion FD is reset by the reset transistor 23, and a data signal (so-called D-phase signal) which is a signal level based on the photoelectric conversion in the photodiode 21 are sequentially output from the pixel 20 in the above circuit configuration example. That is, the pixel signal output from the pixel 20 includes the reset signal at the time of reset and the data signal at the time of the photoelectric conversion in the photodiode 21.

[0043] [Semiconductor chip structure] Examples of the semiconductor chip structure of the CMOS image sensor 1 having the above configuration include a flat semiconductor chip structure and a stacked semiconductor chip structure. As for the pixel structure, when the substrate surface on which the wiring layer is formed is defined as the front surface (front side), the pixel structure may be a back-illuminated pixel structure that captures light irradiated from the back surface side on the opposite side, or a front-illuminated pixel structure that captures light irradiated from the front surface side.

[0044] The flat semiconductor chip structure and the stacked semiconductor chip structure will be briefly described below.

[0045] (Flat-type semiconductor chip structure) 3A is a perspective view showing a typical flat-type chip structure of the CMOS image sensor 1. As shown in FIG. 3A, the flat-type semiconductor chip structure is a structure in which each component of the peripheral circuit section of the pixel array section 11 is formed on the same semiconductor substrate 41 as the pixel array section 11, in which the pixels 20 are arranged in a matrix. Specifically, the row selection section 12, the analog-digital conversion section 13, the logic circuit section 14, the timing control section 15, and the like are formed on the same semiconductor substrate 41 as the pixel array section 11. Pads 42 for external connection and power supply are provided, for example, on both left and right ends of the first-layer semiconductor chip 41.

[0046] (Stacked semiconductor chip structure) Fig. 3B is an exploded perspective view showing a schematic diagram of the stacked semiconductor chip structure of the CMOS image sensor 1. As shown in Fig. 3B, the stacked semiconductor chip structure, or the so-called stacked structure, has at least two semiconductor chips, a first-layer semiconductor chip 43 and a second-layer semiconductor chip 44, stacked together.

[0047] In this stacked semiconductor chip structure, the first-layer semiconductor chip 43 is a pixel chip in which a pixel array section 11 is formed, in which pixels 20, each including a photoelectric conversion element (e.g., a photodiode 21), are arranged two-dimensionally in a matrix. Pads 42 for external connection and power supply are provided on, for example, both left and right ends of the first-layer semiconductor chip 43.

[0048] The second-layer semiconductor chip 44 is a circuit chip on which the peripheral circuit section of the pixel array section 11, i.e., the row selection section 12, the analog-digital conversion section 13, the logic circuit section 14, and the timing control section 15 are formed. Note that the arrangement of the row selection section 12, the analog-digital conversion section 13, the logic circuit section 14, and the timing control section 15 is merely an example, and is not limited to this arrangement example.

[0049] The pixel array section 11 on the first layer semiconductor chip 43 and the peripheral circuit section on the second layer semiconductor chip 44 are electrically connected via a Cu-Cu direct bond that directly bonds Cu electrodes together, a through silicon via (TSV), a bond (not shown) consisting of a microbump, or the like.

[0050] According to the above-described stacked semiconductor chip structure, a process suitable for fabricating the pixel array section 11 can be applied to the first-layer semiconductor chip 43, and a process suitable for fabricating the circuit section can be applied to the second-layer semiconductor chip 44. This allows the process to be optimized when manufacturing the CMOS image sensor 1. This allows the process to be optimized when manufacturing the CMOS image sensor 1. In particular, advanced processes can be applied when fabricating the circuit section.

[0051] [Example of analog-to-digital conversion section] Next, a description will be given of an example of the configuration of the analog-digital conversion unit 13. Here, it is assumed that each analog-digital converter of the analog-digital conversion unit 13 is a single-slope analog-digital converter.

[0052] 4 shows an example of the configuration of the analog-to-digital conversion unit 13. In the CMOS image sensor 1, the analog-to-digital conversion unit 13 is made up of a set of multiple single-slope analog-to-digital converters provided corresponding to each pixel column of the pixel array unit 11. Here, the single-slope analog-to-digital converter 130 in the nth column will be described as an example.

[0053] The analog-digital converter 130 has a circuit configuration including a comparator 131 and a counter 132. The single-slope analog-digital converter 130 uses a reference signal generated by a reference signal generating unit 16. The reference signal generating unit 16 is, for example, a digital-analog converter (DAC) and generates a reference signal V RAMP is generated and given as a reference signal to a comparator 131 provided for each pixel column.

[0054] The comparator 131 detects the analog pixel signal V VSL is used as a comparison input, and the ramp wave reference signal V RAMP The comparator 131 compares the two signals with each other using, for example, the reference signal V RAMP is the pixel signal V VSL When the reference signal V RAMP is the pixel signal V VSL The output goes to a second state (e.g., a low level) when: VSL The comparison result is a pulse signal having a pulse width corresponding to the signal level, specifically, the magnitude of the signal level.

[0055] The counter 132 receives a reference signal V RAMPA clock signal CLK is provided from the timing control unit 15 at the same timing as the supply start timing of the analog pixel signal V. The counter 132 performs a counting operation in synchronization with the clock signal CLK to measure the period of the pulse width of the output pulse of the comparator 131, that is, the period from the start of the comparison operation to the end of the comparison operation. The count result (count value) of the counter 132 is VSL is digitized and supplied to the logic circuit unit 14 as a digital value.

[0056] According to the analog-to-digital conversion unit 13 consisting of a set of the above-mentioned single-slope type analog-to-digital converters 130, the ramp wave reference signal V RAMP and an analog pixel signal V read out from the pixel 20 through the signal line 32. VSL A digital value can be obtained from the time information until the magnitude relationship with the signal changes.

[0057] In the above example, the analog-to-digital conversion unit 13 is configured such that the analog-to-digital converters 130 are arranged in a one-to-one correspondence with the pixel columns of the pixel array unit 11. However, it is also possible to configure the analog-to-digital converters 130 to be arranged in units of multiple pixel columns.

[0058] [About the comparator in an analog-to-digital converter] In the above-mentioned single-slope analog-digital converter 130, a comparator having a differential amplifier configuration is generally used as the comparator 131. However, in the case of a comparator having a differential amplifier configuration, it is necessary to ensure an input range according to the signal amount of the pixel 20, so that the power supply voltage V DD must be set relatively high, which results in a problem that the power consumption of the analog-to-digital converter 130, and therefore the power consumption of the CMOS image sensor 1, becomes relatively high.

[0059] In response to this, there is a conventional technique in which a P-channel MOS (Metal-Oxide-Semiconductor) transistor is provided, with an analog pixel signal input to its source electrode and a predetermined reference signal input to its gate electrode, and the load current source of the pixel (pixel circuit) is used as the current source for the comparator (see, for example, Patent Document 1). This conventional technique can reduce power consumption compared to a technique in which a current source is provided for the comparator separately from the pixel circuit.

[0060] [Prior Art Comparator] A conventional comparator will now be described.

[0061] (Example of a circuit configuration of a comparator according to the prior art) An example of the circuit configuration of a comparator according to the prior art is shown in Fig. 5. Here, for the sake of simplicity of the drawing, the circuit configuration for one pixel column is shown.

[0062] As shown in FIG. 5, a comparator 131 according to the prior art includes a capacitance element C 01 , Auto-zero switch SW AZ , input transistor PT 11 , input side load current source I 11 , output transistor PT 12 , and the output load current source I 12 The configuration is equipped with the following.

[0063] In the pixel 20, the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25 are configured as a circuit made up of, for example, N-channel MOS transistors. 11 A P-channel MOS transistor is used as the

[0064] The input transistor PT is a P-channel MOS transistor. 11 is one end of the signal line 32 and the input side load current source I 11 Specifically, the input transistor PT 11The source electrode of is connected to one end of the signal line 32, and the drain electrode of is connected to the input side load current source I 11 This connects the input transistor PT 11 The source electrode of the pixel 11 is connected to an analog pixel signal V VSL is entered.

[0065] Input side load current source I 11 The other end of the load current source I is connected to a low-potential power supply, for example, ground GND. 11 is the input transistor PT 11 and the signal line 32.

[0066] Capacitive element C 01 is the ramp reference signal V RAMP Input terminal T 11 and the input transistor PT 11 The reference signal V RAMP This acts as an input capacitance to absorb the offset. 11 The analog pixel signal V VSL is input to the source electrode through the signal line 32, and a ramp wave reference signal V RAMP is the capacitance element C 01 The signal is input to the gate electrode via

[0067] Input transistor PT 11 is the ramp wave reference signal V RAMP and the analog pixel signal V VSL The difference between the input transistor PT 11 The gate-source voltage V gs is amplified and the drain voltage V d The output is as follows:

[0068] Auto-zero switch SW AZ is the input transistor PT 11 The input terminal T 12The on (closed) / off (open) control is performed by the drive signal AZ input via the auto-zero switch SW AZ When the input transistor PT 11 The auto-zero switch SW AZ can be constructed using P-channel or N-channel MOS transistors.

[0069] Output transistor PT 12 is, for example, a P-channel MOS transistor, and is connected to one end of the signal line 32 and the output side load current source I 12 Specifically, the output transistor PT 12 The source electrode of the output side load current source I 12 This connects the output transistor PT 12 The source electrode of the pixel 11 is connected to a pixel signal V VSL is entered.

[0070] Output side load current source I 12 The other end of the load current source I is connected to a low-potential power supply, for example, ground GND. 12 is the output transistor PT 12 and the signal line 32.

[0071] Output transistor PT 12 The gate electrode of the input transistor PT 11 This connects the drain electrode of the output transistor PT 12 The gate electrode of the input transistor PT 11 A drain voltage of is input.

[0072] Output transistor PT 12 is an analog pixel signal V input to the source electrode through a signal line 32. VSL and the gate electrode of the input transistor PT 11Drain voltage V d A signal OUT indicating whether the voltage difference between the analog pixel signal V and the VSL and the ramp reference signal V RAMP As a result of the comparison with the drain electrode, 13 Output through.

[0073] The comparator 131 according to the conventional technique having the above configuration uses a load current source I 11 and the load current source I 12 The comparator 131 having this circuit configuration can reduce the power consumption of the analog-to-digital converter 130, and therefore the power consumption of the CMOS image sensor 1. In other words, the comparator 131 according to the conventional technology is a super-low power consumption type comparator.

[0074] Furthermore, in the comparator 131 according to the prior art, the input transistor PT 11 The drain-source voltage of the output transistor PT 12 The analog pixel signal V VSL and the ramp wave reference signal V RAMP The comparison result can be inverted at the timing that coincides with the change in the signal level, thereby reducing nonlinearity caused by an error in the inversion timing and improving the image quality of the image data.

[0075] (Problems with comparators related to conventional technology) As described above, the conventional comparator 131 has an input transistor PT 11 2. The signal line 32 that transmits the signal read out from the pixel 20 and the input side load current source I 11 In this way, the signal line 32 and the input side load current source I 11 Between the input transistor PT 11 By inserting the drain-source voltage V dsAs a result, the lower limit of the potential of the signal line 32 at which linearity is guaranteed increases, and the dynamic range of the entire CMOS image sensor 1 decreases.

[0076] First Embodiment of the Present Disclosure In order to solve the above problems, the CMOS image sensor 1 according to the first embodiment of the present disclosure includes a signal line 32 for transmitting a signal read from the pixel 20 and an input-side load current source I 11 The input transistor PT 11 The charge-voltage conversion unit of the pixel 20, i.e., the floating diffusion FD, is provided with a comparator 131 having a predetermined reference signal, for example, a ramp wave (inclined waveform) reference signal V that changes linearly with a predetermined slope. RAMP The reference signal supply unit supplies a reference signal.

[0077] Ramp wave reference signal V RAMP to the floating diffusion FD, the potential of the signal line 32 when the comparator 131 is inverted can be made constant regardless of the amount of incident light to the pixel 20. Since the potential of the signal line 32 when the comparator 131 is inverted (i.e., the inversion potential of the comparator 131) is constant regardless of the amount of incident light, the operating range of the node of the signal line 32 can be expanded, and as a result, the dynamic range of the entire CMOS image sensor 1 can be expanded. Furthermore, since the inversion potential of the comparator 131 is constant, a part or all of the power supply voltage of the pixel 20 can be lowered compared to the case of a comparator according to the conventional technology, the power consumption of the entire CMOS image sensor 1 can be reduced.

[0078] [Example of circuit configuration for one pixel column including comparators] FIG. 6 shows an example of a circuit configuration for one pixel column including comparators in the CMOS image sensor 1 according to the first embodiment of the present disclosure.

[0079] The CMOS image sensor 1 according to the first embodiment of the present disclosure is composed of, for example, P-channel MOS transistors, and is connected to one end of a signal line 32 and an input-side load current source I11 The input transistor PT 11 The comparator 131 has an input transistor PT 11 The source electrode is connected to one end of the signal line 32, and the drain electrode is connected to the input side load current source I 11 This connects the input transistor PT 11 The source electrode of the pixel 11 is connected to an analog pixel signal V VSL is input to the input transistor PT 11 In the case of the above, it is desirable to short-circuit the back gate and the source electrode in order to suppress the back gate effect.

[0080] The comparator 131 has an input transistor PT 11 In addition, the capacitance element C 01 , Auto-zero switch SW AZ , input side load current source I 11 , capacitance element C 02 , input clamp transistor PT 13 , input clamp transistor NT 11 , output transistor PT 12 , output load current source I 12 , and the output clamp transistor NT 12 The capacitance element C 01 is the input transistor PT 11 and a node of a predetermined reference voltage.

[0081] Here, the input transistor PT 11 The gate electrode of the capacitance element C 01 By inputting a fixed voltage (e.g., ground GND) as a predetermined reference voltage through RAMP Compared to when the capacitance element C 01 The advantage is that the size of the

[0082] Auto-zero switch SW AZ is the input transistor PT 111. The input terminal T 12 The on / off control is performed by the drive signal AZ input via the auto-zero switch SW AZ When the input transistor PT 11 The auto-zero switch SW AZ can be constructed using P-channel or N-channel MOS transistors.

[0083] Input side load current source I 11 One end of the transistor PT 11 The other end is connected to the drain electrode of the input side load current source I 11 is the input transistor PT 11 and the signal line 32.

[0084] Capacitive element C 02 is the input transistor PT 11 Specifically, the capacitance element C 02 One end of the input transistor PT 11 is connected to the source electrode of the capacitance element C 02 The other end of the input transistor PT 11 The drain electrode of the capacitance element C 02 is the bandwidth limiting capacity.

[0085] Input clamp transistor PT 13 is, for example, a P-channel MOS transistor, and the input transistor PT 11 The input clamp transistor PT 13 The input transistor PT 11 When the input transistor PT is in a non-conducting state, 11 This serves to suppress the decrease in the drain voltage.

[0086] Input clamp transistor NT 11 For example, the input transistor PT 11 The source electrode of the input transistor PT 11 The drain electrode of the input clamp transistor NT 11 A predetermined bias voltage bias1 is applied to the gate electrode of the input transistor PT 11 Drain voltage V d Therefore, it is possible to directly prevent the supply of the drain current from being stopped.

[0087] Output transistor PT 12 is, for example, a P-channel MOS transistor, and is connected to one end of the signal line 32 and the output side load current source I 12 Specifically, the output transistor PT 12 The source electrode of the output side load current source I 12 This connects the output transistor PT 12 The source electrode of the pixel 11 is connected to a pixel signal V VSL is input to the output transistor PT 12 In the case of the above, it is desirable to short-circuit the back gate and the source electrode in order to suppress the back gate effect.

[0088] Output side load current source I 12 One end is connected to the output transistor PT 12 The other end is connected to the drain electrode of the output side load current source I 12 is the output transistor PT 12 and the signal line 32.

[0089] Output transistor PT 12 The gate electrode of the input transistor PT 11This connects the drain electrode of the output transistor PT 12 The gate electrode of the input transistor PT 11 A drain voltage of is input.

[0090] Output transistor PT 12 is an analog pixel signal V input to the source electrode through a signal line 32. VSL and the gate electrode of the input transistor PT 11 Drain voltage V d A signal OUT indicating whether the voltage difference between the analog pixel signal V and the VSL and the ramp reference signal V RAMP As a result of the comparison with the drain electrode, 13 Output through.

[0091] Output clamp transistor NT 12 For example, the output transistor PT 12 The source electrode of the output transistor PT 12 The drain electrode of the output clamp transistor NT 12 A predetermined bias voltage bias2 is applied to the gate electrode of the output clamp transistor NT 12 is the output transistor PT 12 Therefore, the lower limit of the drain voltage can be limited.

[0092] As described above, the comparator 131 of the CMOS image sensor 1 according to the first embodiment has, as a current source of the comparator 131 according to the conventional art, an input side load current source I 11 and the output load current source I 12 The comparator 131 having this circuit configuration can reduce the power consumption of the analog-to-digital converter 130, and therefore the power consumption of the CMOS image sensor 1. In other words, the comparator 131 according to the conventional technology is a super-low power consumption type comparator.

[0093] The CMOS image sensor 1 according to the first embodiment includes a signal line 32 and an input-side load current source I 11 The input transistor PT 11 In addition to the comparator 131 having the above configuration, a predetermined reference signal, for example, a ramp wave reference signal V RAMP The reference signal supply unit 50 supplies the reference signal.

[0094] The reference signal supply unit 50 supplies a ramp wave reference signal V RAMP and a reference signal generator 51 that generates a ramp wave reference signal V RAMP The reference signal generating unit 51 generates a reference signal V RAMP (That is, the input transistor PT 11 The reference signal V RAMP ) is a reference signal V RAMP Generate.

[0095] 7 shows a timing chart for explaining the operation of the CMOS image sensor 1 according to the first embodiment. The timing chart in FIG. 7 shows a selection signal SEL for driving the selection transistor 25 of the pixel 20, a reset signal RST for driving the reset transistor 23, a transfer signal TRG for driving the transfer transistor 22, and an analog pixel signal V VSL The timing chart in FIG. 7 further shows the timing relationship between the reference signal V RAMP , Auto-zero switch SW AZ The driving signal AZ and the pixel signal V after the ramp wave is superimposed VSL 4 shows the timing relationship between the

[0096] As described above, the ramp wave reference signal V generated by the reference signal generating unit 51 RAMPis applied to the floating diffusion FD via the input capacitance element 52, and as shown in FIG. 8A, a ramp wave reference signal V RAMP The pixel signal V VSL In the column-parallel analog-to-digital converter 13, the comparator 131 provided for each pixel column reads out the ramp wave reference signal V RAMP The pixel signal V VSL and the input transistor PT 11 As a result, the comparator 131 outputs a ramp wave reference signal V RAMP Based on the timing when the pixel signal V VSL A pulse signal having a pulse width according to the signal level, specifically, a pulse width corresponding to the magnitude of the signal level, is output as the comparison result.

[0097] <Second embodiment of the present disclosure> In the CMOS image sensor 1 according to the first embodiment, the reference signal V RAMP As a reference signal V RAMP (That is, the input transistor PT 11 The reference signal V RAMP The reference signal V RAMP In the case of a signal having a waveform obtained by inverting the ramp waveform in the above, it is necessary to set the settling periods of the reset signal (P-phase signal) and the data signal (D-phase signal) longer.

[0098] To ensure linearity and ensure inversion, the ramp reference signal V RAMP In other words, the ramp reference signal V RAMPconsists of a slope portion and an offset portion. The reason is that the step of the offset portion dulls the waveform in the signal line 32 due to the large time constant of the signal line 32, and it becomes necessary to wait for the settling. However, if the settling period of the reset signal (P-phase signal) and the data signal (D-phase signal) is extended, the total time required for analog-to-digital conversion in the column-parallel analog-to-digital conversion unit 13+ increases accordingly, which results in a decrease in the frame rate and a deterioration in the average power when the power consumption is averaged over time.

[0099] In order to solve this problem, in the CMOS image sensor 1 according to the second embodiment of the present disclosure, a ramp wave reference signal V RAMP The offset part is separated from the ramp waveform and inverted upside down, and the capacitance element C 01 Through the input transistor PT 11 The gate electrode of the first gate electrode is supplied with the first gate electrode.

[0100] [Example of circuit configuration for one pixel column including comparators] FIG. 9 shows an example of a circuit configuration for one pixel column including a comparator of the CMOS image sensor 1 according to the second embodiment of the present disclosure, and FIG. 10 shows a timing chart for explaining the operation of the CMOS image sensor 1 according to the second embodiment.

[0101] In the CMOS image sensor 1 according to the second embodiment, the reference signal generating unit 51 generates a ramp wave reference signal V RAMP is separated into a slope portion and an offset portion, and the slope portion is compared with the reference signal V RAMP1 The offset part is inverted upside down to produce the reference signal V RAMP2 The reference signal for the slope part V RAMP1 is applied to the floating diffusion FD via the input capacitance element 52. The offset portion is a reference signal V RAMP2 is the input terminal T 11 and the capacitance element C 01 Through the input transistor PT11 A predetermined reference voltage is supplied to the gate electrode of each of the transistors.

[0102] As described above, in the CMOS image sensor 1 according to the second embodiment, the reference signal V RAMP The offset part is separated from the ramp waveform and inverted upside down, and the capacitance element C 01 Through the input transistor PT 11 This supplies the pixel signal V VSL The reference signal V RAMP1 Since the offset portion does not have a step, the waveform does not become dull on the signal line 32 due to the large time constant of the signal line 32, and there is no need to wait for the signal line 32 to settle. 11 The gate-source voltage V gs The waveform of “V RAMP1 -V RAMP2 ", which is the original ramp wave reference signal V RAMP Therefore, in terms of circuit operation, the same output as in the case of the CMOS image sensor 1 according to the first embodiment can be obtained.

[0103] <Third embodiment of the present disclosure> In the third embodiment of the present disclosure, in a CMOS image sensor 1 in which a pixel circuit subsequent to a floating diffusion FD, which is a charge-voltage conversion unit, is shared among a plurality of pixels, a ramp wave reference signal V RAMP This is an example that supplies

[0104] [Example of circuit configuration for one pixel column including comparators] FIG. 11 shows an example of a circuit configuration for one pixel column including comparators in the CMOS image sensor 1 according to the third embodiment of the present disclosure.

[0105] 11, for example, a pixel circuit after a floating diffusion FD is shared among four pixels. Specifically, the four pixels are a first pixel including a photodiode 211 and a transfer transistor 221, a second pixel including a photodiode 212 and a transfer transistor 222, a third pixel including a photodiode 213 and a transfer transistor 223, and a fourth pixel including a photodiode 214 and a transfer transistor 224.

[0106] These first to fourth pixels share the pixel circuit after the floating diffusion FD, that is, the floating diffusion FD, the reset transistor 23, the amplification transistor 24, and the selection transistor 25. In the CMOS image sensor 1 according to the third embodiment, a ramp reference signal V generated by a reference signal generating unit 51 is applied to the floating diffusion FD shared among the four pixels. RAMP is applied via an input capacitance element 52.

[0107] In the CMOS image sensor 1 according to the third embodiment of the pixel sharing, a ramp reference signal V RAMP By applying this voltage, it is possible to obtain the same functions and effects as in the case of the CMOS image sensor 1 according to the first embodiment.

[0108] Here, the case where the technique according to the first embodiment is applied to the CMOS image sensor 1 according to the third embodiment shared between pixels has been described as an example. However, the technique according to the second embodiment, that is, the ramp wave reference signal V RAMP The offset part is separated from the ramp waveform and inverted upside down, and the capacitance element C 01 Through the input transistor PT 11 It is also possible to apply a technique for supplying the gate electrode of the semiconductor device to the semiconductor device.

[0109] <Example of the configuration of the reference signal supply unit> Next, for example, in the CMOS image sensor 1 according to the first embodiment, the ramp wave reference signal V RAMP A specific example of the configuration of the reference signal supplying unit 50 that supplies the reference signal to the floating diffusion FD will be described below.

[0110] [Example 1] In the first embodiment, a ramp wave reference signal V RAMP In this example, the reference signal supply unit supplies the reference signal in the column direction of the pixel array in matrix form. FIG.

[0111] In FIG. 12, in correspondence with the circuit configuration example of FIG. 6, etc., the reference signal supply unit 50 (501 to 50 n ) input capacitance element 52 corresponding to each pixel of the pixel array of m rows and n columns, 11 ~C 11 The resistors shown by the symbols of resistive elements represent the wiring resistance of the reference signal supplying section 50. These points are the same in each of the embodiments described later.

[0112] In the reference signal supply unit 50 according to the first embodiment, the reference signal generation unit 51 includes current integration type digital-to-analog converters 531 to 533 provided for each pixel column. n current integration type digital-to-analog converters 531 to 53 n The current integration capacitance is arranged for each pixel along the column direction for each pixel, and the ramp wave reference signal V RAMP The input capacitance element 52 is configured as follows.

[0113] According to the configuration example of the reference signal supply unit 50 according to the first embodiment, a ramp wave reference signal V RAMP Since the wiring is separated, interference through the wiring can be kept extremely small.

[0114] [Example 2] The second embodiment is a modification of the first embodiment, and is an example in which the reference signal generator 51 is commonly disposed for all pixel columns. An example of the configuration of a reference signal supply unit according to the second embodiment is shown in FIG.

[0115] In the reference signal supply unit 50 according to the second embodiment, a reference signal generation unit 51 is commonly arranged for all pixel columns. RAMP A current steering type digital-to-analog converter or a current integration type digital-to-analog converter can be used as the reference signal generating unit 51 that generates the ramp wave reference signal V RAMP Buffers 541 to 54 n to each pixel column.

[0116] According to the configuration example of the reference signal supply unit 50 according to the second embodiment, a ramp wave reference signal V RAMP The wiring is buffer 541~54 n Although the current consumption increases, the ramp wave reference signal V RAMP In addition, the reference signal V RAMP Since the pixel columns are generated, the mismatch between the pixel columns can be reduced.

[0117] [Example 3] The third embodiment is a modification of the second embodiment, in which a reference signal generator 51 is commonly arranged for all pixel columns, and the reference signal V RAMP An example of the configuration of a reference signal supply unit according to the third embodiment is shown in FIG.

[0118] In the reference signal supply unit 50 according to the third embodiment, a reference signal generation unit 51 is commonly arranged for all pixel columns, and a ramp wave reference signal V RAMP , the ramp wave reference signal V RAMP The reference signal V RAMPA current steering type digital-to-analog converter or a current integration type digital-to-analog converter can be used as the reference signal generating unit 51 that generates the reference signal.

[0119] According to the reference signal supplying unit 50 of the third embodiment, the ramp wave reference signal V RAMP Between the wiring and the reference signal supply unit 50, the buffers 541 to 54 of the second embodiment are n Since no buffer is provided for each pixel column, the power consumption can be reduced compared to the reference signal supply unit 50 according to the second embodiment. n Since there is no intervening gap, mismatch between pixel columns can be minimized.

[0120] [Example 4] Example 4 is a modification of Example 3, and is an example in which the pixel array in matrix is ​​driven from both the top and bottom sides. An example of the configuration of a reference signal supply unit according to Example 4 is shown in FIG.

[0121] In the reference signal supply unit 50 according to the fourth embodiment, reference signal generation units 51 are provided on both the top and bottom sides in the pixel column direction of the pixel array in a matrix. 1_1 ,51 1_2 The matrix pixel array is driven from both the top and bottom, that is, the generated ramp wave reference signal V RAMP In this configuration, an example of the configuration of the reference signal supply unit for both top and bottom drive is shown, but the present invention is not limited to this configuration. When the reference signal is supplied from both the top and bottom of the matrix pixel array, the timing may be slightly shifted between the top and bottom due to delays in the control signal, etc., but the reference signal V RAMP Since this is a ramp wave, there is no operational problem even if the timing is slightly off.

[0122] According to the reference signal supply unit 50 of the fourth embodiment, the reference signal V RAMP By supplying the signal, the maximum delay amount can be reduced, and the maximum value of shading and interference and the difference between the upper and lower portions can be suppressed, thereby improving image quality.

[0123] [Example 5] In the fifth embodiment, a ramp wave reference signal V RAMP In this example, the reference signal supply unit supplies the reference signal in the row direction of the pixel array in matrix form. FIG. 16 shows an example of the configuration of a reference signal supply unit according to the fifth embodiment.

[0124] In the reference signal supply unit 50 according to the fifth embodiment, the reference signal generation unit 51 includes current integration type digital-to-analog converters 531 to 533 provided for each pixel row. n current integration type digital-to-analog converters 531 to 53 n The current integration capacitance is arranged for each pixel along the row direction for each pixel row, and the ramp wave reference signal V RAMP The input capacitance element 52 is configured as follows.

[0125] According to the configuration example of the reference signal supplying unit 50 according to the fifth embodiment, the ramp wave reference signal V RAMP Since the wiring is not separated for each pixel column, the ramp wave reference signal V RAMP Although interference via the wiring is more likely to occur than in the case where the wiring is separated, it is possible to keep power consumption low because it is necessary to drive only the pixel row that is reading out the pixel signals.

[0126] [Example 6] Example 6 is a modification of Example 5, and is an example in which the pixel array in matrix is ​​driven from both the left and right sides. An example of the configuration of a reference signal supply unit according to Example 6 is shown in FIG.

[0127] In the reference signal supply unit 50 according to the sixth embodiment, current integration type digital-to-analog converters 53 are provided on both the left and right sides in the pixel row direction of the matrix pixel array. 1_1 ~53 m_1 ,53 1_2 ~53 m_2 is arranged and driven from both the left and right sides of the matrix pixel array, that is, the generated ramp wave reference signal V RAMPis supplied for each pixel row. Here, an example of the configuration of the reference signal supply unit for both left and right drive is shown, but the present invention is not limited to this configuration. When the reference signal is supplied from both the left and right sides of the matrix pixel array, the timing may be slightly shifted between the left and right due to delays in the control signals, etc. RAMP Since this is a ramp wave, there is no operational problem even if the timing is slightly off.

[0128] According to the reference signal supply unit 50 of the sixth embodiment, the ramp wave reference signal V RAMP By supplying the above, the maximum delay amount can be reduced, and the maximum value of shading and interference and the difference between the left and right sides can be suppressed, thereby improving image quality.

[0129] [Example 7] The seventh embodiment is a modification of the fifth embodiment, in which a reference signal generator 51 is commonly arranged for all pixel rows, and the reference signal V RAMP to each pixel row. An example of the configuration of a reference signal supply unit according to the seventh embodiment is shown in FIG.

[0130] In the reference signal supply unit 50 according to the seventh embodiment, the reference signal generation unit 51 is commonly arranged for all pixel rows, and the ramp wave reference signal V RAMP , the ramp wave reference signal V RAMP Switches S1 to S m The ramp reference signal V RAMP A current steering type digital-to-analog converter or a current integration type digital-to-analog converter can be used as the reference signal generating unit 51 that generates the reference signal.

[0131] According to the reference signal supplying unit 50 of the seventh embodiment, the ramp wave reference signal V RAMP Since the wiring is not separated for each pixel column, the ramp wave reference signal V RAMPAlthough interference via the wiring is more likely to occur than when the wiring is separated, the switches S1 to S m In addition, the reference signal V RAMP This reduces mismatches between pixel rows.

[0132] [Example 8] Example 8 is a modification of Example 7, and is an example in which the pixel array in matrix is ​​driven from both the left and right sides. An example of the configuration of a reference signal supply unit according to Example 8 is shown in FIG.

[0133] In the reference signal supply unit 50 according to the eighth embodiment, a reference signal generation unit 51 is provided on both the left and right sides in the pixel row direction of the matrix pixel array. 1_1 ,51 1_2 is arranged and driven from both the left and right sides of the matrix pixel array, that is, the generated ramp wave reference signal V RAMP is supplied for each pixel row. Here, an example of the configuration of the reference signal supply unit for both left and right drive is shown, but the present invention is not limited to this configuration. When the reference signal is supplied from both the left and right sides of the matrix pixel array, the timing may be slightly shifted between the left and right due to delays in the control signals, etc. RAMP Since this is a ramp wave, there is no operational problem even if the timing is slightly off.

[0134] According to the reference signal supply unit 50 of the eighth embodiment, the ramp wave reference signal V RAMP By supplying the above, the maximum delay amount can be reduced, and the maximum value of shading and interference and the difference between the left and right sides can be suppressed, thereby improving image quality.

[0135] [Example 9] In the ninth embodiment, a reference signal V RAMP 20 shows an example of a configuration of a reference signal supplying unit according to the ninth embodiment.

[0136] In the reference signal supply unit 50 according to the ninth embodiment, a reference signal generation unit 51 is provided in common for all pixels, and a ramp wave reference signal V RAMP is supplied to all pixels in a pixel unit in a mesh shape. As the reference signal generating unit 51, a current steering type digital-analog converter or a current integration type digital-analog converter can be used.

[0137] According to the configuration example of the reference signal supplying unit 50 according to the ninth embodiment, the ramp wave reference signal V RAMP Since the wiring is not separated for each pixel column, the ramp wave reference signal V RAMP Although there is a possibility of interference through the wiring compared to when the wiring is separated, the reference signal V RAMP Since no buffer is interposed between the wiring and the reference signal generating unit 51, power consumption can be kept small. RAMP , the mismatch between pixel rows / pixel columns can be minimized.

[0138] [Example 10] The tenth embodiment is a modification of the ninth embodiment, and the reference signal V RAMP In this example, a buffer is interposed between the wiring and the reference signal generating unit 51. An example of the configuration of a reference signal supplying unit according to the tenth embodiment is shown in FIG.

[0139] In the reference signal supply unit 50 according to the tenth embodiment, a ramp wave reference signal V RAMP Under the configuration that supplies the reference signal V RAMP Buffers 541 to 54 are provided between the wiring and the reference signal generating unit 51. n As the reference signal generating unit 51, a current steering type digital-to-analog converter or a current integration type digital-to-analog converter can be used.

[0140] According to the configuration example of the reference signal supply unit 50 according to the tenth embodiment, the reference signal VRAMP Buffers 541 to 54 are provided between the wiring and the reference signal generating unit 51. n Although the power consumption increases compared to when there is no intervening signal, the settling can be improved and the ramp wave reference signal V RAMP In addition, the reference signal V RAMP , the mismatch between pixel rows / pixel columns can be minimized.

[0141] [Example 11] In the eleventh embodiment, a ramp wave reference signal V RAMP In this example, the reference signal supply unit supplies the reference signal from the center of the pixel array in matrix along the column direction. FIG. 22 shows an example of the configuration of a reference signal supply unit according to the eleventh embodiment.

[0142] In the reference signal supply unit 50 according to the eleventh embodiment, a reference signal generation unit 51 is provided outside the pixel matrix near the center of the pixel matrix in common with respect to all pixels, and a ramp wave reference signal V RAMP Switch S 11 ,S 12 and wiring L 11 ,L 12 The reference signal generating unit 51 may be a current steering type digital-to-analog converter or a current integration type digital-to-analog converter.

[0143] A ramp wave reference signal V along the pixel column direction RAMP The upper and lower wiring that supplies 11 ,L 12 can be electrically connected at the center of the matrix pixel array by a connection portion 55 such as a Cu-Cu direct bond.

[0144] According to the configuration example of the reference signal supply unit 50 according to the eleventh embodiment, a ramp wave reference signal V RAMPBy supplying the reference signal to the reference signal generating unit 51, the wiring of the upper half or the lower half of the pixel array in matrix from which pixel signals are not read out can be separated. As a result, the load resistance and load capacitance of the reference signal generating unit 51 can be halved, thereby reducing the power consumption of the reference signal generating unit 51 and, ultimately, the power consumption of the entire CMOS image sensor 1.

[0145] <Pixel circuit configuration example> Next, a ramp wave reference signal V RAMP An example of the circuit configuration of a pixel circuit to which the voltage is applied will be described.

[0146] [Circuit configuration example 1] Circuit configuration example 1 is an example in which a buffer is provided before the input capacitance element 52. A circuit diagram of a pixel circuit according to circuit configuration example 1 is shown in FIG.

[0147] In the pixel circuit according to the circuit configuration example 1, a ramp reference signal V RAMP to the floating diffusion FD via the input capacitance element 52. The buffer 56 has a source follower configuration including a constant current source transistor 57 and an input transistor 58.

[0148] In the source-follower buffer 56, a constant current source transistor 57 is connected between the anode electrode of the photodiode 21 and the input terminal of the input capacitance element 52, and a predetermined bias voltage V BIAS The input transistor 58 is connected between a node at a predetermined potential and the input end of the input capacitance element 52, and a ramp reference signal V RAMP is applied.

[0149] Here, consider the case where the buffer 56 is not provided in front of the input capacitance element 52. If the buffer 56 is not provided in front of the input capacitance element 52, it is considered that the signal may flow back from the pixel circuit side to the reference signal generation unit 51 side, making it easier for interference to occur.

[0150] In contrast, the pixel circuit according to circuit configuration example 1 has buffer 56 provided in front of input capacitance element 52, thereby making it possible to suppress interference caused by a signal flowing back from the pixel circuit side to reference signal generation unit 51 side. In addition, since the load on buffer 56 in the source follower configuration is minimized, the power consumption of buffer 56 can be kept low.

[0151] [Circuit configuration example 2] Circuit configuration example 2 is an example in which constant current source transistor 57 of the buffer is provided on a chip separate from the pixel. A circuit diagram of a pixel circuit according to circuit configuration example 2 is shown in FIG.

[0152] The pixel circuit according to circuit configuration example 2 is based on the stacked semiconductor chip structure shown in FIG. 3B, and when providing a source-follower buffer 56 within the pixel, a constant current source transistor 57 is provided on a chip separate from the pixel chip (corresponding to the first-layer semiconductor chip 43 shown in FIG. 3B), i.e., on a circuit chip (corresponding to the second-layer semiconductor chip 44 shown in FIG. 3B).

[0153] The pixel chip and the circuit chip are electrically connected via a joint 61 consisting of, for example, a Cu-Cu direct joint that directly joins Cu electrodes together. On the pixel chip side, a switching transistor 59 is connected between the joint 61 and the input end of the input capacitance element 52, and a selection signal SEL is applied to the gate electrode of the switching transistor 59. On the circuit chip side, a sample / hold circuit 60 is connected to the gate electrode of the constant current source transistor 57.

[0154] According to the pixel circuit of circuit configuration example 2, the sample / hold circuit 60, which is difficult to arrange within a pixel due to spatial constraints, can be connected to the gate electrode of the constant current source transistor 57 on the circuit chip side, so that bias noise can be blocked and output noise can be suppressed.

[0155] [Circuit configuration example 3] Circuit Configuration Example 3 is an example in which a reference signal generating unit is provided within a pixel. A circuit diagram of a pixel circuit according to Circuit Configuration Example 3 is shown in FIG.

[0156] In the pixel circuit according to circuit configuration example 3, input capacitance element 52 provided for each pixel is used as a capacitance element for current integration, and a current integration digital-to-analog converter (DAC) for generating a reference signal is formed within the pixel together with constant current source transistor 71 made of a P-channel MOS transistor. A reset transistor 72 is connected between the input end of input capacitance element 52 and the anode electrode of photodiode 21, and a reset signal RST is applied to the gate electrode of reset transistor 72.

[0157] According to the pixel circuit of circuit configuration example 3, input capacitance element 52 is used as a capacitance element for current integration, and a current integration DAC for generating a reference signal is formed within the pixel. This eliminates the need to form a current integration DAC for generating a reference signal on the circuit chip, thereby enabling the circuit chip to be miniaturized, and ultimately the entire stacked semiconductor chip to be miniaturized.

[0158] <Example of inter-chip wiring structure in stacked semiconductor chip structure> Next, an example of an electrical wiring structure between semiconductor chips in a stacked semiconductor chip structure in which a plurality of semiconductor chips are stacked will be described.

[0159] [Wiring structure example 1] Wiring structure example 1 is an example of an electrical wiring structure between chips in a two-layer stacked chip structure. An example of the inter-chip wiring structure according to wiring structure example 1 is shown in Fig. 26. The left side of Fig. 26 shows a plan view of a semiconductor chip, and the right side of Fig. 26 shows a schematic diagram of the wiring structure of each semiconductor chip. This point is the same for each wiring structure example described later.

[0160] The inter-chip wiring structure according to wiring structure example 1 has a two-layer laminated chip structure in which a first-layer semiconductor chip 43 and a second-layer semiconductor chip 44 are laminated. The first-layer semiconductor chip 43 is a pixel chip in which pixels 20 including photodiodes 21 are formed. The second-layer semiconductor chip 44 is a circuit chip in which comparators 131 constituting a column-parallel analog-digital conversion unit 13 and a reference signal generation unit 51 consisting of, for example, a digital-analog converter (DAC) are formed.

[0161] The first-layer semiconductor chip 43, which is a pixel chip, and the second-layer semiconductor chip 44, which is a circuit chip, receive a ramp reference signal V RAMP For each floating diffusion FD to which the reference signal V is supplied, for example, a Cu electrode 61a and a Cu electrode 61b are directly connected to each other via a junction 61 formed of a Cu-Cu direct junction. RAMP The distribution of the wiring L 13 Furthermore, the signal lines 32 on the semiconductor chip 43 in the first layer and the comparators 131 on the semiconductor chip 44 in the second layer are electrically connected for each pixel column via connection parts 63. This also applies to wiring structure examples 2 and 3 described later.

[0162] [Wiring structure example 2] The wiring structure example 2 is an example in which, in a two-layer laminated chip structure, electrical connection between chips is made at the output section of the reference signal generating section 51. An example of the inter-chip wiring structure according to the wiring structure example 2 is shown in FIG.

[0163] In the inter-chip wiring structure according to the wiring structure example 2, the output section of the reference signal generating section 51 formed in the semiconductor chip 44 in the second layer, which is the circuit chip, is electrically connected to the semiconductor chip 43 in the first layer, which is the pixel chip, via a joint 61 made of Cu-Cu direct bonding. In the case of the wiring structure example 2, the ramp wave reference signal V RAMP The distribution of the wiring L 14 As shown by black circles (●) on the first-layer semiconductor chip 43 in the left diagram of FIG. 14 The input capacitance element 52 is electrically connected to the wiring structure example 2. The wiring structure example 2 has an advantage in that it is not necessary to provide the junction 61 directly below the pixel.

[0164] [Wiring structure example 3] The third wiring structure example is an example in which a reference signal generating unit 51 is provided for each pixel in a two-layer stacked chip structure. An example of an inter-chip wiring structure according to the third wiring structure example is shown in FIG.

[0165] In the inter-chip wiring structure according to the wiring structure example 3, the first-layer semiconductor chip 43, which is a pixel chip, has a reference signal generating unit 51 for each pixel. The second-layer semiconductor chip 44, which is a circuit chip, has a ramp wave reference signal V RAMP The bias voltage generated by the bias generation unit 62 is transmitted to the first-layer semiconductor chip 43 via a joint 61 formed of, for example, a Cu-Cu direct joint, and is then connected to a wiring L of the reference signal generation unit 51 provided for each pixel in the first-layer semiconductor chip 43. 14 Powered by.

[0166] [Wiring structure example 4] The fourth wiring structure example is an example of an electrical wiring structure between chips in a three-layer stacked chip structure. An example of the inter-chip wiring structure according to the fourth wiring structure example is shown in FIG.

[0167] The inter-chip wiring structure according to wiring structure example 4 has a three-layer stacked chip structure in which a first-layer semiconductor chip 43, a second-layer semiconductor chip 44, and a third-layer semiconductor chip 45 are stacked. In the first-layer semiconductor chip 43, photodiodes 21 and transfer transistors 22 are arranged in pixel units. In the second-layer semiconductor chip 44, components of the pixels 20 except for the photodiodes 21 and transfer transistors 22 are formed. In the three-layer semiconductor chip 45, comparators 131 constituting the column-parallel analog-digital conversion unit 13 and a reference signal generation unit 51 consisting of, for example, a digital-analog converter (DAC) are formed.

[0168] The first-layer semiconductor chip 43 and the second-layer semiconductor chip 44 are electrically connected for each pixel via a connection portion 64 made of Cu-Cu direct bonding or a through-silicon via (TSV) or the like. This is also the case in wiring structure examples 5 and 6 described later. The second-layer semiconductor chip 44 and the third-layer semiconductor chip 45 are connected to each other by a ramp reference signal V RAMP is supplied to each floating diffusion FD, the floating diffusion FD is electrically connected via a joint 61 formed of, for example, Cu-Cu direct bonding. The semiconductor chip 44 in the second layer and the semiconductor chip 45 in the third layer are electrically connected via a connection 65 for each pixel column. This is also the case in wiring structure examples 5 and 6 described later. In the case of wiring structure example 4, the ramp wave reference signal V RAMP The distribution of the wiring L 13 This will be carried out through.

[0169] According to the inter-chip wiring structure of wiring structure example 4, the first-layer semiconductor chip 43 only has the photodiode 21 and the transfer transistor 22 formed thereon, so that the pixel aperture ratio can be set large. This point is also the same in wiring structure example 5 and wiring structure example 6 described later.

[0170] [Wiring structure example 5] The fifth wiring structure example is an example in which, in a three-layer stacked chip structure, electrical connection between chips is made at the output section of the reference signal generating section 51. An example of an inter-chip wiring structure according to the fifth wiring structure example is shown in FIG.

[0171] In the inter-chip wiring structure according to the wiring structure example 5, the output section of the reference signal generating section 51 formed in the three-layer semiconductor chip 45 is electrically connected to the second-layer semiconductor chip 44 via a joint section 61 formed of a Cu-Cu direct bond. In the case of the wiring structure example 5, the ramp wave reference signal V RAMP The distribution of the wiring L 14 This will be carried out through.

[0172] [Wiring structure example 6] The sixth wiring structure example is an example in which a reference signal generating unit 51 is provided for each pixel in a three-layer stacked chip structure. An example of an inter-chip wiring structure according to the sixth wiring structure example is shown in FIG.

[0173] In the inter-chip wiring structure according to the wiring structure example 6, the second-layer semiconductor chip 44 has a reference signal generating unit 51 for each pixel. In the third-layer semiconductor chip 45, the reference signal generating unit 51 generates a ramp wave reference signal V RAMP The bias voltage generated by the bias generation unit 62 is transmitted to the second-layer semiconductor chip 44 via a joint 61 formed of, for example, Cu-Cu direct bonding, and is then connected to the reference signal generation unit 51 provided for each pixel in the second-layer semiconductor chip 44 via a wiring L. 14 Powered by.

[0174] <Modification> Although the technology according to the present disclosure has been described above based on preferred embodiments, the technology according to the present disclosure is not limited to these embodiments. The configurations and structures of the imaging devices described in the above embodiments are merely examples and can be modified as appropriate.

[0175] For example, the circuit configuration of the comparator 131 in each of the above embodiments is merely an example, and the present invention is not limited to the above circuit configuration. 02 , input clamp transistor PT 13 , input clamp transistor NT 11 , and the output clamp transistor NT 12 The circuit may have a configuration in which at least one of the above is omitted.

[0176] <Application Examples> The imaging device according to the present embodiment described above can be used in various devices for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, as shown in Fig. 32. Specific examples of various devices are listed below.

[0177] ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as on-board sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving (such as automatic stopping) and for recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles, etc. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices that take blood vessel images using infrared light - Equipment used for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication - Devices used for beauty purposes, such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp - Devices used for sports, such as action cameras and wearable cameras for sports use Agricultural equipment such as cameras for monitoring fields and crop conditions

[0178] <Application examples of the technology disclosed herein> The technology according to the present disclosure can be applied to various products. More specific application examples will be described below.

[0179] [Electronic device of the present disclosure] Here, the present invention will be described as being applied to imaging systems such as digital still cameras and video cameras, portable terminal devices having an imaging function such as mobile phones, and electronic devices such as copiers that use an imaging device in an image reading section.

[0180] (Example of imaging system) FIG. 33 is a block diagram showing an example of the configuration of an imaging system that is an example of the electronic device of the present disclosure.

[0181] 33, an imaging system 100 according to this example includes an imaging optical system 101 including a lens group and the like, an imaging unit 102, a DSP (Digital Signal Processor) circuit 103, a frame memory 104, a display device 105, a recording device 106, an operation system 107, and a power supply system 108. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.

[0182] The imaging optical system 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102. The imaging unit 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal. The DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.

[0183] The frame memory 104 is used to store data as appropriate during signal processing in the DSP circuit 103. The display device 105 is made up of a panel-type display device such as a liquid crystal display device or an organic EL (electro luminescence) display device, and displays moving images or still images captured by the imaging unit 102. The recording device 106 records the moving images or still images captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disc, or an HDD (Hard Disk Drive).

[0184] An operation system 107, under the operation of a user, issues operation commands for various functions of the imaging device 100. A power supply system 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display device 105, recording device 106, and operation system 107 as operating power sources to these devices.

[0185] In the imaging system 100 having the above configuration, the imaging device according to the embodiment described above can be used as the imaging unit 102. According to the imaging device, the power consumption of the analog-digital converter can be reduced, so that the power consumption of the imaging device can be reduced. Furthermore, even if a buffer is provided before a capacitive element for absorbing an offset in a single-slope analog-digital converter in order to increase the driving force of a ramp wave reference signal and reduce the output impedance, the noise of the buffer can be reduced without connecting the output end of the buffer between pixel columns, so that a high-quality captured image can be obtained.

[0186] [Application to moving objects] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as an imaging device mounted on any type of moving object such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor).

[0187] FIG. 34 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0188] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 34, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0189] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0190] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0191] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0192] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0193] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0194] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0195] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0196] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0197] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 34, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0198] FIG. 35 is a diagram showing an example of the installation position of the imaging unit 12031.

[0199] In FIG. 35, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0200] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0201] 35 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0202] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0203] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0204] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0205] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0206] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 and the like among the configurations described above. By applying the technology according to the present disclosure to the imaging unit 12031 and the like, the dynamic range of the entire imaging device can be expanded and the power consumption of the imaging device can be reduced, which can contribute to the reduction in power consumption of the vehicle control system.

[0207] <Configurations that the present disclosure can take> The present disclosure may also be configured as follows.

[0208] A. Imaging device [A-01] Load current source, a comparator having an input transistor connected between a signal line transmitting a signal read out from a pixel and a load current source; a reference signal supplying unit that supplies a predetermined reference signal to the charge-voltage conversion unit of the pixel; Equipped with Imaging device. [A-02] The predetermined reference signal is a voltage having a slope waveform that changes linearly with a predetermined slope. The imaging device described in [A-01] above. [A-03] The comparator compares the signal voltage on which the ramp waveform voltage is superimposed, supplied through the signal line, with a predetermined reference voltage. The imaging device described in [A-02] above. [A-04] The voltage of the ramp waveform consists of a slope portion and an offset portion, The slope of the voltage of the ramp waveform is input to the charge-voltage converter via a capacitance element, The offset portion of the voltage of the ramp waveform is inverted in polarity with respect to the slope portion and input to the comparator as a predetermined reference voltage. The imaging device described in [A-03] above. [A-05] The reference signal supply unit supplies a predetermined reference signal to a charge-voltage conversion unit shared among a plurality of pixels. The imaging device according to any one of [A-01] to [A-04] above. [A-06] The reference signal supply unit A reference signal generator that generates a predetermined reference signal; and an input capacitance element that applies the reference signal generated by the reference signal generation unit to a charge-voltage conversion unit of the pixel; The imaging device according to any one of [A-01] to [A-05] above. [A-07] The reference signal supply unit supplies a reference signal to the charge-voltage conversion unit of the pixel along the column direction of a pixel array in which the pixels are arranged two-dimensionally in a matrix. The imaging device described in [A-06] above. [A-08] The reference signal generation unit is commonly arranged for all pixel columns of a pixel array in which pixels are arranged two-dimensionally in a matrix. The imaging device described in [A-07] above. [A-09] The reference signal generation unit is arranged on both sides in the column direction of a pixel array in which pixels are arranged two-dimensionally in a matrix. The imaging device described in [A-08] above. [A-10] The reference signal supply unit supplies a reference signal to the charge-voltage conversion unit of the pixel along the row direction of a pixel array in which the pixels are arranged two-dimensionally in a matrix. The imaging device described in [A-06] above. [A-11] The reference signal generation unit is commonly arranged for all pixel rows in a pixel array in which pixels are arranged two-dimensionally in a matrix. The imaging device according to [A-10] above. [A-12] The reference signal generation unit is arranged on both sides in the row direction of a pixel array in which pixels are arranged two-dimensionally in a matrix. The imaging device according to [A-10] or [A-11] above. [A-13] The reference signal generation unit supplies a reference signal to the pixel charge-voltage conversion unit on a pixel-by-pixel basis to each pixel of the pixel array in which the pixels are arranged two-dimensionally in a matrix. The imaging device described in [A-06] above. [A-14] The reference signal generation unit supplies a reference signal to the charge-voltage conversion unit of the pixel along the column direction from the center of the pixel array in which the pixels are arranged two-dimensionally in a matrix. The imaging device described in [A-06] above. [A-15] The pixel has a buffer provided in front of the input capacitance element. The imaging device described in [A-06] above. [A-16] The reference signal generating unit is provided in a pixel. The imaging device described in [A-06] above. [A-17] A stacked semiconductor chip structure formed by stacking at least two semiconductor chips, The pixels and the comparators are formed on different semiconductor chips. The imaging device according to any one of [A-06] to [A-16] above. [A-18] A first layer semiconductor chip and a second layer semiconductor chip are stacked, The first layer of the semiconductor chip has pixels formed on it. A comparator and a reference signal generating unit are formed on the second layer semiconductor chip. The imaging device described in [A-17] above. [A-19] A first layer semiconductor chip, a second layer semiconductor chip, and a third layer semiconductor chip are stacked together, The first layer of the semiconductor chip has a photoelectric conversion element formed on it. The second layer of the semiconductor chip contains the pixel components, excluding the photoelectric conversion element. The third layer semiconductor chip has a comparator and a reference signal generating unit formed thereon. The imaging device described in [A-17] above.

[0209] ≪B.Electronic equipment≫ [B-01] Load current source, a comparator having an input transistor connected between a signal line transmitting a signal read out from a pixel and a load current source; a reference signal supplying unit that supplies a predetermined reference signal to the charge-voltage conversion unit of the pixel; Equipped with An electronic device having an imaging device. [B-02] The predetermined reference signal is a voltage having a slope waveform that changes linearly with a predetermined slope. The electronic device described in [B-01] above. [B-03] The comparator compares the signal voltage on which the ramp waveform voltage is superimposed, supplied through the signal line, with a predetermined reference voltage. The electronic device described in [B-02] above. [B-04] The voltage of the ramp waveform consists of a slope portion and an offset portion, The slope of the voltage of the ramp waveform is input to the charge-voltage converter via a capacitance element, The offset portion of the voltage of the ramp waveform is inverted in polarity with respect to the slope portion and input to the comparator as a predetermined reference voltage. The electronic device described in [B-03] above. [B-05] The reference signal supply unit supplies a predetermined reference signal to a charge-voltage conversion unit shared among a plurality of pixels. The electronic device according to any one of [B-01] to [B-04] above. [B-06] The reference signal supply unit A reference signal generator that generates a predetermined reference signal; and an input capacitance element that applies the reference signal generated by the reference signal generation unit to a charge-voltage conversion unit of the pixel; The electronic device described in any one of [B-01] to [B-05] above. [B-07] The reference signal supply unit supplies a reference signal to the charge-voltage conversion unit of the pixel along a column direction of a pixel array in which the pixels are arranged two-dimensionally in a matrix. The electronic device described in [B-06] above. [B-08] The reference signal generation unit is commonly arranged for all pixel columns of a pixel array in which pixels are arranged two-dimensionally in a matrix. The electronic device described in [B-07] above. [B-09] The reference signal generation unit is arranged on both sides in the column direction of a pixel array in which pixels are arranged two-dimensionally in a matrix. The electronic device described in [B-08] above. [B-10] The reference signal supply unit supplies a reference signal to the charge-voltage conversion unit of the pixel along the row direction of a pixel array in which the pixels are arranged two-dimensionally in a matrix. The electronic device described in [B-06] above. [B-11] The reference signal generation unit is commonly arranged for all pixel rows in a pixel array in which pixels are arranged two-dimensionally in a matrix. The electronic device described in [B-10] above. [B-12] The reference signal generation unit is arranged on both sides in the row direction of a pixel array in which pixels are arranged two-dimensionally in a matrix. The electronic device according to [B-10] or [B-11] above. [B-13] The reference signal generation unit supplies a reference signal to the pixel charge-voltage conversion unit on a pixel-by-pixel basis to each pixel of the pixel array in which the pixels are arranged two-dimensionally in a matrix. The electronic device described in [B-06] above. [B-14] The reference signal generation unit supplies a reference signal to the charge-voltage conversion unit of the pixel along the column direction from the center of the pixel array in which the pixels are arranged two-dimensionally in a matrix. The electronic device described in [B-06] above. [B-15] The pixel has a buffer provided in front of the input capacitance element. The electronic device described in [B-06] above. [B-16] The reference signal generating unit is provided in the pixel. The electronic device described in [B-06] above. [B-17] A stacked semiconductor chip structure formed by stacking at least two semiconductor chips, The pixels and the comparators are formed on different semiconductor chips. The electronic device according to any one of [B-06] to [B-16] above. [B-18] A first layer semiconductor chip and a second layer semiconductor chip are stacked, The first layer of the semiconductor chip has pixels formed on it. A comparator and a reference signal generating unit are formed on the second layer semiconductor chip. The electronic device described in [B-17] above. [B-19] A first layer semiconductor chip, a second layer semiconductor chip, and a third layer semiconductor chip are stacked together, The first layer of the semiconductor chip has a photoelectric conversion element formed on it. The second layer of the semiconductor chip contains the pixel components, excluding the photoelectric conversion element. The third layer semiconductor chip has a comparator and a reference signal generating unit formed thereon. The electronic device described in [B-17] above. [Explanation of symbols]

[0210] 1···CMOS image sensor, 11···pixel array section, 12···row selection section, 13···analog-to-digital conversion section, 14···logic circuit section (signal processing section), 15···timing control section, 16···reference signal generation section, 20···pixel, 21···photodiode, 22···transfer transistor, 23···reset transistor, 24···amplification transistor, 25···selection transistor, 31 (311 to 31 m )···Pixel control line, 32 (321~32 n) signal line, 50 reference signal supply unit, 51 reference signal generation unit, 52 input capacitance element, 130 analog-to-digital converter, 131 comparator, 132 counter, C 11 ,C 12 ,C 13 Capacitive element, I 11 Input side load current source, I 12 ...output side load current source, PT 11 Input transistor, PT 12 Output transistor

Claims

1. load current source, a comparator having an input transistor connected between a signal line transmitting a signal read out from a pixel and a load current source; a reference signal supplying unit that supplies a predetermined reference signal to the charge-voltage conversion unit of the pixel; Equipped with The predetermined reference signal is a voltage having a ramp waveform that changes linearly with a predetermined slope, The comparator compares the signal voltage on which the ramp waveform voltage is superimposed, which is supplied through the signal line, with a predetermined reference voltage; The voltage of the ramp waveform is composed of a slope portion and an offset portion, The slope portion of the voltage of the ramp waveform is input to the charge-to-voltage converter via the input capacitance element, The offset portion of the voltage of the ramp waveform is inverted in polarity with respect to the slope portion and input to the comparator as a predetermined reference voltage. Imaging device.

2. The reference signal supply unit supplies a predetermined reference signal to the charge-voltage conversion unit shared among a plurality of pixels. The imaging device according to claim 1 .

3. The reference signal supply unit A reference signal generating unit that generates a predetermined reference signal. The imaging device according to claim 1 .

4. The reference signal supply unit supplies a reference signal to the charge-voltage conversion unit of the pixel along a column direction of a pixel array in which the pixels are two-dimensionally arranged in a matrix. The imaging device according to claim 3 .

5. the reference signal generating unit is commonly arranged for all pixel columns of a pixel array in which pixels are two-dimensionally arranged in a matrix; The imaging device according to claim 4.

6. The reference signal generating units are arranged on both sides in a column direction of a pixel array in which pixels are two-dimensionally arranged in a matrix. The imaging device according to claim 5 .

7. The reference signal supply unit supplies a reference signal to the charge-voltage conversion unit of the pixel along a row direction of a pixel array in which the pixels are two-dimensionally arranged in a matrix. The imaging device according to claim 3 .

8. the reference signal generating unit is commonly disposed for all pixel rows in a pixel array in which pixels are two-dimensionally arranged in a matrix; The imaging device according to claim 7.

9. The reference signal generating units are arranged on both sides in a row direction of a pixel array in which pixels are two-dimensionally arranged in a matrix. The imaging device according to claim 7.

10. The reference signal generation unit supplies a reference signal to the charge-voltage conversion unit of the pixel on a pixel-by-pixel basis to each pixel of the pixel array in which the pixels are two-dimensionally arranged in a matrix. The imaging device according to claim 3 .

11. The reference signal generation unit supplies a reference signal to the charge-voltage conversion unit of the pixel along a column direction from a center portion of the pixel array in which the pixels are two-dimensionally arranged in a matrix. The imaging device according to claim 3 .

12. The pixel has a buffer provided in front of the input capacitance element. The imaging device according to claim 3 .

13. The reference signal generating unit is provided in the pixel. The imaging device according to claim 3 .

14. A stacked semiconductor chip structure is formed by stacking at least two semiconductor chips, The pixels and the comparators are formed on different semiconductor chips. The imaging device according to claim 3 .

15. A first layer semiconductor chip and a second layer semiconductor chip are stacked, Pixels are formed on the first layer of the semiconductor chip, A comparator and a reference signal generating unit are formed on the second layer semiconductor chip. The imaging device according to claim 14.

16. A first layer semiconductor chip, a second layer semiconductor chip, and a third layer semiconductor chip are stacked together, A photoelectric conversion element is formed on the first layer semiconductor chip, The second layer of semiconductor chips has pixel components formed thereon, excluding photoelectric conversion elements. A comparator and a reference signal generating unit are formed on the third layer semiconductor chip. The imaging device according to claim 14.

17. load current source, a comparator having an input transistor connected between a signal line transmitting a signal read out from a pixel and a load current source; a reference signal supplying unit that supplies a predetermined reference signal to the charge-voltage conversion unit of the pixel; Equipped with The predetermined reference signal is a voltage having a ramp waveform that changes linearly with a predetermined slope, The comparator compares the signal voltage on which the ramp waveform voltage is superimposed, which is supplied through the signal line, with a predetermined reference voltage; The voltage of the ramp waveform is composed of a slope portion and an offset portion, The slope portion of the voltage of the ramp waveform is input to the charge-to-voltage converter via the input capacitance element, The offset portion of the voltage of the ramp waveform is inverted in polarity with respect to the slope portion and input to the comparator as a predetermined reference voltage. An electronic device having an imaging device.

Images