Power conversion device, semiconductor switch device and manufacturing method

Abstract

To increase the current of a main circuit that controls ON / OFF with multiple semiconductor switching elements with the main circuit side connected in parallel.SOLUTION: A power converter in an embodiment includes; multiple semiconductor switching elements; and a drive unit. The multiple semiconductor switching elements are connected in parallel at the main circuit side. The drive unit is configured to be settable to output a control signal at different timings for each of the multiple semiconductor switching elements and to supply the control signal to the semiconductor switching element.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] FIELD Embodiments of the present invention relate to a power conversion device, a semiconductor switch device, and a manufacturing method. [Background technology]

[0002] Some power conversion devices include multiple semiconductor switching elements in one package, with the main circuit sides of these semiconductor switching elements connected in parallel to each other. However, the current flowing through the main circuit is not distributed to each semiconductor switching element, and the current is concentrated in a specific semiconductor switching element among the multiple semiconductor switching elements, which can cause the specific semiconductor switching element to fail. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-92820 A Summary of the Invention [Problem to be solved by the invention]

[0004] The problem that the present invention aims to solve is to provide a power conversion device, a semiconductor switch device, and a manufacturing method that can increase the current of a main circuit that is on / off controlled by a plurality of semiconductor switching elements connected in parallel on the main circuit side. [Means for solving the problem]

[0005] The power conversion device of the embodiment includes a plurality of semiconductor switching elements and a drive device. The plurality of semiconductor switching elements are connected in parallel on the main circuit side. The drive device includes The input gate pulse is By setting, a control signal is sent to each of the plurality of semiconductor switching elements at different timings. As The control signal can be output. of The above MultipleThe drive device can set a delay time of the control signal for each of the plurality of semiconductor switching elements with reference to the period of the reference clock for each of the plurality of semiconductor switching elements, and the delay time of the control signal is set so that the semiconductor switching elements in a non-conductive state start to conduct at the same time, thereby supplying a control signal to each of the plurality of semiconductor switching elements in accordance with the set delay time. From the gate pulse Delay Before The control signal is output. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a configuration diagram of a power conversion device according to an embodiment. [Diagram 2] FIG. 2 is a configuration diagram of a semiconductor switch according to an embodiment. [Figure 3A] FIG. 4 is a configuration diagram of a semiconductor switch of a comparative example. [Figure 3B] 3B is a diagram for explaining the operation of the semiconductor switch of the comparative example shown in FIG. 3A. [Figure 4] 1 is a schematic configuration diagram of a semiconductor switch device including a semiconductor switch driving device according to an embodiment; [Figure 5A] FIG. 4 is a configuration diagram for measuring a delay time according to an embodiment. [Figure 5B] 4 is a flowchart showing a part of a manufacturing process of the semiconductor switch device according to the embodiment. [Figure 5C] 4 is a flowchart showing a part of a manufacturing process of the semiconductor switch device according to the embodiment. [Figure 6] 5A and 5B are diagrams for explaining waveforms of gate drive signals according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The power conversion device, the semiconductor switch device, and the manufacturing method according to the embodiments will be described below. In the following description, being electrically connected may simply be referred to as being "connected." In this specification, "based on XX" means "based on at least XX" and includes the case where it is based on another element in addition to XX. Furthermore, "based on XX" is not limited to the case where XX is directly used, but also includes the case where it is based on XX that has been subjected to calculation or processing. "XX" is any element (for example, any information).

[0008] (Embodiment) FIG. 1 is a configuration diagram of a power conversion device 1 according to an embodiment. The power conversion device 1 drives a motor 2. The motor 2 is, for example, a three-phase AC motor. The power conversion device 1 includes, for example, an inverter 10 and a control device 20.

[0009] The inverter 10 includes, for example, legs 11 to 13. The inverter 10 converts DC power into three-phase AC power. The legs 11 to 13 are configured similarly and correspond to U-phase, V-phase, and W-phase windings (not shown) of the electric motor 2, respectively. The inverter 10 supplies the three-phase AC power to the electric motor 2.

[0010] The inverter 10 and the control device 20 are connected by optical fibers and insulated from each other. The control device 20 supplies signals to the inverter 10 for switching a plurality of semiconductor switches included in the inverter 10 between an on state and an off state. For example, the control device 20 transmits gate pulses GPSp and GPsn of optical signals.

[0011] Here, an example of the configuration of each leg will be described, taking leg 11 as a representative example. The leg 11 includes semiconductor switches Q1 and Q3, semiconductor switch drivers 101 and 103, and optical / electrical converters (indicated as "O / E" in the drawing) OEp and OEn. The semiconductor switches Q1 and Q3 are an example of a main circuit section.

[0012] The semiconductor switches Q1 and Q3 each include a plurality of semiconductor switching elements of the same type. For example, an IGBT (Insulated Gate Bipolar Transistor) is used as the semiconductor switching element. The semiconductor switches Q1 and Q3 are connected in series on the main circuit side, with the semiconductor switch Q1 on the positive side (referred to as the p-side) and the semiconductor switch Q3 on the negative side (referred to as the n-side).

[0013] The input side of the semiconductor switch driver 101 is connected to the output side of a common optical-electrical converter OEp (indicated as "O / E" in the figure). The optical-electrical converter OEp receives a gate pulse GPSp from the control device 20, generates a gate pulse GPregp, and supplies the gate pulse GPregp to the semiconductor switch driver 101. The semiconductor switch driver 101 outputs a gate drive signal generated based on the gate pulse GPregp supplied to the input side from the output side. The semiconductor switch Q1 receives the gate drive signal output from the semiconductor switch driver 101 and switches between an on state and an off state.

[0014] The input sides of the semiconductor switch driver 103 are connected to the output side of a common photoelectric converter OEn (indicated as "O / E" in the figure). The photoelectric converter OEn receives a gate pulse GPsn of an optical signal from the control device 20, generates a gate pulse GPregn, and supplies the gate pulse GPregn to the semiconductor switch driver 103. The semiconductor switch driver 103 outputs, from its output side, a gate drive signal generated based on the gate pulse GPregn supplied to its input side. The semiconductor switch Q3 receives the gate drive signal output from the semiconductor switch driver 103 and switches between an on state and an off state.

[0015] The control device 20 controls the inverter 10 in response to a command from a higher-level device (not shown) and the detection result of the state of the electric motor 2. The gate pulse GPSp and the gate pulse GPsn are an example of a control signal from the control device 20 to the inverter 10.

[0016] The power conversion device 1 configured in this manner can control the rotation speed of the electric motor 2 and the like.

[0017] For example, at least the semiconductor switches Q1 and Q3 are housed in a common package (a housing not shown) or in individual packages. A more specific example is shown below. A semiconductor switch driving device 101, an opto-electrical converter OEp, and a semiconductor switch Q1 are provided in a single package, which is called a semiconductor switch device 102. Similarly, a semiconductor switch driving device 103, an opto-electrical converter OEn, and a semiconductor switch Q3 are provided in a single package, which is called a semiconductor switch device 104. The semiconductor switch device 102 and the semiconductor switch device 104 are configured similarly to each other. When the semiconductor switch device 102 and the semiconductor switch device 104 are referred to without distinction, they are simply called the semiconductor switch device 100. The semiconductor switch device 100 is sometimes called a "module" of a switching element for power conversion. Hereinafter, when the semiconductor switch device 100 is specifically described, the semiconductor switch device 102 will be taken as an example.

[0018] The semiconductor switch Q1 will be mainly described with reference to Fig. 2. Fig. 2 is a configuration diagram of the semiconductor switch Q1 according to the embodiment.

[0019] The semiconductor switch Q1 includes semiconductor switching elements Qa to Qd. The main circuit sides of these semiconductor switching elements Qa to Qd are connected in parallel to each other. The main circuit sides being connected in parallel to each other means, for example, that the collectors of the semiconductor switching elements Qa to Qd are connected to each other and the emitters are connected to each other. In the case of the semiconductor switch Q1, the control terminals (gates) of the semiconductor switching elements Qa to Qd are electrically insulated so that they can be controlled independently of each other.

[0020] Hereinafter, a case where the current flowing to the main circuit side is distributed to the semiconductor switching elements Qa to Qd will be described. By distributing the current flowing to the main circuit side to each of the semiconductor switching elements Qa to Qd, the loss generated in the semiconductor switching elements can be distributed to each of them. Here, a comparative example will be shown and the differences from the comparative example in the embodiment will be described.

[0021] First, Fig. 3A and Fig. 3B illustrate a semiconductor switch Q of a comparative example. Fig. 3A is a configuration diagram of the semiconductor switch Q of the comparative example. Fig. 3B is a diagram for explaining the operation of the semiconductor switch Q of the comparative example shown in Fig. 3A.

[0022] The semiconductor switch Q of the comparative example also includes semiconductor switching elements Qa to Qd, similar to the semiconductor switch Q1 of the embodiment. The main circuit sides of the semiconductor switching elements Qa to Qd in the semiconductor switch Q are also connected in parallel to each other. The collectors of the semiconductor switching elements Qa to Qd are each connected to a connecting conductor LN1, and the emitters thereof are each connected to a connecting conductor LN2.

[0023] In the comparative example, the control terminals of the semiconductor switching elements Qa to Qd in the semiconductor switch Q are connected in parallel to each other. For example, a wiring LGB is connected to the output of a certain drive circuit D. For example, the wiring LGB is branched to the semiconductor switching elements Qa to Qd. The control terminals of the semiconductor switching elements Qa to Qd are connected to the respective ends of the branched ends.

[0024] By switching the voltage output by the drive circuit D, the voltages at the control terminals of the semiconductor switching elements Qa to Qd change accordingly, switching the conductive states of the semiconductor switching elements Qa to Qd. As a result, it is expected that the current of the main circuit will be diverted from the semiconductor switching elements Qa to Qd, as shown in Figure 3A.

[0025] However, in the comparative example, the semiconductor switching elements Qa to Qd may not switch simultaneously. For example, the semiconductor switching elements Qa to Qd are arranged in a package, but due to differences in the positions where the semiconductor switching elements Qa to Qd are arranged, or differences in the paths of the control signals for controlling the semiconductor switching elements Qa to Qd from the semiconductor switching elements Qa to Qd to the control terminals thereof, there may be variations in the timing at which the voltage change of the control signal reaches the control terminals of the semiconductor switching elements Qa to Qd. As a result, there may be variations in the timing at which the semiconductor switching elements Qa to Qd are switched on / off. FIG. 3B shows a model of a state in which such an event occurs.

[0026] As described above, when the timing of on / off switching varies, current can be concentrated in a specific semiconductor switching element among the multiple semiconductor switching elements, as shown in Figure 3B, causing an imbalance with the current flowing in the other semiconductor switching elements, resulting in degradation of the specific semiconductor switching element.

[0027] In contrast, in the semiconductor switch Q1 of the embodiment, the control terminals of the semiconductor switching elements Qa to Qd are configured to be electrically independent as shown in Fig. 2. This can be used to prevent variation in the timing at which the voltages of the control terminals of the semiconductor switching elements Qa to Qd in the semiconductor switch Q1 change.

[0028] FIG. 4 is a schematic configuration diagram of a semiconductor switch device 102 including a semiconductor switch driving device 101 according to an embodiment. The semiconductor switch driver 101 may be configured as, for example, a single semiconductor device. A typical example of the semiconductor switch driver 101 is a field programmable gate array (FPGA), but may be another type of application specific integrated circuit (ASIC).

[0029] For example, the semiconductor switch driver 101 includes an input buffer circuit IB, delay time adjustment units 101a to 101d, output buffer circuits Da to Dd, and a clock distribution unit 101k. The delay time adjustment units 101a to 101d are collectively referred to as an adjustment unit 101TD.

[0030] Furthermore, the semiconductor switch driver 101 includes, as signal terminals, a terminal Tck, a signal input terminal Ti, signal output terminals Toa to Tod, a reference potential terminal Tcom, and a power supply terminal (not shown).

[0031] The terminal Tck is connected to the output of the reference signal source OSC, and receives the reference signal Sync from the reference signal source OSC.

[0032] The signal input terminal Ti is connected to the output of the photoelectric converter OEp, and a gate pulse GPregp is supplied from the photoelectric converter OEp. The signal output terminals Toa to Tod are each connected to a semiconductor switch Q1. For example, the signal output terminal Toa is connected to a control terminal of the semiconductor switching element Qa via a wiring LGa. The signal output terminal Tob is connected to a control terminal of the semiconductor switching element Qb via a wiring LGb. The signal output terminal Toc is connected to a control terminal of the semiconductor switching element Qc via a wiring LGc. The signal output terminal Tod is connected to a control terminal of the semiconductor switching element Qd via a wiring LGd.

[0033] The clock distribution unit 101k receives a reference signal Sync from a reference signal source OSC via a terminal Tck and generates a clock ck. The clock distribution unit 101k supplies the clock ck to the delay time adjustment units 101a to 101d. For example, the clock distribution unit 101k may be a PLL that generates a clock ck with a relatively high frequency.

[0034] The input buffer circuit IB detects a gate pulse GPregp supplied from the optical-electrical converter OEp via a signal input terminal Ti, and supplies a pulse signal corresponding to this to the delay time adjustment units 101a to 101d.

[0035] The delay time adjustment units 101a to 101d receive the pulse signal and the clock ck, delay the pulse signal supplied from the input buffer circuit IB by a predetermined delay time, and output the delayed signal. The delay time of the delay time adjustment units 101a to 101d is set for each delay time adjustment unit so as to be an integer multiple of the period of the clock ck, for example. There is no restriction on the specific configuration of the delay time adjustment units 101a to 101d, and the delay circuit may be of a general configuration using a shift register having a desired number of stages (size), a FIFO (First In, First Out) type buffer memory, or the like.

[0036] The inputs of the output buffer circuits Da to Dd are connected to the outputs of the delay time adjustment units 101a to 101d, respectively. The outputs of the output buffer circuits Da to Dd are connected to the signal output terminals Toa to Tod. The output buffer circuits Da to Dd generate gate drive signals based on the pulse signals delayed by the delay time adjustment units 101a to 101d, respectively.

[0037] The adjustment unit 101TD adjusts at least the timing of outputting the first control signal, of the timing of outputting the first control signal and the timing of outputting the second control signal, so that the timing at which the output buffer circuit Da (first drive unit) outputs a gate drive signal (first control signal) for the semiconductor switching element Qa (first semiconductor switching element) and the timing at which the output buffer circuit Db (second drive unit) outputs a gate drive signal (second control signal) for the semiconductor switching element Qa (second semiconductor switching element) are aligned.

[0038] Furthermore, the timing at which the output buffer circuit Dc outputs a gate drive signal to the semiconductor switching element Qc and the timing at which the output buffer circuit Dd outputs a gate drive signal to the semiconductor switching element Qd are adjusted by adjustment unit 101TD so that they are further aligned to the timing achieved as described above.

[0039] For example, the delay time adjustment unit 101a delays the timing when the output buffer circuit Da outputs a gate drive signal (first control signal) by a delay time of a length based on a first set value. The delay time adjustment unit 101b delays the timing when the output buffer circuit Db outputs a gate drive signal (second control signal) by a delay time of a length based on a second set value. The delay time adjustment unit 101c delays the timing when the output buffer circuit Dc outputs a gate drive signal (third control signal) by a delay time of a length based on a third set value. The delay time adjustment unit 101d delays the timing when the output buffer circuit Dd outputs a gate drive signal (fourth control signal) by a delay time of a length based on a fourth set value. In this way, the delay time adjustment units 101a to 101d determine the timing for each semiconductor switching element based on the settings. The delay time adjustment units 101a to 101d adjust the delay times of the above timings according to the lengths based on the above settings.

[0040] As described above, by setting a desired delay time in the delay time adjustment units 101a to 101d, it becomes possible to align the timing at which the state of the gate signals supplied to the control terminals of the semiconductor switching elements Qa to Qd changes. In this embodiment, the resolution for aligning the timing depends on the length of the cycle of the clock ck. Therefore, it is preferable to make the cycle of the clock ck relatively short.

[0041] By adjusting the timing as desired through the above settings, it becomes difficult for current to concentrate in a specific semiconductor switching element among the semiconductor switching elements Qa to Qd. Here, the index value that specifies the maximum current that can be switched on / off in the entire semiconductor switching device 100 is called the "rated current value of the semiconductor switching device 100."

[0042] When the current flowing through the main circuit is not distributed to each semiconductor switching element as in the comparative example, but is concentrated in a specific semiconductor switching element among the multiple semiconductor switching elements, it is necessary to ensure that even the concentrated current does not exceed the allowable current value of the semiconductor switching element, and this can be satisfied by suppressing the rated current value.

[0043] In contrast, in the case of the semiconductor switch device 100 of the present embodiment, it is possible to distribute the current flowing through the main circuit of the semiconductor switch device 100 to a plurality of semiconductor switching elements. For example, by anticipating the distribution of the current, the rated current value of the semiconductor switch device 100 can be set to a value closer to the total allowable current value of the semiconductor switching elements Qa to Qd.

[0044] (manufacturing process) A manufacturing process (manufacturing method) for adjusting the delay time of the embodiment will be described with reference to Fig. 5A to Fig. 5C. Fig. 5A is a configuration diagram for measuring the delay time of the embodiment. A general-purpose measuring instrument such as an oscilloscope not shown in Fig. 5A may be used to measure the voltage, which will be described later. Figs. 5B and 5C are flow charts showing a part of the manufacturing process of the semiconductor switch device 100 of the embodiment.

[0045] The delay time may be adjusted, for example, for each type of semiconductor switch device 100 to determine the amount of adjustment. Using the adjustment result, the delay time of each semiconductor switch device 100 is set for each device.

[0046] First, a manufacturing process for determining the switching timing (delay time) of the semiconductor switch Q1 will be described. When the semiconductor switch device 100 is in an initial state before the delay time is set, the delay time is set to 0 in the delay time adjustment units 101a to 101d, that is, no delay is generated.

[0047] First, the electrical components associated with the semiconductor switch Q1 are mounted on a board (step SA12). The board is a plate-like member having a surface to be thermally coupled to a heat sink. The surface to be thermally coupled to the heat sink forms one surface that will be on the outside of the package of the semiconductor switch device 100. The electrical components are mounted on a surface that will be on the inside of the package of the semiconductor switch device 100 (the surface opposite to the surface mentioned above). The electrical components associated with the semiconductor switch Q1 include semiconductor switching elements Qa to Qd.

[0048] Next, electrical connections are made. The electrical connections include, for example, the following connections: A control terminal (Qag) of the semiconductor switching element Qa (first semiconductor switching element) is connected to a signal output terminal Toa on the output side of the output buffer circuit Da (step SA14). A control terminal of the semiconductor switching element Qb (second semiconductor switching element) is connected to a signal output terminal Tob on the output side of the output buffer circuit Db (step SA16). The same is done for the semiconductor switching elements Qc and Qd (step SA18).

[0049] Next, the first propagation delay time of the first control signal output by the output buffer circuit Da is measured using the configuration shown in FIG. 5A (step SA20). For example, the timing at which the gate drive signal (first control signal) at the output of the output buffer circuit Da changes from ON to OFF is compared with the timing at which the gate drive signal at the control terminal of the semiconductor switching element Qa changes from ON to OFF, and the difference is measured as the first propagation delay time. Instead of or in addition to the above, the timing at which the gate drive signal changes from OFF to ON may be used. In this case, for example, the voltage V1 at the signal output terminal Toa when the potential of Tcom is used as a reference, and similarly, the voltage V2 at the control terminal of the semiconductor switching element Qa may be used for the analysis. The voltage V1 at the signal output terminal Toa and the voltage V2 at the control terminal of the semiconductor switching element Qa may be obtained from the results of measurements using a general-purpose measuring device. In this case, there is no need to provide sensors in the semiconductor switch device 100 for measuring the voltage V1 at the signal output terminal Toa and the voltage V2 at the control terminal of the semiconductor switching element Qa, which is effective in reducing the cost of the semiconductor switch device 100.

[0050] Similarly, the second propagation delay time of the gate drive signal (second control signal) output by the output buffer circuit Db is measured (step SA22). The propagation delay time between the gate drive signal output by the output buffer circuit Dc and the gate drive signal output by the output buffer circuit Dd is measured.

[0051] Next, based on the propagation delay time including the first propagation delay time and the second propagation delay time, the adjustment amount of the adjustment unit 101TD is determined so that there is no difference in the timing of state changes of the gate drive signals reaching each control terminal of the semiconductor switching elements Qa to Qd (step SA24).

[0052] For example, the adjustment amount may be determined based on the timing of the semiconductor switching element whose gate drive signal tends to arrive latest among the gate drive signals arriving at each control terminal of semiconductor switching elements Qa to Qd, so as to delay the timing of the gate drive signal of the semiconductor switching element that arrives earlier.

[0053] A desired delay time may be determined as the adjustment amount in accordance with the procedure of the manufacturing process of the semiconductor switch device 100. An adjustment amount is determined for delaying the gate drive signal so that the conductive state of the semiconductor switch Q1 transitions at the desired timing determined by the procedure.

[0054] Next, a manufacturing process for manufacturing the semiconductor switch device 100 in which the switching timing of the semiconductor switch Q1 is adjusted based on the adjustment amount determined by the above procedure will be described with reference to FIG. 5C.

[0055] A delay time based on the determined adjustment amount is set in adjustment unit 101TD in semiconductor switch driver 101 (step SB12). As described above, semiconductor switch driver 101 includes a delay circuit that delays a signal by, for example, a desired delay time. In order to set the delay time of this adjustment unit 101TD, for example, data specifying the desired delay time may be written to semiconductor switch driver 101 as data for specifying the delay time of the delay circuit. As a result, a delay circuit based on the above data is formed in semiconductor switch driver 101.

[0056] The semiconductor switch driver 101 is attached to a socket mounted on a board and mounted on the board (step SB14). A cover is attached to the board (step SB16), completing the assembly of the semiconductor switch device 100. After this, inspections including a functional test are performed on the semiconductor switch device 100 (step SB18).

[0057] According to the above procedure, the manufacture of the semiconductor switching device 100 is completed.

[0058] 6A and 6B are diagrams for explaining the waveforms of the gate drive signals in the embodiment, in which Fig. 6A shows the state before adjustment (referred to as an unadjusted state), and Fig. 6B shows the state after adjustment.

[0059] 6(a) shows, from the top to the bottom, a gate pulse GPreg supplied to the semiconductor switch Q1, a gate drive signal SQag supplied to the control terminal of the semiconductor switching element Qa, and a gate drive signal SQdg supplied to the control terminal of the semiconductor switching element Qd. The horizontal axis of this timing chart indicates the passage of time.

[0060] At time t11, the gate pulse GPreg rises, and at time t12, the gate pulse GPreg falls.

[0061] The input buffer IB of Z101 detects the rising edge of the gate pulse GPreg at time t11. When the input buffer IB detects the rising edge of the gate pulse GPreg at time t11, Z101 outputs the gate drive signal SQag from the output buffer circuit Da in synchronization with this. When the delay time of the gate drive signal SQag is not adjusted (unadjusted state), Z101 sets the delay adjustment time to 0. The delay adjustment time is the time added for adjustment to the delay time when passing through Z101.

[0062] In the above state, the gate drive signals SQag and SQdg are output, and the rising edge of the gate drive signal SQag is detected at time t11A, and the rising edge of the gate drive signal SQdg is detected at time t11D. Similarly, the falling edge of the gate drive signal SQag is detected at time t12A, and the falling edge of the gate drive signal SQdg is detected at time t12D. The waveforms of each gate drive signal indicate the amplitude of each gate drive signal detected at the position of the gate terminal of each semiconductor switching element.

[0063] As shown in Fig. 6(a), the gate drive signal SQdg was detected to be delayed by a delay time tofa with respect to the gate drive signal SQag. The waveforms of the gate drive signals shown here are equivalent to the required characteristics of each semiconductor switching element, and the shape of the waveform may be changed as appropriate. The most typical waveform of the gate drive signal is a square wave pulse of a positive voltage, and the voltage during the period when each semiconductor switching element is turned off may be biased to a negative voltage.

[0064] As described above, if there is a delay of about the delay time tofa between the gate drive signals SQag and SQdg, then as described above, there will be variation in the timing at which the semiconductor switching elements Qa and Qd are turned on and off. Therefore, as shown in Fig. 6(b), it is advisable to delay the gate drive signal SQag and adjust it so that this delay time becomes 0. Furthermore, in addition to the above, it is also advisable to delay the gate drive signals SQbg and SQcg and adjust them so that their respective delay times become 0.

[0065] By adjusting as described above, the timing of the rise and fall of the four gate drive signals, gate drive signal SQag to gate drive signal SQdg, is aligned at each control terminal of the multiple semiconductor switching elements, thereby making it possible to manufacture the semiconductor switch device 100 in which the main circuit side has a larger current that is on / off controlled by multiple semiconductor switching elements connected in parallel.

[0066] According to the above embodiment, the gate drive signals SQag and SB to be supplied to the semiconductor switches Q1 and Q2 can be generated from one reference gate pulse (GPreg). The phases of the gate drive signals SQag and SB to be supplied to the semiconductor switches Q1 and Q2 can be adjusted to have the desired waveforms by adjusting the delay time from the common gate pulse. This makes it possible to reduce losses due to switching by speeding up the on / off switching of the semiconductor switches while suppressing voltage jumps in the gate pulse. Note that in the above example, the adjustment of the phase has been described, but the amplitude may be adjusted to obtain the desired waveform.

[0067] (Modification of the embodiment) A modified example of the embodiment will be described. In the above embodiment, the semiconductor switch device 100 capable of adjusting the delay time based on the cycle of the clock ck has been described, but the present invention is not limited to this. In this modified example, the delay time in the semiconductor switch device 100 is configured to be adjustable by adjusting, for example, the wiring length of the signal in the semiconductor switch device 100, the number of gate stages provided in the path of each signal, etc. The semiconductor switch device 100 of the modified example can obtain the same effect as the embodiment by adjusting the wiring length of the signal in the semiconductor switch device 100, the number of gate stages provided in the path of each signal, etc., instead of or in addition to adjusting the delay time based on the cycle of the clock ck.

[0068] According to at least one of the embodiments described above, the power conversion device 1 includes a plurality of semiconductor switching elements and a drive device. The main circuit sides of the plurality of semiconductor switching elements are connected in parallel. The drive device can output a control signal at different timings for each of the plurality of semiconductor switching elements by setting, and supplies the control signal to the semiconductor switching elements. This can reduce the variation in on / off timing of the plurality of semiconductor switching elements connected in parallel on the main circuit side, and ultimately can increase the current of the main circuit that is on / off controlled by the plurality of semiconductor switching elements connected in parallel on the main circuit side.

[0069] The control device 20 may be realized, at least in part, by a software function unit that functions when a processor such as a CPU executes a program, or may be realized entirely by a hardware function unit such as an LSI.

[0070] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention.

[0071] For example, the number of semiconductor switching elements in the semiconductor switch device 100 is not limited as long as it is two or more. [Explanation of symbols]

[0072] 1...power conversion device, 2...motor (M), 10...inverter, 11, 12, 13...leg, 20...control device, 101, 103...semiconductor switch drive device, 100, 102, 104...semiconductor switch device, Qa, Qb, Qc, Qd...semiconductor switching element, Da...output buffer circuit (first drive unit), Db...output buffer circuit (second drive unit), 101TD...adjustment unit, 101a...delay time adjustment unit (first delay time adjustment unit), 101b...delay time adjustment unit (second delay time adjustment unit)

Claims

1. A plurality of semiconductor switching elements having main circuit sides connected in parallel; a drive device that can output the input gate pulse as a control signal at different timings for each of the plurality of semiconductor switching elements by setting, and supplies the control signals to the plurality of semiconductor switching elements; Equipped with The drive device is a delay time of a control signal for each of the plurality of semiconductor switching elements can be set for each of the plurality of semiconductor switching elements with reference to a period of the reference clock; The delay times of the control signals are set so that the semiconductor switching elements in the non-conductive state start to conduct at the same time, The control signal is outputted after being delayed from the gate pulse according to the set delay time. Semiconductor switching device.

2. The drive device is a delay time adjustment unit that determines a delay time of the control signal for each of the semiconductor switching elements based on the setting; The semiconductor switch device according to claim 1 .

3. The drive device is A delay time adjustment unit that adjusts the delay time to a length based on the setting. The semiconductor switch device according to claim 1 .

4. The rated current value is greater than the allowable current value of one of the semiconductor switching elements. The semiconductor switch device according to claim 1 .

5. The plurality of semiconductor switching elements include A first semiconductor switching element; A second semiconductor switching element; Equipped with The drive device is a first driver that supplies a first control signal as the control signal to the first semiconductor switching element; a second driver that supplies a second control signal as the control signal to the second semiconductor switching element; a delay time adjustment unit that adjusts a timing to output at least the first control signal according to the setting; The semiconductor switch device according to claim 1 .

6. A semiconductor switch device according to any one of claims 1 to 5; A control device for controlling the semiconductor switch device; A power conversion device comprising:

7. A plurality of semiconductor switching elements having main circuit sides connected in parallel; a drive device that can output the input gate pulse as a control signal at different timings for each of the plurality of semiconductor switching elements by setting, and supplies the control signals to the plurality of semiconductor switching elements; A method for manufacturing a semiconductor switch device comprising: measuring a first timing at which a logic state of the control signal output by the drive device changes; measuring a second timing at which a logic state of a control signal supplied to each control terminal of the plurality of semiconductor switching elements changes; specifying a difference between the first timing and the second timing using a period of the clock, specifying a delay time of the control signal for each semiconductor switching element, and then determining an adjustment amount of the delay time so as to delay the timing of the control signal of the semiconductor switching element which tends to arrive the latest based on the timing of the semiconductor switching element which tends to arrive the latest, and setting a timing for outputting the control signal by adjusting the delay time for each semiconductor switching element; Including, A delay time based on the predetermined adjustment amount is applied to the control signal of the semiconductor switching element, thereby reducing the variation in timing at which the logical state of the control signal changes at each control terminal of the plurality of semiconductor switching elements. A method for manufacturing a semiconductor switch device.

Images