Apparatus and method for performing box queries in ray traversal hardware - Patents.com

Abstract

To provide an apparatus and method for box-box testing.SOLUTION: For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator constructing a BVH including a plurality of hierarchically arranged BVH nodes; and traversal circuitry of traversing query boxes through the BVH. The traversal circuitry is configured to read the BVH node from the top of a BVH node stack and read a query box from a local storage or memory. The traversal circuitry further comprises: box-box testing circuitry and / or logic of comparing maximum and minimum X, Y and Z coordinates of the BVH node and generating an overlap indication if overlap is detected for each of the X, Y and Z dimensions; distance determination circuitry and / or logic of generating a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and / or logic of sorting the BVH node within a set of one or more additional BVH nodes based on the distance value.SELECTED DRAWING: Figure 63

Description

[Technical field]

[0001] The present invention relates generally to the field of graphics processors, and more particularly to an apparatus and method for asynchronous ray tracing. [Background technology]

[0002] Ray tracing is a technique in which light propagation is simulated through physically based rendering. It is widely used in cinematic rendering and, until just a few years ago, was considered to be very resource intensive for real-time performance. One of the key operations in ray tracing is processing visibility queries for ray-scene intersections, known as "ray traversal", which computes ray-scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH). [Brief description of the drawings]

[0003] A better understanding of the present invention can be obtained from the following detailed description taken in conjunction with the following drawings. [Figure 1] FIG. 1 is a block diagram of a computer system having a processor with one or more processor cores and a graphics processor. [Figure 2A] 1 illustrates a computing system and graphics processor provided in accordance with embodiments described herein. [Figure 2B] 1 illustrates a computing system and graphics processor provided in accordance with embodiments described herein. [Figure 2C] 1 illustrates a computing system and graphics processor provided in accordance with embodiments described herein. [Figure 2D] 1 illustrates a computing system and graphics processor provided in accordance with embodiments described herein. [Figure 3A] 1 shows a block diagram of a further graphics processor and computation accelerator architecture provided by embodiments described herein. [Figure 3B] 1 shows a block diagram of a further graphics processor and computation accelerator architecture provided by embodiments described herein. [Figure 3C] 1 shows a block diagram of a further graphics processor and computation accelerator architecture provided by embodiments described herein. [Figure 4] FIG. 1 is a block diagram of a graphics processing engine for a graphics processor. [Figure 5A] 5 illustrates thread execution logic 500 including an array of processing elements for use in a graphics processor core according to embodiments described herein. [Figure 5B] 5 illustrates thread execution logic 500 including an array of processing elements for use in a graphics processor core according to embodiments described herein. [Figure 6] 6 shows a further execution unit 600 according to an embodiment. [Figure 7] 1 shows a graphics processor execution unit instruction format. [Figure 8] FIG. 1 is a block diagram of a graphics processor including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a rendering output pipeline. [Figure 9A] FIG. 2 is a block diagram showing a graphics processor command format. [Figure 9B] FIG. 2 is a block diagram showing a graphics processor command sequence. [Figure 10] 1 illustrates an exemplary graphics software architecture for a data processing system. [Figure 11A] 1 illustrates an exemplary IP core development function of one embodiment. [Figure 11B]1 illustrates various packaging features of different embodiments. [Figure 11C] 1 illustrates various packaging features of different embodiments. [Figure 11D] 1 illustrates various packaging features of different embodiments. [Figure 12] 1 illustrates an exemplary system of a system-on-chip integrated circuit that can be manufactured using one or more IP cores. [Figure 13] 1 illustrates an exemplary graphics processor of a system-on-chip integrated circuit that may be manufactured using one or more IP cores. [Figure 14] FIG. 13 shows a graphics processor 1340 including one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B. [Figure 15] 1 illustrates an architecture for performing initial training of a machine learning architecture. [Figure 16] We show how a machine learning engine is continuously trained and updated during runtime. [Figure 17] We show how a machine learning engine is continuously trained and updated during runtime. [Figure 18A] Shows how machine learning data is shared across networks. [Figure 18B] Shows how machine learning data is shared across networks. [Figure 19] A method for training a machine learning engine is presented. [Figure 20] 13 shows how nodes exchange ghost region data to perform distributed denoising operations. [Figure 21] 1 illustrates an architecture in which image rendering and denoising operations are distributed among multiple nodes. [Figure 22] Further details of the architecture for distributed rendering and denoising are presented. [Diagram 23] A method for performing distributed rendering and denoising is presented. [Figure 24] Demonstrate machine learning methods. [Diagram 25] 1 shows multiple interconnected general-purpose graphics processors. [Figure 26] A set of convolutional and fully connected layers for machine learning implementation is shown. [Figure 27] Here is an example of a convolutional layer. [Figure 28] 1 shows an example of a set of interconnected nodes in a machine learning implementation. [Figure 29] We present a training framework in which a neural network learns using a training dataset. [Figure 30A] An example of model parallelism and data parallelism will be given. [Figure 30B] This refers to a system on a chip (SoC). [Diagram 31] 1 illustrates a processing architecture including a ray tracing core and a tensor core. [Diagram 32] 1 shows an example of a beam. [Diagram 33] 1 shows an apparatus for performing beam tracing. [Diagram 34] 1 shows an example of a beam hierarchy. [Diagram 35] 1 illustrates a method for performing beam tracing. [Diagram 36] 1 shows an example of a distributed ray tracing engine. [Figure 37] Illustrates the compression performed by the ray tracing system. [Figure 38] Illustrates the compression performed by the ray tracing system. [Figure 39] We show how it can be implemented on a ray tracing architecture. [Diagram 40] 1 illustrates an exemplary hybrid ray tracing apparatus. [Diagram 41] This shows the stack used for ray tracing computations. [Diagram 42] Further details are given for a hybrid ray tracing device. [Diagram 43] 2 shows the bounding volume hierarchy. [Diagram 44] Shows the call stack and traversal state storage. [Diagram 45] Methods for traversal and intersection are presented. [Figure 46A] Shows how multiple dispatch cycles are required to execute a particular shader. [Figure 46B] Shows how multiple dispatch cycles are required to execute a particular shader. [Figure 47] Shows how a single dispatch cycle can execute multiple shaders. [Figure 48] Shows how a single dispatch cycle can execute multiple shaders. [Figure 49] 1 illustrates an architecture for executing ray tracing instructions. [Figure 50] A method for executing ray tracing instructions within a thread is presented. [Figure 51] FIG. 2 is a diagram of a bounding volume according to an embodiment. [Figure 52A] 1 shows a representation of a bounding volume hierarchy. [Figure 52B] 1 shows a representation of a bounding volume hierarchy. [Figure 53] FIG. 1 is a diagram of a ray-box intersection test according to an embodiment; [Figure 54] 16 is a block diagram illustrating an example quantized BVH node 1610 according to an embodiment. [Figure 55] FIG. 11 is a block diagram of a complex floating-point data block used by a quantized BVH node according to a further embodiment. [Figure 56] 1 illustrates a ray-box intersection using quantized values ​​to define a child bounding box relative to a parent bounding box according to an embodiment. [Figure 57]FIG. 13 is a flow diagram of BVH decompression and traversal logic according to an embodiment. [Figure 58] FIG. 2 is a diagram of an example two-dimensional coplanar bounding box. [Figure 59] FIG. 13 is a flow diagram of shared surface BVH logic according to an embodiment. [Figure 60] 1 illustrates one embodiment of an architecture including a traversal circuit for performing box-box testing. [Figure 61] 1 illustrates one embodiment of a traversal circuit with box-to-box test logic. [Figure 62A] 1 illustrates different box-to-box mapping configurations for determining box overlap. [Figure 62B] 1 illustrates different box-to-box mapping configurations for determining box overlap. [Figure 63] 1 illustrates one embodiment of a method for box-box testing. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. However, it will be apparent to one skilled in the art that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the underlying principles of the embodiments of the invention.

[0005] [Exemplary Graphics Processor Architecture and Data Types] (System Overview) 1 is a block diagram of a processing system 100 according to an embodiment. System 100 may be used in a single processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform embedded in a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices, such as in Internet-of-things (IoT) devices with wired or wireless connections to local or wide area networks.

[0006] In one embodiment, the system 100 can include, be coupled to, or be integrated into a server-based gaming platform, a gaming console, including a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, the system 100 is part of a mobile Internet-connected device, such as a mobile phone, a smart phone, a tablet computing device, or a laptop with a small internal storage capacity. The processing system 100 can also include, be coupled to, or be integrated into a wearable device, such as a smart watch wearable device; smart eyewear or clothing that provides visual, audio, haptic output to supplement a real-world visual, audio, haptic experience, or is enhanced with augmented reality (AR) or virtual reality (VR) capabilities to provide text, audio, graphics, video, holographic images or video, or haptic feedback; other augmented reality (AR) devices; or other virtual reality (VR) devices. In some embodiments, the processing system 100 can include, be coupled to, or be integrated into a television or set-top box device. In one embodiment, system 100 may include, be coupled to, or be integrated within an autonomous vehicle, such as a bus, a tractor trailer, an automobile, a motor or power cycle, an airplane, or a glider (or any combination thereof). The autonomous vehicle may use system 100 to process the sensed environment around the vehicle.

[0007] In some embodiments, the one or more processors 102 each include one or more processor cores 107 for processing instructions that, when executed, perform operations for system or user software. In some embodiments, at least one of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 may implement Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Words (VLIW). One or more processor cores 107 may process different instruction sets 109, which may include instructions for implementing emulation of other instruction sets. The processor cores 107 may also include other processing devices, such as a Digital Signal Processor (DSP).

[0008] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a Level-3 (L3) cache or a Last Level Cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherency techniques. A register file 106 may also be included in the processor 102 and may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general purpose registers and other registers may be specific to the design of the processor 102.

[0009] In some embodiments, the one or more processors 102 are coupled to one or more interface buses 110 for transmitting communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. In one embodiment, the interface bus 110 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI express), memory buses, or other types of interface buses. In one embodiment, the processor 102 includes an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, and the platform controller hub (PCH) 130 provides connectivity to I / O devices via a local I / O bus.

[0010] Memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other memory device with suitable performance to function as process memory. In one embodiment, memory device 120 may operate as a system memory for system 100 to store data 122 and instructions 121 for use when one or more processors 102 execute applications or processes. Memory controller 116 also couples to an optional external graphics processor 118, which may communicate with one or more graphics processors 108 within processor 102 to perform graphics and media operations. In some embodiments, graphics, media, or compute operations may be assisted by accelerator 112, which is a co-processor that can be configured to perform a specialized set of graphics, media, or compute operations. For example, in one embodiment, accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or compute operations. In one embodiment, accelerator 112 is a ray tracing accelerator that can be used to perform ray tracing operations in cooperation with graphics processor 108. In one embodiment, an external accelerator 119 may be used instead of or in cooperation with accelerator 112.

[0011] In some embodiments, a display device 111 can be connected to the processor 102. The display device 111 can be one or more internal display devices, such as those of a mobile electronic device or laptop device, or one or more external display devices attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display device 111 can be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0012] In some embodiments, the platform controller hub 130 allows peripherals to connect to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, and a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can be connected via a peripheral bus such as a storage interface (e.g., SATA) or a peripheral component interconnect bus (e.g., PCI, PCI express). The touch sensor 125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long-Term Evolution (LTE) transceiver. Firmware interface 128 enables communication with system firmware and may be, for example, a unified extensible firmware interface (UEFI). Network controller 134 may enable network connectivity to a wired network. In some embodiments, a high performance network controller (not shown) couples to interface bus 110. In one embodiment, audio controller 146 is a multi-channel high definition audio controller. In one embodiment, system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system.Platform controller hub 130 may also connect to one or more Universal Serial Bus (USB) controllers 142 for connecting input devices such as a keyboard and mouse combination 143, a camera 144 or other USB input devices.

[0013] It is recognized that the illustrated system 100 is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, instances of memory controller 116 and platform controller hub 130 may be integrated into a separate external graphics processor, such as external graphics processor 118. In one embodiment, platform controller hub 130 and / or memory controller 116 may be external to one or more processors 102. For example, system 100 may include external memory controller 116 and platform controller hub 130, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 102.

[0014] For example, a circuit board ("sled") on which components such as CPUs, memory, and other components are placed that is designed for increased thermal performance can be used. In some examples, processing components such as processors are placed on the top surface of the sled, and near memory such as DIMMs are placed on the bottom surface of the sled. As a result of the increased airflow provided by this design, the components may operate at higher frequencies and power levels than in a typical system, thereby increasing performance. Additionally, the sled is configured to blind mate with power and data communication cables in the rack, thereby enhancing the ability to quickly remove, upgrade, reinstall, and / or replace. Similarly, individual components placed on the sled, such as processors, accelerators, memory, and data storage drives, are configured to be easily upgraded due to the increased spacing between each other. In an exemplary embodiment, the components further include hardware authentication features to prove their authenticity.

[0015] Data centers can utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and Omni-Path. SLEDs can be coupled to switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Cat 5, Cat 5e, Cat 6, etc.). Because of the high bandwidth, low latency interconnect and network architecture, data centers can pool resources such as physically disaggregated memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.), and data storage drives, and provide them to computational resources (e.g., processors) as needed, allowing the computational resources to access the pooled resources as if they were local.

[0016] A power supply or source can provide voltage and / or current to system 100 or any component or system described herein. In one example, the power supply includes an AC-DC (alternating current to direct current) adapter for plugging into an electrical outlet. Such AC power can be a renewable energy (e.g., solar power) source. In one example, the power supply includes a DC source, such as an external AC-DC converter. In one example, the power supply or source includes wireless charging hardware for charging via proximity of a charging field. In one example, the power source can include an internal battery, an AC source, a motion-based source, a solar power source, or a fuel cell source.

[0017] Figures 2A-2D illustrate a computing system and graphics processor provided in accordance with embodiments described herein. Elements of Figures 2A-2D having the same reference numbers (or names) as elements of any other figure herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such.

[0018] 2A is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. Processor 200 may include additional cores, including additional core 202N, represented by a dashed box. Each of processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cache units 206. The internal cache units 204A-204N and shared cache unit 206 represent a cache memory hierarchy within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid-level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4) or other level cache, with the highest level of cache before external memory classified as an LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N.

[0019] In some embodiments, processor 200 may include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. The system agent core 210 provides management functions for various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

[0020] In some embodiments, one or more of processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, system agent core 210 includes components for coordinating operation of cores 202A-202N during multithreaded processing. System agent core 210 may further include a power control unit (PCU), which includes logic and components for coordinating the power state of processor cores 202A-202N and graphics processor 208.

[0021] In some embodiments, processor 200 further includes a graphics processor 208 for performing graphics processing operations. In some embodiments, graphics processor 208 couples to a set of shared cache unit 206 and system agent core 210, including one or more integrated memory controllers 214. In some embodiments, system agent core 210 also includes a display controller 211 for driving the graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within graphics processor 208.

[0022] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of processor 200. However, alternative interconnect units such as a point-to-point interconnect, a switched interconnect, or other technologies, including technologies known in the art, may be used. In some embodiments, graphics processor 208 couples to ring interconnect 212 via I / O link 213.

[0023] The exemplary I / O link 213 represents at least one of several types of I / O interconnects, including an on-package I / O interconnect that provides communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 can use the embedded memory module 218 as a shared last-level cache.

[0024] In some embodiments, the processor cores 202A-202N are homogenous cores that execute the same instruction set architecture. In other embodiments, the processor cores 202A-202N are heterogeneous with respect to instruction set architecture (ISA), where one or more of the processor cores 202A-202N execute a first instruction set while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous with respect to microarchitecture, where one or more cores having relatively high power consumption are combined with one or more power cores having lower power consumption. In one embodiment, the processor cores 202A-202N are heterogeneous with respect to computational capability. Additionally, the processor 200 can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

[0025] FIG. 2B is a block diagram of hardware logic of a graphics processor core 219 according to some embodiments described herein. Elements of FIG. 2B having the same reference numbers (or names) as elements of any other figures herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such. The graphics processor core 219 may be one or more graphics cores, sometimes referred to as a core slice, in a modular graphics processor. The graphics processor core 219 is an example of one graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 219 may include a fixed function block 230 coupled to multiple sub-cores 221A-221F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0026] In some embodiments, fixed function block 230 includes a geometry / fixed function pipeline 231 that may be shared by all sub-cores in graphics processor core 219, for example in a low-performance and / or low-power graphics processor implementation. In various embodiments, geometry / fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., 3D pipeline 312 as in Figures 3 and 4 described below), a video front-end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer (e.g., unified return buffer 418 in Figure 4 described below).

[0027] In one embodiment, the fixed function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core 219 and other processor cores in the system-on-chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that can be configured to manage various functions of the graphics processor core 219, including thread dispatch, scheduling, and preemption. The media pipeline 234 (e.g., the media pipeline 316 in Figures 3 and 4) includes logic for implementing decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. The media pipeline 234 performs media operations via requests to compute or sample logic in the sub-cores 221-221F.

[0028] In one embodiment, the SoC interface 232 enables the graphics processor core 219 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 232 can also enable communication with fixed function devices within the SoC, such as a camera image processing pipeline, and enable and / or implement the use of global memory atomics that may be shared between the graphics processor core 219 and the CPU within the SoC. The SoC interface 232 can also implement power management controls for the graphics processor core 219 and enable an interface between the clock domain of the graphics core 219 and other clock domains within the SoC. In one embodiment, the SoC interface 232 enables receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. Commands and instructions can be dispatched to the media pipeline 234 when media operations are performed, and to the geometry and fixed function pipelines (e.g., geometry and fixed function pipelines 231, geometry and fixed function pipelines 237) when graphics processing operations are performed.

[0029] Graphics microcontroller 233 can be configured to perform various scheduling and management tasks for graphics processor core 219. In one embodiment, graphics microcontroller 233 can perform graphics and / or compute workload scheduling on various graphics parallel engines in execution unit (EU) arrays 222A-222F, 224A-224F in sub-cores 221A-221F. In this scheduling model, host software executing on a CPU core of an SoC including graphics processor core 219 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. The scheduling operations include determining which workload to run next, submitting the workload to a command streamer, pre-empting existing workloads running on the engines, monitoring the progress of the workloads, and notifying the host software when the workloads are completed. In one embodiment, graphics microcontroller 233 can also implement low power or idle states for graphics processor core 219, providing graphics processor core 219 with the ability to save and restore registers within graphics processor core 219 between low power state transitions independent of the operating system and / or graphics driver software on the system.

[0030] Graphics processor core 219 may have more or less than the illustrated sub-cores 221A-221F and may have up to N modular sub-cores. For each set of N sub-cores, graphics processor core 219 may also include shared function logic 235, shared and / or cache memory 236, geometry / fixed function pipeline 237, and further fixed function logic 238 for accelerating various graphics and computational operations. Shared function logic 235 may include logic units related to shared function logic 420 of FIG. 4 (e.g., samplers, mathematical operations, and / or inter-thread communication logic) that may be shared by each of the N sub-cores in graphics processor core 219. Shared and / or cache memory 236 may be a last level cache for the set of N sub-cores 221A-221F in graphics processor core 219 and may function as a shared memory accessible by multiple sub-cores. Geometry / fixed function pipeline 237 may be included in place of geometry / fixed function pipeline 231 in fixed function block 230 and may include the same or similar logical units.

[0031] In one embodiment, graphics processor core 219 includes further fixed function logic 238, which may include various fixed function acceleration logic used by graphics processor core 219. In one embodiment, further fixed function logic 238 includes a further geometry pipeline for use with position only shading. In position only shading, there are two geometry pipelines: geometry / fixed function pipeline 238, the full geometry pipeline in 231, and a cull pipeline, which is a further geometry pipeline that may be included in further fixed function logic 238. In one embodiment, the cull pipeline is a trimmed down version of the full geometry pipeline. The full pipeline and the cull pipeline may run different instances of the same application, with each instance having a separate context. Position only shading may hide lengthy culling runs of discarded triangles, allowing shading to complete sooner in some cases. For example, in one embodiment, the culling pipeline logic in the additional fixed function logic 238 can execute a position shader in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline fetches and shades only the position attributes of vertices without performing rasterization and rendering of pixels to a frame buffer. The culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled or not. The full pipeline (which may be called a reconstruction pipeline in this case) can consume the visibility information to skip culled triangles to shade only visible triangles that are eventually passed to the rasterization stage.

[0032] In one embodiment, the additional fixed function logic 238 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementations that include optimizations for machine learning training or inference.

[0033] Within each graphics sub-core 221A-221F is a set of execution resources that can be used to execute graphics, media, and compute operations as required by a graphics pipeline, a media pipeline, or a shader program. The graphics sub-cores 221A-221F include a number of EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD / IC) logic 223A-223F, 3D (e.g., texture) samplers 225A-225F, media samplers 226A-226F, shader processors 227A-227F, and shared local memory (SLM) 228A-228F. The EU arrays 222A-222F, 224A-224F each include a number of execution units, which are general purpose graphics processing units capable of performing floating point and integer / fixed point logical operations in service of graphics, media or compute operations including graphics, media and compute shader programs. The TD / IC logic 223A-223F performs local thread dispatch and thread control operations for the execution units within the sub-cores and provides communication between threads executing on the execution units of the sub-cores. The 3D samplers 225A-225F can read textures or other 3D graphics related data into memory. The 3D samplers can read texture data differently based on the configured sample state and the texture format associated with a given texture. The media samplers 226A-226F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each graphics sub-core 221A-221F can alternately include a unified 3D and media sampler. Threads executing on execution units within each of the sub-cores 221A-221F can utilize shared local memory 228A-228F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0034] 2C illustrates a graphics processing unit (GPU) 239 that includes a dedicated set of graphics processing resources arranged into multi-core groups 240A-240N. Details of only a single multi-core group 240A are provided, it being recognized that the other multi-core groups 240B-240N may include the same or similar sets of graphics processing resources.

[0035] As shown, multi-core group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. Scheduler / dispatcher 241 schedules and dispatches graphics threads for execution on the various cores 243, 244, 245. A set of register files 242 stores operand values ​​used by cores 243, 244, 245 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

[0036] One or more combined level 1 (L1) cache and shared memory units 247 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc. locally within each multicore group 240A. One or more texture units 247 may also be used to perform texture operations such as texture mapping and sampling. A level 2 (L2) cache 253 is shared by all or a subset of the multicore groups 240A-240N and stores graphics data and / or instructions for multiple simultaneous graphics threads. As shown, the L2 cache 253 may be shared among multiple multicore groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to memory 249, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0037] Input / output (I / O) circuitry 250 couples GPU 239 to one or more I / O devices 252, such as a digital signal processor (DSP), a network controller, or a user input device. On-chip interconnects may be used to couple I / O device 252 to GPU 239 and memory 249. One or more I / O memory management units (IOMMUs) 251 of I / O circuitry 250 directly couple I / O device 252 to system memory 249. In one embodiment, IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, I / O device 252, CPU 246, and GPU 239 may share the same virtual address space.

[0038] In one implementation, IOMMU 251 supports virtualization. In this case, IOMMU 251 may manage (e.g., in system memory 249) a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses. The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped on context switches (e.g., so that a new context is provided access to the associated set of page tables). Although not shown in FIG. 2C, each of cores 243, 244, 245 and / or multicore groups 240A-240N may include a translation lookaside buffer (TLB) for caching guest virtual-to-guest physical translations, guest physical-to-host physical translations, and guest virtual-to-host physical translations.

[0039] In one embodiment, CPU 246, GPU 239 and I / O devices 252 are integrated into a single semiconductor chip and / or chip package. The illustrated memory 249 may be integrated on the same chip or may be coupled to memory controller 248 via an off-chip interface. In one implementation, memory 249 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, although the underlying principles of the invention are not limited to this particular implementation.

[0040] In one embodiment, tensor cores 244 include multiple execution units specifically designed to perform matrix operations, which are the fundamental computational operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and inference. Tensor cores 244 may perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32-bit), half-precision floating point (e.g., 16-bit), integer word (16-bit), byte (8-bit), and half-byte (4-bit). In one embodiment, the neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to construct a high-quality final image.

[0041] In a deep learning implementation, parallel matrix multiplication operations may be scheduled to run on tensor cores 244. Training neural networks, in particular, requires a significant number of matrix dot product operations. To process N×N×N matrix multiplication inner product formulas, tensor cores 244 may include at least N dot product processing elements. Before the matrix multiplication begins, one entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded every N cycles. There are N dot products to be processed every cycle.

[0042] Matrix elements may be stored in different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for tensor cores 244 to ensure that the most efficient precision is used for different workloads (e.g., inference workloads that can tolerate quantization to bytes and half-bytes, etc.).

[0043] In one embodiment, ray tracing core 245 accelerates ray tracing computations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, ray tracing core 245 includes ray traversal / intersection circuitry for performing ray traversal using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. Ray tracing core 245 may also include circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar construct). In one embodiment, ray tracing core 245 performs traversal and intersection operations in coordination with image denoising techniques described herein, at least some of which may be executed on tensor core 244. For example, in one embodiment, tensor core 244 implements a deep learning neural network to perform denoising of frames generated by ray tracing core 245. However, the CPU 246, the graphics core 243 and / or the ray tracing core 245 may also implement all or part of the denoising and / or deep learning algorithms.

[0044] Additionally, as noted above, a distributed approach to denoising may be used, where the GPU 239 is in a computing device coupled to other computing devices over a network or high speed interconnect. In this embodiment, the interconnected computing devices share neural network learning / training data to improve the speed at which the overall system learns to perform denoising for different types of image frames and / or different graphics applications.

[0045] In one embodiment, the ray tracing core 245 handles all BVH traversal and ray-primitive intersections, preventing the graphics core 243 from being overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing ray-triangle intersection tests (e.g., traversed intersecting rays). Thus, in one embodiment, the multi-core group 240A can simply launch a ray probe, and the ray tracing core 245 independently performs ray traversal and intersections and returns hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. The other cores 243, 244 are freed to perform other graphics or compute work while the ray tracing core 245 performs traversal and intersection operations.

[0046] In one embodiment, each ray tracing core 245 includes a traversal unit for performing BVH test operations and an intersection unit for performing ray-primitive intersection tests. The intersection unit generates a "hit", "no hit", or "multi-hit" response and provides it to the appropriate thread. Between traversal and intersection operations, the execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed to perform other forms of graphics work.

[0047] In one particular embodiment described below, a hybrid rasterization / ray tracing approach is used in which work is distributed between the graphics core 243 and the ray tracing core 245.

[0048] In one embodiment, the ray tracing core 245 (and / or other cores 243, 244) includes a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR), including the DispatchRays command, and hardware support for ray generation shaders, closest-hit shaders, any-hit shaders, and miss shaders, allowing for the allocation of a unique set of shaders and textures for each object. Another ray tracing platform that may be supported by the ray tracing core 245, graphics core 243, and tensor core 244 is Vulkan 1.1.85. However, it should be noted that the principles underlying the present invention are not limited to any particular ray tracing ISA.

[0049] In general, the various cores 245, 244, 243 may support a ray tracing instruction set that includes ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit and exception instructions / functions. More specifically, one embodiment includes ray tracing instructions for performing the following functions:

[0050] Ray Generation - Ray generation commands may be executed for each pixel, sample, or other user-defined allocation of work.

[0051] Closest-Hit - The closest-hit command may be executed to find the closest intersection point of a ray with a primitive in the scene.

[0052] Any-Hit - The any-hit command identifies multiple intersections between rays and primitives in a scene to potentially identify new nearest intersection points.

[0053] Intersection - The intersection command performs ray-primitive intersection tests and outputs the results.

[0054] Per-primitive Bounding box Construction - This instruction constructs a bounding box around a given primitive or group of primitives (e.g., when constructing a new BVH or other acceleration data structure).

[0055] Miss - Indicates that the ray misses all geometry in the scene or a specified area of ​​the scene.

[0056] Visit - Indicates the child volume through which the ray travels.

[0057] Exceptions - Contains exception handlers of various types (e.g., called for various error conditions).

[0058] 2D is a block diagram of a general purpose graphics processing unit (GPGPU) 270 that can be configured as a graphics processor and / or computer accelerator according to embodiments described herein. GPGPU 270 can be interconnected with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system and / or memory buses. In one embodiment, memory 271 is a system memory that may be shared with one or more CPUs 246, and memory 272 is a device memory dedicated to GPGPU 270. In one embodiment, components within GPGPU 270 and device memory 272 may be mapped to memory addresses accessible to one or more CPUs 246. Access to memories 271 and 272 may be achieved via memory controller 268. In one embodiment, memory controller 268 may include an internal direct memory access (DMA) controller 269 or may include logic for performing operations otherwise performed by a DMA controller.

[0059] GPGPU 270 includes multiple cache memories, including L2 cache 253, L1 cache 254, instruction cache 255, and shared memory 256, at least some of which may be partitioned as cache memories. GPGPU 270 also includes multiple computation units 260A-260N. Each computation unit 260A-260N includes a set of vector registers 261, scalar registers 262, vector logic unit 263, and scalar logic unit 264. Computation units 260A-260N may also include local shared memory 265 and program counter 266. Computation units 260A-260N may be coupled with constant cache 267, which may be used to store constant data, which is data that does not change during execution of a kernel or shader program executing on GPGPU 270. In one embodiment, constant cache 267 is a scalar data cache, and cached data may be fetched directly into scalar registers 262.

[0060] During operation, one or more CPUs 246 can write commands to registers or memory within GPGPU 270 that are mapped into an accessible address space. Command processor 257 can read commands from registers or memory and determine how these commands are to be processed within GPGPU 270. Thread dispatcher 258 can then dispatch threads to computation units 260A-260N to execute these commands. Each computation unit 260A-260N can execute threads independently of the other computation units. Additionally, each computation unit 260A-260N can be independently configured for conditional computation and can conditionally output the results of the computation to memory. Command processor 257 can interrupt one or more CPUs 246 when a submitted command is completed.

[0061] Figures 3A-3C show block diagrams of further graphics processor and computation accelerator architectures provided in accordance with embodiments described herein. Elements of Figures 3A-3C having the same reference numbers (or names) as elements of any other figure herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such.

[0062] 3A is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores or other semiconductor devices such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates with commands located in the processor memory via a memory-mapped I / O interface to registers on the graphics processor. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing the memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0063] In some embodiments, the graphics processor 300 also includes a display controller 302 for driving display output data to a display device 318. The display controller 302 includes hardware for one or more overlay surfaces for the display and composition of multiple layers of video or user interface elements. The display device 318 can be an internal or external display device. In one embodiment, the display device 318 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 for encoding, decoding, or transcoding media to, from, or between, one or more media coding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9, ​​and Joint Photographic Experts Group (JPEG) formats such as Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1 and JPEG and Motion JPEG (MJPEG) formats.

[0064] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterization operations, including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a computation engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0065] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable and fixed function elements that perform various tasks within the elements and / or generate execution threads to 3D / media subsystem 315. While 3D pipeline 312 can be used to perform media operations, embodiments of GPE 310 also include a media pipeline 316 that is used specifically to perform media operations such as video post-processing and image enhancement.

[0066] In some embodiments, the media pipeline 316 includes a fixed function or programmable logic unit for performing one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encoding acceleration, instead of or for the video codec engine 306. In some embodiments, the media pipeline 316 further includes a thread generation unit that generates threads for execution on the 3D / media subsystem 315. The generated threads perform calculations for the media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0067] In some embodiments, the 3D / Media subsystem 315 includes logic for executing threads created by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / Media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units for processing the 3D and media threads. In some embodiments, the 3D / Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0068] FIG. 3B illustrates a graphics processor 320 having a tiled architecture according to embodiments described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A in graphics engine tiles 310A-310D. Each graphics engine tile 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each graphics engine tile 310A-310D can also be connected to memory modules or memory devices 326A-326D via memory interconnects 325A-325D. The memory devices 326A-326D can use any graphics memory technology. For example, the memory devices 326A-326D can be graphics double data rate (GDDR) memories. In one embodiment, memory devices 326A-326D are high-bandwidth memory modules (HBM) that may be on-die with their respective graphics engine tiles 310A-310D. In one embodiment, memory devices 326A-326D are stacked memory devices that may be stacked on top of their respective graphics engine tiles 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D resides on a separate chiplet that is coupled to a base die or base substrate, as described in further detail in Figures 11B-11D.

[0069] The graphics processing engine cluster 322 can be connected to an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 can enable communication between the graphics engine tiles 310A-310D and components such as the video codec 306 and one or more copy engines 304. The copy engines 304 can be used to move data to, from, or between the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 can also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 may optionally include a display controller 302 to enable connection to an external display device 318. The graphics processor may also be configured as a graphics or computation accelerator. In an accelerator configuration, the display controller 302 and the display device 318 may be omitted.

[0070] Graphics processor 320 may be connected to a host system via host interface 328. Host interface 328 may enable communication between graphics processor 320, system memory, and / or other system components. Host interface 328 may be, for example, a PCI Express bus or other type of host system interface.

[0071] FIG. 3C illustrates a computation accelerator 330 according to an embodiment described herein. The computation accelerator 330 may include architecture similarities to the graphics processor 320 of FIG. 3B and is optimized for computation acceleration. The computation engine cluster 332 may include a set of computation engine tiles 340A-340D that include execution logic optimized for parallel or vector-based general-purpose computation operations. In some embodiments, the computation engine tiles 340A-340D do not include fixed-function graphics processing logic, while in one embodiment, one or more of the computation engine tiles 340A-340D may include logic for performing media acceleration. The computation engine tiles 340A-340D may be connected to memories 326A-326D via memory interconnects 325A-325D. The memories 326A-326D and memory interconnects 325A-325D may be of similar technology as the graphics processor 320 or may be different. The graphics compute engine tiles 340A-340D may also be interconnected via a set of tile interconnects 323A-323F, which may be connected to and / or by the fabric interconnect 324. In one embodiment, the compute accelerator 330 includes a large L3 cache 336, which may be configured as a device-wide cache. The compute accelerator 330 may also be connected to a host processor and memory via a host interface 328, similar to the graphics processor 320 of FIG. 3B.

[0072] (Graphics Processing Engine) FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3A and may also represent the graphics engine tiles 310A-310D of FIG. 3B. Elements of FIG. 4 having the same reference numbers (or names) as elements of any other figure herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and media pipeline 316 of FIG. 3A are shown. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, in at least one embodiment, a separate media and / or image processor is coupled to the GPE 410.

[0073] In some embodiments, the GPE 410 is coupled to or includes a command streamer 403 that provides a command stream to the 3D pipeline 312 and / or the media pipeline 316. In some embodiments, the command streamer 403 is coupled to a memory, which may be a system memory or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 403 receives commands from the memory and sends the commands to the 3D pipeline 312 and / or the media pipeline 316. The commands are instructions fetched from a ring buffer that stores commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer may further include a batch command buffer that stores a batch of multiple commands. The commands for the 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 312 and / or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process commands and data by executing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 414. In one embodiment, the graphics core array 414 includes one or more blocks of graphics cores (e.g., graphics core 415A, graphics core 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources including general-purpose and graphics-specific execution logic for performing graphics and computational operations, and fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0074] In various embodiments, the 3D pipeline 312 may include fixed function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. General purpose execution logic (e.g., execution units) within the graphics cores 415A-414B of the graphics core array 414 includes support for a variety of 3D API shader languages ​​and can execute multiple concurrent threads of execution associated with multiple shaders.

[0075] In some embodiments, graphics core array 414 includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution unit includes general purpose logic that is programmable to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic can perform processing operations in parallel or in conjunction with general purpose logic in processor core 107 of FIG. 1 or cores 202A-202N as in FIG. 2A.

[0076] Output data generated by threads executing on the graphics core array 414 can output data to memory in a unified return buffer (URB) 418. The URB 418 can store data for multiple threads. In some embodiments, the URB 418 can be used to transmit data between different threads executing on the graphics core array 414. In some embodiments, the URB 418 can also be used for synchronization between the threads on the graphics core array and fixed function logic in the shared function logic 420.

[0077] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of GPE 410. In one embodiment, the execution resources are dynamically scalable such that they may be enabled or disabled as needed.

[0078] The graphics core array 414 couples to shared functionality logic 420 that includes multiple resources shared among the graphics cores in the graphics core array. The shared functionality in the shared functionality logic 420 is a hardware logic unit that provides specialized supplemental functionality to the graphics core array 414. In various embodiments, the shared functionality logic 420 includes, but is not limited to, sampler 421, numeric arithmetic 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 in the shared functionality logic 420.

[0079] Shared functions are implemented at least when the demand for a given specialized function is insufficient to be included within the graphics core array 414. Instead, a single instantiation of that specialized function is implemented as a standalone entity within the shared function logic 420 and shared among the execution resources within the graphics core array 414. The exact set of functions shared among and included within the graphics core array 414 varies by embodiment. In some embodiments, certain shared functions within the shared function logic 420 that are used more extensively by the graphics core array 414 may be included within the shared function logic 416 within the graphics core array 414. In various embodiments, the shared function logic 416 within the graphics core array 414 may include some or all of the logic within the shared function logic 420. In one embodiment, all of the logic elements within the shared function logic 420 may be duplicated within the shared function logic 416 of the graphics core array 414. In one embodiment, the shared function logic 420 is omitted in favor of the shared function logic 416 within the graphics core array 414.

[0080] (Execution unit) 5A-5B illustrate thread execution logic 500 including an array of processing elements used in a graphics processor core in accordance with embodiments described herein. Elements of FIG. 5A-5B having the same reference numbers (or names) as elements of any other figures herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such. FIG. 5A-5B illustrates an overview of thread execution logic 600, which may represent the hardware logic shown in each of sub-cores 221A-221F of FIG. 2B. FIG. 5A illustrates an execution unit in a general-purpose graphics processor, and FIG. 5B illustrates an execution unit that may be used in a computational accelerator.

[0081] As shown in FIG. 5A, in some embodiments, the thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit array including multiple execution units 508A-508N, a sampler 510, a shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 508A, 508B, 508C, 508D-508N-1, and 508N) based on the computational requirements of a workload. In one embodiment, the included components are interconnected via an interconnect fabric that couples to each of the components. In some embodiments, the thread execution logic 500 includes one or more connections to a memory, such as a system memory or a cache memory, through one or more of the instruction cache 506, the data port 514, the sampler 510, and the execution units 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a stand-alone programmable general-purpose computational unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number of individual execution units.

[0082] In some embodiments, the execution units 508A-508N are primarily used to execute shader programs. The shader processor 502 can process various shader programs and dispatch execution threads associated with the shader programs via the thread dispatcher 504. In one embodiment, the thread dispatcher includes logic for arbitrating thread initiation requests from the graphics and media pipelines and instantiating the requested threads on one or more execution units within the execution units 508A-508N. For example, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In some embodiments, the thread dispatcher 504 can also handle run-time thread creation requests from the executing shader programs.

[0083] In some embodiments, the execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). Each of the execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operation allows for an efficient execution environment when faced with higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multiple issue per clock into a pipeline capable of integer, single and double precision floating point operations, SIMD branching capability, logical operations, transcendental operations, and a variety of other operations. While waiting for data from memory or one of the shared functions, dependent logic within the execution units 508A-508N causes the waiting thread to sleep until the requested data is returned. While the waiting thread is sleeping, hardware resources may be allocated to process other threads. For example, during the delay associated with a vertex shader operation, the execution unit may execute operations of a pixel shader, fragment shader, or other type of shader program (including a different vertex shader). Various embodiments may be applied to use execution through the use of Single Instruction Multiple Threads (SIMT) as an alternative to or in addition to the use of SIMD. Reference to a SIMD core or operation may also apply to SIMT or to SIMD in combination with SIMT.

[0084] Each execution unit in execution units 508A-508N operates on an array of data elements. The number of data elements is the "execution size" or number of channels of an instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating point data types.

[0085] The execution unit instruction set includes SIMD instructions. Various data elements can be stored as packed data types in registers, and the execution unit processes the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 54-bit packed data elements (QW (Quad-Word) sized data elements), eight separate 32-bit packed data elements (DW (Double Word) sized data elements), sixteen separate 16-bit packed data elements (W (Word) sized data elements), or thirty-two separate 8-bit data elements (B (byte) sized data elements). However, different vector widths and register sizes are possible.

[0086] In one embodiment, one or more execution units can be coupled to a fused execution unit 509A-509N having thread control logic (507A-507N) common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in a fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to the embodiment. Furthermore, various SIMD widths can be executed per EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, fused execution unit 509A includes a first EU 508A, a second EU 508B, and thread control logic 507A that is common to the first EU 508A and the second EU 508B. Thread control logic 507A controls the threads executing on fused graphics execution unit 509A and enables each EU in fused execution units 509A-509N to execute using a common instruction pointer register.

[0087] One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 for caching thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 512) are included for caching thread data during thread execution. Threads executing on the execution logic 500 can also store explicitly managed data in shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 510 includes specialized texture or media sampling functionality for processing texture or media data during the sampling process before providing the sampled data to the execution units.

[0088] During execution, the graphics and media pipeline sends thread start requests to the thread execution logic 500 via thread creation and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 502 is invoked to further compute output information and write the results to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated between the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 502 then executes pixel or fragment shader programs provided by an application programming interface (API). To execute the shader programs, the shader processor 502 dispatches threads to the execution units (e.g., 508A) via the thread dispatcher 504. In some embodiments, the shader processor 502 uses texture sampling logic within the sampler 510 to access texture data within texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment or discard one or more pixels from further processing.

[0089] In some embodiments, data port 514 provides a memory access mechanism for thread execution logic 500 to output processed data to memory for further processing on the graphics processor output pipeline. In some embodiments, data port 514 includes or is coupled to one or more cache memories (e.g., data cache 512) for caching data for memory access via the data port.

[0090] In one embodiment, the execution logic 500 may also include a ray tracer 505 that may provide ray tracing acceleration functionality. The ray tracer 505 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be similar to the ray tracing instruction set supported by the ray tracing core 245 in FIG. 2C, or may be different.

[0091] 5B illustrates exemplary internal details of an execution unit 508 according to an embodiment. The graphics execution unit 508 may include an instruction fetch unit 537, a general register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, a send unit 530, a branch unit 532, a set of SIMD floating point units 534, and in one embodiment, a set of dedicated integer SIMD ALUs 535. The GRF 524 and ARF 526 include a set of general purpose register files and architectural register files associated with each concurrent hardware thread that may be active in the graphics execution unit 508. In one embodiment, per-thread architectural state is maintained in the ARF 526, while data used during thread execution is stored in the GRF 524. The execution state of each thread, including an instruction pointer for each thread, may be held in thread-specific registers within the ARF 526.

[0092] In one embodiment, the graphics execution unit 508 has an architecture that is a combination of simultaneous multi-threading (SMT) and fine-grained interleaved multi-threading (IMT). The architecture has a modular configuration that can be tweaked at design time based on the target number of simultaneous threads and the number of registers per execution unit, and the execution unit resources are divided among the logic used to execute the multiple simultaneous threads. The number of logical threads that can be executed by the graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0093] In one embodiment, the graphics execution unit 508 can issue multiple instructions simultaneously, each of which may be a different instruction. The thread arbiter 522 of the graphics execution unit thread 508 can dispatch the instruction to one of the send unit 530, the branch unit 532, or the SIMD FPU 534 for execution. Each execution thread can access 128 general purpose registers in the GRF 524, each of which can store 32 bytes and is accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4K bytes in the GRF 524, although embodiments are not so limited and other embodiments may provide greater or lesser register resources. In one embodiment, the graphics processing unit 508 is divided into seven hardware threads that can independently perform computational operations, although the number of threads per execution unit can also vary according to the embodiment. For example, in one embodiment, up to 16 hardware threads are supported. In an embodiment in which the seven threads can access 4K bytes, the GRF 524 can store a total of 28K bytes. If 16 threads can access 4K bytes, then the GRF524 can store a total of 64K bytes. Flexible addressing modes can allow registers to be addressed together to effectively build wider registers or represent strided rectangular block data structures.

[0094] In one embodiment, memory operations, sampler operations and other longer latency system communications are dispatched via "send" instructions implemented by messages passing through send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to achieve SIMD divergence and eventual convergence.

[0095] In one embodiment, the graphics execution unit 508 includes one or more SIMD floating point units (FPUs) 534 for performing floating point operations. In one embodiment, the FPUs 534 also support integer calculations. In one embodiment, the FPUs 534 can SIMD perform up to M 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPUs provides extended math capabilities supporting high throughput transcendental math functions and double precision 54-bit floating point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present and may be specifically optimized for performing operations related to machine learning calculations.

[0096] In one embodiment, an array of multiple instances of the graphics execution unit 508 can be instantiated in a graphics sub-core grouping (e.g., sub-slices). For scalability, a product architect can select the exact number of execution units per sub-core group. In one embodiment, the execution unit 508 can execute instructions across multiple execution channels. In a further embodiment, each thread executing on the graphics execution unit 508 executes on a different channel.

[0097] FIG. 6 illustrates a further execution unit 600 according to one embodiment. The execution unit 600 may be, for example, but not limited to, a compute-optimized execution unit for use in the compute engine tiles 340A-340D of FIG. 3C. Variations of the execution unit 600 may also be used in the graphics engine tiles 310A-310D of FIG. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch / prefetch unit 603, and an instruction decode unit 604. The execution unit 600 further includes a register file 606 that stores registers that can be allocated to hardware threads within the execution unit. The execution unit 600 further includes a send unit 607 and a branch unit 608. In one embodiment, the send unit 607 and the branch unit 608 can operate similarly to the send unit 530 and the branch unit 532 of the graphics execution unit 508 of FIG. 5B.

[0098] The execution unit 600 also includes a computation unit 610 that includes multiple different types of functional units. In one embodiment, the computation unit 610 includes an ALU unit 611 that includes an array of arithmetic logic units. The ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. The integer and floating point operations may be performed simultaneously. The computation unit 610 can also include a systolic array 612 and a numeric operation unit 613. The systolic array 612 includes a W-wide and D-deep network of data processing units that can be used to systolicly perform vector or other data parallel operations. In one embodiment, the systolic array 612 can be configured to perform matrix operations such as a matrix dot product operation. In one embodiment, the systolic array 612 supports 16-bit floating point operations and 8-bit and 4-bit integer operations. In one embodiment, the systolic array 612 can be configured to accelerate machine learning operations. In such an embodiment, systolic array 612 may be configured to support the bfloat 16-bit floating point format. In one embodiment, numeric arithmetic unit 613 may be included to perform a particular subset of numeric operations in a more efficient and lower power manner than ALU unit 611. Numeric arithmetic unit 613 may include a variation of numeric arithmetic logic that may be found within the shared function logic of a graphics processing engine provided by other embodiments (e.g., numeric arithmetic logic 422 of shared function logic 420 of FIG. 4). In one embodiment, numeric arithmetic unit 613 may be configured to perform 32-bit and 64-bit floating point operations.

[0099] The thread control unit 601 includes logic for controlling the execution of threads in the execution units. The thread control unit 601 may include thread arbitration logic for starting, stopping, and preempting the execution of threads in the execution units 600. The thread state unit 602 may be used to store thread states for threads assigned to execute on the execution units 600. Storing thread states in the execution units 600 allows for rapid preemption of threads when they become blocked or idle. The instruction fetch / prefetch unit 603 may fetch instructions from an instruction cache of a higher level of execution logic (e.g., instruction cache 506 as in FIG. 5A). The instruction fetch / prefetch unit 603 may also issue prefetch requests for instructions to be loaded into the instruction cache based on an analysis of currently executing threads. The instruction decode unit 604 may be used to decode instructions to be executed by the computation units. In one embodiment, the instruction decode unit 604 may be used as a secondary decoder for decoding complex instructions into constituent micro-operations.

[0100] Execution unit 600 further includes a register file 606 that can be used by hardware threads executing on execution unit 600. The registers in register file 606 can be divided among logic used to execute multiple simultaneous threads within compute units 610 of execution unit 600. The number of logical threads that can be executed by graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of register file 606 can vary between embodiments based on the number of hardware threads supported. In one embodiment, register renaming may be used to dynamically assign registers to hardware threads.

[0101] 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. The solid lined boxes indicate components that are typically included in an execution unit instruction, while the dashed lines include components that are optional or are only included in a subset of the instructions. In some embodiments, the instruction format 700 described and illustrated is a macro instruction, in that it is an instruction that is supplied to an execution unit as the instruction is processed, as opposed to a micro operation that results from an instruction decode.

[0102] In some embodiments, the graphics processor execution units natively support instructions in 128-bit instruction format 710. A 64-bit compact instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. While the native 128-bit instruction format 710 provides access to all instruction options, some options and operations are restricted in the 64-bit format 730. The native instructions available in the 64-bit format 730 vary depending on the embodiment. In some embodiments, the instruction is compacted in part using a set of index values ​​in index field 713. The execution unit hardware references a set of compaction tables based on the index values ​​and uses the output of the compaction tables to reconstruct the native instruction in the 128-bit instruction format 710. Instructions of other sizes and formats may also be used.

[0103] For each format, the instruction opcode 712 defines the operation that the execution unit is to perform. The execution unit executes each instruction in parallel among the multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation among each color channel representing a texture or picture element. By default, the execution unit executes each instruction among all data channels of an operand. In some embodiments, the instruction control field 714 allows control of certain execution options such as channel selection (e.g., prediction) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710, the exec size field 716 limits the number of data channels that are executed in parallel. In some embodiments, the exec size field 716 is not available for use with the 64-bit compact instruction format 730.

[0104] Some execution unit instructions have up to three operands, including two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions may have a third source operand (e.g., SRC2 724), and the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0105] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether direct or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0106] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and in a second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0107] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. When the direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. When the indirect register addressing mode is used, the register address of one or more operands may be calculated based on an address register value and an address immediate field in the instruction.

[0108] In some embodiments, instructions are grouped based on a bit field in the opcode 712 to simplify opcode decode 740. In an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode groupings shown are merely examples. In some embodiments, the move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares the five most significant bits (MSBs), with move (mov) instructions being of the form 0000xxxxb and logic instructions being of the form 0001xxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions of the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 746 includes a mix of instructions including synchronization instructions (e.g., wait, send) in the format of 0011xxxxb (e.g., 0x30). The parallel math instruction group 748 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the format of 0100xxxxb (e.g., 0x40). The parallel math group 748 performs arithmetic operations in parallel between data channels. The vector math group 750 includes arithmetic instructions (e.g., dp4) in the format of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands. In one embodiment, the illustrated opcode decode 740 can be used to determine which portion of the execution unit is used to execute the decoded instruction. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), can be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic.

[0109] (Graphics Pipeline) Figure 8 is a block diagram of another embodiment of a graphics processor 800. Elements of Figure 8 having the same reference numbers (or names) as elements of any other figure may operate or function in a similar manner as described elsewhere herein, including, but not limited to, those described herein.

[0110] In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a rendering output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor in a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 800 via a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by a command streamer 803, which provides instructions to individual components of geometry pipeline 820 or media pipeline 830.

[0111] In some embodiments, command streamer 803 directs the operation of a vertex fetcher 805, which reads vertex data from memory and executes the vertex processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides the vertex data to a vertex shader 807, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute the vertex processing instructions by dispatching execution threads to execution units 852A-852B via thread dispatcher 831.

[0112] In some embodiments, the execution units 852A-852B are an array of vector processors with an instruction set for performing graphics and media operations. In some embodiments, the execution units 852A-852B have an attached L1 cache 851 that is specific to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

[0113] In some embodiments, the geometry pipeline 820 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operations. A programmable domain shader 817 provides back-end evaluation of the tessellation output. A tessellator 813 operates at the hull shader 811's direction and includes special purpose logic for generating a set of detailed geometric objects based on a coarse geometric model provided as input to the geometry pipeline 820. In some embodiments, if tessellation is not used, the tessellation components (e.g., hull shader 811, tessellator 813, and domain shader 817) can be bypassed.

[0114] In some embodiments, a complete geometric object can be processed by the geometry shader 819 via one or more threads dispatched to execution units 852A-852B, or can proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in earlier stages of the graphics pipeline. The geometry shader 819 receives input from the vertex shader 807 if tessellation is disabled. In some embodiments, the geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation if the tessellation unit is disabled.

[0115] Prior to rasterization, a clipper 829 processes the vertex data. The clipper 829 may be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 873 in the rendering output pipeline 870 dispatches pixel shaders to convert geometric objects into per-pixel representations. In some embodiments, pixel shader logic is included in the thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access un-rasterized vertex data via the stream output unit 823.

[0116] The graphics processor 800 has an interconnect bus, interconnect fabric, or other interconnect mechanism for passing data and messages between the major components of the processor. In some embodiments, the execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via data port 856 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, the sampler 854, caches 851, 858, and the execution units 852A-852B each have a separate memory access path. In one embodiment, the texture cache 858 can also be configured as a sampler cache.

[0117] In some embodiments, the rendering output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a window / mask unit for performing fixed function triangle and line rasterization. An associated rendering cache 878 and depth cache 879 are also available in some embodiments. A pixel operations component 877 performs pixel-based operations on the data, although in some instances pixel operations related to 2D operations (e.g., bit-block image transfer with blending) are performed by the 2D engine 841 or are replaced by the display controller 843 using an overlay display surface at display time. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing sharing of data without using main system memory.

[0118] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from the command streamer 803. In some embodiments, the media pipeline 830 includes a separate command streamer. In some embodiments, the video front end 834 processes the media commands before sending the commands to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function to generate threads that dispatch to the thread execution logic 850 via the thread dispatcher 831.

[0119] In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples to the graphics processor via ring interconnect 802 or other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 includes special purpose logic that can operate independently of the 3D pipeline. In some embodiments, display controller 843 couples to a display device (not shown), which may be a system integrated display device such as in a laptop computer or an external display device attached via a display device connector.

[0120] In some embodiments, the geometry pipeline 820 and the media pipeline 830 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and compute APIs, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines are also supported if a mapping from the future API's pipeline to the graphics processor's pipeline is possible.

[0121] (Graphics Pipeline Programming) Figure 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Figure 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. The solid lined boxes in Figure 9A indicate components that are typically included in a graphics command, while the dashed lines include components that are optional or are included in only a subset of the graphics commands. The example graphics processor command format 900 of Figure 9A includes data fields to identify the client 902, the command operation code (opcode) 904, and the data 906 of the command. Sub-opcodes 905 and command size 908 are also included in some commands.

[0122] In some embodiments, the client 902 specifies a client unit of the graphics device that will process the command data. In some embodiments, the graphics processor command parser inspects the client field of each command to condition further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the command. When a command is received by a client unit, the client unit reads the opcode 904 and, if present, the sub-opcode 905 to determine the operation to perform. The client unit executes the command using the information in the data field 906. For some commands, an explicit command size 908 is assumed to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned over multiples of double words. Other command formats may be used.

[0123] The flow diagram in Figure 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to set up and execute a set of graphics operations to completion. A sample command sequence is shown and described for purposes of example only, and embodiments are not limited to these particular commands or this command sequence. Additionally, commands may be issued as a batch of commands within a command sequence such that the graphics processor processes the sequence of commands at least partially concurrently.

[0124] In some embodiments, a graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipelines to complete commands currently pending for that pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate simultaneously. A pipeline flush is performed to cause the active graphics pipelines to complete pending commands. In response to a pipeline flush, the graphics processor's command parser pauses command processing until the active drawing engines complete pending operations and the associated read caches are invalidated. Optionally, any data in the rendering cache that is marked as "dirty" may be flushed to memory. In some embodiments, the pipeline flush command 912 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0125] In some embodiments, the pipeline select command 913 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 913 is only needed once in an execution context before issuing a pipeline command, unless the context issues commands for both pipelines. In some embodiments, a pipeline flush command 912 is needed immediately before switching pipelines via the pipeline select command 913.

[0126] In some embodiments, pipeline control commands 914 are used to configure the graphics pipeline for operations and to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state for active pipelines. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and to clear data from one or more cache memories in active pipelines before processing a batch of commands.

[0127] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for each pipeline to write data to. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers to which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform inter-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0128] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on the pipeline determination 920, the command sequence is adjusted to either the 3D pipeline 922, beginning with a 3D pipeline state 930, or the media pipeline 924, beginning with a media pipeline state 940.

[0129] Commands for configuring the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, steady color state, depth buffer state, and other state variables that should be configured before 3D primitive commands are processed. The values ​​of these commands are determined at least in part based on the particular 3D API being used. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass certain pipeline elements if they are not used.

[0130] In some embodiments, the 3D primitive 932 command is used to submit a 3D primitive to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 932 command are forwarded to a vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 932 command is used to perform vertex operations on the 3D primitives via vertex shaders. To process the vertex shaders, the 3D pipeline 922 dispatches shader execution threads to the graphics processor execution units.

[0131] In some embodiments, the 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a "go" or "kick" command in a command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometry processing on 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel backend operations may also be included for these operations.

[0132] In some embodiments, the graphics processor command sequence 910 follows a media pipeline 924 path when performing media operations. In general, the particular use and manner of programming for the media pipeline 924 depends on the media or computational operations being performed. Certain media decode operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline may also be bypassed and media decode may be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to rendering graphics primitives.

[0133] In some embodiments, the media pipeline 924 is configured in a similar manner to the 3D pipeline 922. A set of commands to configure the media pipeline state 940 is dispatched or placed in a command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 include data to configure the media pipeline elements used to process the media object. This includes data to configure the video decoding and video encoding logic in the media pipeline, such as the encoding or decoding format. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0134] In some embodiments, the media object command 942 provides a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing the video data to be processed. In some embodiments, all media pipeline state must be valid before issuing the media object command 942. Once the pipeline state is configured and the media object command 942 is queued, the media pipeline 924 is triggered via an execute command 944 or equivalent execute event (e.g., a register write). The output from the media pipeline 924 may then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations.

[0135] (Graphics Software Architecture) 10 illustrates an exemplary graphics software architecture for a data processing system 1000 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. The graphics application 1010 and the operating system 1020 each execute within the system memory 1050 of the data processing system.

[0136] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language, such as Direct3D's High-Level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application also includes executable instructions 1014 in a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0137] In some embodiments, the operating system 1020 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variation of the Linux® kernel. The operating system 1020 can support a graphics API 1022, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is used, the operating system 1020 uses a front-end shader compiler 1024 to compile the HLSL shader instructions 1012 into a low-level shader language. The compilation can be a just-in-time (JIT) compilation, or the application can perform pre-compilation of the shaders. In some embodiments, the high-level shaders are compiled into the low-level shaders during compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate format, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0138] In some embodiments, the user mode graphics driver 1026 includes a back-end shader compiler 1027 for converting the shader instructions 1012 into a hardware-specific representation. When the OpenGL API is being used, the shader instructions 1012 in the GLSL high-level language are passed to the user mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 uses operating system kernel mode functions 1028 to communicate with a kernel mode graphics driver 1029. In some embodiments, the kernel mode graphics driver 1029 communicates with a graphics processor 1032 to dispatch commands and instructions.

[0139] (IP core implementation) One or more aspects of at least one embodiment may be implemented by representational code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions that represent various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations, known as "IP cores," are reusable units of logic for an integrated circuit that may be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be provided to various customers or manufacturing facilities, which load the hardware model into manufacturing machines that manufacture the integrated circuit. The integrated circuit may be manufactured to perform the operations described in connection with any of the embodiments described herein.

[0140] FIG. 11A is a block diagram illustrating an IP core development system 1100 that may be used to fabricate an integrated circuit to perform operations according to an embodiment. The IP core development system 1100 may be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). A design facility 1130 may generate a software simulation 1110 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 1110 may be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and / or timing simulation. A register transfer level (RTL) design 1115 may then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers and includes associated logic that is executed using the modeled digital signals. In addition to the RTL design 1115, a lower level design at the logic or transistor level may also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

[0141] The RTL design 1115 or equivalent may be further synthesized by a design function into a hardware model 1120, which may be a hardware description language (HDL) or other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 1140 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design may be transmitted over a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The manufacturing facility 165 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0142] 11B illustrates a cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processors or accelerator devices described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 coupled to a substrate 1180. The logic 1172, 1174 may be at least partially implemented in hardware of configurable logic or fixed function logic and may include one or more portions of any of the processor cores, graphics processors, or other accelerator devices described herein. Each unit of logic 1172, 1174 may be implemented in a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180 and may include, but is not limited to, interconnects such as bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the package substrate 1180 may include other suitable types of substrates. The package assembly 1170 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0143] In some embodiments, the units of logic 1172, 1174 are electrically coupled to a bridge 1182 configured to route electrical signals between the logic 1172, 1174. The bridge 1182 may be a high density interconnect structure that provides a path for the electrical signals. The bridge 1182 may include a bridge substrate comprised of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide chip-to-chip connections between the logic 1172, 1174.

[0144] Although two units of logic 1172, 1174 and bridge 1182 are shown, the embodiments described herein may include more or fewer logic units on one or more dies. Bridge 1182 may be omitted when logic is included on a single die, and thus one or more dies may be connected by zero or more bridges. Alternatively, multiple dies or logic units may be connected by one or more bridges. Additionally, multiple logic units, dies and bridges may be connected to each other in other possible configurations, including three-dimensional configurations.

[0145] FIG. 11C illustrates a package assembly 1190 including multiple units of hardware logic chiplets connected to a substrate 1180 (e.g., a base die). The graphics processing units, parallel processors, and / or computational accelerators described herein can be constructed from multiple silicon chiplets fabricated separately. In this context, a chiplet is an at least partially packaged integrated circuit that includes separate units of logic that can be assembled into a larger package with other chiplets. Multiple sets of chiplets with different IP core logic can be assembled into a single device. Additionally, chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between different types of IP within a GPU. IP cores can be fabricated using different process technologies and can be configured during fabrication. This avoids the complexity of converging multiple IPs into the same fabrication process, especially on large SoCs with multiple flavors of IP. Enabling the use of multiple process technologies improves time to market and provides a cost-effective way to create multiple product SKUs. Additionally, the decomposed IP is susceptible to being independently power-gated, allowing components not being used in a given workload to be powered off, reducing overall power consumption.

[0146] The hardware logic chiplets can include special purpose hardware logic chiplets 1172, logic or I / O chiplets 1174, and / or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I / O chiplets 1174 may be implemented at least in part in configurable logic or fixed function logic hardware and can include one or more portions of any of the processor cores, graphics processors, parallel processors, or other accelerator devices described herein. The memory chiplets 1175 can be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0147] Each chiplet can be fabricated as a separate semiconductor die and can be coupled to substrate 1180 via interconnect structures 1173. Interconnect structures 1173 can be configured to route electrical signals between the various chiplets and logic within substrate 1180. Interconnect structures 1173 can include, but are not limited to, interconnects such as bumps or pillars. In some embodiments, interconnect structures 1173 can be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic, I / O, and memory chiplets.

[0148] In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the substrate 1180 may include other suitable types of substrates. The package assembly 1190 can be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0149] In some embodiments, the logic or I / O chiplets 1174 and the memory chiplets 1175 can be electrically coupled via a bridge 1187 configured to route electrical signals between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 can be a high density interconnect structure that provides a path for electrical signals. The bridge 1187 can include a bridge substrate comprised of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide chip-to-chip connections between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 can also be referred to as a silicon bridge or an interconnect bridge. For example, in some embodiments, the bridge 1187 is an Embedded Multi-die Interconnect Bridge (EMIB). In some embodiments, the bridge 1187 can simply be a direct connection from one chiplet to another.

[0150] Substrate 1180 can include hardware components for I / O 1191, cache memory 1192, and other hardware logic 1193. Fabric 1185 can be embedded within substrate 1180 to enable communication between various logic chiplets and logic 1191, 1193 within substrate 1180. In one embodiment, I / O 1191, fabric 1185, cache, bridges, and other hardware logic 1193 can be integrated into a base die that is stacked on top of substrate 1180.

[0151] In various embodiments, package assembly 1190 can include fewer or more components and chiplets interconnected by fabric 1185 or one or more bridges 1187. Chiplets in package assembly 1190 can be arranged in a 3D or 2.5D arrangement. In general, bridge structures 1187 can be used to provide point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. Fabric 1185 can be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and / or I / O chiplets. In one embodiment, cache memory 1192 in the substrate can function as a global cache for package assembly 1190, part of a distributed global cache, or a dedicated cache for fabric 1185.

[0152] 11D illustrates a package assembly 1194 including a replaceable chiplet 1195 according to an embodiment. The replaceable chiplet 1195 can be assembled into a standardized slot on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be similar to other bridge interconnects described herein, for example, an EMIB. Memory chiplets can also be connected to logic or I / O chiplets via a bridge interconnect. I / O and logic chiplets can communicate via an interconnect fabric. The base chiplet can support one or more slots in a standardized format for one of logic or I / O or memory / cache.

[0153] In one embodiment, the SRAM and power delivery circuitry can be fabricated in one or more of the base chiplets 1196, 1198, which can be fabricated using a different process technology relative to the replaceable chiplet 1195 stacked on top of the base chiplet. For example, the base chiplets 1196, 1198 can be fabricated using a larger process technology, and the replaceable chiplet can be fabricated using a smaller process technology. One or more of the replaceable chiplets 1195 can be memory (e.g., DRAM) chiplets. Different memory densities can be selected for the package assembly 1194 based on the power and / or performance targeted for the product using the package assembly 1194. Additionally, logic chiplets with different numbers and types of functional units can be selected at assembly time based on the power and / or performance targeted for the product. Additionally, chiplets containing different types of IP logic cores can be inserted into the slots of the replaceable chiplets, enabling hybrid processor designs where IP blocks of different technologies can be mixed and matched.

[0154] Exemplary System-on-Chip Integrated Circuits 12-14 illustrate an exemplary integrated circuit and associated graphics processor that may be manufactured using one or more IP cores in accordance with various embodiments described herein. In addition to what is shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0155] 12 is a block diagram illustrating an example system-on-chip integrated circuit 1200 that may be manufactured using one or more IP cores in accordance with an embodiment. The example integrated circuit 1200 includes one or more application processors 1205 (e.g., a CPU) and at least one graphics processor 1210, and may further include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I / O controller 1236. 2 S / I 2 The integrated circuit may further include peripheral or bus logic including a C controller 1240. Additionally, the integrated circuit may include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including a flash memory and a flash memory controller. Memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits further include an embedded security engine 1270.

[0156] 13-14 are block diagrams illustrating example graphics processors for use within an SoC in accordance with embodiments described herein. FIG. 13A illustrates an example graphics processor 1310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with embodiments. FIG. 13B illustrates a further example graphics processor 1340 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with embodiments. The graphics processor 1310 of FIG. 13A is an example of a low-power graphics processor core. The graphics processor 1340 of FIG. 13B is an example of a high-performance graphics processor core. Each of the graphics processors 1310, 1340 may be a variation of the graphics processor 1210 of FIG. 12.

[0157] As shown in FIG. 13, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D-1315N-1, and 1315N). The graphics processor 1310 can execute different shader programs through separate logic such that the vertex processor 1305 is optimized to execute operations for vertex shader programs, while one or more fragment processors 1315A-1315N execute fragment (e.g., pixel) shader operations for fragment or pixel shader programs. The vertex processor 1305 executes the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to generate a frame buffer that is displayed on a display device. In one embodiment, fragment processors 1315A-1315N are optimized to execute fragment shader programs such as those provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs such as those provided in the Direct 3D API.

[0158] Graphics processor 1310 further includes one or more memory management units (MMUs) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual-to-physical address mapping for graphics processor 1310, including vertex processor 1305 and / or fragment processors 1315A-1315N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1325A-1325B. In one embodiment, one or more MMUs 1320A-1320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220 of Figure 12, such that each processor 1205-1220 can participate in a shared or unified virtual memory system. One or more circuit interconnects 1330A-1330B enable graphics processor 1310 to interface with other IP cores in the SoC via the SoC's internal bus or direct connections, according to an embodiment.

[0159] As shown in Figure 14, graphics processor 1340 includes one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of graphics processor 1310 of Figure 13. Graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F-1355N-1, and 1355N), which provides a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary between embodiments and implementations. Additionally, graphics processor 1340 includes an inter-core task manager 1345 that functions as a thread dispatcher for dispatching execution threads to one or more shader cores 1355A-1355N, and a tile unit 1358 that accelerates tile operations for tile-based rendering, where rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within the scene or to optimize use of internal caches.

[0160] [Ray tracing with machine learning] As mentioned above, ray tracing is a graphics processing technique in which light propagation is simulated through physically based rendering. One of the key operations in ray tracing is processing visibility queries, which require traversal and intersection testing of nodes in a bounding volume hierarchy (BVH).

[0161] Ray tracing and path tracing based techniques calculate images by tracing rays and paths through each pixel and using random sampling to calculate advanced effects such as shadows, glossiness, indirect lighting, etc. Using only a few samples is fast but produces a noisy image, while using many samples produces a high quality image but at a very high cost.

[0162] Machine learning includes any circuitry, program code, or combination thereof that can incrementally improve the performance of a specified task or make incrementally more accurate predictions or decisions. Some machine learning engines can perform tasks or make predictions / decisions without being explicitly programmed to perform these tasks or make these predictions / decisions. There are a variety of machine learning techniques, including, but not limited to, supervised and semi-supervised learning, unsupervised learning, and reinforcement learning.

[0163] In the past few years, a breakthrough solution to ray tracing / path tracing for real-time use has emerged in the form of "denoising", a process that uses image processing techniques to generate high-quality filtered / denoised images from noisy, low-sample inputs. The most effective denoising techniques rely on machine learning techniques where the machine learning engine learns what the noisy image would look like if it were computed with many more samples. In one particular embodiment, the machine learning is performed by a convolutional neural network (CNN), although the principles underlying the invention are not limited to CNN implementations. In such implementations, training data is generated with low-sample inputs and ground-truths. The CNN is trained to predict a convergence pixel from a neighborhood of noisy pixel inputs around the pixel in question.

[0164] While not perfect, this AI-based denoising technique has proven surprisingly effective. It is important to note, however, that good training data is required, as otherwise the network may predict incorrect results. For example, if an animation movie studio trained a denoising CNN on past movies with scenes on land, and then tried to use the trained CNN to denoise frames from a new movie set on water, the denoising operation would perform suboptimally.

[0165] To address this issue, training data can be dynamically collected during rendering, and a machine learning engine such as a CNN may be continuously trained based on the currently running data, thus continually improving the machine learning engine for the task at hand. Thus, the training phase may still be performed before runtime, but continues to adjust the machine learning weights as needed during runtime. Thereby, the high cost of computing the reference data required for training is avoided by restricting the generation of training data to a sub-region of the image every frame or every N frames. In particular, a noisy input of a frame is generated to denoise the entire frame with the current network. Furthermore, a small region of reference pixels is generated and used for continuous training, as described below.

[0166] Although a CNN implementation is described herein, any form of machine learning engine may be used, including, but not limited to, systems that perform supervised learning (e.g., building a mathematical model of a set of data that includes both an input and a desired output), unsupervised learning (e.g., evaluating input data for a particular type of structure), and / or a combination of supervised and unsupervised learning.

[0167] Existing denoising implementations operate in a training phase and a runtime phase. During the training phase, a network topology is defined that receives an NxN pixel region with various per-pixel data channels such as pixel color, depth, normal, normal deviation, primitive ID, and albedo, and generates the final pixel color. A set of "representative" training data is generated using one frame's worth of low sample count inputs, with reference to a "desired" pixel color calculated at a very high sample count. The network is trained towards these inputs, generating a set of "ideal" weights for the network. In these implementations, the reference data is used to train the network weights, making the network's output most closely match the desired result.

[0168] At runtime, pre-computed ideal network weights are loaded and the network is initialized. For each frame, a low-sample image of the denoised input (i.e., the same one used for training) is generated. For each pixel, a given neighborhood of the pixel's input is run through the network to predict the "denoised" pixel color, producing the denoised frame.

[0169] Figure 15 shows an implementation of initial training. A machine learning engine 1500 (e.g., a CNN) receives high sample count image data 1702, an NxN pixel region with various per-pixel data channels such as pixel color, depth, normal, normal deviation, primitive ID, and albedo, and generates the final pixel color. Representative training data is generated using one frame's worth of low sample count inputs 1501. The network is trained on these inputs to generate a set of "ideal" weights 1505 that the machine learning engine 1500 then uses at runtime to denoise the low sample count image.

[0170] To improve upon the above technique, the denoising stage is enhanced to generate new training data every frame or subset of frames (e.g., every N frames where N=2, 3, 4, 10, 25, etc.). In particular, as shown in Fig. 16, one or more regions in each frame, referred to herein as "new reference regions" 1602, are selected, which are rendered at high sample counts into a separate high sample count buffer 1604. A low sample count buffer 1603 stores low sample count input frames 1601 (including low sample regions 1604 that correspond to the new reference regions 1602).

[0171] The position of the new reference region 1602 may be selected randomly, or alternatively, the position of the new reference region 1602 may be adjusted in a pre-specified manner for each new frame (e.g., using a pre-defined movement of the region between frames, being restricted to a specified region in the center of the frame, etc.).

[0172] Regardless of how the new reference region is selected, it is used by the machine learning engine 1600 to continually refine and update the trained weights 1605 used for denoising. In particular, the reference pixel color from each new reference region 1602 is rendered with the noisy reference pixel input from the corresponding low sample count region 1607. Supplemental training is then performed on the machine learning engine 1600 using the high sample count reference region 1602 and the corresponding low sample count region 1607. In contrast to the initial training, this training is performed continuously during runtime for each new reference region 1602, thereby ensuring that the machine learning engine 1600 is trained accurately. For example, per-pixel data channels (e.g., pixel color, depth, normal, normal deviation, etc.) may be evaluated, and the machine learning engine 1600 uses the per-pixel data channels to adjust the trained weights 1605. As in the training case (FIG. 15), the machine learning engine 1600 is trained towards an ideal set of weights 1605 to remove noise from low sample count input frames 1601 and generate denoised frames 1620. However, the trained weights 1605 are continually updated based on new image characteristics of new types of low sample count input frames 1601.

[0173] The retraining operations performed by the machine learning engine 1600 may be executed simultaneously in a background process on a graphics processor unit (GPU) or host processor. A rendering loop, which may be implemented as a driver component and / or a GPU hardware component, may continually generate new training data (e.g., in the form of new reference regions 1602) to place in a queue. A background training process running on the GPU or host processor may continually read new training data from this queue and retrain the machine learning engine 1600, updating it with new weights 1605 at appropriate intervals.

[0174] 17 shows an example of such an implementation, in which a background training process 1700 is implemented by a host CPU 1710. In particular, the background training process 1700 uses new reference regions 1602 with high sample counts and corresponding low sample regions 1604 to continually update trained weights 1605, thereby updating the machine learning engine 1600.

[0175] As shown in FIG. 18A for a non-limiting example of a multiplayer online game, different host machines 1820-1822 individually generate reference regions that background training processes 1700A-C send to a server 1800 (e.g., a game server, etc.). The server 1800 then runs training on the machine learning engine 1810 using the new reference regions received from each of the hosts 1821-1822 and updates the weights 1805 as described above. The server 1800 sends these weights 1805 to the host machine 1820, which stores the weights 1605A-C and updates each respective machine learning engine (not shown) accordingly. The server 1800 may be provided with a large number of reference regions in a short period of time, allowing it to efficiently and accurately update the weights for any given application (e.g., an online game) run by a user.

[0176] As shown in FIG. 18B, different host machines may generate new trained weights (e.g., based on the training / reference domain 1602 described above) and share the new trained weights with a server 1800 (e.g., a game server, etc.), or alternatively, may use a peer-to-peer sharing protocol. A machine learning management component 1810 on the server uses the new weights received from each of the host machines to generate a set of combining weights 1805. The combining weights 1805 may be, for example, averages generated from the new weights and continuously updated as described herein. Once generated, copies of the combining weights 1605A-C may be sent to and stored in each of the host machines 1820-1821, which may then use the combining weights as described herein to perform denoising operations.

[0177] A semi-closed loop update mechanism can also be used by the hardware manufacturer. For example, the reference network may be included as part of the driver distributed by the hardware manufacturer. The driver generates new training data using the techniques described herein and continually sends these back to the hardware manufacturer, who then uses this information to continue improving the machine learning implementation for the next driver update.

[0178] In an exemplary implementation (e.g., batch movie rendering on a render farm), renderers send newly generated training regions to a dedicated server or database (within the studio's render farm), which aggregates this data from multiple rendering nodes over time. A separate process on a separate machine continuously improves the studio's dedicated denoising network, so that new rendering jobs always use the most recently trained network.

[0179] The machine learning method is illustrated in Figure 19. The method may be implemented in the architectures described herein, but is not limited to any particular system or graphics processing architecture.

[0180] At 1901, as part of an initial training stage, low and high sample count image data are generated for multiple image frames. At 1902, a machine learning denoising engine is trained using the high / low sample count image data. For example, a set of convolutional neural network weights associated with pixel features may be updated following the training. However, any machine learning architecture may be used.

[0181] At runtime, low sample count image frames are generated at 1903 along with at least one reference region having a high sample count. At 1904, the high sample count reference regions are used by the machine learning engine and / or separate training logic (e.g., background training module 1700) to continually refine the training of the machine learning engine. For example, the high sample count reference regions may be used in combination with corresponding portions of low sample count images to continue to teach the machine learning engine 1904 how to most effectively perform denoising. For example, in a CNN implementation, this may include updating weights associated with the CNN.

[0182] Variations of the above may be implemented, such as the manner in which the feedback loop to the machine learning engine is configured, the entity that generates the training data, how the training data is fed back to the training engine, and how the improved network is provided to the rendering engine. Additionally, while the above example performs continuous training using a single reference region, any number of reference regions may be used. Additionally, as noted above, the reference regions may be of different sizes, may be used on different numbers of image frames, and may be placed at different locations within the image frames using different techniques (e.g., randomly, according to a predefined pattern, etc.).

[0183] Additionally, although a convolutional neural network (CNN) is described as an example of the machine learning engine 1600, the principles underlying the present invention may be implemented using any type of machine learning engine that can continually refine its results using new training data. By way of example and not limitation, other machine learning implementations include group method of data handling (GMDH), long short-term memory, deep reservoir computing, deep belief network, tensor deep stacking network, and deep predictive coding network, to name a few.

[0184] [Apparatus and method for efficient variance noise removal] As mentioned above, denoising has become a key feature for real-time ray tracing with smooth noise-free images. Rendering can occur across distributed systems on multiple devices, but to date, all existing denoising frameworks run on a single instance on a single machine. When rendering occurs across multiple devices, they may not have all rendered pixels accessible to compute the denoised portion of the image.

[0185] A distributed denoising algorithm is presented that works with both artificial intelligence (AI) and non-AI based denoising techniques. Regions of the image are either already distributed among the nodes from distributed rendering computations or split and distributed from a single framebuffer. If necessary, ghost regions of nearby regions are collected from nearby nodes to compute sufficient denoising, and the resulting tiles are composited into the final image.

[0186] (Distributed Processing) Figure 20 shows multiple nodes 2021-2023 performing rendering. Although only three nodes are shown for simplicity, the underlying principles of the invention are not limited to any particular number of nodes. In fact, a single node may be used to implement a particular embodiment of the invention.

[0187] Nodes 2021-2023 each render a portion of the image, resulting in regions 2011-2013 in this example. Although rectangular regions 2011-2013 are shown in FIG. 20, regions of any shape may be used and any device may process any number of regions. The regions required by the nodes to perform a sufficiently smooth denoising operation are called ghost regions 2011-2013. In other words, ghost regions 2001-2003 represent the totality of data required to perform denoising at a specified level of quality. Reducing the quality level reduces the size of the ghost regions and therefore the amount of data required, while increasing the quality level increases the ghost regions and the corresponding data required.

[0188] If a node, such as node 2021, has a local copy of the portion of ghost region 2001 required to denoise its region 2011 at a specified level of quality, the node obtains the necessary data from one or more "neighboring" nodes, such as node 2022, which owns a portion of ghost region 2001 as shown. Similarly, if node 2022 has a local copy of the portion of ghost region 2002 required to denoise its region 2012 at a specified level of quality, node 2022 obtains the necessary ghost region data 2032 from node 2021. The obtaining may be performed over a bus, interconnect, high speed memory fabric, network (e.g., fast Ethernet), or may be an on-chip interconnect in a multi-core chip that can distribute rendering work among multiple cores (e.g., used to render large images with either extreme resolution or time variation). Each node 2021-2023 may include a separate execution unit or a designated set of execution units within a graphics processor.

[0189] The specific amount of data transmitted will depend on the denoising technique being used. Additionally, the data from the ghost regions may include any data necessary to improve the denoising of the respective regions. For example, the ghost region data may include image color / wavelength, intensity / alpha data and / or normals. However, the underlying principles of the present invention are not limited to any particular set of ghost region data.

[0190] (More details) For slower networks or interconnects, compression of this data can be utilized using existing general purpose lossless or lossy compression. Examples include, but are not limited to, zlib, gzip, and LZMA (Lempel-Ziv-Markov chain algorithm). Additionally, content-specific compression may be used by noting that deltas in ray hit information between frames may be very sparse, and when a node already has a delta collected from a previous frame, only samples that contribute to that delta need to be sent. These can be selectively pushed to node i, which collects these samples, or node i can request samples from other nodes. Lossless compression is used for certain types of data and program code, and lossy compression is used for other types of data.

[0191] FIG. 21 shows further details of the interactions between the nodes 2021-2022. Each node 2021-2022 includes ray tracing rendering circuitry 2081-2082 for rendering the respective image regions 2011-2012 and ghost regions 2001-2002. The denoisers 2100-2111 perform denoising operations on the regions 2011-2012 for which each node 2021-2022 is responsible for rendering and denoising. For example, the denoisers 2021-2022 may include circuitry, software or any combination thereof for generating the denoised regions 2121-2122, respectively. As mentioned above, when generating the denoised regions, the denoisers 2021-2022 may need to rely on data in ghost regions owned by different nodes (e.g., the denoiser 2100 may need data from the ghost region 2002 owned by the node 2022).

[0192] Thus, the denoisers 2100-2111 may generate denoised regions 2121-2122 using data from the regions 2011-2012 and the ghost regions 2001-2002, respectively, at least some of which may be received from other nodes. The region data managers 2101-2102 may manage data transfers from the ghost regions 2001-2002, as described herein. The compressor / decompressor units 2131-2132 may perform compression and decompression of ghost region data exchanged between the nodes 2021-2022, respectively.

[0193] For example, the region data manager 2101 of node 2021, in response to a request from node 2022, may send data from the ghost region 2001 to a compressor / decompressor 2131, which compresses the data to generate compressed data 2106 for transmission to node 2022, thereby reducing bandwidth on an interconnect, network, bus, or other data communication link. The compressor / decompressor 2132 of node 2022 then decompresses the compressed data 2106, and the denoiser 2111 uses the decompressed ghost data to generate a higher quality denoiser region 2012 than would be possible with data from region 2012 alone. The region data manager 2102 may store the decompressed data from the ghost region 2001 in a cache, memory, register file, or other storage to make it available to the denoiser 2111 when generating the denoiser region 2122. A similar set of operations may be performed to provide data from the ghost region 2002 to the denoiser 2100 on node 2021, which uses the data in combination with data from region 2011 to generate a higher quality denoised region 2121.

[0194] (Data capture or rendering) If the connections between devices such as nodes 2021-2022 are slow (i.e., below a threshold latency and / or threshold bandwidth), it may be faster to render the ghost region locally than to request results from other devices. This can be determined at run-time by tracking the network transaction rate and tracking the rendering time linearly extrapolated to the ghost region size. If it is faster to render out the entire ghost region, then multiple devices may end up rendering the same portion of the image. The resolution of the rendered portion of the ghost region may be adjusted based on the variance of the base region and the determined degree of blurriness.

[0195] (load balancing) Static and / or dynamic load balancing schemes may be used to distribute the processing load among the various nodes 2021-2023. For dynamic load balancing, the variance determined by the denoising filter drives the amount of samples used to render a particular region of the scene, such that low variance blurry regions of the image require fewer samples while requiring more time in denoising. The particular regions assigned to a particular node may be dynamically adjusted based on data from previous frames, or may be dynamically communicated between devices as they are rendering, so that all devices have the same amount of work.

[0196] FIG. 22 illustrates how the monitors 2201-2202 running on the respective nodes 2021-2022 collect performance metric data, including but not limited to the time consumed to send data over the network interfaces 2211-2212, the time consumed in denoising the regions (with or without ghost region data), and the time consumed to render each region / ghost region. The monitors 2201-2202 report these performance metrics to the manager or load balancing node 2201, which analyzes the data to identify the current workload on each node 2021-2022 and potentially determine more efficient modes of processing the various denoising regions 2121-2122. The manager node 2201 then distributes new workloads of the new regions to the nodes 2021-2022 according to the detected load. For example, the manager node 2201 may send more work to nodes that are not overloaded and / or reallocate work from nodes that are overloaded. Additionally, the load balancing node 2201 may send reconfiguration commands to adjust the particular way in which rendering and / or denoising is performed by each of the nodes (some examples of which are described above).

[0197] (Ghost area determination) The size and shape of the ghost regions 2001-2002 may be determined based on a denoising algorithm implemented by the denoisers 2100-2111. These respective sizes may then be dynamically modified based on the detected variance of the samples being denoised. The learning algorithm used for the AI ​​denoising itself may be used to determine the appropriate region size, or in other cases such as bilateral blur, a predefined filter width determines the size of the ghost regions 2001-2002. In an exemplary implementation using a learning algorithm, the machine learning engine may run on the manager node 2201 and / or parts of the machine learning may run on each of the individual nodes 2021-2023 (see, e.g., Figures 18A-B above and related text).

[0198] (Collecting final images) The final image may be generated by collecting the rendered and denoised regions from each of the nodes 2021-2023 without the need for ghost regions or normals. In FIG. 22, for example, the denoised regions 2121-2122 are sent to a region processor 2280 of the manager node 2201 which combines the regions to generate a final denoised image 2290, which is then displayed on the display 2290. The region processor 2280 may combine the regions using various 2D compositing techniques. Although shown as separate components, the region processor 2280 and the denoised image 2290 may be integrated into the display 2290. The various nodes 2021-2022 may use direct transmission techniques to transmit the denoised regions 2121-2122, potentially using various lossy or lossless compression of the region data.

[0199] AI denoising remains a costly operation as games move to the cloud. Thus, distributed processing of denoising across multiple nodes 2021-2022 may be necessary to achieve real-time frame rates for traditional games or virtual reality (VR) that require higher frame rates. Movie studios also often render on large render farms that can be utilized for faster denoising.

[0200] An exemplary method for performing distributed rendering and denoising is shown in Figure 23. The method may be implemented in relation to the system architectures described above, but is not limited to any particular system architecture.

[0201] At 2301, graphics work is dispatched to multiple nodes that perform ray tracing operations to render regions of an image frame. Each node may already have the data necessary to perform the operations in memory. For example, two or more nodes may share a common memory, or the local memory of the nodes may already store data from a previous ray tracing operation. Alternatively or in addition, specific data may be sent to each node.

[0202] At 2302, a "ghost region" required for a specified level of denoising (i.e., an acceptable level of performance) is determined. A ghost region includes any data required to perform the specified level of denoising, including data owned by one or more other nodes.

[0203] Data relating to the ghost regions (or portions thereof) is exchanged between the nodes at 2303. At 2304, each node performs denoising on its respective region (e.g., using the exchanged data), and at 2305 the results are combined to generate a final denoised image frame.

[0204] A manager node or primary node, such as that shown in Figure 22, may dispatch work to the nodes and then combine the work performed by the nodes to generate the final image frame. A peer-based architecture may be used, where the nodes are peers that exchange data to render and denoise the final image frame.

[0205] The nodes described herein (e.g., nodes 2021-2023) may be graphics processing computing systems interconnected via a high speed network. Alternatively, the nodes may be individual processing elements coupled to a high speed memory fabric. All of the nodes may share a common virtual memory space and / or a common physical memory. Alternatively, the nodes may be a combination of CPUs and GPUs. For example, the manager node 2201 described above may be a CPU and / or software running on a CPU, and the nodes 2021-2022 may be GPUs and / or software running on a GPU. A variety of different types of nodes may be used and still adhere to the principles underlying the invention.

[0206] (Example Neural Network Implementation) There are many types of neural networks, and a simple type of neural network is a feedforward network. A feedforward network may be implemented as an acyclic graph in which the nodes are arranged in a hierarchy. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer converts the inputs received by the input layer into a representation that is useful for generating an output at the output layer. The network nodes are fully connected to the nodes of adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of a feedforward network is propagated (i.e., "feed forward") to the nodes of the output layer through an activation function that calculates the state of the nodes in each successive layer in the network based on the coefficients ("weights") respectively associated with each of the edges connecting the layers. Depending on the particular model represented by the algorithm being executed, the output from a neural network algorithm can take a variety of forms.

[0207] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training dataset. Training a neural network involves selecting a network topology, using a set of training data representative of the problem being modeled by the network, and adjusting the weights until the network model performs with minimal error for all instances of the training dataset. For example, during the supervised learning training process of a neural network, outputs generated by the network in response to inputs representing instances in the training dataset are compared with the "correct" labeled outputs for the instances, an error signal representing the difference between the outputs and the labeled outputs is calculated, and the weights associated with the connections are adjusted to minimize the error as the error signal is propagated backwards through the layers of the network. The network is considered "trained" when the error for each output generated from an instance of the training dataset is minimized.

[0208] The accuracy of machine learning algorithms can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can require a significant amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, since the calculations performed in adjusting the coefficients in the neural network naturally lend themselves to parallel implementation. In particular, many machine learning algorithms and software applications are adapted to use parallel processing hardware in general-purpose graphics processing devices.

[0209] 24 is a generalized diagram of a machine learning software stack 2400. Machine learning applications 2402 can be configured to train neural networks using a training dataset or to use trained deep neural networks to implement machine intelligence. Machine learning applications 2402 can include training and inference capabilities for neural networks and / or specialized software that can be used to train the neural networks prior to deployment. Machine learning applications 2402 can implement any type of machine intelligence including, but not limited to, image recognition, mapping and positioning, automated navigation, speech synthesis, medical imaging, or language translation.

[0210] Hardware acceleration for machine learning applications 2402 can be enabled through machine learning framework 2404. Machine learning framework 2404 may be implemented on hardware described herein, such as processing system 100 including processors and components described herein. Elements described for FIG. 24 having the same or similar names as elements of any other figures herein describe the same elements as those of other figures, may operate or function in a similar manner as described elsewhere herein, may include the same components, and may link to other entities, including but not limited to such. Machine learning framework 2404 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without machine learning framework 2404, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then reoptimize the computational logic as new parallel processors are developed. Instead, machine learning applications can be configured to perform the necessary computations using primitives provided by machine learning framework 2404. Exemplary primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed while training a convolutional neural network (CNN). The machine learning framework 2404 can also provide primitives that implement basic linear algebra subprograms performed by many machine learning algorithms, such as matrix and vector operations.

[0211] The machine learning framework 2404 can process input data received from the machine learning application 2402 and generate appropriate inputs to the computation framework 2406. The computation framework 2406 can abstract basic instructions provided to the GPGPU drivers 2408 to enable the machine learning framework 2404 to take advantage of hardware acceleration via the GPGPU hardware 2410 without requiring the machine learning framework 2404 to have detailed awareness of the architecture of the GPGPU hardware 2410. Additionally, the computation framework 2406 can enable hardware acceleration for the machine learning framework 2404 across different types and generations of GPGPU hardware 2410.

[0212] (GPGPU Machine Learning Acceleration) FIG. 25 illustrates a multi-GPU computing system 2500, which may be a variation of the processing system 100. Thus, disclosure of any feature in combination with the processing system 100 herein also discloses the corresponding combination with the multi-GPU computing system 2500, but is not limited to such. Elements of FIG. 25 having the same or similar names as elements of any other figures herein describe the same elements in the other figures, may operate or function in a similar manner as described elsewhere herein, may include the same components, and may link to other entities, but is not limited to such. The multi-GPU computing system 2500 may include a processor 2502 coupled to a plurality of GPGPUs 2506A-D via a host interface switch 2504. The host interface switch 2504 may be, for example, a PCI Express switch device that couples the processor 2502 to a PCI Express bus over which the processor 2502 can communicate with the set of GPGPUs 2506A-D. Each of the plurality of GPGPUs 2506A-D may be an instance of a GPGPU as described above. The GPGPUs 2506A-D can be interconnected via a set of high-speed point-to-point inter-GPU links 2516. The high-speed inter-GPU links can be connected to each of the GPGPUs 2506A-D via a dedicated GPU link. The P2P GPU links 2516 allow direct communication between each of the GPGPUs 2506A-D without requiring communication over the host interface bus to which the processor 2502 is connected. With inter-GPU traffic directed to the P2P GPU links, the host interface bus remains available for system memory access or to communicate with other instances of the multi-GPU computing system 2500, for example, via one or more network devices. Instead of connecting the GPGPUs 2506A-D to the processor 2502 via the host interface switch 2504, the processor 2502 can include direct support for the P2P GPU links 2516 and can thus be directly connected to the GPGPUs 2506A-D.

[0213] (Implementation of machine learning neural networks) The computational architecture described herein can be configured to perform a type of parallel processing that is particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is well known in the art, there are various types of neural network implementations that are used in machine learning. One exemplary type of neural network is the feedforward network described above.

[0214] A second exemplary type of neural network is the Convolutional Neural Network (CNN). CNNs are specialized feed-forward neural networks for processing data with a known grid-like topology, such as image data. Thus, CNNs are commonly used for computer vision and image recognition applications, but may also be used for other types of pattern recognition, such as speech and language processing. The nodes in the CNN input layer are organized into sets of "filters" (feature detectors excited by receptive fields in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. CNN computation involves applying a convolutional mathematical operation to each filter to generate the filter's output. Convolution is a special type of mathematical operation performed by two functions to generate a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function for the convolution may be called the input, and the second function may be called the convolution kernel. The output may be called a feature map. For example, the input to a convolutional layer may be a multidimensional array of data that defines the various color components of the input image. The convolution kernel can be a multidimensional array of parameters, which are adapted by a training process for the neural network.

[0215] A recurrent neural network (RNN) is a family of feed-forward neural networks that contain feedback connections between layers. RNNs allow for the modeling of sequential data by sharing parameter data between different parts of the neural network. The architecture of an RNN contains cycles. A cycle represents the influence of a variable's current value on its own value at a future time point, since at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing, due to the variability that language data can comprise.

[0216] The figures described below show exemplary feedforward, CNN and RNN networks and explain the general process for training and deploying each of these types of networks, respectively, with the understanding that these descriptions are exemplary and non-limiting, and that the concepts illustrated are generally applicable to deep neural networks and machine learning techniques.

[0217] The above exemplary neural network can be used to perform deep learning. Deep learning is machine learning using deep neural networks. Deep neural networks used in deep learning are artificial neural networks that are composed of multiple hidden layers, as opposed to shallow neural networks that contain only a single hidden layer. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network allow for multi-stage pattern recognition that results in reduced output error compared to shallow machine learning techniques.

[0218] A deep neural network used in deep learning typically includes a front-end network for performing feature recognition coupled to a back-end network, which represents a computational model that can perform operations (e.g., object classification, speech recognition, etc.) based on feature representations provided to the model. Deep learning allows machine learning to be performed without the need for hand-crafted feature engineering to be performed on the model. Instead, the deep neural network can learn features based on statistical structures or correlations in the input data. The learned features can be provided to a computational model that can map the detected features to an output. The computational model used by the network is generally specialized for the particular task being performed, with different models being used to perform different tasks.

[0219] Once a neural network is constructed, a learning model can be applied to the network to train the network to perform a particular task. The learning model describes how to adjust the weights in the model to reduce the network's output error. Backpropagation of error is a common method used to train neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each of the neurons in the output layer. The error values ​​are then propagated backwards until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from these errors using an algorithm such as a stochastic gradient descent algorithm to update the neural network weights.

[0220] 26-27 show an exemplary convolutional neural network. FIG. 26 shows various layers within a CNN. As shown in FIG. 26, an exemplary CNN used to model image processing can receive an input 2602 describing the red, green, and blue (RGB) components of an input image. The input 2602 can be processed by multiple convolutional layers (e.g., convolutional layer 2604, convolutional layer 2606). The output from the multiple convolutional layers can optionally be processed by a set of fully connected layers 2608. As described above for feedforward networks, neurons in a fully connected layer have full connections to all activations of the previous layer. The output from the fully connected layer 2608 can be used to generate an output result from the network. The activations in the fully connected layer 2608 can be calculated using matrix multiplication instead of convolution. Not all CNN implementations utilize fully connected layers. For example, in some implementations, the convolutional layer 2606 can generate the output for the CNN.

[0221] Convolutional layers are sparsely connected and differ from traditional neural network configurations found in the fully connected layer 2608. Traditional neural network layers are fully connected, such that every output unit interacts with every input unit. Convolutional layers, however, are sparsely connected because the output of the convolution of the field is input to the nodes of the subsequent layer (instead of each state value of each of the nodes in the field), as shown. The kernels associated with the convolutional layers perform the convolution operation, and the output is sent to the next layer. The dimensionality reduction performed within the convolutional layers is one aspect that allows CNNs to scale to process large images.

[0222] 27 shows exemplary computational steps within a convolutional layer of a CNN. The input to the convolutional layer 2712 of the CNN can be processed in three stages in the convolutional layer 2714. The three stages can include a convolution stage 2716, a detection stage 2718, and a pooling stage 2720. The convolutional layer 2714 can then output data to a successive convolutional layer. The final convolutional layer of the network can generate output feature map data or provide input to a fully connected layer, for example, to generate a classification value for input to the CNN.

[0223] The convolution stage 2716 performs several convolutions in parallel to generate a set of linear activations. The convolution stage 2716 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (such as a neuron) connected to a particular region in the input. This can be determined as a local region associated with the neuron. The neuron calculates the dot product between the neuron's weight and the region in the local input to which the neuron is connected. The output from the convolution stage 2716 defines a set of linear activations that are processed by successive stages of the convolution layer 2714.

[0224] The linear activations may be processed by a detection stage 2718. In the detection stage 2718, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the non-linear character of the entire network without affecting the receptive fields of the convolutional layers. Several types of non-linear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x)=max(0,x), such that the activation is thresholded at zero.

[0225] The pooling stage 2720 uses a pooling function that replaces the output of the convolutional layer 2706 with a summary statistic of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that small translations to the input do not change the pooled output. Local translation invariance can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 2720, including max pooling, average pooling, and l2-norm pooling. Furthermore, some CNN implementations do not include a pooling stage. Instead, such implementations substitute a further convolution stage with an increased stride relative to the previous convolution stage.

[0226] The output from the convolutional layer 2714 may then be processed by the next layer 2722, which may be one of a further convolutional layer or a fully connected layer 2708. For example, the first convolutional layer 2704 in FIG. 27 may output to a second convolutional layer 2706, which may output to the first layer of fully connected layers 2808.

[0227] FIG. 28 illustrates an exemplary recurrent neural network 2800. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be constructed in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on a series of prior inputs. For example, RNNs may be used to perform statistical language modeling to predict the next word given a previous sequence of words. The illustrated RNN 2800 can be described as having an input layer 2802 that receives input vectors, a hidden layer 2804 that implements a recurrent function, a feedback mechanism 2805 that allows a "memory" of previous states, and an output layer 2806 that outputs the results. The RNN 2800 operates on a time-step basis. The state of the RNN at a given time step is influenced based on the previous time step via the feedback mechanism 2805. For a given time step, the state of the hidden layer 2804 is defined by the previous state and the input at the current time step. An initial input (x1) at a first time step may be processed by the hidden layer 2804. A second input (x2) may be processed by the hidden layer 2804 using state information determined during processing of the initial input (x1). A given state may be calculated as s_t=f(Ux_t+Ws_(t-1)), where U and W are parameter matrices. The function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or the normalization function f(x)=max(0,x). However, the particular mathematical function used in the hidden layer 2804 may vary depending on the particular implementation details of the RNN 2800.

[0228] In addition to the basic CNN and RNN networks described above, variations of these networks may be possible. One example of a variation of an RNN is the long short term memory (LSTM) RNN. LSTM RNNs can learn long-term dependencies that may be necessary to process longer sequences of language. A variation of a CNN is the convolutional deep belief network, which has a similar structure to a CNN and is trained in a similar manner to a deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of random (random) variables. DBNs can be trained layer-by-layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining an optimal initial set of weights for the neural network.

[0229] FIG. 29 illustrates the training and deployment of deep neural networks. Once a given network is structured for a task, the neural network is trained using a training dataset 2902. Various training frameworks 2904 have been developed to allow hardware acceleration of the training process. For example, the machine learning frameworks described above may be configured as training frameworks. The training frameworks 2904 can pull in an untrained neural network 2906, allowing the untrained neural net to be trained using parallel processing resources as described herein to generate a trained neural net 2908.

[0230] To begin the training process, initial weights may be selected randomly or by pre-training using a deep belief network. Training cycles are then performed in either a supervised or unsupervised manner.

[0231] Supervised learning is a learning method in which training is performed as an intermediary operation, such as when a training dataset 2902 includes inputs paired with desired outputs for the inputs, or when a training dataset includes inputs with known outputs and the output of the neural network is manually scored. The network processes the inputs and compares the resulting output against the expected or desired output. Errors are then back-propagated through the system. The training framework 2904 can be adjusted to adjust the weights that control the untrained neural network 2906. The training framework 2904 can provide tools to monitor how the untrained neural network 2906 is converging towards a model suitable for generating correct answers based on known input data. The training process occurs iteratively as the network weights are adjusted to refine the output generated by the neural network. The training process can continue until the neural network reaches a desired statistical accuracy associated with the trained neural net 2908. The trained neural network 2908 can then be deployed to implement any number of machine learning operations.

[0232] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, a training dataset 2902 includes input data without associated output data. An untrained neural network 2906 can learn groupings within the unlabeled inputs and determine how individual inputs relate to the overall dataset. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 2907 that can perform operations useful for reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points within an input dataset that deviate from normal patterns of data.

[0233] Variations on supervised and unsupervised training may also be used. Semi-supervised learning is a technique that includes a mixture of labeled and unlabeled data of the same distribution in the training data set 2902. Incremental learning is a variation of supervised learning, where input data is continually used to further train the model. Incremental learning allows the trained neural network 2908 to adapt to new data 2912 without forgetting the knowledge instilled in the network during initial training.

[0234] The training process, whether supervised or unsupervised, especially for deep neural networks, can be too computationally intensive for a single computing node. Instead of using a single computing node, a distributed network of computing nodes can be used to accelerate the training process.

[0235] 30A is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes, such as those described above, to perform supervised or unsupervised training of a neural network. The distributed computing nodes may each include one or more host processors and one or more general purpose processing nodes, such as a massively parallel general purpose graphics processing unit. As shown, distributed learning can be performed with model parallelism 3002, data parallelism 3004, or a combination of model and data parallelism.

[0236] In model parallelism 3002, different computational nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Advantages of model parallelism include the ability to scale, especially for large models. Splitting up the computations associated with different layers of a neural network allows for the training of very large neural networks where all layer weights do not fit into the memory of a single computational node. In some examples, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0237] In data parallelism 3004, different nodes of the distributed network have a complete instance of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. Different approaches to data parallelism are possible, but all data parallel training approaches require a technique to combine the results and synchronize the model parameters between each node. Exemplary approaches for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transferring parameters from the nodes to the parameter server, updates to the model are transferred. Additionally, update-based data parallelism can be performed in a distributed manner, with updates being compressed and transferred between nodes.

[0238] The combined model and data parallelism 3006 can be implemented, for example, in a distributed system where each compute node contains multiple GPUs. Each node can have a complete instance of the model, and separate GPUs within each node are used to train different parts of the model.

[0239] Distributed training has increased overhead relative to training on a single machine, but the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques to enable high-bandwidth inter-GPU data transfers and accelerated remote data synchronization.

[0240] (Example machine learning application) Machine learning can be applied to solve a variety of technical problems, including, but not limited to, computer vision, autonomous driving and navigation, speech recognition, and language processing. Traditionally, computer vision has been one of the most active research areas for machine learning applications. Applications of computer vision range from replicating human visual capabilities, such as facial recognition, to creating new categories of visual capabilities. For example, computer vision applications can be configured to recognize sound waves from vibrations induced in objects seen in a video. Parallel processor accelerated machine learning allows computer vision applications to be trained using significantly larger training datasets than previously feasible, allowing inference systems to be deployed using low-power parallel processors.

[0241] Parallel processor accelerated machine learning has applications in autonomous driving including lane and road sign recognition, obstacle avoidance, navigation and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein enable rapid training of increasingly complex neural networks used in autonomous driving solutions and enable deployment of low power inference processors on moving platforms suitable for integration into autonomous vehicles.

[0242] Parallel processor accelerated deep neural networks have enabled machine learning approaches to automatic speech recognition (ASR), which involves the generation of a function that computes the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled the replacement of hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0243] Parallel processor accelerated machine learning can also be used to accelerate natural language processing. Automated learning procedures can utilize statistical inference algorithms to generate models that are robust to erroneous or unusual inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0244] Parallel processing platforms used for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically massively parallel and include optimizations for accelerating multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include the massively parallel general-purpose graphics processing units and / or multi-GPU computing systems described herein. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and self-driving vehicles.

[0245] FIG. 30B illustrates an exemplary inference system on a chip (SOC) 3100 suitable for performing inference using the trained model. Elements of FIG. 30B having the same or similar names as elements of any other figures herein describe the same elements as those of the other figures, may operate or function in a similar manner as described elsewhere herein, may include the same components, and may be linked to other entities, including but not limited to such. The SOC 3100 may integrate processing components including a media processor 3102, a vision processor 3104, a GPGPU 3106, and a multi-core processor 3108. The SOC 3100 may further include an on-chip memory 3105 that may enable a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low power operation to enable deployment in various machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 3100 may be used as part of a master control system for an autonomous vehicle. When the SOC3100 is configured for use in an autonomous vehicle, the SOC will be designed and configured to comply with the relevant functional safety references of the deployment jurisdiction.

[0246] During operation, the media processor 3102 and the vision processor 3104 can work together to accelerate computer vision operations. The media processor 3102 can enable low latency decoding of multiple high resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 3105. The vision processor 3104 can then analyze the decoded video and perform pre-processing operations on frames of the decoded video in preparation for processing the frames using a trained image recognition model. For example, the vision processor 3104 can accelerate the convolution operations of a CNN used to perform image recognition on high resolution video data, while the back-end model calculations are performed by the GPGPU 3106.

[0247] The multi-core processor 3108 may include control logic to assist in ordering and synchronizing data transfers and shared memory operations performed by the media processor 3102 and the vision processor 3104. The multi-core processor 3108 may also function as an application processor for executing software applications that can utilize the inference computational power of the GPGPU 3106. For example, at least a portion of the navigation and driving logic may be implemented in software that executes on the multi-core processor 3108. Such software may issue computational workloads directly to the GPGPU 3106, or the computational workloads may be issued to the multi-core processor 3108, which may offload at least a portion of these operations to the GPGPU 3106.

[0248] The GPGPU3106 may include processing clusters within the massively parallel general purpose graphics processing unit DPLAB00, such as low power configurations of processing clusters DPLAB06A-DPLAB06H. The processing clusters within the GPGPU3106 may support instructions specifically optimized for performing inference calculations on trained neural networks. For example, the GPGPU3106 may support instructions for performing low precision calculations, such as 8-bit and 4-bit integer vector operations.

[0249] [Ray Tracing Architecture] In one implementation, a graphics processor includes circuitry and / or program code for performing real-time ray tracing. A dedicated set of ray tracing cores may be included in the graphics processor to perform various ray tracing operations described herein, including ray traversal and / or ray intersection operations. In addition to the ray tracing cores, multiple sets of graphics processing cores for performing programmable shading operations and multiple sets of tensor cores for performing matrix operations on tensor data may also be included.

[0250] FIG. 31 illustrates an exemplary portion of one such graphics processing unit (GPU) 3105 including a dedicated set of graphics processing resources arranged in multi-core groups 3100A-3100N. The graphics processing unit (GPU) 3105 may be a variation of the graphics processor 300, the GPGPU 1340, and / or any other graphics processor described herein. Thus, disclosure of any feature of the graphics processor also discloses the corresponding combination with the GPU 3105, but is not limited to such. Additionally, elements of FIG. 31 having the same or similar names as elements of any other figure herein describe the same elements as in the other figures, may operate or function in a similar manner as described elsewhere herein, may include the same components, and may be linked to other entities, but is not limited to such. Although details of only a single multi-core group 3100A are provided, it will be appreciated that the other multi-core groups 3100B-N may comprise the same or similar sets of graphics processing resources.

[0251] As shown, multi-core group 2100A may include a set of graphics cores 3130, a set of tensor cores 3140, and a set of ray tracing cores 3150. Scheduler / dispatcher 241 schedules and dispatches graphics threads for execution on the various cores 3130, 3140, 3150. A set of register files 3120 stores operand values ​​used by cores 3130, 3140, 3150 when executing graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. The tile registers may be implemented as a combined set of vector registers.

[0252] One or more level 1 (L1) caches and texture units 3160 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc. locally within each multicore group 3100A. A level 2 (L2) cache 3180 is shared by all or a subset of the multicore groups 3100A-3100N and stores graphics data and / or instructions for multiple simultaneous graphics threads. As shown, the L2 cache 3180 may be shared among multiple multicore groups 3100A-3100N. One or more memory controllers 3170 couple the GPU 3105 to memory 3198, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0253] An input / output (IO) circuit 3195 couples the GPU 3105 to one or more I / O devices 3195, such as a digital signal processor (DSP), a network controller, or a user input device. An on-chip interconnect may be used to couple the I / O devices 3190 to the GPU 3105 and to memory 3198. One or more IO memory management units (IOMMUs) 3170 of the IO circuit 3195 directly couple the IO devices 3190 to the system memory 3198. The IOMMUs 3170 manage multiple sets of page tables to map virtual addresses to physical addresses in the system memory 3198. Additionally, the IO devices 3190, the CPU 3199, and the GPU 3105 may share the same virtual address space.

[0254] IOMMU 3170 also supports virtualization. In this case, IOMMU 3170 may manage (e.g., in system memory 3198) a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses. The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped on context switch (e.g., so that a new context is provided access to the associated set of page tables). Although not shown in FIG. 31, each of cores 3130, 3140, 3145 and / or multicore groups 3100A-3100N may include a translation lookaside buffer (TLB) for caching guest virtual-to-guest physical translations, guest physical-to-host physical translations, and guest virtual-to-host physical translations.

[0255] The CPU 3199, GPU 3105 and IO devices 3190 may be integrated into a single semiconductor chip and / or chip package. The illustrated memory 3198 may be integrated on the same chip or may be coupled to the memory controller 3170 via an off-chip interface. In one implementation, the memory 3198 includes GDDR6 memory that shares the same virtual address space as other physical system level memory, although the underlying principles of the invention are not limited to this particular implementation.

[0256] The tensor cores 3140 include multiple execution units specifically designed to perform matrix operations, which are the fundamental computational operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and inference. The tensor cores 3140 may perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32-bit), half-precision floating point (e.g., 16-bit), integer word (16-bit), byte (8-bit), and half-byte (4-bit). Neural network implementations may also extract features of each rendered scene, potentially combining details from multiple frames to construct a high-quality final image.

[0257] In a deep learning implementation, parallel matrix multiplication operations may be scheduled to run on the tensor cores 3140. Training neural networks, in particular, requires a significant number of matrix dot product operations. To process N×N×N matrix multiplication inner product formulas, the tensor cores 3140 may include at least N dot product processing elements. Before the matrix multiplication begins, one entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded every N cycles. There are N dot products to be processed every cycle.

[0258] Matrix elements may be stored in different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for tensor cores 3140 to ensure that the most efficient precision is used for different workloads (e.g., inference workloads that can tolerate quantization to bytes and half-bytes, etc.).

[0259] The ray tracing core 3150 may be used to accelerate ray tracing computations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, the ray tracing core 3150 may include ray traversal / intersection circuitry to perform ray traversal using a bounding volume hierarchy (BVH) and identify intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 3150 may also include circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar configuration). In one embodiment, the ray tracing core 3150 performs traversal and intersection operations in coordination with image denoising techniques described herein, at least some of which may be executed on the tensor core 3140. For example, the tensor core 3140 may implement a deep learning neural network to perform denoising of frames generated by the ray tracing core 3150. However, the CPU 3199, graphics core 3130 and / or ray tracing core 3150 may also implement all or part of the denoising and / or deep learning algorithms.

[0260] Additionally, as noted above, a distributed approach to denoising may be used, with the GPU 3150 in a computing device coupled over a network or high speed interconnect to other computing devices. The interconnected computing devices may further share neural network learning / training data to improve the speed at which the overall system learns to perform denoising for different types of image frames and / or different graphics applications.

[0261] The ray tracing cores 3150 may handle all BVH traversal and ray-primitive intersections, preventing the graphics core 3130 from being overloaded with thousands of instructions per ray. Each ray tracing core 3150 may include a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuitry for performing ray-triangle intersection tests (e.g., traversed intersecting rays). Thus, the multi-core group 3100A can simply launch a ray probe, and the ray tracing cores 3150 independently perform ray traversal and intersections and return hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. The other cores 3130, 3140 may be freed to perform other graphics or compute work while the ray tracing cores 3150 perform traversal and intersection operations.

[0262] Each ray tracing core 3150 may include a traversal unit for performing BVH test operations and an intersection unit for performing ray-primitive intersection tests. The intersection unit may then generate a "hit," "no hit," or "multi-hit" response and provide it to the appropriate thread. Between traversal and intersection operations, the execution resources of other cores (e.g., graphics core 3130 and tensor core 3140) may be freed up to perform other forms of graphics work.

[0263] A hybrid rasterization / ray tracing approach may also be used, in which work is distributed between the graphics core 3130 and the ray tracing core 3150.

[0264] The ray tracing core 3150 (and / or other cores 3130, 3140) may include a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR), including the DispatchRays command, as well as hardware support for ray generation shaders, closest-hit shaders, any-hit shaders, and miss shaders, allowing for the allocation of a unique set of shaders and textures for each object. Another ray tracing platform that may be supported by the ray tracing core 3150, graphics core 3130, and tensor core 3140 is Vulkan 1.1.85. However, it should be noted that the principles underlying the present invention are not limited to any particular ray tracing ISA.

[0265] In general, the various cores 3150, 3140, 3130 may support a ray tracing instruction set that includes ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit and exception instructions / functions. More specifically, ray tracing instructions for performing the following functions may be included:

[0266] Ray Generation - Ray generation commands may be executed for each pixel, sample, or other user-defined allocation of work.

[0267] Closest-Hit - The closest-hit command may be executed to find the closest intersection point of a ray with a primitive in the scene.

[0268] Any-Hit - The any-hit command identifies multiple intersections between rays and primitives in a scene to potentially identify new nearest intersection points.

[0269] Intersection - The intersection command performs ray-primitive intersection tests and outputs the results.

[0270] Per-primitive Bounding box Construction - This instruction constructs a bounding box around a given primitive or group of primitives (e.g., when constructing a new BVH or other acceleration data structure).

[0271] Miss - Indicates that the ray misses all geometry in the scene or a specified area of ​​the scene.

[0272] Visit - Indicates the child volume through which the ray travels.

[0273] Exceptions - Contains exception handlers of various types (e.g., called for various error conditions).

[0274] [Hierarchical beam tracing] Bounding volume hierarchies are commonly used to improve the efficiency with which operations are performed on graphics primitives and other graphics objects. A BVH is a hierarchical tree structure built on a set of geometric objects. At the top of the tree structure is a root node that encloses all of the geometric objects in a given scene. Individual geometric objects are enclosed in bounding volumes that form the leaf nodes of the tree. These nodes are then grouped into smaller sets and enclosed in larger bounding volumes. These are then also recursively grouped and enclosed in other larger bounding volumes, finally resulting in a tree structure with a single bounding volume represented by the root node at the top of the tree. Bounding volume hierarchies are used to efficiently support various operations on sets of geometric objects, such as collision detection, primitive culling, and ray traversal / intersection operations used in ray tracing.

[0275] In a ray tracing architecture, rays are traversed through the BVH to determine ray-primitive intersections. For example, if a ray does not pass through the root node of the BVH, the ray does not intersect with any of the primitives enclosed by the BVH, and no further processing is required for the ray with respect to this set of primitives. If a ray passes through the first child node of a BVH but not the second child node, the ray does not need to be tested against primitives enclosed by the second child node. In this way, the BVH provides an efficient mechanism for testing ray-primitive intersections.

[0276] A group of consecutive rays, called a "beam," may be tested against the BVH rather than individual rays. Figure 32 shows an example beam 3201, shown diagrammatically with four different rays. Any rays that intersect with a patch 3200 defined by the four rays are considered to be in the same beam. Although the beam 3201 in Figure 32 is defined by a rectangular arrangement of rays, the beam may be defined in a variety of other ways (e.g., a circle, an ellipse, etc.) while still adhering to the principles underlying the invention.

[0277] FIG. 33 illustrates how the ray tracing engine 3310 of the GPU 3320 implements the beam tracing techniques described herein. In particular, the ray generation circuit 3304 generates a number of rays on which traversal and intersection operations are performed. However, rather than performing traversal and intersection operations on individual rays, the traversal and intersection operations are performed using a hierarchy of beams 3307 generated by the beam hierarchy construction circuit 3305. A beam hierarchy is similar to a bounding volume hierarchy (BVH). For example, FIG. 34 provides an example of a primary beam 3400 that may be subdivided into multiple different components. In particular, the primary beam 3400 may be divided into quadrants 3401-3404, and each quadrant may itself be divided into sub-quadrant such as sub-quadrant A-D within the quadrant 3404. The primary beam may be subdivided in various ways. For example, the primary beam may be divided into halves (rather than quarters), each half may be divided into halves, etc. Regardless of how the subdivision is done, a hierarchical structure is created similar to a BVH, e.g., with a root node representing the primary beam 3400, first level child nodes (each represented by a quadrant 3401-3404), second level child nodes for each sub-quadrant A-D, etc.

[0278] Once the beam hierarchy 3307 is constructed, the traversal / intersection circuit 3306 may perform traversal / intersection operations using the beam hierarchy 3307 and the BVH 3308. In particular, the beam may be tested against the BVH and portions of the beam that do not intersect with any portion of the BVH may be culled. Using the data shown in Figure 34, for example, if the sub-beams associated with sub-regions 3402 and 3403 do not intersect with the BVH or a particular branch of the BVH, they may be culled with respect to the BVH or branch. The remaining portions 3401, 3404 may be tested against the BVH by performing a depth-first search or other search algorithm.

[0279] A method for ray tracing is shown in Figure 35. The method may be implemented within the context of the graphics processing architectures listed above, but is not limited to any particular architecture.

[0280] At 3500, a primary beam is constructed containing multiple rays, and at 3501, the beam is subdivided and a hierarchical data structure is generated to create the beam hierarchy. Operations 3500-3501 may be performed as a single integrated operation to build a beam hierarchy from multiple rays. At 3502, the beam hierarchy is used with the BVH to cull rays (from the beam hierarchy) and / or nodes / primitives from the BVH. At 3503, ray-primitive intersections are determined for the remaining rays and primitives.

[0281] [Lossy and lossless packet compression in distributed ray tracing systems] Ray tracing computations may be distributed among multiple computing nodes coupled together over a network. For example, Figure 36 shows a ray tracing cluster 3600 including multiple ray tracing nodes 3610-3613 performing ray tracing computations in parallel and potentially combining the results at one of the nodes. In the illustrated architecture, the ray tracing nodes 3610-3613 are communicatively coupled to a client-side ray tracing application 3630 via a gateway.

[0282] One of the challenges of a distributed architecture is the large amount of packetized data that must be transmitted between each of the ray tracing nodes 3610-3613. Both lossless and lossy compression techniques may be used to reduce the data transmitted between the ray tracing nodes 3610-3613.

[0283] To implement lossless compression, rather than sending packets filled with the results of a particular type of operation, data or commands are sent that allow the receiving node to reconstruct the results. For example, stochastically sampled area lights and ambient occlusion (AO) operations do not necessarily require a direction. Thus, the sending node can simply send a random seed, which is then used by the receiving node to perform the random sampling. For example, if a scene is distributed among nodes 3610-3612, to sample light 1 at points p1-p3, only the light ID and origin need to be sent to nodes 3610-3612. Each node may then stochastically sample the light independently. The random seed may be generated by the receiving node. Similarly, for the primary ray hit point, ambient occlusion (AO) and soft shadow sampling can be calculated on nodes 3610-3612 without waiting for the original point for successive frames. Additionally, if a set of rays are known to go to a light source at the same point, a command may be sent to the receiving node identifying the light source, which the receiving node applies to the set of rays.As another example, if there are N ambient occlusion rays penetrating a single point, a command may be sent to generate N samples from this point.

[0284] Various further techniques may be applied for lossy compression. For example, a quantization factor may be used to quantize all coordinate values ​​related to BVH, primitives, and rays. Additionally, 32-bit floating point values ​​used for data such as BVH nodes and primitives may be converted to 8-bit integer values. In an exemplary implementation, the bounds of a ray packet are stored with full precision, but the individual ray points P1-P3 are transmitted as indexed offsets into the bounds. Similarly, multiple local coordinate systems may be generated that use 8-bit integer values ​​as local coordinates. The location of the start point of each of these local coordinate systems may be encoded using full precision (e.g., 32-bit floating point) values, effectively connecting the global and local coordinate systems.

[0285] Below is an example of lossless compression: Below is an example of a ray data format used internally in a ray tracing program: struct Ray { uint32 pixId; uint32 materialID; uint32 instanceID; uint64 primitiveID; uint32 geometryID; uint32 lightID; float origin[3]; float direction[3]; float t0; float t; float time; float normal[3]; / / used for geometry intersections float u; float v; float wavelength; float phase; / / Interferometry float refractedOffset; / / Schlieren-esque float amplitude; float weight; }; Instead of sending the raw data for each node generated, this data can be compressed by grouping values ​​and creating implicit rays with applicable metadata where possible.

[0286] (Bundling and grouping of ray data) Flags may be used to mask or common data with modifiers. struct RayPacket { uint32 size; uint32 flags; list <ray>rays; } for example, RayPacket.rays=ray_1~ray_256 (All starting points are shared) All ray data is packed except that only a single origin is stored across all rays if RayPacket.flags is set for RAYPACKET_COMMON_ORIGIN. If a RayPacket is unpacked upon receipt, the origin is filled in from the single origin value.

[0287] (The origin is only shared among some rays.) All ray data is packed, except for rays that share an origin. For each unique shared origin in each group, an operator is packed that identifies the operation (the shared origin), remembers the origin, and masks which rays share information. Such operations can be done on any shared values ​​between nodes, such as material IDs, primitive IDs, origins, directions, normals, etc. struct RayOperation { uint8 operationID; void* value; uint64 mask; } (Implicit Ray Transmission) Often, ray data can be derived at the receiving end with minimal meta-information used to generate it. A very common example is generating multiple secondary rays to probabilistically sample an area. Instead of the sender generating secondary rays and sending them out for the receiver to act on, the sender can send a command that a ray needs to be generated along with any dependent information, and the ray is generated at the receiving end. When a ray is initially generated by the sender, and it needs to decide which receiver to send it to, a random seed can be sent to regenerate the exact same ray.

[0288] For example, to sample hit points with 64 shadow rays sampling an area light source, all 64 rays intersect the area from the same calculation N4. A RayPacket is created with a common origin and normal. More data may be sent if we want the receiver to shade the resulting pixel's contribution, but for this example we will assume we only want to return whether the ray hits other node data or not. A RayOperation is created for the generated shadow ray operation and assigned a sampled light ID value and a random seed. When N4 receives the ray packet, it generates fully embedded ray data by embedding the shared origin data into all rays and setting the direction based on the ray ID probabilistically sampled with the random seed to generate the same rays as the original sender generated. When the results are returned, only binary results for all rays need to be returned, which can be handled by a mask on the rays.

[0289] Sending the original 64 rays in this example would have used 104 bytes x 64 rays = 6656 bytes. If the returning rays were sent in raw form as well, this would also double to 13312 bytes. Using lossless compression by only sending the ray generation operations on the common ray origin, normal, seed and id, only 29 bytes are sent along with the 8 bytes returned for the intersected masks. This results in a compression rate of the data that needs to be sent over the network of ~360:1. This does not include the overhead for processing the messages themselves, which need to be identified in some way, but that is implementation dependent. Other operations may be performed to recalculate the ray origin and direction from the pixel id for primary rays, to recalculate the pixel id based on the range in the ray packet, and many other possible implementations for recalculating values. Similar operations can be used for any single ray or group of rays sent, including shadows, reflections, refractions, ambient occlusion, intersections, volume intersections, shadowing, bounced reflections, etc. in path tracing.

[0290] FIG. 37 shows further details of two ray tracing nodes 3710-3711 performing compression and decompression of ray tracing packets. In particular, when the first ray tracing engine 3730 is ready to send data to the second ray tracing engine 3731, the ray compression circuit 3720 performs lossy and / or lossless compression of the ray tracing data as described herein (e.g., converting 32-bit values ​​to 8-bit values, using raw data instead of instructions to reconstruct the data, etc.). The compressed ray packet 3701 is transmitted from the network interface 3725 to the network interface 3726 over a local network (e.g., a 10 Gb / s, 100 Gb / s Ethernet network). The ray decompression circuit then decompresses the ray packet, if necessary. For example, it may execute commands to reconstruct the ray tracing data (e.g., using a random seed to perform random sampling for lighting calculations). The ray tracing engine 3731 then uses the received data to perform ray tracing calculations.

[0291] In the reverse direction, ray compression circuitry 3741 compresses the ray data, network interface 3726 transmits the compressed ray data over the network (e.g., using techniques described herein), ray decompression circuitry 3740 decompresses the ray data as needed, and ray tracing engine 3730 uses the data in ray tracing calculations. Although shown as separate units in Figure 37, ray decompression circuits 3740-3741 may be integrated within ray tracing engines 3730-3731, respectively. For example, to the extent that the compressed ray data includes commands to reconstruct the ray data, these commands may be executed by the respective ray tracing engines 3730-3731.

[0292] 38, the beam compression circuit 3720 may include a lossy compression circuit 3801 for performing the lossy compression techniques described herein (e.g., converting 32-bit floating point coordinates to 8-bit integer coordinates) and a lossless compression circuit 3803 for performing the lossless compression techniques (e.g., sending commands and data to enable the beam recompression circuit 3821 to reconstruct the data). The beam decompression circuit 3721 includes a lossy decompression circuit 3802 and a lossless decompression circuit 3804 for performing lossless decompression.

[0293] Another exemplary method is shown in Figure 39. The method may be implemented on a ray tracing architecture or other architectures described herein, but is not limited to any particular architecture.

[0294] At 3900, ray data is received from a first ray tracing node to be transmitted to a second ray tracing node. At 3901, a lossy compression circuit performs lossy compression on the first ray tracing data, and at 3902, a lossless compression circuit performs lossless compression on the second ray tracing data. At 3903, the compressed ray tracing data is transmitted to the second ray tracing node. At 3904, a lossy / lossless decompression circuit performs lossy / lossless decompression of the ray tracing data, and at 3905, the second ray tracing node performs a ray tracing operation using the decompressed data.

[0295] [Hardware-accelerated hybrid ray tracing graphics processor] Next, a hybrid rendering pipeline is presented that performs rasterization on the graphics core 3130 and ray tracing operations on the ray tracing core 3150, graphics core 3130 and / or CPU 3199 cores. For example, the rasterizer and depth test may be performed on the graphics core 3130 instead of the primary ray casting stage. The ray tracing core 3150 may then generate secondary rays for light reflection, refraction and shadows. Furthermore, certain areas of the scene are selected where the ray tracing core 3150 performs ray tracing operations (e.g., based on material property thresholds such as high reflectance levels), while other areas of the scene are rendered with rasterization on the graphics core 3130. This hybrid implementation may be used for real-time ray tracing applications where latency is a critical issue.

[0296] The ray traversal architecture described below may, for example, use existing single instruction multiple data (SIMD) and / or single instruction multiple thread (SIMT) graphics processors to perform programmable shading and control of ray traversal while accelerating key functions such as BVH traversal and / or intersection using dedicated hardware. SIMD occupancy of the incoherent path may be improved by regrouping shaders generated at specific points during traversal and before shading. This is accomplished using dedicated hardware that dynamically sorts shaders on-chip. Recursion is managed by splitting functions into continuations that execute when returning and regrouping the continuations before execution for improved SIMD occupancy.

[0297] Programmable control of ray traversal / intersection is achieved by decomposing traversal functionality into inner traversals that can be implemented as fixed-function hardware, and outer traversals that run on the GPU processor and allow programmable control through user-defined traversal shaders. The cost of transferring traversal contexts between hardware and software is reduced by conservatively truncating inner traversal state during the transition between inner and outer traversals.

[0298] Programmable control of ray tracing can be expressed through different shader types, listed below in Table A. There can be multiple shaders per type, for example each material can have a different hit shader.

[0299] [Table 1] Recursive ray tracing may begin with an API function that instructs the graphics processor to start a set of primary shaders or intersection circuits that can generate ray-scene intersections for primary rays. This then generates other shaders, such as traversal shaders, hit shaders, or miss shaders. A shader that generates a child shader can also receive return values ​​from the child shader. A callable shader is a generic function that can be directly generated by other shaders and can also return values ​​to the calling shader.

[0300] Figure 40 shows a graphics processing architecture including shader execution circuitry 4000 and fixed function circuitry 4010. The general purpose execution hardware subsystem includes multiple single instruction multiple data (SIMD) and / or single instructions multiple threads (SIMT) cores / execution units (EUs) 4001 (i.e., each core may include multiple execution units), one or more samplers 4002, and a level 1 (L1) cache 4003 or other form of local memory. The fixed function hardware subsystem 4010 includes a message unit 4004, a scheduler 4007, a ray BVH traversal / intersection circuitry 4005, a sorting circuit 4008, and a local L1 cache 4006.

[0301] During operation, the primary dispatcher 4009 dispatches a set of primary rays to the scheduler 4007, which schedules the work to shaders executing on the SIMD / SIMT cores / EUs 4001. The SIMD cores / EUs 4001 may be the ray tracing cores 3150 and / or the graphics cores 3130 described above. The execution of the primary shaders generates further work to be performed (e.g., one or more child shaders and / or further work to be performed by fixed function hardware). The message unit 4004 distributes the work generated by the SIMD cores / EUs 4001 to the scheduler 4007, accessing the free stack pool, the sorting circuit 4008 or the ray-BVH intersection circuit 4005 as needed. If further work is sent to the scheduler 4007, it is scheduled for processing on the SIMD / SIMT cores / EUs 4001. Prior to scheduling, sorting circuitry 4008 may sort rays into groups or bins (e.g., grouping rays with similar characteristics) as described herein. Ray-BVH intersection circuitry 4005 performs intersection testing of rays with BVH volumes. For example, ray-BVH intersection circuitry 4005 may compare ray coordinates to the BVHs at each level to identify volumes that the ray intersects.

[0302] Shaders can be referenced using a shader record, a user-allocated structure that contains a pointer to an entry function, vendor-specific metadata, and global arguments to the shader executed by the SIMD core / EU 4001. Each execution instance of a shader is associated with a call stack that may be used to store arguments passed between parent and child shaders. The call stack may also store references to continuation functions that are executed upon call return.

[0303] Figure 41 shows an example set of allocated stacks 4101, including a primary shader stack, a hit shader stack, a traversal shader stack, a continuation function stack, and a ray-BVH intersection stack, which may be implemented by fixed function hardware 4010, as described. A new shader invocation may implement a new stack from a free stack pool 4102. Call stacks, e.g., stacks consisting of the set of allocated stacks, may be cached in local L1 caches 4003, 4006 to reduce access latency.

[0304] There may be a limited number of call stacks, each with a fixed maximum size "Sstack" allocated in a contiguous region of memory. Therefore, the base address of a stack can be calculated directly from the stack index (stack index, SID) as base address = SID * Sstack. Stack IDs may be allocated and deallocated by the scheduler 4007 when scheduling work to a SIMD core / EU 4001.

[0305] The primary dispatcher 4009 may include a graphics processor command processor that dispatches primary shaders in response to dispatch commands from the host (e.g., CPU). The scheduler 4007 may receive these dispatch requests and, if it can allocate a stack ID per SIMD lane, starts the primary shader on the SIMD processor thread. The stack ID may be allocated from a free stack pool 4102 that is initialized at the start of the dispatch command.

[0306] An executing shader can spawn child shaders by sending a spawn message to message unit 4004. This command contains the stack ID associated with the shader and also contains pointers to the child shader records for each active SIMD lane. A parent shader can only issue this message once per active lane. After sending spawn messages for all relevant lanes, the parent shader may exit.

[0307] Shaders executing on the SIMD core / EU 4001 can also generate fixed function tasks such as ray-BVH intersection using generate messages with shader record pointers reserved for the fixed function hardware. As described above, the message unit 4004 sends generated ray-BVH intersection work to the fixed function ray-BVH intersection circuit 4005 and callable shaders directly to the sort circuit 4008. The sort circuit may group shaders by shader record pointers to derive SIMD batches with similar characteristics. Thus, stack IDs from different parent shaders can be grouped into the same batch by the sort circuit 4008. The sort circuit 4008 sends the grouped batches to the scheduler 4007, which accesses the shader records from the graphics memory 2511 or the last level cache (LLC) 4020 and starts the shaders on the processor threads.

[0308] Continuations may be treated as callable shaders and may be referenced through shader records. When a child shader is generated and returns a value to a parent shader, a pointer to the continuation shader record may be pushed on the call stack 4101. When the child shader returns, the continuation shader record may be popped from the call stack 4101 and a continuation shader may be generated. Optionally, the generated continuation may be passed through a sort unit in the same way as a callable shader and started on a processor thread.

[0309] As shown in FIG. 42, the sorting circuit 4008 groups tasks generated by shader record pointers 4201A, 4201B, 4201n to create SIMD batches for shading. The stack IDs or context IDs in the sorted batches can be grouped from different dispatches and different input SIMD lanes. The grouping circuit 4210 may perform the sorting using a content addressable memory (CAM) structure 4201 that includes multiple entries with each entry identified by a tag 4201. As described above, the tag 4201 may be a corresponding shader record pointer 4201A, 4201B, 4201n. The CAM structure 4201 may store a limited number of tags (e.g., 32, 64, 128, etc.) each associated with an incomplete SIMD batch corresponding to a shader record pointer.

[0310] For an incoming generate command, each SIMD lane has a corresponding stack ID (shown as one of 16 context IDs 0-15 in each CAM entry) and a shader record pointer 4201A-B,...n (which acts as a tag value). The grouping circuit 4210 may compare the shader record pointer of each lane to the tags 4201 in the CAM structure 4201 to find a matching batch. If a matching batch is found, the stack ID / context ID may be added to the batch. If not, a new entry with a new shader record pointer tag may be created, possibly removing an old entry for an incomplete batch.

[0311] A running shader can deallocate its call stack when it is empty by sending a deallocate message to the message unit, which relays the deallocate message to the scheduler, which returns the stack ID / context ID of the active SIMD lane to the free pool.

[0312] A hybrid approach for ray traversal computation using a combination of fixed function ray traversal and software ray traversal is presented. It thus provides the flexibility of software traversal while maintaining the efficiency of fixed function traversal. Figure 43 shows an acceleration structure that can be used for hybrid traversal, which is a two-level tree with a single top-level BVH 4300 and several lower-level BVHs 4301 and 4302. Graph elements to show the inner traversal path 4303, the outer traversal path 4304, the traversal node 4305, the leaf node with a triangle 4306, and the leaf node with a custom primitive 4307 are shown on the right.

[0313] A leaf node 4306 with a triangle in the top level BVH 4300 can reference a triangle, a custom primitive intersection shader record, or a traversal shader record. A leaf node 4306 with a triangle in a lower level BVH 4301-4302 can only reference triangle and custom primitive intersection shader records. The type of reference is encoded in the leaf node 4306. An internal traversal 4303 indicates traversal within each BVH 4300-4302. Internal traversal operations include ray-BVH intersection calculations, while traversal between BVH structures 4300-4302 is known as external traversal. Internal traversal operations can be implemented efficiently in fixed function hardware, while external traversal operations can be performed with acceptable performance by programmable shaders. Thus, internal traversal operations may be performed using fixed function circuitry 4010, and external traversal operations may be performed using shader execution circuitry 4000, which includes a SIMD / SIMT core / EU 4001 for executing programmable shaders.

[0314] It should be noted that the SIMD / SIMT core / EU 4001 may sometimes be referred to herein simply as a "core," "SIMD core," "EU," or "SIMD processor" for brevity. Similarly, the ray-BVH traversal / intersection circuit 4005 may sometimes be referred to simply as a "traversal unit," "traversal / intersection unit," or "traversal / intersection circuit." When alternative terminology is used, the particular name used to designate the respective circuit / logic does not change the underlying function that the circuit / logic performs as described herein.

[0315] Additionally, although shown as a single component in FIG. 40 for purposes of illustration, the traversal / intersection unit 4005 may include a separate traversal unit and a separate intersection unit, each of which may be implemented in circuitry and / or logic as described herein.

[0316] When a ray intersects with a traversal node during an inner traversal, a traversal shader may be generated. The sorting circuit 4008 may group these shaders by shader record pointers 4201A-4201B, n to create a SIMD batch, which is initiated by the scheduler 4007 for SIMD execution on the graphics SIMD core / EU 4001. The traversal shader can modify the traversal in several ways, allowing a wide range of applications. For example, the traversal shader can select a BVH at a coarser level of detail (LOD) or transform the ray to enable rigid body transformation. The traversal shader may then generate an inner traversal for the selected BVH.

[0317] Inner traversals compute ray-BVH intersections by traversing the BVH and computing ray-box and ray-triangle intersections. Inner traversals are generated in the same way as shaders, by sending messages to the messaging circuit 4004, which relays corresponding generation messages to the ray-BVH intersection circuit 4005, which computes the ray-BVH intersections.

[0318] The stack for the inner traversal may be stored locally in the fixed function circuitry 4010 (e.g., in the L1 cache 4006). When the ray intersects with a leaf node corresponding to a traversal or intersection shader, the inner traversal may terminate and the inner stack may be truncated. The truncated stack, along with the ray and a pointer to the BVH, may be written to memory at a location specified by the calling shader, and the corresponding traversal or intersection shader may then be generated. If the ray intersects with any triangle during the inner traversal, the corresponding hit information may be provided as an input argument to these shaders, as shown in the code below. These generated shaders may be grouped by the sorting circuitry 4008 to create a SIMD batch for execution. struct HitInfo { float barycentrics[2]; float tmax; bool innerTravComplete; uint primID; uint geomID; ShaderRecord* leafShaderRecord; } Truncating the internal traversal stack reduces the cost of spilling it to memory. The technique is described in Restart Trail for Stackless BVH Traversal, High Performance Graphics (2010), pp. 107-111, where a 42-bit restart trail and a 6-bit depth value may be applied at the top of the stack to truncate the stack to a small number of entries. The restart trail indicates the branches already taken in the BVH, and the depth value indicates the depth of the traversal corresponding to the last stack entry. This is enough information to restart the internal traversal at a later time.

[0319] The inner traversal is complete when the inner stack is empty and there are no BVH nodes to test. In this case, an outer stack handler is spawned which pops the top of the outer stack and resumes the traversal if the outer stack is not empty.

[0320] The outer traversal may execute a main traversal state machine and may be implemented in program code executed by the shader execution circuitry 4000. Under the following conditions, (1) when a new ray is generated by a hit shader or a primary shader, (2) when a traversal shader selects a BVH for traversal, and (3) when an outer stack handler resumes inner traversal for a BVH, it may generate an inner traversal query.

[0321] As shown in Figure 44, before an inner traversal is generated, space is allocated on the call stack 4405 for the fixed function circuit 4010 to store a truncated inner stack 4410. The call stack and offsets 4403-4404 to the top of the inner stack are maintained in a traversal state 4400 which is also stored in memory 2511. The traversal state 4400 also includes hit information for rays in world space 4401 and object space 4402 and the nearest intersecting primitive.

[0322] The traversal shaders, intersection shaders and external stack handlers are all generated by the ray-BVH intersection circuit 4005. The traversal shaders are allocated on the call stack 4405 before starting a new internal traversal for the second level BVH. The external stack handlers are the shaders responsible for updating the hit information and resuming any pending internal traversal tasks. The external stack handlers are also responsible for generating hit or miss shaders when the traversal is complete. A traversal is complete when there are no pending internal traversal queries to be generated. When the traversal is complete and an intersection is found, a hit shader is generated; otherwise, a miss shader is generated.

[0323] The hybrid traversal scheme described above uses a two-level BVH hierarchy, but any number of BVH levels may also be implemented with corresponding changes in the implementation of the outer traversal.

[0324] Additionally, while a fixed function circuit 4010 for performing ray-BVH intersection is described above, other system components may also be implemented in the fixed function circuit. For example, the outer stack handlers described above may be internal (user invisible) shaders that could potentially be implemented in the fixed function BVH traversal / intersection circuit 4005. This implementation may be used to reduce the number of dispatched shader stages and round trips between the fixed function intersection hardware 4005 and the processor.

[0325] The examples described herein enable programmable shading and ray traversal control using user-defined functions that can run with greater SIMD efficiency on existing and future GPU processors. Programmable control of ray traversal enables several important features such as procedural instancing, probabilistic level-of-detail selection, custom primitive intersections, and lazy BVH updates.

[0326] A programmable multiple instruction multiple data (MIMD) ray tracing architecture that supports speculative execution of hit and intersection shaders is also provided. In particular, the architecture focuses on reducing the scheduling and communication overhead between the programmable SIMD / SIMT core / execution units 4001 and the fixed function MIMD traversal / intersection units 4005 described above with respect to FIG. 40 in a hybrid ray tracing architecture. Described below is a multiple speculative execution scheme for hit and intersection shaders that can be dispatched in a single batch from the traversal hardware avoiding several traversal and shading round trips. Dedicated circuitry may be used to implement these techniques.

[0327] Embodiments of the present invention are particularly beneficial in use cases where execution of multiple hit or intersection shaders from a ray traversal query is desired, which imposes significant overhead when implemented without dedicated hardware support. These include, but are not limited to, nearest k-hit queries (which initiate a hit shader for the nearest k intersections) and multiple programmable intersection shaders.

[0328] The techniques described herein may be implemented as extensions to the architecture shown in Figure 40 (and described with respect to Figures 40-44). In particular, this embodiment of the invention builds on this architecture with extensions to improve performance for the use cases described above.

[0329] A performance limitation of the hybrid ray tracing ray traversal architecture is the overhead of initiating traversal queries from the execution units and invoking programmable shaders from the ray tracing hardware. When multiple hit or intersection shaders are invoked during the traversal of the same ray, this overhead generates "execution roundtrips" between the programmable cores 4001 and the traversal / intersection unit 4005. This also puts additional pressure on the sort unit 4008, which must extract SIMD / SIMT coherence from the individual shader invocations.

[0330] Several aspects of ray tracing require programmable control that can be expressed through different shader types (i.e. primary, hit, any hit, miss, intersection, traversal, callable) listed in Table A above. There can be multiple shaders per type; for example, each material can have a different hit shader. Several of these shader types are defined in the current Microsoft Ray Tracing API.

[0331] As a simple observation, recursive ray tracing starts with an API function that instructs the GPU to start a set of primary shaders that can generate ray-scene intersections (implemented in hardware and / or software) for primary rays. This then generates other shaders, such as traversal shaders, hit shaders, or miss shaders. Shaders that generate child shaders can also receive return values ​​from the child shaders. Callable shaders are generic functions that can be directly generated by other shaders and can also return values ​​to the calling shader.

[0332] Ray traversal computes ray-scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH). Recent research has shown that the efficiency of ray-scene intersection computation can be improved by an order of magnitude or more by using techniques that are more suitable for fixed-function hardware, such as reduced precision arithmetic, BVH compression, per-ray state machines, dedicated intersection pipelines, and custom caches.

[0333] The architecture shown in Figure 40 includes a system in which an array of SIMD / SIMT cores / execution units 4001 interact with a fixed function ray tracing / intersection unit 4005 to perform programmable ray tracing. Programmable shaders are mapped to SIMD / SIMT threads on the execution units / cores 4001, and SIMD / SIMT utilization, execution, and data coherence are important for optimal performance. Ray queries often destroy coherence for a variety of reasons, including: · Traversal divergence: BVH traversal durations vary significantly between rays, favoring asynchronous ray processing. · Execution divergence: Rays generated from different lanes of the same SIMD / SIMT thread may result in different shader invocations. Data access differences: For example, rays hitting different faces sample different BVH nodes, primitives and shaders access different textures, and various other scenarios can cause data access differences.

[0334] The SIMD / SIMT core / execution unit 4001 may be a variation of the core / execution units described herein, including the graphics cores 415A-415B, the shader cores 1355A-N, the graphics core 3130, the graphics execution unit 608, the execution units 852A-852B, or any other core / execution unit described herein. The SIMD / SIMT core / execution unit 4001 may be used in place of the graphics cores 415A-415B, the shader cores 1355A-1355N, the graphics core 3130, the graphics execution unit 608, the execution units 852A-852B, or any other core / execution unit described herein. Thus, disclosure of any feature in combination with graphics cores 415A-415B, shader cores 1355A-1355N, graphics core 3130, graphics execution unit 608, execution units 852A-852B, or any other core / execution unit described herein also discloses a corresponding combination with SIMD / SIMT core / execution unit 4001 of FIG. 40, but is not limited to such.

[0335] The fixed-function ray tracing / intersection unit 4005 may overcome the first two challenges by processing each ray individually and out of order. However, this splits the SIMD / SIMT groups. The sort unit 4008 is therefore responsible for forming new coherent SIMD / SIMT groups of shader invocations that are again dispatched to the execution units.

[0336] It is easy to realize the advantages of such an architecture compared to a purely software-based ray tracing implementation directly on a SIMD / SIMT processor. However, there is overhead associated with message transmission between the SIMD / SIMT core / execution unit 4001 (here sometimes simply referred to as a SIMD / SIMT processor or core / EU) and the MIMD traversal / intersection unit 4005. Furthermore, the sort unit 4008 may not extract full SIMD / SIMT utilization from non-coherent shader invocations.

[0337] Use cases can be identified where shader invocations may be particularly frequent during traversal. Extensions are described for hybrid MIMD ray tracing processors to significantly reduce communication overhead between the cores / EUs 4001 and the traversal / intersection unit 4005. This can be particularly advantageous when finding the k-closest intersections and programmable intersection shader implementations. However, it should be noted that the techniques described herein are not limited to any particular processing scenario.

[0338] A summary of the high level cost of ray tracing context switching between the Core / EU 4001 and the Fixed Function Traversal / Intersection Unit 4005 is provided below. Most of the performance overhead is caused by these two context switches every time a shader invocation is required during a single ray traversal.

[0339] Each SIMD / SIMT lane that initiates a ray generates a generate message to the traversal / intersection unit 4005 associated with the BVH to be traversed. The data (ray traversal context) is relayed to the traversal / intersection unit 4005 via the generate message and (cached) memory. When the traversal / intersection unit 4005 is ready to assign a new hardware thread to the generate message, it loads the traversal state and performs the traversal on the BVH. There is also some setup cost that needs to be performed before the first traversal step of the BVH.

[0340] Figure 45 shows the operational flow of the programmable ray tracing pipeline. The shaded elements, including traversal 4502 and intersection 4503, may be implemented in fixed function circuitry, while the remaining elements may be implemented in programmable cores / execution units.

[0341] The primary ray shader 4501 sends work to a traversal circuit that traverses the current ray through the BVH (or other acceleration structure) in 4502. When a leaf node is reached, the traversal circuit calls the intersection circuit in 4503, which, if it identifies a ray-triangle intersection, calls the any-hit shader in 4504 (which may return a result to the traversal circuit as shown).

[0342] Alternatively, the traversal may terminate before reaching a leaf node and either the closest hit shader is called at 407 (if a hit is recorded) or the miss shader is called at 4506 (if a miss).

[0343] An intersection shader may be invoked when the traversal circuit reaches a custom primitive leaf node, as shown at 4505. The custom primitive may be any non-triangular primitive such as a polygon or polyhedron (e.g., a tetrahedron, voxel, hexahedron, wedge, pyramid or other "unstructured" volume). The intersection shader 4505 identifies any intersection between the ray and the custom primitive to an any-hit shader 4504 that implements any-hit processing.

[0344] When the hardware traversal 4502 reaches a programmable stage, the traversal / intersection unit 4005 may generate a shader dispatch message to the associated shader 4505-4507, corresponding to a single SIMD lane of the execution unit used to execute the shader. Because dispatches can occur on rays of any order and diverge in the programs being invoked, a sort unit 4008 may accumulate multiple dispatch calls to extract a coherent SIMD batch. The updated traversal state and optional shader arguments may be written to memory 2511 by the traversal / intersection unit 4005.

[0345] In the k-nearest intersection problem, the closest hit shader 4507 is run for the first k intersections. In traditional methods, this means terminating the ray traversal when it finds the closest intersection, calling the hit shader, and generating a new ray from the hit shader to find the next closest intersection (the offset of the ray's start point ensures that the same intersection does not occur again). It is easy to realize that this implementation requires the generation of k rays for a single ray. Other implementations work with an any hit shader 4504, which is called for every intersection and maintains a global list of closest intersections, using an insertion sort operation. The main problem with this approach is that there is no upper bound on the any hit shader invocations.

[0346] As mentioned above, intersection shader 4505 may be invoked for non-triangle (custom) primitives. Depending on the outcome of the intersection test and the traversal state (pending node and primitive intersections), traversal of the same ray may continue even after execution of intersection shader 4505. Thus, finding the closest hit may require several round trips to the execution unit.

[0347] We can also focus on reducing SIMD-MIMD context switches for intersection shaders 4505 and hit shaders 4504, 4507 through modifications to the traversal hardware and shader scheduling model. First, the ray traversal circuitry 4005 delays shader invocations by accumulating multiple potential invocations and dispatching them in larger batches. Additionally, certain invocations that are found to be unnecessary may be removed at this stage. Additionally, the shader scheduler 4007 may aggregate multiple shader invocations from the same traversal context into a single SIMD batch, which results in a single ray generation message. In one exemplary implementation, the traversal hardware 4005 suspends the traversal thread and waits for the results of multiple shader invocations. This mode of operation is referred to herein as "speculative" shader execution, as it allows for the dispatch of multiple shaders, some of which may not be invoked when using sequential invocations.

[0348] FIG. 46A shows an example where a traversal operation encounters multiple custom primitives 4650 in a subtree, and FIG. 46B shows how this can be resolved in three intersection dispatch cycles C1-C3. In particular, the scheduler 4007 may require three cycles to submit work to the SIMD processor 4001, and the traversal circuitry 4005 requires three cycles to provide the results to the sort unit 4008. The traversal state 4601 required by the traversal circuitry 4005 may be stored in a memory such as a local cache (e.g., an L1 cache and / or an L2 cache).

[0349] A. Deferred ray tracing shader invocation The manner in which the hardware traversal state 4601 is managed to allow for the accumulation of multiple potential intersections or hit invocations in the list can also be modified. At a given time during the traversal, each entry in the list may be used to generate a shader invocation. For example, the k nearest intersections can be accumulated in the traversal hardware 4005 and / or in the traversal state 4601 in memory, and a hit shader can be invoked for each element when the traversal is complete. For a hit shader, multiple potential intersections may be accumulated for a subtree in the BVH.

[0350] For the k-nearest neighbor use case, the advantage of this approach is that all hit shaders are called from the same traversal thread during a single traversal operation on traversal circuitry 4005, instead of k-1 round trips to SIMD core / EU 4001 and k-1 new ray generation messages. A potential implementation challenge is that it is not trivial to guarantee the order of execution of hit shaders (the standard "round trip" approach guarantees that the hit shader of the closest intersection is executed first, etc.). This may be addressed by either synchronization or relaxing the ordering of hit shaders.

[0351] For intersection shader use cases, the traversal circuitry 4005 does not know in advance whether a given shader will return a positive intersection test. However, multiple intersection shaders can be speculatively executed, and if at least one returns a positive hit result, it is merged into a global closest hit. A particular implementation needs to find the optimal number of delayed intersection tests to reduce the number of dispatch calls, but avoid invoking too many redundant intersection shaders.

[0352] B. Aggregation of shader invocations from the traversal circuit When dispatching multiple shaders from the same ray generated by the traversal circuitry 4005, branches in the flow of the ray traversal algorithm can be created. This can be problematic for intersection shaders, because the rest of the BVH traversal depends on the results of all dispatched intersection tests. This means that synchronous operations are required to wait for the results of the shader invocations, which can be a challenge with asynchronous hardware.

[0353] The two points for merging the results of shader invocations are the SIMD processor 4001 and the traversal circuitry 4005. With the SIMD processor 4001, multiple shaders can synchronize and aggregate their results using standard programming models. One relatively simple way to do this is to use global atomics and aggregate the results in a shared data structure in memory where the intersection results of multiple shaders can be stored. The last shader can then resolve the data structure and call back to the traversal circuitry 4005 to continue the traversal.

[0354] A more efficient approach may also be implemented that restricts execution of multiple shader invocations to lanes of the same SIMD thread on the SIMD processor 4001. The intersection tests are then reduced locally using SIMD / SIMT reduce operations (without relying on global atomics). This implementation may rely on new circuitry in the sort unit 4008 to keep small batches of shader invocations in the same SIMD batch.

[0355] Execution of the traversal thread may further be paused on the traversal circuitry 4005. Using a traditional execution model, when a shader is dispatched during traversal, the shader thread is terminated and the ray traversal state is saved to memory to allow execution of other ray generation commands while the execution unit 4001 processes the shader. If the traversal thread is simply paused, the traversal state does not need to be stored and the result of each shader can be awaited separately. This implementation may include circuitry to avoid deadlocks and provide sufficient hardware utilization.

[0356] 47-48 show an example of a delay model for invoking a single shader invocation on a SIMD core / execution unit 4001 with three shaders 4701. When reserved, all intersection tests are evaluated within the same SIMD / SIMT group. Therefore, the closest intersection can also be calculated on the programmable core / execution unit 4001.

[0357] As described above, all or part of the shader aggregation and / or deferral may be performed by the traversal / intersection circuitry 4005 and / or the core / EU scheduler 4007. Figure 47 shows how a shader delay / aggregation circuitry 4706 in the scheduler 4007 delays the scheduling of shaders associated with a particular SIMD / SIMT thread / lane until a specified trigger event occurs. Upon detecting the trigger event, the scheduler 4007 dispatches the multiple aggregated shaders in a single SIMD / SIMT batch to the core / EU 4001.

[0358] 48 shows how a shader delay / aggregation circuit 4805 in the traversal / intersection circuit 4005 can delay the scheduling of shaders associated with a particular SIMD thread / lane until a specified trigger event occurs. Upon detecting the trigger event, the traversal / intersection circuit 4005 presents the shaders aggregated in a single SIMD / SIMT batch to a sort unit 4008.

[0359] It should be noted, however, that the shader deferral and aggregation techniques may be implemented in various other components, such as sort unit 4008, or may be distributed among multiple components. For example, traversal / intersection circuit 4005 may perform a first set of shader-intensive operations, and scheduler 4007 may perform a second set of shader-intensive operations to ensure that shaders of SIMD threads are efficiently scheduled on cores / EUs 4001.

[0360] The "triggering event" that causes the aggregated shaders to be dispatched to a core / EU may be a processing event, such as a particular number of accumulated shaders or a minimum latency associated with a particular thread. Alternatively or additionally, the triggering event may be a time event, such as a particular duration from the delay of a first shader or a particular number of processor cycles. Other variables, such as the current workload on the core / EU 4001 and traversal / intersection unit 4005, may also be evaluated by the scheduler 4007 to determine when to dispatch a SIMD / SIMT batch of shaders.

[0361] Different embodiments of the invention may be implemented using different combinations of the above techniques, depending on the requirements of the particular system architecture and application being used.

[0362] [Raytracing instructions] The ray tracing instructions described below are included in the instruction set architecture (ISA) that supports the CPU 3199 and / or GPU 3105. When executed by the CPU, single instruction multiple data (SIMD) instructions may utilize vector / packed source and destination registers to perform the described operations and may be decoded and executed by the CPU core. When executed by the GPU 3105, the instructions may be executed by the graphics core 3130. For example, any of the execution units (EUs) 4001 described above may execute the instructions. Alternatively or additionally, the instructions may be executed by execution circuitry on the ray tracing core 3150 and / or tensor core 3140.

[0363] Figure 49 illustrates an architecture for executing the ray tracing instructions described below. The illustrated architecture may be integrated into one or more of the cores 3130, 3140, 3150 described above (see, e.g., Figure 31 and associated text), or may be included in a different processor architecture.

[0364] During operation, the instruction fetch unit 4903 fetches ray tracing instructions 4900 from the memory 3198 and the decoder 4995 decodes the instructions. In one implementation, the decoder 4995 decodes the instructions to generate executable operations (e.g., uops or micro-ops in a micro-coding core). Alternatively, some or all of the ray tracing instructions 4900 may be executed without decoding, and thus such a decoder 4904 is not required.

[0365] In either implementation, the scheduler / dispatcher 4905 schedules and dispatches instructions (or operations) among the functional units (FUs) 4910-4912. The illustrated implementation includes a vector FU 4910 for executing single instruction multiple data (SIMD) instructions that operate simultaneously on multiple packed data elements stored in vector registers 4915, and a scalar FU 4911 for operating on scalar values ​​stored in one or more scalar registers 4916. An optional ray tracing FU 4912 may operate based on packed data values ​​stored in the vector registers 4915 and / or scalar values ​​stored in the scalar registers 4916. In an implementation without a dedicated FU 4912, the vector FU 4910 and possibly the scalar FU 4911 may execute ray tracing instructions, described below.

[0366] The various FUs 4910-4912 access ray tracing data 4902 (e.g., traversal / intersection data) required to execute the ray tracing instructions 4900 from vector registers 4915, scalar registers 4916, and / or a local cache subsystem 4908 (e.g., an L1 cache). The FUs 4910-4912 may also perform accesses to memory 3198 via load and store operations, and the cache subsystem 4908 may operate independently to cache data locally.

[0367] Ray tracing instructions may be used to increase performance for ray traversal / intersection and BVH construction, but they may also be applicable to other areas such as high performance computing (HPC) and general purpose GPU (GPGPU) implementations.

[0368] In the following description, doubleword is sometimes abbreviated as dw and unsigned byte is abbreviated as ub. Additionally, the source and destination registers (e.g., src0, src1, dest, etc.) shown below may refer to vector registers 4915 or, in some cases, a combination of vector registers 4915 and scalar registers 4916. Typically, vector registers 4915 are used when a source or destination value used by an instruction includes packed data elements (e.g., when the source or destination stores N data elements). Other values ​​may use scalar registers 4916 or vector registers 4915.

[0369] (inverse quantization) An example of a Dequantize instruction "dequantizes" a previously quantized value. As an example, in a ray tracing implementation, a particular BVH subtree may be quantized to reduce storage and bandwidth requirements. The Dequantize instruction may be of the form Dequantize dest src0 src1 src2, where source register src0 stores N unsigned bytes, source register src1 stores one unsigned byte, source register src2 stores one floating point value, and destination register dest stores N floating point values. All of these registers may be vector registers 4915. Alternatively, src0 and dest may be vector registers 4915 and src1 and src2 may be scalar registers 4916.

[0370] The following code sequence defines a specific implementation of the inverse quantization instruction. for (int i=0; i <SIMD_WIDTH) { if (execMask[i]) { dst[i]=src2[i]+ldexp(convert_to_float(src0[i]),src1); } } In this example, ldexp multiplies a double-precision floating-point value by the specified integer power of 2 (i.e., ldexp(x,exp)=x*2 exp In the above code, if the execution mask value associated with the current SIMD data element (execMask[i]) is set to 1, the SIMD data element at position i in src0 is converted to a floating-point value and raised to the integer power (2 src1 The corresponding SIMD data element in src2 is multiplied by the corresponding SIMD data element (value) and this value is added to the corresponding SIMD data element in src2. (select min or max) A selective min or max instruction may perform either a min or max operation per lane (i.e., return the minimum or maximum of a set of values) as indicated by the bits of a bitmask. The bitmask may utilize a separate set of vector registers 4915, scalar registers 4916, or mask registers (not shown). The following code sequence: sel_min_max dest src0 src1 src2 defines one particular implementation of a min / max instruction, where src0 stores N doublewords, src1 stores N doublewords, src2 stores one doubleword, and the destination register stores N doublewords.

[0371] The following code sequence defines one particular implementation of the selective min / max command: for (int i=0;i <SIMD_WIDTH) { if (execMask[i]) { dst[i]=(1< <i)&src2 ? min(src0[i],src1[i]) : max(src0[i],src1[i]); } } In this example, the value of (1<<i)&src2 (1 left-shifted by i and ANDed with src2) is used to select the minimum or maximum of the i-th data elements of src0 and src1. The operation is performed on the i-th data element only if the execution mask value (execMask[i]) associated with the current SIMD data element is set to 1.

[0372] (Shuffle index instruction) The shuffle index instruction can copy any set of input lanes to the output lanes. For a SIMD width of 32, this instruction can be executed with a lower throughput. This instruction has the form shuffle_index dest src0 src1 <optional flag>, where src0 stores N doublewords, src1 stores N unsigned bytes (i.e., index values), and dest stores N doublewords.

[0373] The following code sequence defines one particular implementation of the shuffle index instruction. for (int i = 0; i < SIMD_WIDTH) { uint8_t srcLane = src1.index[i]; if (execMask[i]) { bool invalidLane = srcLane < 0 || srcLane >= SIMD_WIDTH ||!execMask[srcLaneMod]; if (FLAG) { invalidLane |= flag[srcLaneMod]; } if (invalidLane) { dst[i] = src0[i]; } else { dst[i] = src0[srcLane]; } } } In the code above, the index of src1 identifies the current lane. If the i-th value in the execution mask is set to 1, a check is performed to ensure that the source lane is within the range of 0 to the SIMD width. If so, a flag is set (srcLaneMod) and data element i of the destination is set equal to data element i of src0. If the lane is within range (i.e. valid), the index value of src1 (srcLane0) is used as an index into src0 (dst[i] = src0[srcLane]).

[0374] (Immediate Shuffle Up / Dn / XOR Instructions) The immediate shuffle instruction may shuffle the input data elements / lanes based on an immediate value of the instruction. The immediate value may specify to shift the input lanes by 1, 2, 4, 8 or 16 positions based on the value of the immediate value. Optionally, an additional scalar input register may be specified as a fill value. When the source lane index is invalid, the fill value (if provided) is stored in the destination data element location. If a fill value is not provided, the data element location is set to all zeros.

[0375] The flags register may be used as a source mask: if the flag bit for a source lane is set to 1, the source lane is marked as invalid and the instruction may proceed.

[0376] Below are examples of different implementations of the immediate shuffle instruction. shuffle_ <up dn xor>_<1 / 2 / 4 / 8 / 16> dest src0 <optional src1> <optional flag> shuffle_ <up dn xor>_<1 / 2 / 4 / 8 / 16> dest src0<optional src1><optional flag> In this implementation, src0 stores N doublewords, src1 stores one doubleword for the fill value (if there is one), and dest stores N doublewords containing the result.

[0377] The following code sequence defines one particular implementation of the immediate shuffle instruction: for (int i=0;i <SIMD_WIDTH) { int8_t srcLane; switch(SHUFFLE_TYPE) { case UP: srcLane=i-SHIFT; case DN: srcLane=i+SHIFT; case XOR: srcLane = i^SHIFT; } if (execMask[i]) { bool invalidLane=srcLane<0||srcLane>=SIMD_WIDTH||!execMask[srcLane]; if (FLAG) { invalidLane |=flag[srcLane]; } if (invalidLane) { if (SRC1) dst[i] = src1; else dst[i]=0; } else { dst[i] = src0[srcLane]; } } } Here, the input data element / lane is shifted by 1, 2, 4, 8 or 16 positions based on the value of the immediate. Register src1 is an additional scalar source register and is used as a fill value that is stored into the destination data element location when the source lane index is invalid. If no fill value is provided and the source lane index is invalid, the destination data element location is set to 0. The flag register (FLAG) is used as a source mask. If the flag bit for a source lane is set to 1, the source lane is marked as invalid and the instruction proceeds as above.

[0378] (Indirect shuffle Up / Dn / XOR instructions) An indirect shuffle instruction has a source operand (src1) that controls the mapping from the source lane to the destination lane. An indirect shuffle instruction may be of the form: shuffle_ <up dn xor>dest src0 src1<optional flag> src0 stores N doublewords, src1 stores 1 doubleword, and dest stores N doublewords.

[0379] The following code sequence defines one particular implementation of the immediate shuffle instruction: for (int i=0;i <SIMD_WIDTH) { int8_t srcLane; switch(SHUFFLE_TYPE) { case UP: srcLane=i-src1; case DN: srcLane=i+src1; case XOR: srcLane = i^src1; } if (execMask[i]) { bool invalidLane=srcLane<0||srcLane>=SIMD_WIDTH||!execMask[srcLane]; if (FLAG) { invalidLane |=flag[srcLane]; } if (invalidLane) { dst[i]=0; } else { dst[i] = src0[srcLane]; } } } The indirect shuffle instruction therefore operates in a similar manner to the immediate shuffle instruction described above, except that the mapping of source lanes to destination lanes is controlled by the source register src1 rather than an immediate value.

[0380] (Crosslane min / max command) Cross lane min / max instructions may be supported for floating point and integer data types. A cross lane min instruction may be of the form lane_min dest src0, and a cross lane max instruction may be of the form lane_max dest src0, where src0 stores N double words and dest stores 1 double word.

[0381] As an example, the following code sequence defines one specific implementation of the crosslane minimum: dst = src[0]; for (int i=1;i <SIMD_WIDTH) { if (execMask[i]) { dst = min(dst,src[i]); } } In this example, the doubleword value in data element position i of the source register is compared to the data element in the destination register and the minimum of the two values ​​is copied to the destination register. The cross lane maximum instruction operates in essentially the same manner, the only difference being that the maximum of the data element in position i and the destination value is selected.

[0382] (Crosslane min / max index command) A cross lane minimum index instruction may be of the form lane_min_index dest src0, and a cross lane maximum index instruction may be of the form lane_max_index dest src0, where src0 stores N doublewords and dest stores 1 doubleword.

[0383] As an example, the following code sequence defines one particular implementation of a cross lane minimum index instruction: dst_index=0; tmp=src[0] for (int i=1;i <SIMD_WIDTH) { if (src[i] <tmp&&execMask[i]) { tmp = src[i]; dst_index=i; } } In this example, the destination index spans the destination register and increments from 0 to the SIMD width. If the execution mask bit is set, the data element at location i of the source register is copied to a temporary storage location (tmp) and the destination index is set to data element location i.

[0384] (Crosslane Sorting Network Order) A cross lane sorting network instruction may sort all N input elements using an N-wide (stable) sorting network in either ascending (sortnet_min) or descending (sortnet_max) order. The min / max versions of the instruction may be of the form sortnet_min dest src0 and sortnet_max dest src0, respectively. In one implementation, src0 and dest store N double words. A min / max sort is performed on the N double words in src0, and the ascending elements (for min) or descending elements (for max) are stored in dest in the respective sorted order. An example of a code sequence defining an instruction is dst=apply_N_wide_sorting_network_min / max(src0).

[0385] (Cross Lane Sorting Network Index Instruction) The cross lane sorting network index instruction may sort all N input elements using an N-wide (stable) sorting network, but returns a permutation index in either ascending (sortnet_min) or descending (sortnet_max) order. The min / max versions of the instruction may be of the form sortnet_min_index dest src0 and sortnet_max_index dest src0, where src0 and dest store N double words, respectively. An example code sequence defining the instruction is dst=apply_N_wide_sorting_network_min / max_index(src0).

[0386] A method for executing any of the above instructions is shown in Figure 50. The method may be implemented in the specific processor architectures listed above, but is not limited to any particular processor or system architecture.

[0387] At 5001, instructions of a primary graphics thread are executed on a processor core, which may include, for example, any of the cores described above (e.g., graphics core 3130). Upon reaching ray tracing work within the primary graphics thread, as determined at 5002, the ray tracing instructions are offloaded to a ray tracing execution circuit, which may be in the form of a functional unit (FU) as described above with respect to FIG. 49, or may be a dedicated ray tracing core 3150 as described with respect to FIG. 31.

[0388] In 5003, the ray tracing instructions are decoded and fetched from memory, and in 5005, the instructions are decoded into executable operations (e.g., in embodiments requiring a decoder). In 5004, the ray tracing instructions are scheduled and dispatched for execution by the ray tracing circuitry. In 5005, the ray tracing instructions are executed by the ray tracing circuitry. For example, the instructions may be dispatched and executed on the above FUs (e.g., vector FU 4910, ray tracing FU 4912, etc.) and / or the graphics core 3130 or ray tracing core 3150.

[0389] Upon completion of execution of the ray tracing instructions, the results are stored (e.g., stored in memory 3198) at 5006 and the primary graphics thread is notified at 5007. At 5008, the ray tracing results are processed (e.g., read from memory and integrated into the graphics rendering results) within the context of the primary thread.

[0390] In embodiments, the terms "engine" or "module" or "logic" may refer to, be a part of, or include an application specific integrated circuit (ASIC), electronic circuitry, processor (shared, dedicated or group) and / or memory (shared, dedicated or group) executing one or more software or firmware programs, combinatorial logic circuits, and / or other suitable components that provide the functionality described above. In embodiments, the engine, module or logic may be implemented in firmware, hardware, software, or any combination of firmware, hardware and software.

[0391] [Bounding volume and ray-box intersection testing] FIG. 51 is a diagram of a bounding volume 5102 according to an embodiment. The bounding volume 5102 shown is axis aligned to the three-dimensional axes 5100. However, the embodiment is applicable to different bounding representations (e.g., oriented bounding box, discrete oriented polytope, sphere, etc.) and any number of dimensions. The bounding volume 5102 defines the minimum and maximum extent of the three-dimensional object 5104 along each dimension of the axes 5100. To generate the BVH for a scene, a bounding box is constructed for each object in the set of objects in the scene. A set of parent bounding boxes can then be constructed around the group of bounding boxes constructed for each object.

[0392] Figures 52A-B show a representation of a bounding volume hierarchy for two-dimensional objects. Figure 52A shows a set 5200 of bounding volumes around a set of geometric objects. Figure 52B shows an ordered tree 5202 of the bounding volumes 5200 of Figure 52A.

[0393] As shown in Figure 52A, the set of bounding volumes 5200 includes a root bounding volume N1, which is the parent bounding volume of all other bounding volumes N2 to N7. Bounding volumes N2 and N3 are internal bounding volumes between the root volume N1 and leaf volumes N4 to N7. The leaf volumes N4 to N7 contain the geometric objects O1 to O8 of the scene.

[0394] 52B illustrates an ordered tree 5202 of bounding volumes N1-N7 and geometric objects O1-O8. The illustrated ordered tree 5202 is a binary tree where each node in the tree has two child nodes. A data structure configured to contain information for each node may include bounding information for the node's bounding volume (e.g., a bounding box) and at least a reference to each of the node's child nodes.

[0395] The ordered tree 5202 representation of bounding volumes defines a hierarchy that can be used to perform various operations in hierarchical versions, including, but not limited to, collision detection and ray-box intersection. In the example of ray-box intersection, nodes can be tested in a hierarchical fashion, starting with a root node N1 that is the parent node to all other bounding volume nodes in the hierarchy. If the ray-box intersection test for the root node N1 fails, all other nodes in the tree may be bypassed. If the ray-box intersection test for the root node N1 passes, subtrees of the tree can be tested and traversed or bypassed in an ordered fashion until at least a set of intersecting leaf nodes N4-N7 has been determined. The exact tests and traversal algorithms used can vary according to the embodiment.

[0396] FIG. 53 is an illustration of a ray-box intersection test according to an embodiment. During a ray-box intersection test, a ray 5302 is cast and an equation defining the ray can be used to determine whether the ray intersects with a face defining the bounding box 5300 under test. The ray 5302 can be expressed as O+D·t, where O corresponds to the viewpoint of the ray, D is the direction of the ray, and t is a real value. A change in t can be used to define any point along the ray. The ray 5302 is said to intersect with the bounding box 5300 when the maximum entrance face intersection distance is less than or equal to the minimum exit face distance. For the ray 5302 in FIG. 53, the y-face entrance intersection distance is t min-y 5304. The y-plane exit crossing distance is t max-y 5308. The x-plane incidence intersection distance is t min-x 5306, and the x-plane exit intersection distance is tt max-x 5310. Thus, a given ray 5302 has a time t min-x 5306 is t max-y Since the ray-box intersection test is less than 5308, it can be numerically shown to intersect with the bounding box at least along the x and y planes. To perform the ray-box intersection test using the graphics processor, the graphics processor is configured to store an acceleration data structure that defines at least each bounding box to be tested. For acceleration using a bounding volume hierarchy, references to at least child nodes to the bounding boxes are stored.

[0397] [Compress bounding volume nodes] For axis-aligned bounding boxes in 3D space, the acceleration data structures can store the lower and upper bounds of the bounding box in the third dimension. A software implementation can use 32-bit floating point numbers to store these bounds, which totals 2×3×4=24 bytes per bounding box. For an N-wide BVH node, N boxes and N child references must be stored. In total, the storage for a 4-wide BVH node, assuming 4 bytes per reference, is N*24 bytes + N*4 bytes for the child references, which totals (24+4)*N bytes, for a total of 112 bytes for a 4-wide BVH node and 224 bytes for an 8-wide BVH node.

[0398] In one embodiment, the size of the BVH node is reduced by storing a single more accurate parent bounding box that encloses all child bounding boxes, and storing each child bounding box at a lower accuracy relative to that parent box. Depending on the usage scenario, a different number of representations may be used to store the high accuracy parent bounding boxes and the low accuracy relative child bounds. 54 is a block diagram illustrating an exemplary quantized BVH node 5410, according to an embodiment. The quantized BVH node 5410 may include higher precision values ​​to define the parent bounding box of the BVH node. For example, parent_lower_x 5412, parent_lower_y 5414, parent_lower_z 5416, parent_upper_x 5422, parent_upper_y 5424, and parent_upper_z 5426 may be stored using single or double precision floating point values. The child bounding box values ​​for each child bounding box stored in the node may be quantized and stored as lower precision values, such as a fixed point representation for the bounding box values ​​defined for the parent bounding box. For example, child_lower_x 5432, child_lower_y 5434, and child_lower_z 5436 and child_upper_x 5442, child_upper_y 5444, and child_upper_z 5446 may be stored as lower precision fixed point values. Additionally, a child reference 5452 may be stored for each child. Child reference 5452 may be an index into a table that stores the location of each child node, or may be a pointer to the child node.

[0399] Single or double precision floating point values ​​may be used to store the parent bounding box, and M-bit fixed point values ​​may be used to encode the relative child bounding boxes, as shown in Figure 54. The data structure for the quantized BVH node 5410 in Figure 54 can be defined by the quantized N-wide BVH node shown in Table 1 below.

[0400] [Table 2] The quantized nodes in Table 1 achieve reduced data structure size by quantizing child values ​​while maintaining a baseline level of precision by storing higher precision values ​​within the parent bounding box. In Table 1, Real indicates a higher precision numeric representation (e.g., 32-bit or 64-bit floating point values), UintM indicates a lower precision unsigned integer with M bits of precision used to represent fixed point numbers, and Reference indicates the type used to represent a reference to a child node (e.g., a 4-byte index of an 8-byte pointer).

[0401] A typical instantiation of this technique might use 32-bit child references, single precision floating point values ​​for the parent bounds, and M=8 bits (1 byte) for the relative child bounds. This compressed node requires 6*4+6*N+4*N bytes. With a 4-wide BVH, this amounts to 64 bytes in total (versus 112 bytes in the uncompressed version), and with an 8-byte BVH, this amounts to 104 bytes in total (versus 224 bytes in the uncompressed version).

[0402] To traverse such a compressed BVH node, the graphics processing logic can stretch the relative child bounding boxes and then intersect the stretched node using standard techniques. The uncompressed lower bounds can then be obtained for each dimension x, y, and z. Equation 1 below shows the formula for obtaining the child's lower_x value.

[0403]

number

[0404] [Table 3] Table 2 shows the calculation of a floating point value for the lower bound of a child bounding box, based on floating point values ​​for the extent of the parent bounding box and a fixed point value of the child bounding box stored as an offset from the extent of the parent bounding box. The upper bound of the child may be calculated in a similar manner.

[0405] In one embodiment, stretch performance is improved by using the size of the scaled parent bounding box, e.g. (parent_upper_x-parent_lower_x) / (2 M-1 ) In such an embodiment, the extents of the child bounding boxes may be calculated according to the exemplary logic shown in Table 3.

[0406] [Table 4] It should be noted that in an optimized version, the stretch / dequantization can be formulated as a MAD (multiply-and-add) instruction if hardware support for such instructions exists. In one embodiment, the operations for each child node can be performed using SIMD / vector logic, allowing for simultaneous evaluation of each child within a node.

[0407] While the above approach works well for shader or CPU-based implementations, one embodiment provides specialized hardware configured to perform ray tracing operations, including ray-box intersection tests, using bounding volume hierarchies. In such an embodiment, the specialized hardware can be configured to store additional quantized representations of the BVH node data and automatically dequantize such data when performing ray-box intersection tests.

[0408] FIG. 55 is a block diagram of a composite floating point data block 5500 for use by a quantized BVH node 5510 according to a further embodiment. In one embodiment, logic to support composite floating point data block 5500 may be defined by special logic within the graphics processor, as opposed to a 32-bit single precision floating point or 64-bit double precision floating point representation of the parent bounding box extent. The composite floating point (CFP) data block 5500 may include a one-bit signed bit 5502, a variable size (E-bit) signed integer exponent 5504, and a variable size (K-bit) mantissa 5506. Multiple values ​​for E and K may be configurable by adjusting values ​​stored in configuration registers of the graphics processor. In one embodiment, the values ​​of E and K may be independently configured within a range of values. In one embodiment, a fixed set of interrelated values ​​for E and K may be selected via a configuration register. In one embodiment, a single value for each of E and K is hard-coded into the graphics processor's BVH logic. The values ​​E and K allow the CFP data block 5500 to be used as a customized (e.g., special-purpose) floating-point data type that can be tailored to a data set.

[0409] Using the CFP data block 5500, a graphics processor can be configured to store the bounding box data in quantized BVH nodes 5510. In one embodiment, the lower bounds of the parent bounding boxes (parent_lower_x 5512, parent_lower_y 5514, parent_lower_z 5516) are stored at a level of precision determined by the E and K values ​​selected for the CFP data block 5500. The level of precision of the stored values ​​for the lower bounds of the parent bounding boxes is typically set to a higher precision than the values ​​of the child bounding boxes (child_lower_x 5524, child_upper_x 5526, child_lower_y 5534, child_upper_y 5536, child_lower_z 5544, and child_upper_z 5546), which are stored as fixed point values. Scaled parent bounding box sizes are stored as powers of two (e.g., exp_x 5522, exp_y 5532, exp_z 5542). In addition, references for each child (e.g., child references 5552) can be stored. The size of the quantized BVH nodes 5510 can be scaled based on the width (e.g., number of children) stored at each node, and the amount of storage used to store the child references and bounding box values ​​for the child nodes increases with each additional node.

[0410] The logic for the implementation of the quantized BVH node of Figure 55 is shown in Table 4 below.

[0411] [Table 5] A compound floating point data block (e.g., struct Float) can be defined to represent parent bounding box values, as shown in Table 4. The Float structure includes a 1-bit sign (int1 sign), an E-bit signed integer (intE exp) to store the power of 2 exponent, and a K-bit unsigned integer (uintK mantissa) to represent the mantissa used to store the high precision bounds. For the child bounding box data, M-bit unsigned integers (uintM child_lower_x / y / z, uintM child_upper_x / y / z) can be used to store fixed point numbers to encode potential child bounds.

[0412] In the example of E=8, K=16, M=8, using 32 bits for child references, the QuantizedNodeHW structure of Table 4 has a size of 52 bytes for a 4-wide BVH and 92 bytes for an 8-wide BVH. This is a reduction in structure size over the quantized nodes of Table 1, and a significant reduction in structure size over existing implementations. Note that for mantissa values ​​(K=16), one bit of the mantissa may be implied, reducing the storage requirement to 15 bits.

[0413] The layout of the BVH node structure in Table 4 allows for reduced hardware to perform ray-box intersection tests on child bounding boxes. The hardware complexity is reduced based on several factors: A smaller number of bits can be chosen for K because the relative child bounds add an additional M bits of precision. The scaled parent bounding box sizes are stored as powers of 2 (exp_x / y / z fields), which simplifies the calculations. Additionally, the calculations are refactored to reduce the size of the multipliers.

[0414] In one embodiment, the ray intersection logic of the graphics processor calculates the hit distance of the ray to the axis-aligned faces to perform the ray-box test. The ray intersection logic can use the BVH node logic, including support for the quantized node structure of Table 4. The logic can calculate the distance to the lower bound of the parent bounding box using higher precision parent lower bounds and the quantized relative extents of the child box. Exemplary logic for the x-face calculation is shown in Table 5 below.

[0415] [Table 6] Regarding the logic in Table 5, assuming single-precision floating-point precision to represent the ray, the parent_lower_x value is stored with a 15-bit mantissa, so a 23-bit by 15-bit multiplier can be used. The distance to the lower bound of the parent bounding box on the y and z planes can be calculated similarly to the calculation of dist_peartner_lower_x.

[0416] Using the parent lower bounds, the intersection distance to the relative child bounding box can be calculated for each child bounding box, as illustrated by the calculation of dist_child_lower_x and dist_child_upper_x as per Table 5. The calculation of the dist_child_lower / upper_x / y / z values ​​can be performed using 23-bit by 8-bit multipliers.

[0417] FIG. 56 illustrates a ray-box intersection using quantized values ​​to define a child bounding box 5610 relative to a parent bounding box 5600, according to an embodiment. Applying the ray-box intersection distance determination formula for the x-plane shown in Table 5, the distance along the ray 5602 where the ray intersects the bounds of the parent bounding box 5600 along the x-plane can be determined. A location dist_parent_lower_x 5603 where the ray 5602 intersects the lower bounding surface 5604 of the parent bounding box 5600 can be determined. Based on dist_parent_lower_x 5603, a dist_child_lower_x 5605 where the ray intersects the minimum bounding surface 5606 of the child bounding box 5610 can be determined. Further, based on dist_parent_lower_x 5603, dist_child_upper_x 5607 can be determined for where the ray intersects the maximum bounding plane 5608 of the child bounding box 5610. Similar determinations can be performed for each dimension in which the parent bounding box 5600 and the child bounding box 5610 are defined (e.g., along the y-axis and z-axis). The plane intersection distance can then be used to determine whether the ray intersects the child bounding box. In one embodiment, the graphics processing logic can determine the intersection distances for multiple dimensions and multiple bounding boxes in parallel using SIMD and / or vector logic. Furthermore, at least a first portion of the calculations described herein may be performed on a graphics processor, while a second portion of the calculations may be performed on one or more application processors coupled to the graphics processor.

[0418] FIG. 57 is a flow diagram of BVH decompression and traversal logic 5700 according to an embodiment. In one embodiment, the BVH decompression and traversal logic may reside in special purpose hardware logic of a graphics processor or may be executed by shader logic executing on the execution resources of the graphics processor. The BVH decompression and traversal logic 5700 may cause the graphics processor to perform operations to calculate a distance along a ray to a lower bounding surface of a parent bounding volume, as shown in block 5702. At block 5704, the logic may calculate a distance to a lower bounding surface of a child bounding volume based in part on the calculated distance to the lower bounding surface of the parent bounding volume. At block 5706, the logic may calculate a distance to an upper bounding surface of a child bounding volume based in part on the calculated distance to the lower bounding surface of the parent bounding volume.

[0419] At block 5708, the BVH stretch and traversal logic 5700 can determine a ray intersection for the child bounding volume based in part on the distance to the upper and lower bounding surfaces of the child bounding volume, where the intersection distance for each dimension of the bounding box is used to determine the intersection. In one embodiment, the BVH stretch and traversal logic 5700 determines the ray intersection for the child bounding volume by determining whether the maximum entrance surface intersection distance of the ray is less than or equal to the minimum exit surface distance. In other words, a ray intersects a child bounding volume when the ray enters the bounding volume along all of the defined surfaces before exiting the bounding volume along any of the defined surfaces. If the BVH stretch and traversal logic 5700 determines at 5710 that the ray intersects the child bounding volume, the logic can traverse the child node for the bounding volume to test the child bounding volumes in the child node, as shown at block 5712. At block 5712, node traversal can be performed and a reference to the node associated with the intersected bounding box can be accessed. The child bounding volume becomes the parent bounding volume and the children of the intersected bounding volume can be evaluated. If the BVH decompression and traversal logic 5700 determines at 5710 that the ray does not intersect with the child bounding volume, then the branch of the bounding hierarchy associated with the child bounding volume is skipped, as shown at block 5714. This is because the ray does not intersect with a bounding volume until further down the subtree branch associated with the non-intersected child bounding volume.

[0420] [Further compression via coplanar bounding boxes] For any N-wide BVH using bounding boxes, the bounding volume hierarchy can be constructed such that each of the six sides of the 3D bounding box is shared by at least one child bounding box. For 3D co-surface bounding boxes, 6×log2 N bits can be used to indicate whether a given face of the parent bounding box is shared with a child bounding box. For N=4 for 3D co-surface bounding boxes, 12 bits are used to indicate the shared faces, with each of the two bits being used to identify which of the four children reuses each potentially shared parent face. Each bit can be used to indicate whether the parent face is reused for a particular child. For 2-wide BVHs, for each face of the parent bounding box, six additional bits can be added to indicate whether the bounding box face (e.g., side) is shared by the child. Although the SPBB concept can be applied to any number of dimensions, in one embodiment, the benefits of SPBBs are generally greatest for 2-wide (e.g., binary) SPBBs.

[0421] The use of shared surface bounding boxes can further reduce the amount of data stored when using BVH node quantization as described herein. In a 3D 2-wide BVH example, the 6 shared surface bits can reference min_x, max_x, min_y, max_y, min_z, and max_z for the parent bounding box. If the min_x bit is zero, the first child inherits the shared surface from the parent bounding box. For children that share a surface with the parent bounding box, the quantized value for that surface does not need to be stored, which reduces the storage and decompression costs of the node. Additionally, high precision values ​​for the surfaces can be used for the child bounding box.

[0422] FIG. 58 is a diagram of an example two-dimensional shared plane bounding box 5800. The two-dimensional (2D) shared plane bounding box (SPBB) 5800 includes a left child 5802 and a right child 5804. In a 2D binary SPBPP, 4log2 2 additional bits can be used to indicate which of the four shared faces of the parent bounding box are shared, with a bit associated with each face. In one embodiment, a zero can be associated with the left child 5802 and a one can be associated with the right child, such that the shared plane bits for the SPBB 5800 are min_x=0, max_x=1, min_y=0, max_y=0, and the left child 5802 shares the lower_x, upper_y, and lower_y faces with the parent SPB 5800, and the right child 5804 shares the upper_x face.

[0423] FIG. 59 is a flow diagram of the shared-plane BVH logic 5900 according to an embodiment. The shared-plane BVH logic 5900 can be used to reduce the number of quantized values ​​stored for the lower and upper bounds of one or more child bounding boxes, reduce stretch / dequantization costs for a BVH node, and improve the accuracy of values ​​used in ray-box intersection tests for child bounding boxes of a BVH node. In one embodiment, as shown in block 5902, the shared-plane BVH logic 5900 includes defining a parent bounding box for a set of child bounding boxes such that the parent bounding box shares one or more faces with one or more child bounding boxes. The parent bounding box can be defined in one embodiment by selecting a set of existing axis-aligned bounding boxes for geometric objects in the scene and defining the parent bounding box based on the minimum and maximum ranges of the set of bounding boxes in each face. For example, the top value for each face of the parent bounding box is defined as the maximum value for each plane in the set of child bounding boxes. At block 5904, the shared surface BVH logic 5900 can encode shared child faces for each face of a parent bounding box. As shown in block 5906, the shared surface BVH logic 5900 can inherit parent surface values ​​for child faces that have shared faces during ray-box intersection testing. The shared surface values ​​for the children can be inherited with higher precision and the parent surface values ​​can be stored in the BVH node structure, and generating and storing lower precision quantized values ​​for the shared faces can be bypassed.

[0424] [Apparatus and method for box-to-box testing] Photon mapping is a two-pass global illumination rendering technique that approximates a rendering formula for integrating light emission at any point in space. Rays (e.g., photons) from the light source and rays from the camera are traced independently until a termination criterion is met. They are then connected to a second processing stage to generate an emission value.

[0425] Photon mapping is known to render some lighting effects very efficiently, such as caustics cast by a glass object onto a table. To render this effect, the photon mapper emits virtual photons from the light source towards the glass object, calculates their refracted paths through the object, and records the photon positions on the table as hits. In a second pass, the renderer performs standard path tracing from the camera and estimates the light intensity at a point on the table by calculating the photon density (i.e. the collected photons near that point).

[0426] One embodiment of the present invention uses box queries to perform efficient photon collection on ray traversal hardware. In addition to calculating photon density, the box queries described herein are general enough to be used for other applications such as enumerating all light sources that illuminate a point or region in space, computing the nearest surface point for a given query position, collecting photons in a fixed region of space, and collecting the nearest photons to a query point.

[0427] 60 illustrates an exemplary ray tracing architecture in which embodiments of the present invention may be implemented. In this embodiment, traversal circuitry 6002 may be configured or programmed with box / box test logic 6003 for performing box-box tests (i.e., in addition to performing ray-box tests when traversing rays through the nodes of the BVH), as described below.

[0428] The illustrated embodiment includes shader execution circuitry 4000 for executing shader program code and processing associated ray tracing data 4902 (e.g., BVH node data and ray data), ray tracing acceleration circuitry 6010 including traversal circuitry 6002 and intersection circuitry 6003 for performing traversal and intersection operations, respectively, and memory 3198 for storing program code and associated data processed by the RT acceleration circuitry 6010 and the shader execution circuitry 4000.

[0429] In one embodiment, the shader execution circuitry 4000 includes multiple cores / execution units 4001 that execute shader program code to perform various forms of data parallel operations. For example, in one embodiment, the cores / execution units 4001 can execute a single instruction across multiple lanes, with each instance of the instruction operating on data stored in a different lane. In a SIMT implementation, for example, each instance of the instruction is associated with a different thread. During execution, the L1 cache stores certain ray tracing data (e.g., recently or frequently accessed data) for efficient access.

[0430] The set of primary rays may be dispatched to a scheduler 4007, which schedules the work for the shaders execute...

Claims

1. a bounding volume hierarchy (BVH) generator for constructing a BVH including a plurality of hierarchically arranged BVH nodes; a multi-function traversal circuit for traversing a query box through the BVH and for traversing a ray through the BVH; Including, The multifunction traversal circuitry reads a BVH node from the top of a BVH node stack and reads a query box from local storage or memory, the multifunction traversal circuitry: box-box testing circuitry and / or logic for comparing maximum and minimum X, Y and Z coordinates of the BVH nodes to the query box and generating an overlap indication if an overlap is detected for each of the X, Y and Z dimensions; a distance determination circuit and / or logic for generating a distance value representative of the extent of overlap between the BVH node and the query box; sorting circuitry and / or logic for sorting the BVH nodes within a set of one or more further BVH nodes based on the distance values; The apparatus further comprises:

2. 2. The apparatus of claim 1, further comprising an inverse quantization circuit and / or logic for generating the maximum and minimum X, Y, and Z coordinates for the BVH node by inverse quantizing quantized X, Y, and Z coordinates associated with the BVH node.

3. The distance determination circuit includes: determining a first poke distance from a first axis-aligned direction and a second poke distance from a second axis-aligned direction for each of X, Y, and Z coordinates, the first poke distance indicating an overlap when the query box pokes through the BVH node from the first axis-aligned direction and the second poke distance indicating an overlap when the query box pokes through the BVH node from the second axis-aligned direction; selecting a minimum of the first and second penetration distances for each of the X, Y and Z coordinates; The apparatus of claim 1 , further comprising:

4. The apparatus of claim 1 , wherein the BVH node and the set of one or more further BVH nodes comprise nodes at a common level of the BVH.

5. 5. The apparatus of claim 4, wherein the distance determination circuitry and / or logic determines one or more further distance values ​​associated with the set of one or more further BVH nodes, and the sorting circuitry generates a sorted order of the BVH nodes and the set of one or more further BVH nodes based on the distance values ​​and the one or more further distance values.

6. The apparatus of claim 5 , wherein the BVH node and the set of one or more further BVH nodes are sorted into the BVH node stack in the sort order.

7. 7. The apparatus of claim 1, wherein the multi-function traversal circuitry further comprises a ray traversal circuitry for traversing the ray through the BVH, the ray traversal circuitry comprising ray test circuitry and / or logic for determining whether the ray hits the BVH node, the ray test circuitry and / or logic comprising the box-box test circuitry and / or logic or a portion thereof.

8. 8. The apparatus of claim 7, wherein if the ray testing circuitry and / or logic determines that the ray hits the BVH node, the distance determination circuitry determines a hit distance value representing the coordinates at which the ray hits the BVH node, and the sorting circuitry and / or logic sorts the BVH nodes within the set of one or more further BVH nodes based on one or more further hit distance values ​​associated with the set of one or more further BVH nodes.

9. constructing a bounding volume hierarchy (BVH) including a plurality of hierarchically arranged BVH nodes; reading a BVH node from the top of a BVH node stack by a multifunction traversal circuit, the multifunction traversal circuit being configured to traverse a query box through the BVH and to traverse a ray through the BVH, wherein to traverse a query box through the BVH, the multifunction traversal circuit comprises: reading a query box from local storage or memory; comparing the maximum and minimum X, Y and Z coordinates of the BVH nodes to the query box; generating an overlap indication if an overlap is detected for each of the X, Y and Z dimensions; generating a distance value representing the extent of overlap between the BVH node and the query box; and sorting the BVH nodes within a set of one or more further BVH nodes based on the distance values; The method includes:

10. 10. The method of claim 9, wherein the multifunction traversal circuit performs operations of dequantizing quantized X, Y, and Z coordinates associated with the BVH nodes to generate the maximum and minimum X, Y, and Z coordinates.

11. The distance value is determining a first poke distance from a first axis-aligned direction and a second poke distance from a second axis-aligned direction for each of X, Y, and Z coordinates, the first poke distance indicating an overlap when the query box pokes through the BVH node from the first axis-aligned direction and the second poke distance indicating an overlap when the query box pokes through the BVH node from the second axis-aligned direction; selecting a minimum of the first and second penetration distances for each of the X, Y and Z coordinates; 10. The method of claim 9, wherein the method is generated by performing

12. 12. The method of claim 9, wherein the BVH node and the set of one or more further BVH nodes comprise nodes at a common level of the BVH.

13. determining one or more further distance values ​​associated with the set of one or more further BVH nodes; generating a sort order for the set of the BVH nodes and the one or more further BVH nodes based on the distance values ​​and the one or more further distance values; The method of claim 12 further comprising:

14. The method of claim 13 , wherein the BVH node and the set of one or more further BVH nodes are sorted into the BVH node stack in the sort order.

15. 15. The method of claim 9, further comprising the step of traversing the ray through the BVH by comparing, with the multifunction traversal circuitry, the coordinates of the ray with the maximum and minimum X, Y and Z coordinates of the BVH nodes, wherein a common set of test circuitry and / or logic is used to determine whether the ray hits the BVH node and is also used to compare the maximum and minimum X, Y and Z coordinates of the BVH nodes with the query box.

16. If it is determined that the ray hits the BVH node, the method comprises: determining a hit distance value representing the coordinates at which the ray hits the BVH node; sorting the BVH nodes within the set of one or more additional BVH nodes based on one or more additional hit distance values ​​associated with the set of one or more additional BVH nodes; The method of claim 15 further comprising:

17. When executed by a machine, the program causes the machine to: constructing a bounding volume hierarchy (BVH) including a plurality of hierarchically arranged BVH nodes; an operation of reading a BVH node from a top of a BVH node stack by a multifunction traversal circuit, the multifunction traversal circuit being configured to traverse a query box through the BVH and to traverse a ray through the BVH, the multifunction traversal circuit comprising: reading a query box from local storage or memory; comparing the maximum and minimum X, Y and Z coordinates of the BVH nodes to the query box; generating an overlap indication if an overlap is detected for each of the X, Y and Z dimensions; generating a distance value representing the extent of overlap between the BVH node and the query box; and further performing the operation of sorting the BVH nodes within a set of one or more further BVH nodes based on the distance values; A program that executes the following.

18. 20. The program of claim 17, further causing the multifunction traversal circuit to perform the operation of dequantizing quantized X, Y, and Z coordinates associated with the BVH nodes to generate the maximum and minimum X, Y, and Z coordinates.

19. The distance value is: determining a first poke distance from a first axis-aligned direction and a second poke distance from a second axis-aligned direction for each of X, Y, and Z coordinates, the first poke distance indicating an overlap when the query box pokes through the BVH node from the first axis-aligned direction and the second poke distance indicating an overlap when the query box pokes through the BVH node from the second axis-aligned direction; selecting a minimum of the first and second penetration distances for each of the X, Y and Z coordinates; The program according to claim 17, which is generated by the machine executing the program.

20. 20. The program of claim 17, wherein the BVH node and the set of one or more further BVH nodes comprise nodes at a common level of the BVH.

21. For said machine, determining one or more further distance values ​​associated with the set of one or more further BVH nodes; generating a sort order for the set of the BVH nodes and the one or more further BVH nodes based on the distance values ​​and the one or more further distance values; The program according to claim 20, further comprising:

22. 22. The method of claim 21, wherein the BVH node and the set of one or more further BVH nodes are sorted into the BVH node stack in the sort order.

23. For said machine, 23. The program of claim 17, further comprising causing the multi-function traversal circuit to perform the operation of traversing the ray through the BVH by comparing the coordinates of the ray with the maximum and minimum X, Y, and Z coordinates of the BVH nodes, wherein a common set of test circuitry and / or logic is used to determine whether the ray hits the BVH node and is also used to compare the maximum and minimum X, Y, and Z coordinates of the BVH nodes with the query box.

24. If it is determined that the ray hits the BVH node, the program causes the machine to: determining a hit distance value representing the coordinates at which the ray hits the BVH node; sorting the BVH nodes within the set of one or more additional BVH nodes based on one or more additional hit distance values ​​associated with the set of one or more additional BVH nodes; The program according to claim 23, further comprising:

25. A machine-readable storage medium storing a program according to any one of claims 17 to 24.

26. means for constructing a bounding volume hierarchy (BVH) including a plurality of hierarchically arranged BVH nodes; a multifunction traversal means for reading a BVH node from a top of a BVH node stack, the multifunction traversal means being configured to traverse a query box through the BVH and to traverse a ray through the BVH, wherein to traverse a query box through the BVH, the multifunction traversal means comprises: reading a query box from local storage or memory; comparing the maximum and minimum X, Y and Z coordinates of the BVH nodes to the query box; generating an overlap indication if an overlap is detected for each of the X, Y and Z dimensions; generating a distance value representing the extent of overlap between the BVH node and the query box; A multi-function traversal means further performing means for sorting the BVH nodes within a set of one or more further BVH nodes based on the distance values; An apparatus comprising:

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