Analog-to-digital conversion circuit and image sensor

Abstract

To provide an image sensor that converts a pixel signal into a digital image with high accuracy.SOLUTION: An analog-to-digital conversion circuit includes a first operational amplifier 120 that compares a lamp voltage RAMP with a voltage to be converted and outputs the result, a second operational amplifier 130 that compares the amplification result of the first operational amplifier 120 transmitted to a first input terminal INN2 with a reference voltage VDDA transmitted to a second input terminal INP2, and outputs the result, a leakage current measuring device 650 that measures a leakage current to the first input terminal INN2, and a leakage current generator 660 that passes the same amount of current as the leakage current measured by the leakage current measuring device 650 to the second input terminal INP2.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] This patent document relates to image sensors. [Background technology]

[0002] CMOS image sensors (CIS) have a trade-off between speed and power. Therefore, currently, CMOS image sensors mainly use a column-parallel structure that has an optimal trade-off between speed and power, and because of this, it is difficult to integrate an analog-to-digital converter (ADC) in a narrow pixel width, so a simple single-slope analog-to-digital converter (ADC) is mainly used.

[0003] Delta Reset Sampling (DRS) is an example of Correlated Double Sampling (CDS), which is a method for removing reset noise from a pixel signal by reading out the pixel's reset value and subtracting two components after reading out the pixel signal. Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present invention can provide an image sensor that converts pixel signals into a digital image with high accuracy. [Means for solving the problem]

[0005] An analog-to-digital conversion circuit according to one embodiment of the present invention can include a first operational amplifier that compares a ramp voltage with a voltage to be converted and outputs the result, a second operational amplifier that compares the amplified result of the first operational amplifier transmitted to a first input terminal with a reference voltage transmitted to a second input terminal and outputs the result, a leakage current meter that measures a leakage current to the first input terminal, and a leakage current generator that flows a current to the second input terminal in the same amount as the leakage current measured by the leakage current meter.

[0006] An image sensor according to one embodiment of the present invention may include a pixel, a first operational amplifier that compares a ramp voltage with an output voltage of the pixel and outputs the result, a second operational amplifier that compares an amplified result of the first operational amplifier transmitted to a first input terminal with a reference voltage transmitted to a second input terminal and outputs the result, a leakage current meter that measures a leakage current to the first input terminal, a leakage current generator that flows a current of the same amount as the leakage current measured by the leakage current meter to the second input terminal, and a digital code generation circuit that generates image data using the output of the second operational amplifier. Effect of the Invention

[0007] Embodiments of the present invention allow image sensors to produce better quality digital images. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram showing the configuration of an image sensor 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram of one embodiment of a pixel 110 of FIG. [Diagram 3] 2 is a diagram showing a ramp voltage RAMP and an output voltage PIXEL of a pixel of the image sensor 100 of FIG. 1. [Figure 4] FIG. 2 is a block diagram of an embodiment of the first operational amplifier 120 and the second operational amplifier 130 of FIG. [Diagram 5]4 is a diagram showing how the output terminal VOUT1 of the first operational amplifier and the input terminal INN2 of the second operational amplifier change when the ramp voltage RAMP changes as shown in FIG. 3. [Figure 6] FIG. 6 is a diagram showing the configuration of an image sensor 600 according to another embodiment of the present invention. [Figure 7] FIG. 7 is a block diagram of an embodiment of the leakage current measuring device 650 and the leakage current generator 660 of FIG. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In the following, the most preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the technical idea of ​​the present invention. In describing the present invention, known configurations that are not related to the gist of the present invention may be omitted. It should be noted that when referring to the components in each drawing, the same components are preferably given the same reference numerals even if they are shown in different drawings.

[0010] FIG. 1 is a diagram showing the configuration of an image sensor 100 according to an embodiment of the present invention.

[0011] As shown in FIG. 1, the image sensor 100 may include a pixel 110, a first operational amplifier 120, a second operational amplifier 130, a digital code generating circuit 140, switches 121, 122, 131, 132, and capacitors 123, 124, 133, 134.

[0012] The pixel 110 can output a pixel signal PIXEL using the sensed light. A plurality of pixels 110 can be provided in an array configuration including a plurality of rows and columns, but only one pixel 110 is illustrated here for ease of explanation.

[0013] The first operational amplifier 120 may receive a pixel signal PIXEL and a ramp voltage RAMP via capacitors 123 and 124. The first operational amplifier 120 may compare the levels of the pixel signal PIXEL input to the input terminal INN1 via the capacitor 123 and the ramp voltage RAMP input to the input terminal INP1 via the capacitor 124, and output the result to an output terminal VOUT1. The input terminal INN1 may be a negative (-) input terminal, the input terminal INP1 may be a positive (+) input terminal, the output terminal OUT1 may be a positive (+) output terminal, and the output terminal VOUT1_COM may be a negative (-) output terminal.

[0014] The second operational amplifier 130 can receive the output VOUT1 of the first operational amplifier 120 at an input terminal INN2 via a capacitor 133, and can receive a reference voltage at a second input terminal INP2 via a capacitor 134. Here, a power supply voltage VDDA is used as the reference voltage. The second operational amplifier 130 can compare the voltage levels of the input terminals INN2 and INP2, and output the result to an output terminal VOUT2. The input terminal INN2 can be a negative (-) input terminal, the input terminal INP2 can be a positive (+) input terminal, the output terminal VOUT2 can be a positive (+) output terminal, and the output terminal VOUT2_COM can be a negative (-) output terminal.

[0015] The switches 121, 122, 131, and 132 may be for an auto-zeriong operation of the operational amplifiers 120 and 130. During the auto-zeroing operation, the switches 121, 122, 131, and 132 may be turned on. The switch 121 may electrically connect the input terminal INN1 and the output terminal VOUT1 of the first operational amplifier 120, and the switch 122 may electrically connect the input terminal INP1 and the output terminal VOUT1_COM of the first operational amplifier 120. The switch 131 may electrically connect the input terminal INN2 and the output terminal VOUT2 of the second operational amplifier 130, and the switch 132 may electrically connect the input terminal INP2 and the output terminal VOUT2_COM of the second operational amplifier 130. Each of the switches 121 and 122 may include a PMOS transistor, and each of the switches 131 and 132 may include an NMOS transistor. Although the switches 121, 122, 131, and 132 are each configured with one transistor in this example, the switches 121, 122, 131, and 132 may each be configured with two or more transistors. The signal S1 can be activated to a low level during an auto-zeroing operation to turn on the switches 121 and 122, and the signal S2 can be activated to a high level during an auto-zeroing operation to turn on the switches 131 and 132.

[0016] The digital code generation circuit 140 can generate image data IMG using a signal from the output terminal VOUT2 of the second operational amplifier 130. A pixel signal corresponding to the sensed light is output from the pixel 110 first, followed by a reset signal. The second operational amplifier 130 outputs a result of comparing the pixel signal with a ramp voltage first, followed by a result of comparing the reset signal with the ramp voltage. The digital code generation circuit 140 can generate image data IMG, which is digital information corresponding to a value obtained by subtracting the reset signal from the pixel signal, using the output of the second operational amplifier 130.

[0017] FIG. 2 is a block diagram of one embodiment of pixel 110 of FIG.

[0018] As shown in FIG. 2, the pixel 110 may include a photodetector 201 , a capacitor 203 , a reset transistor 205 , a transfer transistor 207 , a drive transistor 209 , and a select transistor 211 .

[0019] The photodetector 201 may perform a photoelectric conversion function. The photodetector may be connected between a ground voltage terminal and a node A. The photodetector 201 may receive light from an external source and generate a photo charge based on the received light. The photodetector 201 may be realized using at least one of a photodiode, a phototransistor, a photogate, a pinned photodiode, and a combination thereof.

[0020] The reset transistor 205 can transmit a power supply voltage VDDA to the node A in response to a reset signal RX. During the reset operation, since both the reset signal RX and the transmission signal TX are activated, both the reset transistor 205 and the transmission transistor 207 can be turned on. Therefore, the photocharge stored in the floating diffusion node FD can be reset by the reset operation.

[0021] The transfer transistor 207 may electrically connect the node A, to which the photodetector 201 is connected, to a floating diffusion node FD in response to a transfer signal TX.

[0022] The floating diffusion node FD may be a node where charges corresponding to light sensed by the photodetector 201 or charges corresponding to an initialization voltage are accumulated. A capacitor 203 may be connected to the floating diffusion node FD.

[0023] The driving transistor 209 may have a gate connected to the floating diffusion node FD, and a drain and a source connected between a power supply voltage terminal VDDA and the selection transistor 211. The driving transistor 209 may serve to amplify the voltage of the floating diffusion node FD.

[0024] In response to a selection signal SX, the selection transistor 211 can output the voltage amplified by the driving transistor 209 to the pixel signal PIXEL.

[0025] FIG. 3 is a diagram showing the ramp voltage RAMP and the pixel output voltage PIXEL of the image sensor 100 of FIG.

[0026] 3, "GR" denotes a global reset period. During this period, both the reset signal RX and the transfer signal TX are activated to a high level, and both the reset transistor 205 and the transfer transistor 207 are turned on. This resets the floating diffusion node FD of the pixel 110.

[0027] "GE" denotes a global exposure period. During this period, the reset signal RX may be inactivated to a low level to turn off the reset transistor 205, and the transfer signal TX may be activated to a high level to turn on the transfer transistor 207. Thus, photocharges due to light detected by the photodetector 201 may be transferred to the floating diffusion node FD.

[0028] After the global exposure period GE and before the signal readout period SR, an auto-zeroing operation may be performed on the first operational amplifier 120 and the second operational amplifier 130. During the auto-zeroing operation, the switches 121, 122, 131, and 132 may all be turned on.

[0029] "SR" represents a signal readout period. During this period, the reset signal RX and the transfer signal TX are inactivated to a low level to turn off the reset transistor 205 and the transfer transistor 207, and the selection signal SX is activated to turn on the selection transistor 211. Thus, a voltage corresponding to the photocharge stored in the floating diffusion node FD may be output from the pixel 110. That is, the output voltage PIXEL of the pixel 110 here may be a voltage corresponding to the pixel signal. During the signal readout period SR, from the time when the ramp voltage RAMP starts to fall to the time when the ramp voltage RAMP meets the output voltage PIXEL of the pixel, that is, the time when the voltage level of the output terminal of the second operational amplifier VOUT2 is inverted, the digital code generation circuit 140 may count the clock to generate a digital code corresponding to the pixel signal.

[0030] "RR" represents a reset readout period. During this period, the reset signal RX and the transfer signal TX are activated to a high level to turn on the reset transistor 205 and the transfer transistor 207, and the selection signal SX is activated to turn on the selection transistor 211. Thus, the floating diffusion node FD is reset, and a voltage corresponding to the reset floating diffusion node may be output from the pixel 110. That is, the output voltage PIXEL of the pixel 110 here may be a voltage corresponding to the reset value. During the reset readout period RR, from the time when the ramp voltage RAMP starts to fall to the time when the ramp voltage RAMP meets the output voltage PIXEL of the pixel, that is, the time when the voltage level of the output terminal of the second operational amplifier VOUT2 is inverted, the digital code generation circuit 140 may count the clock to generate a digital code corresponding to the reset value.

[0031] The digital code generation circuit 140 can generate image data IMG corresponding to the Signal-Reset value by subtracting the value of the digital code corresponding to the reset value generated in the reset readout section RR from the value of the digital code corresponding to the pixel signal generated in the signal readout section SR.

[0032] Fig. 4 is a block diagram of an embodiment of the first operational amplifier 120 and the second operational amplifier 130 of Fig. 1. In Fig. 4, switches 121, 122, 131, and 132 and capacitors 123, 124, 133, and 134 are also shown.

[0033] 4, the first operational amplifier 120 may include NMOS transistors M0 to M5 and PMOS transistors M6 and M7. The NMOS transistors M0 and M1 may adjust the amount of current flowing through the first operational amplifier 120 in response to bias voltages VBIAS1 and VCASC1. The NMOS transistors M2 and M3 may be used to receive signals from the input terminals INN1 and INP1. The NMOS transistors M4 and M5 and the PMOS transistors M6 and M7 may be used to differentially amplify the signals input via the NMOS transistors M2 and M3.

[0034] The second operational amplifier 130 may include PMOS transistors M8 to M13 and NMOS transistors M14 and M15. The PMOS transistors M8 and M9 may adjust the amount of current flowing through the second operational amplifier 130 in response to bias voltages VBIAS2 and VCASC2. The PMOS transistors M10 and M11 may be used to receive signals from the input terminals INN2 and INP2. The PMOS transistors M12 and M13 and the NMOS transistors M14 and M15 may be used to differentially amplify the signals input via the PMOS transistors M10 and M11.

[0035] The transistors connected to the input terminals INN1 and INP1 in the first operational amplifier 120 are NMOS transistors M2 and M3, and the transistors connected to the input terminals INN2 and INP2 in the second operational amplifier 130 are PMOS transistors M10 and M11. For this reason, when the switches 121, 122, 131, and 132 are turned on to perform an auto-zeroing operation, the input terminals INN1 and INP1 and the output terminals VOUT1 and VOUT1_COM of the first operational amplifier 120 become a 'VDDA-Vthp' level, and the input terminals INN2 and INP2 and the output terminals VOUT2 and VOUT2_COM of the second operational amplifier 130 become a 'Vthn' level. Here, Vthn may be a threshold voltage of an NMOS transistor, and Vthp may be a threshold voltage of a PMOS transistor.

[0036] FIG. 5 is a diagram showing how the output terminal VOUT1 of the first operational amplifier and the input terminal INN2 of the second operational amplifier change when the ramp voltage RAMP changes as in FIG.

[0037] 5, the output terminal VOUT1 of the first operational amplifier 120 can start from an auto-zeroing level "VDDA-Vthp", and the input terminal INN2 of the second operational amplifier 130 can start from an auto-zeroing level "Vthn". The voltage levels of the two terminals VOUT1 and INN2 are different from each other, but can swing the same because they are coupled by the capacitor 133.

[0038] Since the swing width of the ramp voltage RAMP is large, the swing width of the output terminal VOUT1 is also large. If the input terminal INN2 swings in the same manner as the output terminal VOUT1, the input terminal INN2 must swing to a level 501 below the ground voltage. However, when the voltage level of the input terminal INN2 drops to a level below the ground voltage, a leakage current is generated from the switch 131 to the input terminal INN2, and the input terminal INN2 can only swing to a level 502. As the voltage level of the input terminal INN2 drops to a negative voltage level, a forward bias is generated in the PN junction of the NMOS transistor that constitutes the switch 131, causing a leakage current to flow from the switch 131 to the input terminal INN2, and as a result, the voltage level of the input terminal INN2 increases.

[0039] If the voltage of the input terminal INN2 cannot swing to level 501 due to leakage current and swings only to level 502, the voltage level of the input terminal INN2 will not fluctuate as shown by the solid line but will fluctuate as shown by the dotted line, which may cause an error in the reset read operation. The offset OFFSET in the drawing represents the fluctuation in the voltage level of the input terminal INN2 due to leakage current, and an error may occur in the reset read operation by the amount of this offset OFFSET value.

[0040] FIG. 6 is a diagram showing the configuration of an image sensor 600 according to another embodiment of the present invention.

[0041] 6, the image sensor 600 may include the pixel 110, the first operational amplifier 120, the second operational amplifier 130, the digital code generating circuit 140, the switches 121, 122, 131, 132, the capacitors 123, 124, 133, 134, a leakage current meter 650, and a leakage current generator 660. That is, the image sensor 600 of FIG. 6 may further include a leakage current meter 650 and a leakage current generator 660 compared to the image sensor 100 of FIG.

[0042] The leakage current measuring device 650 can measure the leakage current flowing into the input terminal INN2 of the second operational amplifier 130. As described in conjunction with Fig. 5, as the voltage level of the input terminal INN2 decreases to a negative voltage level equal to or lower than the ground voltage, a leakage current flows from the switch 131 to the input terminal INN2, and the leakage current measuring device 650 can measure the amount of this leakage current. The leakage current measuring device 650 can directly or indirectly measure the leakage current flowing into the input terminal INN2.

[0043] The leakage current generator 660 can cause the same amount of current as the leakage current measured by the leakage current measuring device 650 to flow to the input terminal INP2. Since the leakage current generator 660 causes the same amount of leakage current as the leakage current generated at the input terminal INN2 to flow to the input terminal INP2, the same amount of offset as that at the input terminal INN2 can also occur at the input terminal INP2. Since the second operational amplifier 130 is a differential amplifier, it amplifies the voltage difference between the input terminals INN2 and INP2. However, if the same amount of offset occurs at both the input terminals INN2 and INP2, no problem can occur in the operation of the second operational amplifier 130.

[0044] The offset problem described in FIG. 5 can be solved by using a leakage current meter 650 to determine the amount of leakage current flowing into input terminal INN2, and using a leakage current generator 660 to cause the same amount of leakage current to flow into input terminal INP2 as into input terminal INN2.

[0045] 6, the remaining components except for the pixel 110 are components for converting the analog voltage PIXEL output from the pixel 110 into image data IMG, which is a digital code. Therefore, the present invention can be applied not only to image sensors but also to general analog-to-digital conversion circuits for converting analog voltages into digital codes.

[0046] FIG. 7 is a block diagram of one embodiment of the leakage current measurement device 650 and the leakage current generator 660 of FIG.

[0047] 7, the leakage current measuring device 650 can indirectly measure the leakage current flowing through the input terminal INN2 of the second operational amplifier 130. The leakage current measuring device 650 can include a dummy first operational amplifier 720, a dummy second operational amplifier 730, dummy switches 721, 722, 731, 732, dummy capacitors 723, 724, 733, 734, and a measuring device 770.

[0048] The configuration named "dummy" can be configured in the same way as the other configuration. For example, the dummy second operational amplifier 730 can be configured in the same way as the second operational amplifier 130. The configuration named "dummy" is a configuration for making the amount of dummy leakage current flowing to the input terminal XINN2 of the dummy second operational amplifier 730 the same as the amount of leakage current flowing to the input terminal INN2 of the second operational amplifier 130, and is not a configuration for actually performing an analog-to-digital conversion operation. Therefore, it is not necessary for an actual pixel to be connected to the dummy first operational amplifier 720.

[0049] The measuring device 770 can generate a leakage voltage VSENS corresponding to a dummy leakage current flowing through the input terminal XINN2 of the dummy second operational amplifier 730. The measuring device 770 can include a current mirror 771 and a current-voltage converter 775.

[0050] The current mirror 771 includes NMOS transistors 772 and 773 , and the mirroring operation of the current mirror 771 allows a dummy leakage current flowing through the drain of the NMOS transistor 772 to be mirrored to the drain of the NMOS transistor 773 .

[0051] The current-voltage converter 775 may include a PMOS transistor having a source terminal to which a power supply voltage VDDA is applied, a drain connected to the drain of the NMOS transistor 773, and a drain and gate connected to each other. The current-voltage converter 775 may generate a leakage voltage VSENS that is a voltage corresponding to the dummy leakage current mirrored to the drain terminal of the NMOS transistor 773.

[0052] The leakage current generator 660 may include a PMOS transistor having a leakage voltage VSENS applied to its gate to pass a current from the power supply voltage terminal VDDA to the input terminal INP2. The PMOS transistor of the leakage current generator 660 has the same voltage VSENS applied to its gate as the PMOS transistor 775 of the current-voltage converter 775, so that the same amount of current as the PMOS transistor of the current-voltage converter 775, i.e., the same amount of current as the dummy leakage current, can pass to the input terminal INP2.

[0053] 6, the image sensor 600 is illustrated as including one second operational amplifier 130, but the image sensor 600 may include a plurality of second operational amplifiers. In this case, a leakage current generator 660 must be provided separately for each of the plurality of second operational amplifiers, but the plurality of second operational amplifiers may share one leakage current measuring device 650.

[0054] Although the technical concept of the present invention has been specifically described by the above-mentioned preferred embodiments, it should be noted that the above-mentioned embodiments are for the purpose of explanation and not for the purpose of limiting the present invention. In addition, a person skilled in the art of the present invention will understand that various embodiments are possible within the scope of the technical concept of the present invention. [Explanation of symbols]

[0055] 600 Image Sensor 110 pixels 120 First operational amplifier 130 Second operational amplifier 140 Digital Code Generator Circuit 121, 122, 131, 132 Switches 123, 124, 133, 134 Capacitors 650 Leakage current meter 660 Leakage Current Generator

Claims

1. a first operational amplifier that compares the ramp voltage with a voltage to be converted and outputs the result of the comparison; a second operational amplifier that compares the amplification result of the first operational amplifier transmitted to a first input terminal with a reference voltage transmitted to a second input terminal, and outputs the result; a leakage current measuring device for measuring a leakage current to the first input terminal; a leakage current generator that supplies a current having the same amount as the leakage current measured by the leakage current measuring device to the second input terminal; An analog-to-digital conversion circuit comprising:

2. The leakage current measuring device includes: a dummy second operational amplifier configured similarly to the second operational amplifier; a measuring device that generates a leakage voltage corresponding to a dummy leakage current flowing through a dummy first input terminal of the dummy second operational amplifier; 2. The analog-to-digital conversion circuit according to claim 1, comprising:

3. The measuring instrument is a current mirror that mirrors a current flowing through the dummy first input terminal; a current-to-voltage converter for generating the leakage voltage corresponding to the current mirrored by the current mirror; 3. The analog-to-digital conversion circuit according to claim 2, comprising:

4. The current-to-voltage converter includes:

4. The analog-to-digital conversion circuit according to claim 3, further comprising a PMOS transistor having a drain through which the mirrored current flows and a source to which a pull-up voltage is applied, the drain and the gate of which are connected together.

5. The leakage current generator includes:

3. The analog-to-digital conversion circuit according to claim 2, wherein a current flows through said second input terminal in response to said leakage voltage.

6. The leakage current measuring device includes:

3. The analog-to-digital conversion circuit of claim 2, further comprising a dummy first operational amplifier configured similarly to said first operational amplifier.

7. a first switch for connecting the positive output terminal of the first operational amplifier to the negative input terminal of the first operational amplifier during an autozeroing operation; a second switch for connecting the negative output terminal of the first operational amplifier to the positive input terminal of the first operational amplifier during the auto-zeroing operation; a third switch for connecting the first input terminal and the positive output terminal of the second operational amplifier during the auto-zeroing operation; a fourth switch for connecting the second input terminal and the negative output terminal of the second operational amplifier during the auto-zeroing operation; The analog-to-digital conversion circuit of claim 1 further comprising:

8. The third switch is 8. The analog-to-digital conversion circuit of claim 7, comprising one or more PMOS transistors.

9. 2. The analog-to-digital conversion circuit according to claim 1, further comprising a digital code generation circuit for generating a digital code using an output of the second operational amplifier.

10. Pixels and a first operational amplifier for comparing a ramp voltage with the output voltage of the pixel and outputting the result; a second operational amplifier that compares the amplification result of the first operational amplifier transmitted to a first input terminal with a reference voltage transmitted to a second input terminal, and outputs the result; a leakage current measuring device for measuring a leakage current to the first input terminal; a leakage current generator that supplies a current having the same amount as the leakage current measured by the leakage current measuring device to the second input terminal; a digital code generating circuit for generating image data using the output of the second operational amplifier; An image sensor comprising:

11. The leakage current measuring device includes: a dummy second operational amplifier configured similarly to the second operational amplifier; a measuring device that generates a leakage voltage corresponding to a dummy leakage current flowing through a dummy first input terminal of the dummy second operational amplifier; The image sensor of claim 10 .

12. The measuring instrument is a current mirror that mirrors a current flowing through the dummy first input terminal; a current-to-voltage converter for generating the leakage voltage corresponding to the current mirrored by the current mirror; 12. The image sensor of claim 11, comprising:

13. The current-to-voltage converter includes:

13. The image sensor of claim 12, further comprising a PMOS transistor having a drain through which the mirrored current flows and a source to which a pull-up voltage is applied, the drain and the gate of which are connected together.

14. The leakage current generator includes:

12. The image sensor of claim 11, wherein the image sensor flows a current at the second input terminal in response to the leakage voltage.

15. The leakage current measuring device includes: The image sensor of claim 11 , further comprising a dummy first operational amplifier configured similarly to the first operational amplifier.

16. a first switch for connecting the positive output terminal of the first operational amplifier to the negative input terminal of the first operational amplifier during an autozeroing operation; a second switch for connecting the negative output terminal of the first operational amplifier to the positive input terminal of the first operational amplifier during the auto-zeroing operation; a third switch for connecting the first input terminal and the positive output terminal of the second operational amplifier during the auto-zeroing operation; a fourth switch for connecting the second input terminal and the negative output terminal of the second operational amplifier during the auto-zeroing operation; The image sensor of claim 10 further comprising:

17. The third switch is 20. The image sensor of claim 16, comprising one or more PMOS transistors.

Images