Systems and methods for enhanced wafer manufacturing - Patents.com

Abstract

A computing device is provided, the computing device including at least one processor in communication with at least one memory device, the at least one processor being programmed to: store in the at least one memory device a model for simulating a portion of an assembly line, receive scan data of a first inspection of a product being assembled, execute the model using the scan data as an input to generate a final profile of the product, compare the final profile to one or more thresholds, determine whether the final profile exceeds at least one of the one or more thresholds, and adjust a first device if it is determined that the final profile exceeds at least one of the one or more thresholds.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Non-provisional Patent Application No. 16 / 786,579, filed February 10, 2020, the entire disclosure of which is incorporated herein by reference. [Technical field]

[0002] The present invention relates generally to enhanced wafer manufacturing, and more specifically to enhanced wafer analysis using nanotopography during wafer processing. [Background technology]

[0003] Semiconductor wafers are commonly used as substrates in the manufacture of integrated circuit (IC) chips. Chip manufacturers require wafers with extremely flat and parallel surfaces so that the maximum number of chips can be produced from each wafer. After being sliced ​​from the ingot, the wafers typically undergo grinding and polishing steps designed to improve certain surface characteristics such as flatness and parallelism.

[0004] Simultaneous double-sided polishing, which simultaneously polishes both sides of a wafer, can produce wafers with high flatness. Grinders that perform double-sided polishing include the following. These grinders use a wafer clamping device to hold the semiconductor wafer during polishing. The clamping device usually consists of a pair of hydrostatic pads and a pair of grinding wheels. The pads and grinding wheels are arranged opposite each other so as to sandwich the wafer vertically. The hydrostatic pads are useful for creating a fluid barrier between each pad and the wafer surface so that the rigid pads hold the wafer during polishing without physically contacting the wafer. This reduces damage to the wafer due to physical fixation and reduces friction even when the wafer moves (rotates) tangentially relative to the pad surface. While this polishing process can improve the flatness and / or parallelism of the polished wafer surface, it can also cause degradation of the topology of the wafer surface. Specifically, it is known that the misalignment of the clamping surfaces of the hydrostatic pads and grinding wheels is the cause of this. Post-polishing polishing creates a highly reflective mirror wafer surface on the polished wafer, but cannot address the topology degradation.

[0005] To identify and address topology degradation concerns, device and semiconductor material manufacturers consider the nanotopography of the wafer surface. For example, SEMI (Semiconductor Equipment and Materials International), a global trade association for the semiconductor industry, defines nanotopography (SEMI Document 3089) as the deviation of the wafer surface within a spatial wavelength of about 0.2 mm to about 20 mm. This spatial wavelength corresponds very closely to the nanometer-scale surface features of a processed semiconductor wafer. Nanotopography measures the height deviation of one side of a wafer and does not consider the variation in the wafer thickness as in traditional flatness measurements. Two techniques are commonly used to measure nanotopography: light scattering and interferometry. These techniques utilize light reflected from the surface of a polished wafer to detect very small surface variations.

[0006] Double-sided polishing is one process that governs the nanotopography of the finished wafer. Nanotopography defects such as C-marks (PV values ​​generally within a radius of 0-50 mm from the center) and B-rings (PV values ​​generally within a radius of 100-150 mm from the center) form during the polishing process and can lead to significant yield losses. A third type of defect caused by nanotopography is entrance marks that occur on the wafer during wire saw slicing. In double-sided polishing, entrance marks can be reduced if the grinding wheel is oriented in a favorable direction relative to the wafer. The wafer is then etched and measured with a laser-based tool. After this, the wafer is subjected to various post-processing steps such as edge polishing, double-sided polishing, and final polishing, as well as measurements of flatness and edge defects before the nanotopography is checked by the nanomapper.

[0007] In some current systems, potentially hundreds of wafers are processed after polishing before a problem in the polishing process can be detected. Additionally, individual production lines and grinders may have specific characteristics that vary from one machine to another. Thus, there is a need for a system that analyzes wafers to quickly and efficiently detect potential problems in the polishing process to prevent significant losses in time and materials.

[0008] This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. As such, it should be understood that these statements are to be read in this light, and not as admissions of prior art. Summary of the Invention

[0009] In one embodiment, a computing device includes at least one processor (or "processor") in communication with at least one memory device. The processor is programmed to store in the at least one memory device a model for simulating a portion of an assembly line. The processor is also programmed to receive scan data of a first inspection of a product being assembled. The first inspection occurs at a first inspection station of the assembly line after operation of the first device. The processor is programmed to execute the model with the scan data as an input to generate a final profile of the product. The processor is programmed to compare the final profile to one or more thresholds. The processor is further programmed to determine whether the final profile exceeds at least one of the one or more thresholds. If it is determined that the final profile exceeds at least one of the thresholds, the processor is programmed to cause the first device to be adjusted.

[0010] In another aspect, a method for analyzing an assembly line is performed by a computing device including at least one processor in communication with at least one memory device. The method includes storing, in the at least one memory device, a model for simulating a portion of the assembly line. The method also includes receiving scan data of a first inspection of a product to be assembled. The first inspection is located at a first inspection station of the assembly line following a first device of the assembly line. The method further includes running the model using the scan data as an input to generate a final profile of the product. Additionally, the method includes comparing the final profile to one or more thresholds. Additionally, the method includes determining whether the final profile exceeds at least one of the one or more thresholds. If it is determined that the final profile exceeds at least one of the one or more thresholds, the method includes adjusting the first device.

[0011] There are various refinements of the features noted in relation to the above-mentioned aspects. Further features may be incorporated into the above-mentioned aspects as well. These refinements and additional features may exist individually or in any combination. For example, the various features described below in relation to any of the illustrated embodiments may be incorporated into any of the above-mentioned aspects alone or in any combination. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram of a system for processing semiconductor wafers in accordance with at least one embodiment of the present disclosure. [Diagram 2] 2 is a flowchart illustrating an example process for evaluating a wafer using the system shown in FIG. 1. [Diagram 3] 3 is a simplified block diagram of an exemplary system for evaluating a wafer according to the system shown in FIG. 1 and using the process shown in FIG. 2. [Figure 4] 4 illustrates an example configuration of the client computer device illustrated in FIG. 3 according to an embodiment of the present disclosure. [Diagram 5] 4 illustrates an example configuration of the server system illustrated in FIG. 3 according to an embodiment of the present disclosure. [Figure 6] 1 illustrates an example of a line scan process performed by a measurement device in accordance with at least one embodiment. [Figure 7A] 7 is an explanatory diagram further illustrating the exemplary line scan process shown in FIG. 6. [Figure 7B] 7 is an explanatory diagram further illustrating the exemplary line scan process shown in FIG. 6. [Figure 8A] FIG. 2 is a side view of a wafer according to one embodiment of the present disclosure. [Figure 8B] FIG. 2 is a side view of a wafer according to one embodiment of the present disclosure. [Figure 9] FIG. 2 is a top view of a wafer illustrating scan lines obtained for the wafer in accordance with at least one embodiment of the present disclosure. [Figure 10]1 is an example of a graph comparing an average predicted post-polishing radial nanotopography profile to a post-nanotopography measured polishing profile, in accordance with at least one embodiment of the present disclosure. [Figure 11A] 1 is an exemplary graph comparing average predicted nanotopography and measured nanotopography profiles prior to implementing the present disclosure. [Figure 11B] 4 is an exemplary graph comparing average predicted nanotopography to measured nanotopography profiles using the system shown in FIGS. 1 and 3 and the process shown in FIG. 2. [Figure 12A] 1 is another exemplary graph comparing average predicted nanotopography and measured nanotopography profiles prior to implementing the present disclosure. [Figure 12B] 4 is another exemplary graph comparing average predicted nanotopography to measured nanotopography profiles using the system shown in FIGS. 1 and 3 and the process shown in FIG. 2. [Figure 13] 1 is an example of a topography map of the surface of a wafer showing the B ring region and the C mark region.

[0013] Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Embodiments described herein relate to systems and methods for analyzing wafer data, and more particularly, to analyzing a post-polishing surface of a wafer to predict a post-processing surface of the wafer. More particularly, a wafer surface analysis model is executed by a computing device to (1) determine a current state of the wafer, (2) predict a post-processing state of the wafer state based on the current state and the model, and (3) determine whether adjustments need to be made to the grinder based on the post-processing state of the wafer and one or more predefined thresholds. The systems and methods described herein allow for feedback of nanotopography in less time, allowing adjustments that can be made to improve nanotopography to be recognized and implemented with less lag time to improve quality control and / or wafer yield.

[0015] This specification describes computer systems, such as wafer surface analysis computer devices and related computer systems. As described herein, all such computer systems include a processor and a memory. However, any processor in a computer device referred to herein may also refer to one or more processors, where the processor is in one computer device or in multiple computer devices operating in parallel. Additionally, any memory in a computer device referred to herein may also refer to one or more memories, where the memory may be in one computer device or in multiple computer devices operating in parallel.

[0016] As used herein, a processor may include any programmable system, including systems that use microcontrollers, reduced instruction set circuits (RISC), application specific integrated circuits (ASIC), logic circuits, and any other circuitry or processor capable of performing the functions described herein. The above examples are illustrative only, and thus are not intended to limit in any way the definition and / or meaning of the term "processor."

[0017] As used herein, the term "database" may refer to either a body of data, a relational database management system (RDBMS), or both. As used herein, a database may include any collection of data including hierarchical databases, relational databases, flat file databases, object-relational databases, object-oriented databases, and any other structured collection of records or data stored in a computer system. These are exemplary and therefore are not intended to limit in any way the definition and / or meaning of the term database. Examples of RDBMS include, but are not limited to, Oracle® Database, MySQL, IBM® DB2, Microsoft® SQL Server, Sybase®, and PostgreSQL. However, any database that enables the systems and methods described herein may be used. (Oracle is a registered trademark of Oracle Corporation, Redwood Shores, California; IBM is a registered trademark of International Business Machines Corporation, Armonk, New York; Microsoft is a registered trademark of Microsoft Corporation, Redmond, Washington; and Sybase is a registered trademark of Sybase, Dublin, California.)

[0018] In another embodiment, a computer program is provided, the program being embodied on a computer readable medium. In an exemplary embodiment, the system runs on a single computer system without requiring connection to a server computer. In a further exemplary embodiment, the system runs in a Windows environment (Windows is a registered trademark of Microsoft Corporation, Redmond, Washington). In yet another embodiment, the system runs on a mainframe environment and a UNIX server environment (UNIX is a registered trademark of X / Open Company Limited, Berkshire, United Kingdom). In a further embodiment, the system runs on an iOS environment (iOS is a registered trademark of Cisco Systems, Inc., San Jose, CA). In yet another embodiment, the system runs on a Mac OS environment (Mac OS is a registered trademark of Apple Inc., Cupertino, CA). In yet a further embodiment, the system runs on an Android OS (Android is a registered trademark of Google, Inc., Mountain View, CA). In another embodiment, the system runs on the Linux® OS (Linux® is a registered trademark of Linus Torvalds, Boston, MA). The application is designed to be flexible enough to run in a variety of different environments without compromising its primary functionality. In some embodiments, the system includes multiple components distributed among multiple computing devices. One or more of the components are in the form of computer-executable instructions embodied in a computer-readable medium. The systems and processes are not limited to the specific embodiments described herein. Furthermore, each system component and each process can be implemented separately and independently of the other components and processes described herein.Additionally, each component and process can be used in combination with other assembly packages and processes.

[0019] As used herein, elements or steps described in the singular and preceded by the word "a" or "an" should be understood as not excluding a plurality of elements or steps, unless such exclusion is expressly stated. Furthermore, references to an "example embodiment" or "one embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the referenced features.

[0020] As used herein, the terms "software" and "firmware" are used interchangeably and include any computer program stored in memory, including RAM memory, ROM memory, EPROM memory, EEPROM memory, and non-volatile RAM (NVRAM) memory, for execution by a processor. The types of memory listed above are exemplary and thus are not limiting of the types of memory that may be used to store computer programs.

[0021] Furthermore, as used herein, the term "real-time" refers to at least one of the time of occurrence of relevant events, the time of measurement and collection of given data, the time of processing the data, and the time of the system's response to events and environments. In the embodiments described herein, these activities and events occur substantially instantaneously.

[0022] The systems and processes are not limited to the specific embodiments described herein. Furthermore, each system component and each process can be performed independent and separate from other components and processes described herein. Also, each component and each step can be used in combination with other assembly packages and steps.

[0023] 1 is a block diagram of a system 100 for processing semiconductor wafers in accordance with at least one embodiment of the present disclosure. For purposes of this disclosure, system 100 begins with a grinder 105 in the process of silicon wafer manufacturing. In an exemplary embodiment, grinder 105 is a double-sided grinder as described above. In other embodiments, grinder 105 may only be a single-sided grinder.

[0024] After polishing the wafer with the grinder 105, the wafer is analyzed by measuring data with the measurement device 110 to generate a profile of the polished wafer. At this point, the wafer is unetched and unpolished. The measurement device 110 provides measurement data from the polished wafer to a wafer surface analysis (WSA) computing device 115. In some embodiments, the measurement device 110 uses a capacitance probe or a laser-based distance sensor to measure the wafer. Examples of how the measurement device 110 analyzes the wafer can be found below in the description of Figures 6-9. The WSA computing device 115 analyzes the measurement data of the wafer and determines a profile of the wafer after polishing. If the determined profile exceeds any quality threshold, the WSA computing device 115 can determine that the grinder 105 needs to be adjusted.

[0025] In some other embodiments, system 100 includes multiple grinders 105, each grinder 105 polishing a wafer, but each wafer may only be polished once. In these embodiments, WSA computing device 115 tracks the polishing results of each of the multiple grinders 105.

[0026] In the illustrated embodiment, system 100 includes multiple post-polishing apparatus such as, but not limited to, an etching apparatus 120 for etching the polished wafer, a surface metrology apparatus 125 for measuring the flatness of the surface of the etched wafer, a polishing apparatus 130 for polishing the etched wafer, and a nanotopography measurement apparatus 135 for the polished wafer. In other embodiments, other devices may be included in system 100.

[0027] In an exemplary embodiment, WSA computing device 115 includes a model of the devices in system 100, which simulates etching and polishing of a wafer based on measurements of the polished wafer to predict a post-polishing surface of the wafer, which is similar to the surface measured by nanotopography measurement device 135. In an exemplary embodiment, WSA computing device 115 generates the model based on a plurality of historical data for a plurality of wafers produced. The historical data is based on a comparison of the wafers on measurement device 110 (post-polishing) and nanotopography measurement device 135 (post-polishing).

[0028] In an exemplary embodiment, WSA computing device 115 creates a model for each system 100 that it analyzes. For example, a fab may have multiple production lines for manufacturing wafers. For each production line, WSA computing device 115 generates a separate model. In some embodiments, if multiple grinders 105 use the same post-grinding process, WSA computing device 115 may use the same model.

[0029] 2 is a flow chart illustrating an exemplary process 200 for evaluating a wafer using system 100 (shown in FIG. 1). In an exemplary embodiment, the steps of process 200 are performed by WSA computing device 115 (shown in FIG. 1).

[0030] In an exemplary embodiment, a grinder 105 polishes 205 a wafer. This may be a double sided grinder 105 as described above, or any other grinder configured to operate the system 100 described herein. A measurement device 110 (shown in FIG. 1 ) measures the polished wafer 210 and transmits the current post-polishing measurements to a WSA computing device 115. The WSA computing device 115 uses the current post-polishing measurements as input to execute a model 215 of the system 100. In an exemplary embodiment, the post-polishing measurements are the nanotopography of the wafer as measured by the measurement device 110. The WSA computing device 115 uses the execution of the model to generate a predicted wafer profile 220 of the wafer. The predicted wafer profile predicts the nanotopography of the wafer after polishing, as measured by a nanotopography measurement device 135 (shown in FIG. 1 ).

[0031] The WSA computing device 115 compares the predicted wafer profile to one or more predetermined thresholds. In an exemplary embodiment, the predetermined thresholds are requirements for a suitable surface for wafer post-polishing. In an exemplary embodiment, some of the predetermined thresholds and / or requirements are based on one or more user preferences from the wafer manufacturer and / or the customer purchasing the wafer.

[0032] If the wafer is within tolerance 230, not exceeding a predetermined threshold, the system 100 proceeds to step 205 to polish the next wafer. If the wafer is not within tolerance 230, the WSA computing device 115 adjusts 235 the grinder 105. In some embodiments, the WSA computing device 115 adjusts 235 the grinder 105 directly. In other embodiments, the WSA computing device 115 directs another device to adjust 235 the grinder 105. In yet further embodiments, the WSA computing device 115 directs a user to adjust 235 the grinder 105.

[0033] In some embodiments, the WSA computing device 115 determines that the wafer is within tolerance 230, but also determines that the grinder 105 is no longer properly adjusted. In these embodiments, the WSA computing device 115 may determine that the grinder 105 is falling out of proper adjustment based on a current trend of post-polish inspection of multiple wafers. The WSA computing device 115 may recognize the trend and determine that the grinder will need to be adjusted after a certain number of uses or after a certain period of time. In these embodiments, the WSA computing device 115 may determine when the next planned downtime period is for the system 100. If the planned downtime period is before the grinder is expected to fall out of proper adjustment, the WSA computing device 115 may schedule the grinder adjustment to occur during the planned downtime period. The WSA computing device 115 may determine when the grinder 105 is expected to produce an out-of-tolerance wafer based on one or more predefined thresholds, the amount of change in the post-polish results for each wafer, and the model.

[0034] In an exemplary embodiment, the WSA computing device 115 generates the model based on a plurality of historical data including past post-polish measurements from the measurement device 110 and past post-polish measurements from the nanotopography measurement device 135. In an exemplary embodiment, the WSA computing device 115 generates the model by comparing the post-polish measurements and the post-polish measurements of the wafer to determine how the system 100 will change as the wafer is processed. In some embodiments, the WSA computing device 115 stores a generic model for a particular production line (system 100) that is trained using historical inspection data from that production line. In other embodiments, the WSA computing device 115 generates the model entirely from the historical data of that production line. In some further embodiments, the model is continually updated as production continues based on the measurement data of the nanotopography measurement device 135 of the production line. This allows the model to most accurately model the current production line (system 100). In other embodiments, the model is updated or calibrated only every six months or other predetermined period of time. This embodiment is best suited when other equipment in the system 100 does not change regularly or require recalibration. In some embodiments, the model is updated and calibrated for the current state of the production line whenever equipment is replaced, calibrated, or otherwise modified.

[0035] Although the above system 100 and process 200 are described in terms of a semiconductor wafer manufacturing assembly line, one skilled in the art will appreciate that the present disclosure may be used in conjunction with other assembly lines. In these other embodiments, the system 100 would be considered an assembly line 100 for making a product. The assembly line includes a first device 105, a first inspection station 110, a computer device 115, a second device 130, and a second inspection station 135.

[0036] In these embodiments, the computing device 115 stores in at least one memory device a model for simulating a portion of the assembly line 100. The computing device 115 receives 210 scan data of a first inspection of a product being assembled. The first inspection is located at a first inspection station 110 of the assembly line 100, following a first device 105 of the assembly line 100. The computing device 115 runs 215 the model using the scan data as input to generate a final profile of the product.

[0037] The computing device 115 compares 225 the final profile to one or more thresholds. The computing device 115 determines 230 whether the final profile exceeds at least one of the one or more thresholds. If a determination is made that the final profile exceeds at least one of the one or more thresholds, the computing device 115 causes 235 the first device 105 to be adjusted.

[0038] In some further embodiments, the computing device 115 generates a model for simulating a portion of the assembly line 100 based on the plurality of inspection data of the assembly line 100. The model generates a final profile of the product, which simulates an actual profile of the product when it reaches the second inspection station 135. In some further embodiments, the second inspection station 135 is positioned following completion of the assembly line 100. In some embodiments, the plurality of inspection data includes a first plurality of scan data of the plurality of individual products at the first inspection station 110 and a second plurality of scan data of the plurality of individual products at the second inspection station 135. In some still further embodiments, the computing device 115 receives scan data of a second inspection of the product being assembled at the second inspection station 135. The computing device 115 compares the scan data of the second inspection to the final profile. The computing device adjusts the model based on the comparison.

[0039] In some embodiments, the computing device 115 generates one or more adjustments to the first device 105 based on a comparison of the final profile to one or more thresholds and the model. The computing device 115 transmits the one or more adjustments to at least one of the user and the first device 105.

[0040] In some embodiments, if the determination is that the final profile exceeds at least one of the one or more thresholds, the computing device 115 analyzes the multiple pre-tests to determine a trend. The computing device 115 predicts whether a subsequent test of the product is likely to exceed at least one of the one or more thresholds based on the trend. The computing device 115 adjusts the first device 105 based on the trend.

[0041] 3 is a simplified block diagram of an exemplary system 300 for evaluating a wafer using process 200 (shown in FIG. 2) in accordance with system 100 (shown in FIG. 1). In an exemplary embodiment, system 300 is used to analyze a polished wafer to determine whether the wafer falls within an acceptable range after polishing. Additionally, system 300 is a real-time data analysis and classification computer system that includes a wafer surface analysis (WSA) computing device 310 (also known as a WSA server) configured to analyze the wafer and predict future conditions based on the analysis.

[0042] In an exemplary embodiment, the measurement device 305 is configured to scan the surface of the wafer to generate a profile of the wafer. More specifically, the measurement device 305 scans the nanotopography of the wafer and communicates with the WSA computing device 310. The measurement device 305 is connected to the WSA computing device 310 via a variety of wired or wireless interfaces, including, but not limited to, a network such as a local area network (LAN) or wide area network (WAN), a dial-in connection, a cable modem, an Internet connection, wireless, and a special high-speed integrated services digital network (ISDN) line. The measurement device 305 receives data about the surface of the wafer and reports the data to the WSA computing device 310. In other embodiments, the measurement device 305 communicates with one or more client systems 325, which send the measurement data to the WSA computing device 310 in real time or near real time. In some embodiments, a first measurement device 305 measures one side of the wafer and a second measurement device 305 measures the other side of the wafer. In the exemplary embodiment, measurement device 305 is similar to measurement device 110 (shown in FIG. 1) and nanotopography measurement device 135 (shown in FIG. 1).

[0043] As described in more detail above, WSA server 310 is programmed to analyze the wafer and predict the nanotopography of the wafer surface after polishing so that system 300 can rapidly respond to changes that cause the wafer to be out of tolerance. WSA server 310 is programmed to (1) determine a current state of the wafer, (2) predict a post-processing state of the wafer state based on the current state and a model, and (3) determine whether adjustments need to be made to the grinder based on the post-processing state of the wafer and one or more predefined thresholds. In an exemplary embodiment, WSA server 310 is similar to wafer surface analysis computing device 115 (shown in FIG. 1).

[0044] In an exemplary embodiment, client system 325 is a computer that includes a web browser or software application that allows client system 325 to communicate with WSA server 310 using the Internet, a local area network (LAN), or a wide area network (WAN). In some embodiments, client system 325 is communicatively coupled to the Internet through a number of interfaces, including, but not limited to, at least one of the following: the Internet, a LAN, a WAN, or a network such as an integrated services digital network (ISDN), a dial-up connection, a digital subscriber line (DSL), a cellular connection, a satellite connection, and a cable modem. Client system 325 can be any device that can access a network, such as the Internet, including, but not limited to, a desktop computer, a laptop computer, a personal digital assistant (PDA), a cellular phone, a smartphone, a tablet, a phablet, or other web-based connectable device.

[0045] Database server 315 is communicatively coupled to database 320, which stores data. In one embodiment, database 320 is a database including historical data and models. In some embodiments, database 320 is stored remotely from WSA server 310. In some embodiments, database 320 is distributed. In an exemplary embodiment, a person can access database 320 via client system 325 by logging on to WSA server 310.

[0046] FIG. 4 illustrates an example configuration of a client system 325 (shown in FIG. 3) according to one embodiment of the disclosure. A user computing device 402 is operated by a user 401. The user computing device 402 may include, but is not limited to, a measurement device 110, a wafer surface analysis computing device 115, a nanotopography measurement device 135 (all shown in FIG. 1), a measurement device 305, a WSA computing device 310, and a client system 325 (all shown in FIG. 3). The user computing device 402 includes a processor 405 for executing instructions. In some embodiments, executable instructions are stored in a memory area 410. The processor 405 may include one or more processing units (e.g., in a multi-core configuration). The memory area 410 is any device that allows for the storage and retrieval of information, such as executable instructions and / or transaction data. The memory area 410 may include one or more computer-readable media.

[0047] The user computing device 402 also includes at least one media output component 415 for presenting information to the user 401. The media output component 415 is any component capable of communicating information to the user 401. In some embodiments, the media output component 415 includes an output adapter (not shown), such as a video adapter and / or an audio adapter. The output adapter is operably coupled to the processor 405 and operably coupled to an output device, such as a display device (e.g., a cathode ray tube (CRT), a liquid crystal display (LCD), a light emitting diode (LED) display, or an "electronic ink" display) or an audio output device (e.g., a speaker or headphones). In some embodiments, the media output component 415 is configured to present a graphical user interface (e.g., a web browser and / or a client application) to the user 401. The graphical user interface may include, for example, an interface for displaying analysis results of one or more wafers. In some embodiments, the user computing device 402 includes an input device 420 for receiving input from the user 401. The user 401 can select a wafer for which to view the analysis using, but not limited to, an input device 420. The input device 420 may include, for example, a keyboard, a pointing device, a mouse, a stylus, a touch-sensitive panel (e.g., a touchpad or touch screen), a gyroscope, an accelerometer, a position detector, a biometric input device, and / or a voice input device. A single component, such as a touch screen, may function as both an output device for the media output component 415 and as an input device 420.

[0048] User computing device 402 may also include a communications interface 425 that is communicatively coupled to a remote device, such as WSA server 310 (shown in FIG. 3 ). Communications interface 425 may include, for example, a wired or wireless network adapter and / or a wireless data transceiver for use in a mobile communications network.

[0049] Stored in memory area 410 are computer readable instructions for, for example, providing a user interface to user 401 via media output component 415 and, optionally, receiving and processing input from input device 420. The user interface may include a web browser and / or a client application, among other possibilities. The web browser allows a user, such as user 401, to view and interact with media and other information typically embedded in web pages or websites from WSA server 310. The client application allows user 401 to interact with, for example, WSA server 310. For example, the instructions may be stored by a cloud service and output of the execution of the instructions transmitted to media output component 415.

[0050] Processor 405 executes computer-executable instructions for implementing aspects of the present disclosure. In some embodiments, processor 405 is transformed into a special purpose microprocessor by executing computer-executable instructions or being otherwise programmed.

[0051] 5 is a diagram illustrating an example configuration of server system 310 shown in FIG. 3 according to one embodiment of the present disclosure. Server computing device 501 may include, but is not limited to, WSA computing device 115 (shown in FIG. 1), database server 315, and WSA server 310 (all shown in FIG. 3). Server computing device 501 also includes a processor 505 for executing instructions. The instructions may be stored in memory area 510. Processor 505 may include one or more processing units (e.g., a multi-core configuration).

[0052] The processor 505 is operatively coupled to a communications interface 515 such that the server computing device 501 can communicate with remote devices, such as other server computing devices 501, other WSA servers 310, or client systems 325 (shown in FIG. 3). For example, the communications interface 515 can receive requests from client systems 325 over the Internet, as shown in FIG.

[0053] The processor 505 may also be operatively coupled to a storage device 534. The storage device 534 is any computer-operated hardware suitable for storing and / or retrieving data, such as, but not limited to, data associated with the database 320 (shown in FIG. 3). In some embodiments, the storage device 534 is integrated into the server computing device 501. For example, the server computing device 501 may include one or more hard disk drives as the storage device 534. In other embodiments, the storage device 534 is external to the server computing device 501 and may be accessed by multiple server computing devices 501. For example, the storage device 534 may include multiple storage units, such as hard disks and / or solid state disks in a storage area network (SAN), a network attached storage (NAS) system, and / or a redundant array of inexpensive disks (RAID) configuration.

[0054] In some embodiments, the processor 705 is operatively coupled to the storage device 534 via a storage interface 520. The storage interface 520 is any component capable of providing the processor 505 with access to the storage device 534. The storage interface 520 may include, for example, an Advanced Technology Attachment (ATA) adapter, a Serial ATA (SATA) adapter, a Small Computer System Interface (SCSI) adapter, a RAID controller, a SAN adapter, a network adapter, and / or any component that provides the processor 505 with access to the storage device 534.

[0055] The processor 505 executes computer-executable instructions for implementing aspects of the present disclosure. In some embodiments, the processor 505 is transformed into a special purpose microprocessor by executing computer-executable instructions or being otherwise programmed. For example, the processor 505 is programmed with instructions such as those illustrated in FIG. 2.

[0056] 6 illustrates an exemplary line scanning process 600 performed by measurement device 305 (shown in FIG. 3) in accordance with at least one embodiment. In an exemplary embodiment, process 600 is performed by measurement device 115 and nanotopography measurement device 135 as part of system 100 (all shown in FIG. 1) and process 200 (shown in FIG. 2).

[0057] According to the line scan process 600, the wafer W is supported by one or more support pins 603 in contact with the first surface 605 of the wafer. The shape of the supported wafer 609 deflects as a function of gravity and the mass of the wafer W, as shown by a comparison of the shape of the wafer in the absence of gravity (indicated by reference numeral 607) to the shape of the wafer in the supported state (indicated by reference numeral 609). The measurement device 305 measures a plurality of distances (e.g., "distance B") between the first sensor 621A and the first surface 605 (e.g., front surface) along a diameter of the supported wafer 609. Similarly, the measurement device 305 includes a second capacitive sensor 621B for measuring a plurality of distances (e.g., "distance F") between the second sensor 621B and the second surface 605B (e.g., back surface) along a diameter of the supported wafer 609. The obtained data includes a line scan data set corresponding to the diameter. The line scan data set is comprised of a number of distances measured by a first sensor 621A along a diameter of the supported wafer 609 and a number of distances measured by a second sensor 621B along a diameter of the supported wafer 609. The line scan data set is indicative of the wafer profile along the diameter.

[0058] 7A and 7B are diagrams further illustrating an exemplary line scan process 600 (shown in FIG. 6). FIGS. 7A and 7B are diagrams illustrating the line scan process 600 performed by the measurement device 305 to obtain multiple line scan data sets, each of which represents a wafer profile along a particular diameter. As shown in FIG. 7A, a first line scan (indicated by arrow 701) is performed along a first diameter of the wafer. In particular, the first sensor 621A moves in a plane above the first surface 605A in a first direction along the first diameter of the wafer. The first sensor 621A measures the distance between the first sensor 621A and the first surface 605A of the wafer at a predetermined interval (i.e., pitch R, measurement frequency). The predetermined interval is illustrated in FIG. 7A as a mark on the surface of the wafer W. For example, the first sensor 621A may measure the distance at 1 mm or 2 mm intervals along the first diameter of the wafer. The second sensor 621B similarly moves in a first direction in a plane below the second surface 605B to measure the distance between the second sensor 621B and the second surface 605B along a first diameter of the wafer. The first diameter of the wafer may be defined as a function of a reference point. For example, in the illustrated process, the first diameter passes through a notch N located at the periphery of the wafer.

[0059] As shown by FIG. 7B, after completing the first line scan 701, the wafer W rotates (indicated by arrow 709). In particular, the rotation stage 705, which is disposed below the support pins 603, is raised to lift the wafer W to a position (indicated by reference number 707) above the support pins 603. While supporting the wafer at the raised position 707, the rotation stage rotates. As a result, the wafer rotates a number of degrees (θ). The rotation stage 705 is lowered to reposition the rotated wafer on the support pins 603. The position of the support pins 603 relative to the second side of the wafer is shown by hidden lines in FIGS. 7A and 7B. In turn, a line scan (indicated by arrow 715) along the second diameter of the wafer is performed. According to the illustrated process, the first sensor 621A and the second sensor 621B move in a second direction (e.g., opposite to the first direction) along the second diameter of the wafer in a plane corresponding to the first surface 605A and the second surface 605B, respectively. As described above in connection with the first line scan 701, the first and second sensors 621A, 621B measure the distance between the sensors 621A, 621B and the first and second surfaces 605A, 605B of the wafer, respectively, at predetermined intervals along the second diameter of the wafer. The rotation 709 and line scan motions 701, 705 are repeated to obtain each of the multiple line scan data sets.

[0060] In one embodiment, the measurement device 305 uses a self-mass compensation algorithm to determine the shape of the wafer relative to the absence of gravity 607. The self-mass compensation determines the shape of the wafer as a function of the line scan data set, the wafer density, the elastic constant, the diameter of the wafer, and the position of the support pins 603. In one embodiment, the measurement device 305 measures one or more wafer parameters based on the shape of the wafer. The wafer parameters may include one or more of warp, bow, TTV (total thickness variation), and / or GBIR (global backside ideal range). With reference to FIG. 8A, the warp and bow are generally determined with respect to a reference plane. The reference plane is defined as a function of the contact point between the support pins 603 and the surface of the wafer 605a. Specifically, the bow is defined as the absolute value of the difference between the maximum and minimum deviations of the central region from the reference plane. The central region is the locus of points that are equidistant from the surface 605B of the wafer and the backside 605A of the wafer. The bow is defined as the deviation from the reference plane at the center of the wafer. 8B, the GBIR and TTV reflect the linear thickness variation of the wafer and can be calculated based on the difference between the maximum and minimum distances from the backside of the wafer to the reference surface. For example, the measurement device 305 can obtain four line scan data sets, as illustrated by FIG. 9. Each line scan data set represents a radial profile of the wafer.

[0061] Referring again to the system 100 shown in FIG. 1, data obtained by the measurement devices 110, 135 for measuring the nanotopography of the wafer polished by the grinder 105 is transmitted to the WSA computing device 115. For example, the line scan data set and / or the determined wafer shape may be transmitted to the WSA computing device 115. The WSA computing device 115 receives the scan data and executes computer-executable instructions for performing a number of operations for processing the received scan data as described herein. In particular, the WSA computing device 115 predicts the post-polishing nanotopography of the wafer based on the received scan data. In some embodiments, the WSA computing device 115 determines polishing parameters based on the predicted nanotopography of the wafer. The operation of the grinder 105 is adjusted accordingly.

[0062] In one embodiment, the WSA computing device 115 accesses a feedback program for processing the received scan data. The received scan data may include a line scan data set and / or a determined wafer shape of the polished wafer. In particular, the WSA computing device 115 predicts a nanotopography of the polished wafer based on the received bow data. When the measurement device 110 measures the wafer, the wafer has not yet been polished, so the nanotopography of the wafer is predicted, rather than actually measured. The WSA computing device 115 determines one or more polishing parameters based on the predicted nanotopography of the wafer. In one embodiment, the WSA computing device 115 determines a shift parameter. The shift parameter is indicative of a magnitude and direction for moving the pair of polishing wheels to reduce nanotopography degradation caused by misalignment of the polishing wheels. In another embodiment, the WSA computing device 115 additionally or alternatively determines a tilt parameter. The tilt parameter is indicative of an angle for positioning the pair of polishing wheels with respect to the wafer to reduce nanotopography degradation caused by misalignment of the polishing wheels.

[0063] The operation of the grinder 105 is adjusted based on the determined grinding parameters. For example, the grinding wheel may be adjusted as defined by the determined shift and / or tilt parameters. In one embodiment, the grinding wheel is adjusted as a function of the determined shift and / or tilt parameters and a predefined compensation amount. In one embodiment, the grinder 105 is configured to receive the determined grinding parameters and adjust one or more components of the grinder 105 as a function of the determined grinding parameters. In another embodiment, the determined grinding parameters are provided to an operator, who configures the grinder 105 to adjust one or more components of the grinder 105 as a function of the determined grinding parameters.

[0064] FIG. 10 is an example graph comparing an average predicted post-polishing radial nanotopography profile with a nanotopography measured post-polishing profile in accordance with at least one embodiment of the present disclosure.

[0065] FIG. 11A is an exemplary graph comparing average predicted nanotopography and measured nanotopography for detecting the B ring prior to implementation of the present disclosure. FIG. 11B is an exemplary graph comparing average predicted nanotopography and measured nanotopography for detecting the B ring using the systems 100, 300 (shown in FIG. 1 and FIG. 3, respectively) and the process 200 (shown in FIG. 2). FIG. 11B shows improved correlation between predicted and actual results using the system 100 and process 200 described herein. Furthermore, a comparison of FIG. 11A and FIG. 11B shows an increase in correlation from 0.4032 to 0.7323, with 1.0 indicating perfect correlation.

[0066] FIG. 12A is another exemplary graph comparing the average predicted nanotopography and the measured nanotopography for detecting the B ring before implementing the present disclosure. FIG. 12B is another exemplary graph comparing the average predicted nanotopography and the measured nanotopography for detecting the B ring using the system 100, 300 (shown in FIG. 1 and FIG. 3, respectively) and the process 200 (shown in FIG. 2). FIG. 12B shows an improved correlation between the predicted and the actual results using the system 100, the process 200 described herein. Furthermore, a comparison of FIG. 12A and FIG. 12B shows that the correlation has increased from 0.445 to 0.7079, with 1.0 indicating perfect correlation. FIG. 11A and FIG. 11B relate to the first data set, and FIG. 12A and FIG. 12B relate to the second data set.

[0067] FIG. 13 is an example topography map of the surface of a wafer showing the B ring region and the C mark region.

[0068] At least one of the technical solutions provided by the system to address the technical problems may include: (i) improved analysis of the wafer surface, (ii) reduced material loss due to malfunction or improper alignment, (iii) increased speed in wafer analysis, (iv) increased accuracy in wafer analysis, (v) reduced unnecessary adjustments to the grinder, (vi) reduced false positives and false negatives, and (vii) updated analysis calibrated to individual production lines.

[0069] The computer-implemented methods discussed herein may include additional, fewer, or alternative actions, including those discussed elsewhere. The methods may be implemented via one or more local or remote processors, transceivers, servers, and / or sensors (such as processors, transceivers, servers, and / or sensors mounted on a vehicle or mobile device or associated with a smart infrastructure or a remote server) and / or via computer-executable instructions stored on a fixed computer-readable medium or media.

[0070] Additionally, the computer systems discussed herein may include additional, less, or alternative functionality, including that discussed elsewhere. The computer systems discussed herein may include or be executed via computer-executable instructions stored on a non-transitory computer-readable medium or media.

[0071] The processor or processing element may be trained using supervised or unsupervised machine learning, and the machine learning program may employ a neural network, which may be a convolutional neural network, a deep learning neural network, a reinforcement or reinforcement learning module or program, or a composite learning module or program that learns in two or more domains or areas of interest. Machine learning may involve identifying and recognizing patterns in existing data to facilitate prediction of subsequent data. Models may be created based on example inputs to make valid and reliable predictions for new inputs.

[0072] Additionally or alternatively, the machine learning program may be trained by inputting sample data sets or specific data into the program, such as images, object statistics and information, historical estimates, and / or actual repair costs. The machine learning program may utilize deep learning algorithms that may focus primarily on pattern recognition and may be trained after processing multiple examples. The machine learning program may include Bayesian program learning (BPL), speech recognition and synthesis, image or object recognition, optical character recognition, and / or natural language processing, either individually or in combination. The machine learning program may also include natural language processing, semantic analysis, automated reasoning, and / or machine learning.

[0073] Supervised and unsupervised machine learning techniques may be used. In supervised machine learning, a processing element may be provided with example inputs and their associated outputs and may seek to discover general rules that map inputs to outputs, such that when a subsequent new input is provided, the processing element may accurately predict the correct output based on the discovered rules. In unsupervised machine learning, a processing element may be required to find its own structure in unlabeled example inputs. In one embodiment, machine learning techniques may be used to extract data about the wafer surface nanotopography to predict future states.

[0074] Based on these analyses, the processing element may learn how to identify characteristics and patterns that can then be applied to analyses of image data, model data, and / or other data. For example, the processing element may learn how to identify trends that precede a grinder going out of alignment based on a comparison of post-grinding measurements to post-polishing measurements. The processing element may also learn how to identify trends that are not readily apparent based on collected scan data, such as trends that precede a grinder going out of alignment.

[0075] The methods and systems described herein may be implemented using computer programming or engineering techniques, including computer software, firmware, hardware, or any combination or subset. As disclosed above, at least one technical problem of the prior systems is the need for a system for a cost-effective and reliable method of analyzing data to predict nanotopography. The systems and methods described herein address that technical problem. Furthermore, at least one technical solution provided by the system to overcome the technical problem may include: (i) improved analysis of the wafer surface; (ii) reduced loss of material due to malfunction or improper alignment; (iii) increased speed in wafer analysis; (iv) increased accuracy in wafer analysis; and (v) updated analysis calibrated to individual production lines.

[0076] The described methods and systems may be implemented using computer programming or engineering techniques, including computer software, firmware, hardware, or any combination or subset thereof, and the technical effects may be achieved by performing at least one of the following steps:The method includes the steps of: a) storing in at least one memory device a model for simulating a portion of an assembly line; b) receiving scan data of a first inspection of a product being assembled, the first inspection being positioned at a first inspection station of the assembly line following a first device of the assembly line; c) running the model with the scan data as input to generate a final profile of the product; d) comparing the final profile to one or more thresholds; e) determining whether the final profile exceeds at least one of the one or more thresholds; f) adjusting the first device if the determination is that the final profile exceeds at least one of the one or more thresholds; g) generating a model for simulating a portion of an assembly line based on the plurality of inspection data of the assembly line, the assembly line including a second inspection station following a second device of the assembly line, the model generating a final profile of the product that simulates an actual profile of the product when it reaches the second inspection station, is disposed following completion of an assembly line, the plurality of inspection data including a first plurality of scan data of a plurality of individual products at a first inspection station and a second plurality of scan data of a plurality of individual products at a second inspection station; h) receiving scan data of a second inspection of the product being assembled at the second inspection station; i) comparing the scan data of the second inspection to the final profile; j) adjusting the model based on the comparison; k) generating one or more adjustments to the first device based on a comparison of the final profile to the one or more thresholds and the model; l) communicating the one or more adjustments to at least one of a user and the first device; m) if the final profile is determined to exceed at least one of the one or more thresholds, performing at least one of the following steps i)-iii): i) analyzing the plurality of prior inspections to determine a trend; ii) predicting based on the trend whether a subsequent inspection of a subsequent product is likely to exceed at least one of the one or more thresholds; and iii) adjusting the first device based on the trend.

[0077] The methods may be implemented via one or more local or remote processors, transceivers, servers, and / or sensors (such as processors, transceivers, servers, and / or sensors mounted on a vehicle or mobile device or associated with a smart infrastructure or remote servers) and / or via computer-executable instructions stored on a non-transitory computer-readable medium or media. Additionally, the computer systems discussed herein may include additional, less, or alternative functionality, including that discussed elsewhere. The computer systems discussed herein may include or be implemented via computer-executable instructions stored on a non-transitory computer-readable medium or media.

[0078] As used herein, the term "fixed computer-readable medium" is intended to be representative of any tangible computer-based device implemented with a method or technology for short-term and long-term storage of information, such as, for example, computer-readable instructions, data structures, program modules and sub-modules, or other data in any device. Thus, the methods described herein may be encoded as executable instructions embodied in a tangible, fixed, computer-readable medium, including, but not limited to, storage and / or memory devices. Such instructions, when executed by a processor, cause the processor to perform at least a portion of the methods described herein. Furthermore, as used herein, the term "fixed computer-readable medium" includes all tangible computer-readable media, including fixed computer storage, including, but not limited to, volatile and non-volatile media, as well as firmware, physical and virtual storage, CD-ROMs, DVDs, and any other digital source, such as a network or the Internet, and digital means yet to be developed, with the only exception being a transitory propagating signal.

[0079] This written description uses examples to disclose various implementations, including the best mode, and is intended to enable any person skilled in the art to practice the various implementations, including making and using any device or system, and performing any incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have elements that do not differ from the literal language of the claims, or if they include equivalent elements that do not differ substantially from the literal language of the claims.

[0080] When introducing elements of the disclosure or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the element. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. The use of specific orientation terms (e.g., "top," "bottom," "side," etc.) is for convenience of description and does not require a particular orientation of the items being described.

[0081] Because various changes may be made in the structures and methods described above without departing from the scope of the present disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawings be interpreted as illustrative and not in a limiting sense.

Claims

1. 1. A computing apparatus including at least one processor in communication with at least one memory device, the at least one processor comprising: storing in at least one memory device a model for simulating a portion of an assembly line; receiving scan data of a first inspection of a product being assembled, the first inspection being located at a first inspection station on the assembly line following a first device on the assembly line; running the model using the scan data as input to generate a final profile of the product; comparing the final profile to one or more thresholds; determining whether the final profile exceeds at least one of the one or more thresholds; and adjusting the first device if a determination is made that the final profile exceeds at least one of the one or more thresholds; It is programmed to If a determination is made that the final profile exceeds at least one of the one or more thresholds, the at least one processor further comprises: analyzing the plurality of preliminary tests to determine a trend; predicting, based on the trend, whether a subsequent inspection of a subsequent product is likely to exceed at least one of the one or more thresholds; and adjusting the first device based on the trend; A computer device programmed to perform the steps of:

2. 10. The computer apparatus of claim 1, wherein the at least one processor is further programmed to generate a model for simulating a portion of an assembly line based on the plurality of inspection data of the assembly line.

3. 3. The computer apparatus of claim 2, wherein the assembly line includes a second inspection station following the second device on the assembly line, and the model simulates an actual profile of the product upon reaching the second inspection station to generate a final profile of the product.

4. 4. The computer system of claim 3, wherein the second inspection station is located following completion of the assembly line.

5. 4. The computer system of claim 3, wherein the plurality of inspection data includes a first plurality of scan data of the plurality of individual products at a first inspection station and a second plurality of scan data of the plurality of individual products at a second inspection station.

6. The at least one processor further comprises: receiving scan data of a second inspection of the product being assembled at a second inspection station; comparing the scan data of the second exam to the final profile; and adjusting the model based on the comparison; 6. A computer apparatus according to claim 5 programmed to:

7. 2. The computer system of claim 1, wherein the article is a semiconductor wafer.

8. The computer apparatus of claim 7 , wherein the first device is a grinder and the first inspection station includes a nanotopography measurement device.

9. The at least one processor further comprises: generating one or more adjustments to the first device based on a comparison of the final profile to one or more thresholds and models; and transmitting the one or more adjustments to at least one of the user and the first device; 2. A computer apparatus according to claim 1 programmed to:

10. 1. A method for analyzing an assembly line, the method being implemented by a computer apparatus including at least one processor in communication with at least one memory device, the method comprising: storing in at least one memory device a model for simulating a portion of an assembly line; receiving scan data of a first inspection of a product being assembled, the first inspection being located at a first inspection station on the assembly line following a first device on the assembly line; running the model using the scan data as input to generate a final profile of the product; comparing the final profile to one or more thresholds; determining whether the final profile exceeds at least one of the one or more thresholds; adjusting the first device if the determination is that the final profile exceeds at least one of the one or more thresholds; Including, If the determination is that the final profile exceeds at least one of the one or more thresholds, analyzing a plurality of prior tests to determine a trend; predicting, based on the trend, whether a subsequent test of a subsequent product is likely to exceed at least one of the one or more thresholds; and adjusting the first device based on the trend; The method includes:

11. 11. The method of claim 10, further comprising generating a model for simulating a portion of the assembly line based on the plurality of inspection data of the assembly line.

12. 12. The method of claim 11, wherein the assembly line includes a second inspection station following the second device on the assembly line, and the model generates a final profile of the product that simulates an actual profile of the product upon reaching the second inspection station.

13. 13. The method of claim 12, wherein the second inspection station is located following completion of the assembly line.

14. 13. The method of claim 12, wherein the plurality of inspection data includes a first plurality of scan data of the plurality of individual products at a first inspection station and a second plurality of scan data of the plurality of individual products at a second inspection station.

15. receiving scan data of a second inspection of the product being assembled at a second inspection station; comparing the scan data of the second exam to the final profile; and adjusting the model based on the comparison; The method of claim 14 further comprising:

16. The method of claim 10, wherein the article is a semiconductor wafer.

17. The method of claim 16 , wherein the first device is a grinder and the first inspection station includes a nanotopography measurement instrument.

18. generating one or more adjustments to the first device based on a comparison of the final profile to one or more thresholds and models; and transmitting the one or more adjustments to at least one of the user and the first device; The method of claim 10 further comprising:

Images