Junction memory device and method for fabricating same - Patents.com

Abstract

To disclose embodiments of a three dimensional (3D) memory device formed by a bonded semi-conductor device and a method for forming the three dimensional (3D) memory device.SOLUTION: In one example, a method for forming a bonded semi-conductor device includes the following operations. First, a first wafer and a second wafer are formed. The first wafer may comprise a functional layer over a substrate. Single crystal silicon may not be essential to the substrate, and the substrate may not include single crystal silicon. The first wafer may be inverted to bond to the second wafer to form a bonded semiconductor device, such that the substrate is above the functional layer. At least a portion of the substrate may be removed to form a top surface of the bonded semiconductor device. Further, bond pads may be formed over the top surface.SELECTED DRAWING: Figure 2D

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to junction three-dimensional (3D) memory devices and methods for fabricating the same. [Background technology]

[0002] Planar memory cells are scaled to smaller dimensions through improvements in process technology, circuit design, program algorithms, and fabrication processes. However, as memory cell geometries approach lower limits, planar processes and fabrication techniques become more difficult and costly. As a result, storage density for planar memory cells approaches an upper limit.

[0003] 3D memory structures can address the density limitations of planar memory cells and include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention [Means for solving the problem]

[0004] SUMMARY OF THE DISCLOSURE Disclosed herein are embodiments of methods and structures for forming a wafer, and methods and structures for forming a bonded semiconductor structure with a wafer.

[0005] In one example, a method for forming a bonded semiconductor device is disclosed. The method includes the following acts: Initially, a first wafer and a second wafer are formed. The first wafer may include a functional layer over a substrate. In one example, single crystal silicon is not required for the substrate. The first wafer may be inverted for bonding to the second wafer to form the bonded semiconductor device, such that the substrate is over the functional layer. At least a portion of the substrate may be removed to form a top surface of the bonded semiconductor device. Additionally, bond pads may be formed over the top surface.

[0006] In another example, a method for forming a semiconductor device is disclosed. The method includes the following acts: First, an insulating material layer can be formed over a substrate. In one example, single crystal silicon is not required for the substrate. The insulating material layer can be patterned to form an isolation structure and to form a plurality of trenches in the isolation structure. Semiconductor material can be deposited to fill the plurality of trenches to form a plurality of array base regions in the isolation structure, the isolation structure isolating the plurality of array base regions from one another. Further, a plurality of memory arrays can be formed over the plurality of array base regions, and an insulating structure can be formed to cover the plurality of memory arrays and the plurality of array base regions.

[0007] In yet another example, a method for forming a semiconductor device is disclosed. The method includes the following acts: First, an insulating material layer can be formed over a substrate, in one example, not necessarily single crystal silicon. A semiconductor material layer can be formed over the insulating material layer. The semiconductor material layer can be patterned to remove portions of the semiconductor material layer, expose other insulating material layers, and form a plurality of array base regions. A material the same as the insulating material layer can be deposited to fill spaces formed by the removed portions of the semiconductor material layer, connect with the insulating material layer, and form an isolation structure. A plurality of memory arrays can be formed over the plurality of array base regions, and an isolation structure can be formed to cover the plurality of memory arrays and the plurality of array base regions.

[0008] In a further example, a junction semiconductor device is disclosed. The junction semiconductor device comprises a functional layer across a wafer. The functional layer can include a plurality of array base regions within an insulating structure that is coupled to a plurality of memory arrays across a plurality of memory arrays. A top surface dimension of each one of the plurality of array base regions can be different from a bottom surface dimension. The functional layer can also comprise an isolation structure that covers and insulates the plurality of array base regions from each other.

[0009] In different examples, a wafer is disclosed. The wafer may comprise a functional layer over a substrate. The functional layer may comprise an isolation structure over the substrate. The isolation structure may surround and insulate the plurality of array base regions from one another. The wafer may also comprise a plurality of memory arrays over the plurality of array base regions. A top surface of each one of the plurality of array base regions may have dimensions different from a bottom surface. The wafer may further comprise an isolation structure covering the plurality of memory arrays and the plurality of array base regions, and a plurality of interconnect structures within the isolation structure over the plurality of memory arrays.

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0011] [Figure 1A] 1A-1D are cross-sectional views of an example wafer at different stages of an example fabrication process according to some embodiments of the present disclosure. [Figure 1B] 1A-1D are cross-sectional views of an example wafer at different stages of an example fabrication process according to some embodiments of the present disclosure. [Figure 1C] 1A-1D are cross-sectional views of an example wafer at different stages of an example fabrication process according to some embodiments of the present disclosure. [Figure 1D] 1A-1D are cross-sectional views of an example wafer at different stages of an example fabrication process according to some embodiments of the present disclosure. [Figure 2A] 1A-1D are cross-sectional views of example bonded wafers at different stages of an example fabrication process according to some embodiments of the present disclosure. [Figure 2B] 1A-1D are cross-sectional views of example bonded wafers at different stages of an example fabrication process according to some embodiments of the present disclosure. [Figure 2C] 1A-1D are cross-sectional views of example bonded wafers at different stages of an example fabrication process according to some embodiments of the present disclosure. [Figure 2D]1A-1D are cross-sectional views of example bonded wafers at different stages of an example fabrication process according to some embodiments of the present disclosure. [Figure 3A] 1A-1C illustrate an example process flow for forming an example array forming wafer according to some embodiments of the present disclosure. [Figure 3B] 1A-1D illustrate an example process flow for forming an example bonded wafer according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0013] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be employed in a variety of other applications.

[0014] It is noted that references herein to "one embodiment," "embodiment," "example embodiment," "some embodiments," and the like, mean that the disclosed embodiment may include a particular feature, structure, or characteristic, but all embodiments may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in the context of an embodiment, it is within the knowledge of one of ordinary skill in the art to implement such feature, structure, or characteristic in the context of other embodiments, whether or not explicitly described.

[0015] Generally, terminology may be understood, at least in part, from use in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, "one" or "the" and the like may be understood to convey either a singular use or a plural use, depending at least in part on the context. Also, the term "based on" may be understood not to be intended to convey necessarily an exclusive set of factors, but instead may allow for the presence of additional factors not necessarily explicitly recited, again depending at least in part on the context.

[0016] The meanings of "on", "above", and "across" in this disclosure should be interpreted broadly such that "on" not only means "directly on" something, but also includes the meaning of "on" something with an intermediate feature or layer between them, and "above" or "across" not only means "above" or "across" something, but also includes the meaning of "above" or "across" something without an intermediate feature or layer between them (i.e., directly on top of something).

[0017] Additionally, spatially relative terms such as "below," "below," "down," "above," "above" and the like may be used herein for ease of description to describe the relationship of one element or feature to other elements or features as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or to other orientations) and the spatially relative descriptions used herein may be similarly interpreted accordingly.

[0018] As used herein, the term "substrate" refers to a material onto which a subsequent layer of material is added. The substrate itself may be patterned. Materials added onto the substrate may be patterned or left unpatterned. Additionally, substrates may include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, substrates may be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0019] As used herein, the term "layer" refers to a material portion that includes a region with a thickness. A layer can extend throughout an underlying or overlying structure, or can have an extension less than that of the underlying or overlying structure. Furthermore, a layer can be a uniform or non-uniform region of a continuous structure with a thickness less than that of the continuous structure. For example, a layer can be located between any pair of horizontal planes, between the top and bottom surfaces of a continuous structure, or on such top and bottom surfaces. A layer can extend laterally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (on which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0020] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter for a component or process operation that is set during a design phase or process of a product, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations or tolerances in the manufacturing process. As used herein, the term "about" refers to a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0021] As used herein, the term "3D memory device" refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as "memory strings", such as NAND memory strings) in a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to the side of the substrate. As used herein, the x-axis and y-axis (not shown) may each represent a horizontal direction and may lie in a horizontal plane. The z-axis may represent a vertical direction and may be perpendicular to the horizontal plane. The y-axis is perpendicular to the xz plane.

[0022] As used herein, the term "wafer" refers to a structure or device that may include any suitable components, such as one or more substrates, various functional components in or on the substrate (e.g., memory arrays, peripheral circuitry, semiconductor devices, interconnects, insulating structures, bond pads, and / or wiring). For example, an array-forming wafer refers to a structure that includes a substrate and a memory array formed over the substrate, a periphery-forming wafer refers to a structure that includes a substrate and a peripheral circuitry formed over the substrate, and a bonded wafer refers to a structure / device formed by bonding two wafers (e.g., an array-forming wafer and a periphery-forming wafer) or any two suitable devices / structures. The term "wafer" does not dictate the form or function of the structure / device in the description.

[0023] In the fabrication of a 3D memory device, the memory array and the peripheral circuits can be formed on different wafers and bonded to form a bonded wafer. The memory array and the peripheral circuits can be formed simultaneously and then bonded to form a bonded memory device. This approach can have several advantages. First, the peripheral circuits can be made less sensitive to the fabrication process of the memory array (e.g., chemical and thermal processes used in the fabrication). The fabrication of the peripheral circuits can have a higher yield and the performance of the peripheral circuits can be improved. Also, the peripheral circuits and the memory array do not need to be formed on the same wafer, so more space can be used to form each of the memory array and the peripheral circuits. Thus, the memory density can be kept small enough to avoid the complications caused by the large memory density in the bonded memory device. Furthermore, the memory array and the peripheral circuits can be fabricated at the same time or at different times, increasing the flexibility of the fabrication. For example, the memory array and the peripheral circuits can be fabricated at the same time and then bonded together to form the bonded memory device, reducing the time for the entire fabrication process.

[0024] However, the fabrication process for forming the junction memory device may require two or more wafers, each of which includes a single crystal substrate, and the cost of the single crystal substrate may increase the fabrication cost for forming the junction memory device.

[0025] Various embodiments according to the present disclosure provide a structure of a wafer for forming a junction memory device, and a fabrication method for forming the structure and the junction memory device. The disclosed structure and method solve the above problems related to the increase in fabrication costs. For example, by replacing the monocrystalline substrate of the wafer for forming the memory array with a suitable low-cost substrate (e.g., a substrate with a lower cost), the cost of the fabrication process for forming the junction memory device can be reduced. Meanwhile, the memory array can be formed over a polycrystalline silicon region on the low-cost substrate to ensure the desired functionality of the memory array. The low-cost substrate can be completely removed or partially removed (e.g., thinned or planarized) after the wafer for forming the memory array and the wafer for forming the peripheral circuitry are bonded together, with little or no impact on the junction memory device. Other devices and / or structures may be formed over the junction memory device after the complete / partial removal of the low-cost substrate. Thus, the fabrication cost for forming the junction memory device can be reduced without compromising the functionality of the junction memory device.

[0026] Each of Figures 1A-1D illustrates an example array-formed wafer (e.g., a wafer for forming a memory array) at a different stage of a fabrication process according to an embodiment of the present disclosure. Each of Figures 2A-2D illustrates a bonded wafer structure at a different stage of a fabrication process according to an embodiment of the present disclosure. The bonded wafer illustrated in Figures 2A-2D can be formed from the array-formed wafer illustrated in Figures 1B and 1C. Figure 3A illustrates an example fabrication process 300 for forming the array-formed wafer illustrated in Figures 1A-1D. Figure 3B illustrates an example fabrication process 310 for forming the bonded wafer illustrated in Figures 2A-2D.

[0027] As shown in Figure 3A, at the beginning of the fabrication process, a base material layer may be formed over a substrate (operation 3001). Figure 1A shows the corresponding structure 100.

[0028] As shown in FIG. 1A, a base material layer 103 can be formed over the substrate 101. The substrate 101 can comprise any suitable substrate having a top surface with sufficient rigidity, smoothness, and uniformity. The substrate 101 can comprise a material that is easy to remove (e.g., easy to peel, etch, and / or planarize). In some embodiments, the substrate 101 comprises a material that is lower cost, commonly used, and / or easier to fabricate. In some embodiments, the substrate 101 does not comprise single crystal silicon. For example, the substrate 101 can comprise polycrystalline silicon, amorphous silicon, a mixture of polycrystalline silicon and amorphous silicon, a compound substrate, a polymer substrate, glass, quartz, graphene, or a combination thereof. The base material layer 103 can comprise any suitable material that can provide electrical insulation between the functional components of the array forming wafer 100. For example, the base material layer 103 can comprise silicon oxide (SiO), silicon nitride (SiN), and / or silicon oxynitride (SiON). In some embodiments, the base material layer 103 comprises silicon oxide. The base material layer 103 may have a thickness of d1 along a direction perpendicular to the top surface of the substrate 101 (e.g., vertical or z-axis). In order to retain a sufficient portion of the base material layer 103 across the substrate 101 to provide insulation between different components, in some embodiments, the thickness d1 is between about 1 μm and about 5 μm, such as between 1 μm and about 5 μm. In some embodiments, the thickness d1 is between about 1.5 μm and about 3 μm, such as between 1.5 μm and 3 μm (e.g., 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 3 μm, any range bounded at the lower end by any of these values, or any range bounded by any two of these values).

[0029] In some embodiments, the array forming wafer 100 comprises a liner layer 102 positioned between the substrate 101 and the base material layer 103. The liner layer 102 may comprise a single layer structure or a multi-layer structure. The liner layer 102 may provide a base for the formation of the base material layer 103. For example, the liner layer 102 may comprise a different structure and / or a different material than the base material layer 103 and the substrate 101. The liner layer 102 may be formed over the substrate 101 and the base material layer 103 may be formed over the liner layer 102 to improve adhesion between the base material layer 103 and the substrate 101, to improve the surface conditions of the substrate 101 for the deposition of the base material layer 103, and / or to reduce stress in the base material layer 103. Thus, the base material layer 103 may be deposited over the substrate 101 with improved uniformity and stability. The liner layer 102 may include any material that may improve the conditions for adhesion and growth of the base material layer 103 over the substrate 101. For example, when the base material layer 103 includes silicon oxide, the liner layer 102 may include titanium nitride and / or titanium. The material composition of the liner layer 102 may depend on the selection of the materials of the substrate 101 and the base material layer 103. In some embodiments, the liner layer 102 comprises a multi-layer structure having one or more materials. In one example, the multi-layer structure can gradually change the surface structure on which the base material layer 103 is deposited, further enhancing the growth of the base material layer 103. The specific structure and properties of the liner layer 102 should be determined based on the materials of the substrate 101 and the base material layer 103 and should not be limited by the embodiments of the present disclosure.

[0030] The base material layer 103 and the liner layer 102 may be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD). In some embodiments, a substrate 101 is provided, and a cleaning process is performed to remove radicals or contaminants on the top surface of the substrate 101. The liner layer 102 and the base material layer 103 may then be deposited successively over the top surface of the substrate 101. In some embodiments, the liner layer 102 includes titanium oxide and is formed by ALD. In some embodiments, the base material layer 103 includes silicon oxide and is formed by CVD. Optionally, a surface planarization process is performed over the base material layer 103 for later formation of other structures / devices (e.g., memory arrays) over the base material layer 103. The planarization process may include one or more of a recess etching process (dry / wet etching) and chemical mechanical polishing (CMP).

[0031] Referring to Figure 3A, after a base material layer is formed over a substrate, a shallow trench isolation (STI) structure may be formed based on the base material layer, and an array base region may be formed in the STI structure. A memory array may be formed over the array base region. An insulating structure may be formed over the memory array and the array base region, and an interconnect structure may be formed in the insulating structure (operation 3002). Figures 1B and 1C each show corresponding structures 110 and 120.

[0032] 1B, one or more array base regions 111 may be formed in the STI structure 113 to provide a foundation for the formation of memory arrays 112. One or more memory arrays 112 may be formed across the array base regions 111. In some embodiments, the thickness / depth d2 of the array base region 111 along the vertical direction (e.g., z-axis) is in the range of about 1 μm to about 3 μm, such as between 1 μm and 3 μm. In some embodiments, the thickness / depth d2 is between about 1.2 μm to about 2.5 μm, such as between 1.2 μm to 2.5 μm (e.g., 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, any range bounded at the lower end by any of these values, or any range bounded by any two of these values). In some embodiments, the distance d3 from the bottom of the array base region 111 to the liner layer 102 (or the substrate 101 if the liner layer 102 is not formed) is in the range of about 1 μm to about 2 μm, such as between 1 μm and 2 μm. In some embodiments, the distance d3 is between about 1.2 μm to about 1.8 μm, such as between 1.2 μm and 1.8 μm (e.g., 1.2 μm, 1.5 μm, 1.8 μm, any range bounded at the lower end by any of these values, or any range bounded by any two of these values). An insulating structure 115 can be formed to cover the memory array 112 and the array base region 111, such that the memory array 112 is within the insulating structure 115 and can be electrically isolated from each other. One or more interconnect structures 114 may be formed in the insulating structure 115 to couple desired devices / structures together or to couple the memory array 112 with other devices / structures.

[0033] The STI structure 113 may be formed by a portion of the base material layer 103 surrounding each array base region 111 and insulating the array base regions 111 from each other and from the substrate 101, for example. The array base regions 111 may include a suitable material or a suitable structure that provides a base for the deposition and fabrication of the memory array 112. The array base regions 111 may have sufficient rigidity, surface uniformity, and / or doping concentration for proper operation of the memory array 112. For example, the array base regions 111 may include a doped semiconductor material and function as a well region. In some embodiments, the array base regions 111 include doped polycrystalline silicon (e.g., P-type or N-type), and the polarity of the dopant is determined, for example, by the polarity of the source electrode of the memory array 112. In some embodiments, the array base regions 111 include P-type polycrystalline silicon.

[0034] The STI structure 113 may be formed by the removed portion of the base material layer 103. The location of the removed portion of the base material layer 103 may correspond to the location of the array base region 111. Any suitable patterning / etching process may be performed to form the STI structure 113. For example, a patterned photoresist layer may be formed over the base material layer 103. The patterned photoresist layer may include openings that expose the portions of the base material layer 103 to be removed. A suitable etching process (e.g., wet / dry etching) may be performed to remove the exposed portions of the base material layer 103 and to form one or more trenches in the base material layer 103. The locations of the trenches correspond to the locations of the memory arrays 112. In some embodiments, the etching time of the etching process is controlled such that a sufficient portion of the base material layer 103 is retained between the bottom of the trench and the top surface of the substrate 101 / liner layer 102. The remaining portions of the base material layer 103 may form the STI structure 113.

[0035] A doped semiconductor material may be formed in the trench to form the array base region 111. In one example, polycrystalline silicon may be deposited to fill the trench. The polycrystalline silicon may be doped with a suitable dopant, for example, by an ion implantation process or an in-situ doping process. In some embodiments, a P-type dopant, such as boron, aluminum, indium, and / or gallium, is doped into the polycrystalline silicon material to form the array base region 111. In some embodiments, a width Wt1 of the top surface of the array base region 111 may be greater than a width Wb1 of the bottom surface of the array base region 111 along the x-axis (or horizontal plane). Optionally, a surface planarization process is performed over the STI structure 113 and the array base region 111 to remove excess material from the formation of the array base region 111 and the STI structure 113. The planarized top surface of the array base region 111 may be sufficiently uniform and / or smooth to facilitate the subsequent formation of the memory array 112. The planarization process may include one or more of a recess etching process (dry / wet etching) and CMP. The slurry used for CMP may be determined based on, for example, the material composition and / or surface area / percentage of the array base region 111 and / or the STI structure 113. For example, the slurry may include a chemical that is primarily used to planarize the material of the STI structure 113 when the surface area of ​​the array base region 111 is sufficiently small compared to the surface area of ​​the STI structure 113 (e.g., less than a predetermined percentage), and vice versa.

[0036] The memory array 112 may be formed across the array base region 111. For illustrative purposes, one memory array 112 is shown as an example across the array base region 111 as shown in FIG. 1B. In various embodiments, the number of memory arrays formed across the array base region 111 is determined by actual design / fabrication requirements. The memory array 112 may include any suitable device / structure in which memory cells are formed. For example, the memory array 112 may have one or more blocks extending along a direction parallel to the top surface of the substrate (e.g., along a horizontal plane or an xy plane), and each memory block may have multiple memory cells. The specific structure of the memory array 112 may be determined by different design / fabrication requirements.

[0037] The memory array 112 may be formed by any suitable process. In one example, multiple sacrificial material layers and multiple insulating material layers may be alternately deposited along the vertical direction over the STI structures 113 and the array base region 111 to form a stack structure. The sacrificial material layers and insulating material layers may have different material compositions and may have the same or different thicknesses. A patterned photoresist layer may be formed over the stack structure to expose the portions of the stack structure to be removed. A suitable etching process (dry / wet etching) may be performed to remove the exposed portions of the stack structure to expose the STI structures 113 and form the array stack in the array base region 111. Each array block may undergo repeated etching along the vertical direction (e.g., z-axis) to form a staircase structure. The staircase structure may be formed, for example, by repeatedly forming an etching mask (e.g., a patterned photoresist layer) over each stack structure to expose the portions of the sacrificial material layers and insulating material layers to be removed, and removing the exposed portions. The etching mask may be repeatedly trimmed / etched to expose the portions of the stack structure to be removed. The sacrificial layer and the base material layer may be repeatedly formed by etching the sacrificial material layer and the insulating material layer. Then, a staircase structure may be formed. A semiconductor passage may be formed in the staircase structure to extend from the top surface of the staircase structure to the array base region 111. A source electrode may be formed in the staircase structure, for example to divide the staircase structure into different memory blocks. A drain electrode may be formed across the staircase structure. A gate electrode (e.g., functioning as a word line) may be formed by replacing the sacrificial layer with a suitable conductor layer such as tungsten, aluminum, cobalt, copper, and / or polycrystalline silicon (or a conductor layer each surrounded by a high-k dielectric layer such as an aluminum oxide layer and / or a silicon oxynitride layer). The alternating conductor layers and base material layers may be stacked along a vertical direction across the array base region 111. The intersection of the gate electrode and the semiconductor passage may form a memory cell.

[0038] To form the semiconductor passages in the staircase structures, a plurality of passage holes may be formed in each of the staircase structures. The plurality of passage holes may be formed by forming a patterned photoresist layer over the staircase structures. The patterned photoresist layer may include a plurality of openings that expose portions of the staircase structures. The locations of the exposed portions of the staircase structures may correspond to the locations of the semiconductor passages. An etching process may be performed to remove the portions of the staircase structures exposed by the openings to expose the substrate 101. The passage holes may be formed. Optionally, a recess etching process may be performed to remove the portions of the substrate 101 exposed at the bottom of each of the passage holes. Optionally, a suitable deposition process may be performed to form a semiconductor portion at the bottom of the passage hole as part of the respective semiconductor passage. The semiconductor portion may contact the subsequently formed passage-forming structure. The semiconductor portion may include a suitable semiconductor material such as polycrystalline silicon, and the deposition process may include CVD, PVD, selective deposition, and / or ALD. The thickness of the semiconductor portion along the vertical direction may be controlled to have a desired range. For example, the top surface of the semiconductor portion may be located between at least two conductor layers along the vertical direction. Optionally, before the via-forming structure is filled into the via hole, a cleaning / recess etch step is performed to remove excess material of the semiconductor portion on the sidewall of the via hole.

[0039] After the semiconductor portions are formed in the via holes, a via-forming structure is formed to fill each via hole. The via-forming structure may, for example, comprise a blocking layer, a memory layer, a tunnel layer, a semiconductor layer, and a dielectric core, which are successively deposited from the sidewall of each via hole to the center of the via hole. Each one of the blocking layer, the memory layer, the tunnel layer, and the semiconductor layer may include a single layer structure or a multilayer structure. For example, the blocking layer may include a bilayer structure. The first blocking layer may include a dielectric metal oxide having a sufficiently large dielectric constant (e.g., greater than 7.9). Examples of the first blocking layer include AlO, hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, and / or alloys thereof. The first blocking layer may be formed by a suitable deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), and / or liquid mist chemical deposition. In some embodiments, the first barrier layer comprises AlO. A second barrier layer can be formed over the first barrier layer and can comprise a different dielectric material than the first barrier layer. For example, the second barrier layer can comprise silicon oxide, silicon oxynitride, and / or silicon nitride. In some embodiments, the second barrier layer comprises silicon oxide and can be formed by any suitable conformal deposition method, such as low pressure CVD (LPCVD) and / or ALD.

[0040] The memory layer may include a charge trapping material and may be formed over the blocking layer. The memory layer may include conductive materials and / or semiconductors such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, alloys thereof, nanoparticles thereof, silicides thereof, and / or polycrystalline or amorphous semiconductor materials (e.g., polycrystalline silicon and amorphous silicon). The memory layer may also include one or more insulating materials such as SiN and / or SiON. In some embodiments, the memory layer includes a SiN layer sandwiched by a SiON layer, which is further sandwiched by a SiN layer. The memory layer may be formed by any suitable deposition method, such as CVD, ALD, and physical vapor deposition (PVD). The tunnel layer may be formed over the memory layer and may include a single layer structure or a multilayer structure and may include SiO, SiN, SiON, dielectric metal oxides, dielectric metal oxynitrides, dielectric metal silicates, and / or alloys thereof. The tunnel layer may be formed by a suitable deposition method, such as CVD, ALD, and / or PVD. In some embodiments, the tunnel layer includes multiple SiON and SiO layers, where the multiple SiON layers are positioned between the memory layer 222 and the SiO layer.

[0041] A semiconductor layer can facilitate the transport of charges and can be formed over the tunnel layer. The semiconductor layer can include one or more semiconductor materials, such as an elemental semiconductor material, a III-V compound semiconductor material, a II-VI compound semiconductor material, and / or an organic semiconductor material. The semiconductor layer can be formed by any suitable deposition method, such as LPCVD, ALD, and / or metal-organic chemical vapor deposition (MOCVD). In some embodiments, the semiconductor layer includes a polycrystalline silicon layer. The dielectric core can include a suitable dielectric material and can fill the space enclosed by the semiconductor layer. In some embodiments, the dielectric core includes SiO (e.g., SiO of sufficiently high purity) and can be formed by any suitable deposition method, such as CVD, LPCVD, ALD, and / or PVD. Optionally, a surface planarization process is performed over the staircase structure to remove excess material from the formation of the semiconductor passage. The planarization process can include one or more of a recess etching process (dry / wet etching) and CMP. In various embodiments, the particular order of forming the different portions of the memory array 112 and the structure of each portion may be determined by design / fabrication considerations and should not be limited by the embodiments of the present disclosure.

[0042] An insulating structure 115 can then be formed to cover the memory array 112 and the array base region 111 and isolate the memory array 112 and the array base region 111 from other structures / devices. The insulating structure 115 can comprise any suitable dielectric material, such as silicon oxide, and can be formed by a suitable deposition process, such as CVD, PVD, and / or ALD. Optionally, a surface planarization process is performed over the insulating structure 115 to planarize a top surface of the insulating structure 115. The planarization process can include one or more of a recess etching process (dry / wet etching) and CMP.

[0043] Various interconnect structures 114 may be formed in the insulating structure 115. For purposes of illustration, the interconnect structures 114 are depicted as blocks in FIG. 1B. The interconnect structures 114 may represent any structure / device (e.g., metal interconnects, contacts, and / or plugs) that conductively couple the array forming wafer 110 to other wafers / structures. For example, the interconnect structures 114 may represent metal interconnects that extend from a top surface of the insulating structure 115 to the memory array 112 (e.g., gate electrodes of the memory array 112). The interconnect structures 114 may include a suitable conductive material, such as tungsten, cobalt, aluminum, and / or copper. In some embodiments, the interconnect structures 114 may be formed by patterning / etching the insulating structure 115 to form openings that couple the top surface of the insulating structure 115 to desired portions of the memory array 112, and filling the openings with a desired conductive material. Patterning / etching the openings may be performed by any suitable etching process (e.g., wet / dry etching), and forming the conductive material may include any suitable deposition process, such as CVD, PVD, sputtering, and / or ALD.

[0044] 1C and 1D each show another exemplary array-forming wafer at a different stage of another fabrication process according to some embodiments. Compared to the structures and processes associated with the array-forming wafer 110, the STI structures and array base regions of the array-forming wafer 130 may be formed differently. In some embodiments, the structures and fabrication processes of the memory array 132, insulating structures 135, and interconnect structures 134 of FIG. 1D may be the same or similar to the memory array 112, insulating structures 115, and interconnect structures 114 of FIG. 1B. The same or similar substrate 101 and liner layer 102 may be used to form the array-forming wafer 110.

[0045] As shown in FIG. 1C, a base material layer may be formed over the substrate 101 (eg, or over the liner layer 102). Unlike the structure 100, the base material layer of FIG. 1C may include an insulating layer 123 over the substrate 100 and an alignment base layer 121 over the insulating layer 123. The material composition of the insulating layer 123 may be the same or similar to the base material layer 103, and the material composition of the alignment base layer 121 may be the same or similar to the alignment base region 111. In some embodiments, the alignment base layer 121 includes polycrystalline silicon or doped polycrystalline silicon, and the insulating layer 123 includes silicon oxide. The thickness d4 of the alignment base layer 121 may be the same or similar to the thickness / depth d2 of the alignment base region 111, and the thickness d5 of the insulating layer 123 may be the same or similar to the distance d3. In some embodiments, the thickness d4 and / or the distance d5 may be other desired values / ranges.

[0046] A patterning / etching process may be performed to form the array base region 131 over the insulating layer 123. For example, a patterned photoresist layer may be formed over the array base layer 121. The patterned photoresist layer may cover the portion of the array base layer 121 that is retained to form the array base region 131 and may include openings that expose the portion of the array base layer 121 that is to be removed. A suitable etching process (e.g., wet / dry etching) may be performed to remove the exposed portion of the array base layer 121 to expose the insulating layer 123. The remaining portion of the array base layer 121 may form the array base region 131. In some embodiments, a width Wt2 of the top surface of the array base region 131 may be smaller than a width Wb2 of the bottom surface of the array base region 131 along the x-axis (or horizontal plane).

[0047] Further, an insulating material may be deposited to fill the space formed by the removal of the portion of the alignment base layer 121 (e.g., between the alignment base regions 131 and on the exposed portion of the insulating layer 123). In some embodiments, the insulating material is the same or similar to the material of the insulating layer 123 and may be formed by any suitable deposition process, such as CVD, PVD, ALD, and / or selective deposition. The insulating material may be deposited to fill the space formed by the removal of the portion of the alignment base layer 121 and to connect with the insulating layer 123. The structure formed by the insulating layer 123 adjacent to the insulating material may form the initial STI structure 133. Optionally, a surface planarization process is performed over the STI structure 133 and the alignment base regions 131 to remove excess material from the formation of the STI structure 133. The planarization process may include one or more of a recess etching process (dry / wet etching) and a chemical mechanical polishing (CMP). The slurry used for CMP may be determined based on, for example, the material composition and / or surface area / percentage of the array base region 131 and / or the STI structure 133. For example, if the surface area of ​​the STI structure 133 is sufficiently small compared to the surface area of ​​the array base region 131, the slurry may include chemicals that are primarily used to planarize the material of the array base region 131, and vice versa. Furthermore, the memory array 132, the insulating structure 135, and the interconnect structure 134 may be formed. The formation of these structures may be referred to in the description of the memory array 112, the insulating structure 115, and the interconnect structure 114.

[0048] The array forming wafer 110 / 120 can be bonded to other structures / devices via interconnect structures 114. In some embodiments, the array forming wafer 110 / 120 and a periphery forming wafer (e.g., a wafer on which peripheral circuitry for operation of a memory device is formed) can be bonded together to form a bonded wafer. Control signals / data can be applied to the peripheral circuitry of the periphery forming wafer to control operation (e.g., read, write, and / or retain) of the memory array. Figures 2A-2D show an example process for forming a bonded wafer with the array forming wafer 110 / 120 and the periphery forming wafer. For ease of viewing, an array forming wafer similar or identical to the array forming wafer 110 is depicted in Figures 2A-2D to explain the fabrication process.

[0049] As shown in Figure 3B, at the beginning of the fabrication process, an array forming wafer and a periphery forming wafer may be provided (operation 3101). Figure 2A shows corresponding structures 200 and 210.

[0050] As shown in Fig. 2A, an array forming wafer 200 and a periphery forming wafer 210 may be provided. The array forming wafer 200 may be the same as or similar to the array forming wafer 110 shown in Fig. 1B. Specifically, the fabrication process and structure of the substrate 101, the liner layer 102, the STI structure 113, the array base region 111, the memory array 112, the insulating structure 115, and the interconnect structure 114 may be similar or the same as the fabrication process and structure of the first substrate 201, the liner layer 202, the STI structure 203, the array base region 204, the memory array 205, the first insulating structure 206, and the first interconnect structure 207, respectively.

[0051] The periphery formed wafer 210 may include any device / structure for applying a bias to the memory array 205 to operate the memory array 205. The periphery formed wafer 210 may include a second substrate 211, a device layer 215 formed over the second substrate 211, a second insulating structure 216 over the device layer 215, and a plurality of second interconnect structures 217 in the second insulating structure 216.

[0052] The second substrate 211 may comprise any suitable material to provide a fabrication basis for the formation of peripheral circuitry. The second substrate 211 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the second substrate 211 is a thinned substrate (e.g., a semiconductor layer) that has been thinned from its normal thickness by grinding, wet / dry etching, and / or CMP. In some embodiments, the second substrate 211 includes single crystal silicon.

[0053] The device layer 215 may represent any functional devices / structures that form the peripheral circuitry in the peripheral forming wafer 210. For example, the device layer 215 may comprise digital, analog, and / or mixed signal peripheral circuitry used to facilitate operation of the formed memory devices. A second insulating structure 216 may cover the device layer 215 to provide insulation between the devices / structures of the device layer 215 and between the device layer 215 and other components of the peripheral forming wafer 210. The second insulating structure 216 may include any suitable dielectric material, such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0054] The second interconnect structure 217 can be formed in the second insulating structure 216 and exposed to couple with the first interconnect structure 207. The second interconnect structure 217 can represent any structure / device (e.g., metal interconnect, contact, and / or plug) that conductively couples the peripherally formed wafer 210 to other wafers / structures. For example, the second interconnect structure 217 can represent a metal interconnect extending from a top surface of the second insulating structure 216 to the device layer 215. The second interconnect structure 217 can include a suitable conductive material such as tungsten, cobalt, aluminum, and / or copper. In some embodiments, the second interconnect structure 217 can be formed by patterning / etching the second insulating structure 216 to form an opening that couples a top surface of the second insulating structure 216 to a desired portion of the device layer 215 and filling the opening with a desired conductive material. The patterning / etching of the openings can be performed by any suitable etching process (e.g., wet / dry etching), and the formation of the conductive material can include any suitable deposition process, such as CVD, PVD, sputtering, and / or ALD. In some embodiments, the arrangement of the second interconnect structures in the second interconnect structure 217 (e.g., the dimensions of the second interconnect structures and the separation distance between the second interconnect structures) can match the arrangement of the first interconnect structures 207 such that each first insulating structure 206 can be bonded with a corresponding second interconnect structure 217. Optionally, a surface planarization process is performed over the second insulating structure 216 and the second interconnect structure 217 to planarize the top surfaces of the second insulating structure 216 and the second interconnect structure 217. The planarization process can include one or more of a recess etching process (dry / wet etching) and CMP.

[0055] The array-forming wafer 200 and the periphery-forming wafer 210 may be formed by different fabrication processes (e.g., separate fabrication processes). In some embodiments, the array-forming wafer 200 and the periphery-forming wafer 210 share the same fabrication operations in some fabrication stages, such as, for example, the formation of the first interconnect structure 207 and the second interconnect structure 217, and / or the planarization process. The specific processes for forming the array-forming wafer 200 and the periphery-forming wafer 210 should be subject to different design / fabrication requirements and should not be limited by the embodiments of the present disclosure.

[0056] 3B, after the array forming wafer and the periphery forming wafer are provided, one of the wafers is flipped for bonding to the other wafer such that the first interconnect structure and the second interconnect structure are bonded to one another (operation 3102). FIG. 2B shows the corresponding bonded wafer 220.

[0057] As shown in FIG. 2B, the array-forming wafer 200 can be flipped over for bonding to the periphery-forming wafer 210. A bonded wafer or a bonded semiconductor device can be formed. That is, the bonded semiconductor device comprises two wafers (e.g., the array-forming wafer 200 and the periphery-forming wafer 210) bonded together. Each first interconnect structure 207 can be bonded to a corresponding second interconnect structure 217. A suitable bonding process can be performed to form a bond between the array-forming wafer 200 and the periphery-forming wafer 210. In some embodiments, the array-forming wafer 200 and the periphery-forming wafer 210 are bonded by a hybrid bond. In some embodiments, the hybrid bond bonds the first interconnect structure 207 to the second interconnect structure 217 and bonds the first insulating structure 206 to the second insulating structure 216. In some embodiments, pressure is applied to form a bond between the first insulating structure 206 and the second insulating structure 216, and heat is applied to form a bond between the first interconnect structure 207 and the second interconnect structure 217. In some embodiments, the surfaces of the first insulating structure 206, the second insulating structure 216, the first interconnect structure 207, and the second interconnect structure 217 are sufficiently uniform such that little or no space is formed between the first insulating structure 206 and the second insulating structure 216 and between the first interconnect structure 207 and the second interconnect structure 217 after bonding.

[0058] 3B, after the array forming wafer and the periphery forming wafer are bonded together, at least a portion of the first substrate is removed (operation 3103). FIG. 2C shows the corresponding bonded wafer 230.

[0059] As shown in FIG. 2C, at least a portion of the first substrate 201 is removed. The remaining portion of the array forming wafer 200 is referred to as the array forming wafer 200-2, which is bonded to the periphery forming wafer 210 to form the bonded wafer 230. For illustrative purposes, the first substrate 201 is shown as being completely removed in FIG. 2C. In some embodiments, the first substrate 201 and the liner layer 202 are removed to expose the STI structures 203. In some embodiments, the STI structures 203 are planarized or recess etched such that a thickness T1 of the STI structures 203 along a vertical direction (e.g., z-axis) ranges from about 1 μm to about 5 μm, such as between 1 μm and 5 μm. In some embodiments, thickness T1 is between about 1.5 μm and about 3 μm, such as between 1.5 μm and 3 μm (e.g., 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 3 μm, any range bounded at the lower end by any of these values, or any range bounded by any two of these values). The portion of STI structure 203 between the exposed surface and the bottom of array base region 204 is sufficiently thick to insulate the device / structure (e.g., device / structure formed across the exposed surface of STI structure 203) from memory array 205. In some embodiments, T2 is in the range of about 1 μm to about 2 μm, such as between 1 μm and 2 μm. In some embodiments, T2 is between about 1.2 μm and about 1.8 μm, such as between 1.2 μm and 1.8 μm (e.g., 1.2 μm, 1.5 μm, 1.8 μm, any range bounded at the lower end by any of these values, or any range bounded by any two of these values). In some embodiments, a portion of the first substrate 201 is retained over the STI structure 203, for example, during subsequent formation of other devices / structures. The first substrate 201 can be referred to as "thin". The amount of material removed from the first substrate 201 should be determined according to different design / fabrication requirements and should not be limited by the embodiments of the present disclosure.

[0060] The removal of the first substrate 201 may include an etching process (e.g., wet / dry etching) and / or a CMP process. The etchant and / or slurry selected to remove the first substrate 201 should be determined based on the material forming the first substrate 201. In some embodiments, the etchant selectively etches the first substrate 201 down to the STI structures 203.

[0061] 3B, after the first substrate is removed or thinned, other structures or devices may be formed over the top surface of the bonded wafer (operation 3104). FIG. 2D shows the corresponding bonded wafer 240.

[0062] As shown in FIG. 2D , other structures / devices may be formed across the top surface of bonded wafer 240, such as one or more bond pads 241. Bond pads 241 may be used, for example, for wiring bond pads, bump attachment locations, and / or electrical connection locations. Bond pads 241 may comprise any suitable material for various uses. For example, if bond pads 241 are wiring bond pads, bond pads 241 may comprise metallic materials such as aluminum, copper, and / or gold. Bond pads 241 may be formed by any suitable method, such as by depositing a layer of the desired bonding material across bonded wafer 240 (e.g., by CVD, sputtering, PVD, e-beam evaporation, and / or ALD) and patterning the deposited material layer (e.g., using a photolithography process and a subsequent etching process) to form bond pads 241 in the desired pattern. In some embodiments, another liner layer (e.g., an adhesive or glue layer) may be formed between the bond pads 241 and the STI structures 203 to improve adhesion between the bonding material and the STI structures 203. Other processes (e.g., more fabrication operations, wiring, and / or packaging) may be performed on the bonded wafer 240.

[0063] In this disclosure, an array-forming wafer is used as an example to illustrate the embodiment. It should be noted that the disclosed structures and methods can be used to form any suitable wafer in which a substrate is thinned or removed in a subsequent fabrication step. The array-forming wafer can be an example of any suitable wafer with a functional layer over an alternative substrate, which may comprise a structure / substrate with sufficient uniformity, rigidity, and / or smoothness for a subsequent fabrication step. The alternative substrate may be easily removed (e.g., peeled, etched, and / or planarized) from the structure to which it is attached, may be of lower cost, and / or may be easily fabricated. The wafer may comprise a memory array, a circuit, a semiconductor device, and / or any other suitable structure / device. Thus, the overall fabrication cost for forming the bonded wafer may be reduced.

[0064] In some embodiments, a method for forming a bonded semiconductor device includes the following operations: Initially, a first wafer and a second wafer are formed. The first wafer may include a functional layer over a substrate. Single crystal silicon may not be required for the substrate, and the substrate may not include single crystal silicon. The first wafer may be inverted to bond to the second wafer to form the bonded semiconductor device, such that the substrate is above the functional layer. At least a portion of the substrate may be removed to form a top surface of the bonded semiconductor device. Additionally, bond pads may be formed over the top surface.

[0065] In some embodiments, forming the first wafer includes forming an isolation structure across the substrate and forming a plurality of array base regions in the isolation structure. The isolation structure can isolate the plurality of array base regions from one another. Forming the first substrate includes forming a plurality of memory arrays across the plurality of array base regions, forming an isolation structure overlying the plurality of memory arrays and the plurality of array base regions, and forming a plurality of interconnect structures in the isolation structure that are exposed at the top surface of the first wafer.

[0066] In some embodiments, forming the isolation structure and forming the plurality of array base regions in the isolation structure includes forming an insulating material layer over the substrate, patterning the insulating material layer to form a plurality of trenches in the insulating material layer, and depositing a semiconductor material to fill the plurality of trenches to form the plurality of array base regions.

[0067] In some embodiments, forming the isolation structure and forming the plurality of array base regions in the isolation structure includes forming another insulating material layer over the substrate, forming a semiconductor material layer over the other insulating material layer, and patterning the semiconductor material layer to remove a portion of the semiconductor material layer to expose the other insulating material layer and form the plurality of array base regions. Forming the isolation structure and forming the plurality of array base regions in the isolation structure includes depositing a material that is the same as the other insulating material layer to fill spaces formed by the removed portions of the semiconductor material layer and to couple with the other insulating material layer to form the isolation structure.

[0068] In one embodiment, the method further comprises performing a planarization process to remove excess material thereon after formation of the plurality of alignment group regions and the isolation structures.

[0069] In some embodiments, forming the insulating material layer and the other insulating material layer includes depositing silicon oxide, and depositing the semiconductor material and forming the semiconductor material layer includes depositing doped polycrystalline silicon.

[0070] In some embodiments, forming a plurality of memory arrays across a plurality of array base areas includes forming at least one memory array across each one of the plurality of array base areas.

[0071] In some embodiments, forming the multiple memory arrays across the multiple array base regions includes forming a staircase structure across each one of the multiple array base regions, forming a via hole extending from a top surface of the staircase structure to the respective array base region, and forming a semiconductor portion at a bottom of the via hole. The semiconductor portion may be coupled to the array base region. Forming the multiple memory arrays across the multiple array base regions may also include forming a via forming structure to fill the via hole and form a semiconductor via.

[0072] In some embodiments, forming the semiconductor portions includes performing a deposition process to form a semiconductor material on the exposed portions of each array base region at the bottom of the via hole.

[0073] In some embodiments, the depositing step for forming the semiconductor material comprises depositing a material that is the same as the material of each of the alignment group regions.

[0074] In some embodiments, the deposition process includes one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and selective evaporation.

[0075] In some embodiments, the method further includes forming a plurality of gate electrodes on the staircase structure to be coupled with the plurality of interconnect structures and to form a plurality of memory cells by intersecting with the semiconductor vias.

[0076] In some embodiments, providing the second wafer includes providing a plurality of other interconnect structures to the substrate.

[0077] In some embodiments, flipping the first wafer to bond to the second wafer to form the bonded semiconductor device includes performing hybrid bonding to bond the first wafer to the second wafer such that interconnect structures of the first wafer are bonded to a plurality of other interconnect structures of the second wafer.

[0078] In some embodiments, the method further includes forming a liner layer between the isolation structure and the substrate.

[0079] In some embodiments, removing at least a portion of the substrate comprises one or more of an etching process, a stripping process, and a planarizing process.

[0080] In some embodiments, a method for forming a semiconductor device includes the following operations: First, a layer of insulating material may be formed over a substrate. Single crystal silicon may not be required for the substrate, and the substrate may not include single crystal silicon. The layer of insulating material may be patterned to form an isolation structure and to form a plurality of trenches in the isolation structure. Semiconductor material may be deposited to fill the plurality of trenches to form a plurality of array base regions in the isolation structure, the isolation structure isolating the plurality of array base regions from one another. Further, a plurality of memory arrays may be formed over the plurality of array base regions, and an insulating structure may be formed to cover the plurality of memory arrays and the plurality of array base regions.

[0081] In some embodiments, the method further comprises performing a planarization process to remove excess material thereon after formation of the plurality of alignment group regions and the isolation structures.

[0082] In some embodiments, forming the insulating material layer includes depositing silicon oxide and depositing the semiconductor material includes depositing doped polycrystalline silicon.

[0083] In some embodiments, a method for forming a semiconductor device includes the following operations: First, an insulating material layer may be formed over a substrate. Single crystal silicon may not be required for the substrate, and the substrate may not include single crystal silicon. A semiconductor material layer may be formed over the insulating material layer. The semiconductor material layer may be patterned to remove portions of the semiconductor material layer, expose other insulating material layers, and form a plurality of array base regions. A material that is the same as the insulating material layer may be deposited to fill spaces formed by the removed portions of the semiconductor material layer, connect with the insulating material layer, and form an isolation structure. A plurality of memory arrays may be formed over the plurality of array base regions, and an isolation structure may be formed to cover the plurality of memory arrays and the plurality of array base regions.

[0084] In some embodiments, the method further comprises performing a planarization process to remove excess material thereon after formation of the plurality of alignment group regions and the isolation structures.

[0085] In some embodiments, forming the layer of insulating material includes depositing silicon oxide, and forming the layer of semiconducting material includes depositing doped polycrystalline silicon.

[0086] In some embodiments, the junction semiconductor device comprises a functional layer across the wafer. The functional layer can include a plurality of array base regions in an insulating structure across the plurality of memory arrays and coupled with the plurality of memory arrays. A top surface dimension of each one of the plurality of array base regions can be different from a bottom surface dimension. The functional layer can also comprise an isolation structure covering and insulating the plurality of array base regions from each other.

[0087] In some embodiments, the isolation structure comprises silicon oxide and the plurality of alignment base regions comprises doped polycrystalline silicon.

[0088] In some embodiments, the plurality of memory arrays comprises a staircase structure with a semiconductor via, the semiconductor via comprising a semiconductor portion coupled to a respective array base region and a via-forming structure across the semiconductor portion. The semiconductor portion may comprise polycrystalline silicon.

[0089] In some embodiments, the plurality of memory arrays further comprise a plurality of gate electrodes intersecting the semiconductor vias to form a plurality of memory cells.

[0090] In some embodiments, the functional layer is bonded to the wafer by bonding to another isolation structure across the substrate, the bonding including first bonds between a plurality of interconnect structures in the isolation structure and a plurality of other interconnect structures in the other isolation structure, and second bonds between the isolation structure and the other isolation structure.

[0091] In some embodiments, the wafer further comprises a device layer within other isolation structures over the substrate, the device layer being coupled to a number of other interconnect structures, hi some embodiments, the memory array is coupled to a number of interconnect structures.

[0092] In some embodiments, the bonded semiconductor device further comprises a bond pad across the isolation structure.

[0093] In some embodiments, the wafer may comprise a functional layer across the substrate. The functional layer may comprise an isolation structure across the substrate. The isolation structure may surround and insulate the plurality of array base regions from one another. The wafer may also comprise a plurality of memory arrays across the plurality of array base regions. A dimension of a top surface of each one of the plurality of array base regions may differ from a dimension of a bottom surface. The wafer may further comprise an isolation structure covering the plurality of memory arrays and the plurality of array base regions, and a plurality of interconnect structures within the isolation structure across the plurality of memory arrays.

[0094] In some embodiments, the isolation structure comprises silicon oxide and the plurality of alignment base regions comprises doped polycrystalline silicon.

[0095] In some embodiments, each of the plurality of memory arrays comprises a staircase structure with a semiconductor via, the semiconductor via comprising a semiconductor portion coupled to a respective array base region and a via-forming structure across the semiconductor portion. The semiconductor portion may comprise polycrystalline silicon.

[0096] In some embodiments, the plurality of memory arrays further comprise a plurality of gate electrodes intersecting the semiconductor vias to form a plurality of memory cells.

[0097] In some embodiments, the thickness of the plurality of array group regions is in the range of about 1 μm to about 3 μm, and the distance from the lower surface of the plurality of array group regions to the substrate is in the range of about 1 μm to about 2 μm.

[0098] In some embodiments, the insulating structure comprises silicon oxide and the plurality of interconnect structures comprises copper.

[0099] The foregoing description of specific embodiments is intended to clarify the broad nature of the disclosure so that others may easily modify and / or adapt such specific embodiments for various applications without undue experimentation by applying the knowledge of those skilled in the art without departing from the broad concepts of the disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments based on the teachings and guidance presented herein. It is to be understood that the expressions or terms in the present specification are for the purpose of description and not of limitation, as the terms or terms in the present specification are interpreted by those skilled in the art in light of the teachings and guidance.

[0100] The embodiments of the present disclosure are described above using functional building blocks that show the implementation of specified functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for convenience of description. Alternative boundaries may be defined as long as the specified functions and their relationships are appropriately implemented.

[0101] The Summary and Abstract may describe one or more exemplary embodiments, but may not describe every exemplary embodiment of the disclosure as contemplated by the inventors, and thus are not intended to be in any way limiting of the disclosure and the appended claims.

[0102] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0103] 100, 110, 120, 130 Structure, array forming wafer 101 Substrate 102 Liner layer 103 Basic material layer 111 Sequence base region 112 Memory Array 113 STI structure 114 Interconnected structure 115 Insulation structure 121 Array Substrate 123 Insulating Layer 130 Array Formation Wafer 131 Sequence base region 132 Memory Array 133 STI structure 134 Interconnected structure 135 Insulation structure 200, 200-2 structure, array forming wafer 201 First Substrate 202 Liner layer 203 STI structure 204 Sequence base area 205 Memory Array 206 First Insulation Structure 207 First Interconnection Structure 210 Structure, peripherally formed wafer 211 Second substrate 215 Equipment layer 216 Second Insulation Structure 217 Second Interconnection Structure 220, 230, 240 Bonded wafers 241 Bonding Pad d1 Thickness d2 Thickness, depth d3 Distance d4 Thickness d5 thickness Wb1, Wb2, Wt1, Wt2 width T1 Thickness

Claims

1. A semiconductor device, comprising: a plurality of array base regions in an STI structure, the array base regions being connected to a plurality of memory arrays and located below the plurality of memory arrays, the array base regions being made of a semiconductor material, the size of a top surface of each of the plurality of array base regions being different from a size of a bottom surface of each of the plurality of array base regions; a layer covering the plurality of array base regions and an insulating structure insulating the plurality of array base regions from one another.

2. 2. The semiconductor device of claim 1, wherein said insulating structure comprises silicon oxide and said plurality of array base regions comprises doped polysilicon.

3. the plurality of memory arrays including a staircase structure having a semiconductor passage; 3. The semiconductor device of claim 2, wherein the semiconductor vias include semiconductor portions connected to respective substrate regions and via-forming structures above the semiconductor portions, the semiconductor portions comprising polycrystalline silicon.

4. 4. The semiconductor device of claim 3, wherein said plurality of memory arrays further include a plurality of gate electrodes intersecting said semiconductor paths to form a plurality of memory cells.

5. The layer comprising the plurality of array base regions and the insulating structure is bonded to another layer comprising another insulating structure above a substrate; 5. The semiconductor device of claim 1, wherein the junctions include first junctions between a plurality of interconnect structures in the insulating structure and a plurality of other interconnect structures in the other insulating structure, and second junctions between the insulating structure and the other insulating structure.

6. the semiconductor device further includes a device layer above the substrate and within the further insulating structure, the device layer being connected to the plurality of further interconnect structures; The semiconductor device of claim 5 , wherein said memory array is connected to said plurality of interconnect structures.

7. The semiconductor device of claim 1 , further comprising a bond pad above the insulating structure.

8. 1. A semiconductor device including a layer over a substrate, the layer comprising: a plurality of memory arrays above a plurality of array base regions made of a semiconductor material, each of the plurality of array base regions having a top surface size different from a bottom surface size; an insulating structure covering the plurality of memory arrays and the plurality of array base regions; a plurality of interconnect structures within the isolation structure and above the plurality of memory arrays.

9. 9. The semiconductor device of claim 8, wherein said insulating structure comprises silicon oxide and said plurality of array base regions comprises doped polysilicon.

10. the plurality of memory arrays including a staircase structure having a semiconductor passage; 10. The semiconductor device of claim 9, wherein the semiconductor vias include semiconductor portions connected to respective substrate regions and via-forming structures above the semiconductor portions, the semiconductor portions comprising polycrystalline silicon.

11. 11. The semiconductor device of claim 10, wherein said plurality of memory arrays further include a plurality of gate electrodes intersecting said semiconductor vias to form a plurality of memory cells.

12. 12. The semiconductor device according to claim 8, wherein the thickness of the plurality of array base regions is in the range of 1 μm to 3 μm, and the distance between the lower surfaces of the plurality of array base regions and the substrate is in the range of 1 μm to 2 μm.

13. 13. The semiconductor device of claim 8, wherein the insulating structure comprises silicon oxide and the plurality of interconnect structures comprises copper.

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