Semiconductor device and display device

Abstract

To provide a bidirectional shift register configured by transistors with the same conductivity type.SOLUTION: A first circuit SR[1] outputs a first signal synchronizing with a first clock signal, a second circuit SR[2] outputs a second signal synchronizing with a second clock signal, and a third circuit SR[3] outputs a third signal synchronizing with a third clock signal. The second circuit SR[2] has first to third transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, the first signal is input to the first terminal, the second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to the first terminal, the second terminal is electrically connected to a gate of the first transistor, and the third clock signal is input to a gate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, a display module, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. Therefore, one aspect of the present invention disclosed in the present specification more specifically relates to a The technical fields of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, and the like. One example is a driving method or a manufacturing method thereof. [Background technology]

[0003] The shift register is used as a driving circuit for a memory device, an image sensor, a display device, etc. In particular, the development of shift registers consisting of transistors of the same polarity is progressing. The technology relating to such a shift register is described in Patent Documents 1 and 2. It has been disclosed.

[0004] The shift registers disclosed in Patent Documents 1 and 2 have only one shift direction. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2004-103226 A [Patent Document 2] JP 2005-050502 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a novel circuit or a driving method thereof. A new method for switching the shift direction of a shift register, which can be applied to at least a part of the shift register It is an object of the present invention to provide a new circuit or a driving method thereof.

[0007] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0008] One embodiment of the present invention is a semiconductor device including a shift register. The flip-flop has first to third flip-flops. The first flip-flop is a first arrangement. The second flip-flop has a function of being able to output a first signal to the second line. The third flip-flop has a function of outputting a second signal to the wiring. The third wiring has a function of outputting a third signal to the third wiring. The first signal is the second signal has a value that is synchronized to a second clock signal; The third signal has a value that is synchronized with the third clock signal. The group includes first to third transistors. One of the source and drain electrodes of the first transistor is electrically connected to a fourth wiring. The other of the first and second transistors is electrically connected to a second wiring. One of the source and drain electrodes of the second transistor is electrically connected to the first wiring. The other terminal is electrically connected to the gate of the first transistor. The source or drain of the third transistor is electrically connected to the fifth wiring. One of the first and second wirings is electrically connected to the third wiring. The other terminal is electrically connected to the gate of the first transistor. The fourth wiring is electrically connected to the sixth wiring. The fourth wiring transmits the second clock signal. The fifth wiring has a function of transmitting the first clock signal. The sixth wiring has a function of being able to transmit a third clock signal. .

[0009] One embodiment of the present invention is a semiconductor device including a shift register. The flip-flop has first to third flip-flops. The first flip-flop is a first arrangement. The second flip-flop has a function of being able to output a first signal to the second line. The third flip-flop has a function of outputting a second signal to the wiring. The third wiring has a function of outputting a third signal to the third wiring. The first signal is the second signal has a value that is synchronized to a second clock signal; The third signal has a value that is synchronized with the third clock signal. The group includes first to third transistors. One of the source and drain electrodes of the first transistor is electrically connected to a fourth wiring. The other of the first and second transistors is electrically connected to a second wiring. One of the source and drain electrodes of the second transistor is electrically connected to a fifth wiring. The other terminal is electrically connected to the gate of the first transistor. The source or drain of the third transistor is electrically connected to the first wiring. One of the first and second wirings is electrically connected to the sixth wiring. The other terminal is electrically connected to the gate of the first transistor. The fourth wiring is electrically connected to the third wiring. The fourth wiring transmits the second clock signal. The fifth wiring has a function of transmitting the first clock signal. The sixth wiring has a function of being able to transmit a third clock signal. .

[0010] One embodiment of the present invention is a semiconductor device including a shift register. The flip-flop includes a first flip-flop and a fifth flip-flop. The second flip-flop has a function of being able to output a first signal to the second line. The third flip-flop has a function of outputting a second signal to the wiring. The fourth flip-flop has a function of outputting a third signal to the third wiring. The fifth flip-flop has a function of outputting a fourth signal to the fourth wiring. The chip has a function of outputting a fifth signal to the fifth wiring. The first signal is The second signal has a value that is synchronized to the first clock signal. The third signal has a value that is synchronized to the third clock signal. The fourth signal is , the fifth signal has a value synchronized to the first clock signal. The third flip-flop has first to fifth transistors. One of the source and the drain of the first transistor is electrically connected to a sixth wiring. The other of the source and the drain of the first transistor is electrically connected to a third wiring. One of the source and the drain of the second transistor is electrically connected to the second wiring. The other of the source or drain of the second transistor is electrically connected to the gate of the first transistor. One of the source and the drain of the third transistor is electrically connected to the fourth wiring. The other of the source and drain of the third transistor is connected to the first transistor. The gate of the fourth transistor is electrically connected to one of the source and drain of the fourth transistor. At least one of the gates of the transistors is electrically connected to the first wiring. The other of the source and drain of the transistor is electrically connected to the gate of a second transistor. The fifth transistor is connected to the source or drain of the fifth transistor. At least one of the sources of the fifth transistor is electrically connected to a fifth wiring. The other of the drains is electrically connected to the gate of the third transistor. has a function capable of transmitting a third clock signal.

[0011] One embodiment of the present invention is a semiconductor device including a shift register. The flip-flop has first to third flip-flops. The first flip-flop is a first arrangement. The second flip-flop has a function of being able to output a first signal to the second line. The third flip-flop has a function of outputting a second signal to the wiring. The third wiring has a function of outputting a third signal to the third wiring. The first signal is the second signal has a value that is synchronized to a second clock signal; The third signal has a value that is synchronized with the third clock signal. The group includes first to fifth transistors. One of the source and drain electrodes of the first transistor is electrically connected to a fourth wiring. The other of the first and second transistors is electrically connected to a second wiring. One of the source and drain electrodes of the second transistor is electrically connected to the first wiring. The other terminal of the third transistor is electrically connected to the gate of the first transistor. One of the source and the drain of the third transistor is electrically connected to a third wiring. The other of the source and drain is electrically connected to the gate of the first transistor. At least one of the source or drain of the transistor and the gate of the fourth transistor One of the first and second wirings is electrically connected to the source or drain of the fourth transistor. The other end is electrically connected to the gate of the second transistor. At least one of the source or drain of the fifth transistor and the gate of the fifth transistor is connected to a third wiring. The other of the source and drain of the fifth transistor is electrically connected to the third transistor. The fourth wiring is electrically connected to the gate of the transistor. It has the function of being able to do this.

[0012] The W (W is the channel width) / L (L is the channel length) of the fourth transistor is It is preferable that the width is 0.8 times or more and 1.2 times or less than the W / L of the transistor.

[0013] The W (W is the channel width) / L (L is the channel length) of the second transistor is It is preferable that the width is 0.8 times or more and 1.2 times or less than the W / L of the transistor.

[0014] Note that the first transistor preferably includes an oxide semiconductor in a channel formation region. .

[0015] One aspect of the present invention is a display module including the semiconductor device and an FPC. be.

[0016] One embodiment of the present invention is a semiconductor device including the above-described semiconductor device or the above-described display module, a speaker, An electronic device having an operation button and / or an antenna. Effect of the Invention

[0017] One aspect of the present invention can provide a novel circuit or a driving method thereof. Novel circuitry applicable to at least a portion of a shift register capable of switching directions Alternatively, a driving method thereof can be provided.

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0019] [Figure 1]FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Diagram 2] 1 is a timing chart illustrating an operation of a device according to one embodiment of the present invention. [Diagram 3] 1 is a timing chart illustrating an operation of a device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Diagram 5] 1 is a timing chart illustrating an operation of a device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a schematic diagram illustrating an apparatus according to one embodiment of the present invention. [Figure 7] FIG. 1 is a schematic diagram illustrating an apparatus according to one embodiment of the present invention. [Figure 8] FIG. 1 is a schematic diagram illustrating an apparatus according to one embodiment of the present invention. [Figure 9] FIG. 1 is a schematic diagram illustrating an apparatus according to one embodiment of the present invention. [Figure 10] 1 is a timing chart illustrating an operation of a device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 19] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 20] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 21] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 22] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 23] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 24] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Diagram 25] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 26] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a circuit diagram illustrating a display device according to one embodiment of the present invention. [Figure 29] 1A to 1C illustrate a structural example of a transistor according to one embodiment of the present invention. [Diagram 30] 1A to 1C illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. [Diagram 31] 1A to 1C illustrate a structural example of a transistor according to one embodiment of the present invention. [Diagram 32] 1A to 1C illustrate a structural example of a transistor according to one embodiment of the present invention. [Diagram 33] FIG. 1 is a top view illustrating one embodiment of a display device. [Diagram 34] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Diagram 35] 1 is a projection diagram illustrating a configuration of an input / output device according to an embodiment. [Diagram 36] FIG. 1 is a cross-sectional view illustrating a configuration of an input / output device according to an embodiment. [Figure 37] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 38] FIG. 1 is a circuit diagram illustrating a device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the above embodiment, and the present invention is not limited to the above embodiment without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that various modifications may be made to the form and details of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0021] In addition, one aspect of the present invention is that any device including an integrated circuit, a display device, and an RF tag falls within the scope of the present invention. The display device includes a liquid crystal display device and a light-emitting device represented by an organic light-emitting device. Light-emitting devices with each pixel, electronic paper, DMD (Digital Micromirror ror device), PDP (Plasma Display Panel), FE D (Field Emission Display), etc. Display devices that display images in a 3D style are included in this category.

[0022] In describing the configuration of the invention using the drawings, the same reference numerals will be used in different drawings. But it is commonly used.

[0023] In this specification, etc., in a drawing or text described in a certain embodiment, It is possible to extract a part of the invention and use it as an embodiment of the invention. If a figure or text describing a certain part is included, the figure or text of that part is taken out. The above-mentioned contents are disclosed as one aspect of the invention and constitute one aspect of the invention. It is possible to say that one aspect of the invention is clear. For example, active elements (such as transistors), wiring, passive elements (such as capacitive elements), conductive layers , insulating layer, semiconductor layer, component, device, operation method, manufacturing method, etc. are described singularly or plurally. In the drawings or the text, it is assumed that a part can be extracted to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitor elements, etc.) to constitute an aspect of the invention. As another example, from the text stating that "A has B, C, D, E, or F", some elements can be arbitrarily extracted to form aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E". For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitor elements, etc.) to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitor elements, etc.) to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitor elements, etc.) to constitute an aspect of the invention. As another example, from the text stating that "A has B, C, D, E, or F", some elements can be arbitrarily extracted to form aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E". As another example, from the text stating that "A has B, C, D, E, or F", some elements can be arbitrarily extracted to form aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E". As another example, from the text stating that "A has B, C, D, E, or F", some elements can be arbitrarily extracted to form aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E". As another example, from the text stating that "A has B, C, D, E, or F", some elements can be arbitrarily extracted to form aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E".

[0024] Also, in this specification, etc., when at least one specific example is described in the drawings or text in a certain embodiment, it is easily understood by those skilled in the art to derive the upper concept of that specific example. Therefore, when at least one specific example is described in the drawings or text in a certain embodiment, the upper concept of that specific example is also disclosed as an aspect of the invention and can constitute an aspect of the invention. And that aspect of the invention can be said to be clear. Also, in this specification, etc., when at least one specific example is described in the drawings or text in a certain embodiment, it is easily understood by those skilled in the art to derive the upper concept of that specific example. Therefore, when at least one specific example is described in the drawings or text in a certain embodiment, the upper concept of that specific example is also disclosed as an aspect of the invention and can constitute an aspect of the invention. Also, in this specification, etc., when at least one specific example is described in the drawings or text in a certain embodiment, it is easily understood by those skilled in the art to derive the upper concept of that specific example. Therefore, when at least one specific example is described in the drawings or text in a certain embodiment, the upper concept of that specific example is also disclosed as an aspect of the invention and can constitute an aspect of the invention. And that aspect of the invention can be said to be clear.

[0025] Also, in this specification, etc., at least the content described in the drawings (even a part of the drawings) is disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for a certain content, if it is described in the drawings, even if it is not described in the text, that content is disclosed as an aspect of the invention and can constitute an aspect of the invention. Also, in this specification, etc., at least the content described in the drawings (even a part of the drawings) is disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for a certain content, if it is described in the drawings, even if it is not described in the text, that content is disclosed as an aspect of the invention and can constitute an aspect of the invention. Also, in this specification, etc., at least the content described in the drawings (even a part of the drawings) is disclosed as an aspect of the invention and can constitute an aspect of the invention. Similarly, a part of the drawings may be regarded as an embodiment of the invention. This is disclosed as one embodiment of the present invention. It can be said that one aspect of the invention is clear.

[0026] (Embodiment 1) In this embodiment, an apparatus according to one embodiment of the present invention will be described.

[0027] The device according to one embodiment of the present invention illustrated in FIG. 1 includes a circuit 100. The circuit 100 includes wiring CK1, wiring CK2, wiring CK3, wiring CK4, wiring SP1, wiring SP2 and N (N is 3 The input terminals 11 and 12 are connected to wirings OUT (a natural number not less than 100) (also referred to as wirings OUT[1] to [N]).

[0028] Wiring CK1, wiring CK2, wiring CK3, wiring CK4, wiring SP1, wiring SP2 and wiring O Each of UT[1] to [N] has the function of transmitting a signal, a potential, a current, etc. , wiring CK1, wiring CK2, wiring CK3, wiring CK4, wiring SP1, wiring SP2, and Each of the wirings OUT[1] to [N] functions as a signal line, a power line, or a current supply line. For example, each of the wiring CK1, the wiring CK2, the wiring CK3, and the wiring CK4 has A signal is input. The signal input to the wiring CK1 (signal V CK1 Also called), wiring CK2 The signal input to CK2 ), the signal input to the wire CK3 (signal V CK 3), and the signal input to the wiring CK4 (signal V CK4 (also called) There is a lock signal. However, the signal V CK1 to signal V CK4 are out of phase with each other. For example, a signal is input to each of the wirings SP1 and SP2. The signal input to SP1 (signal V SP1 ) and the signal (signal No. V SP2 As will be described later, the signal V SP1 and signal V SP2 The data shift direction can be controlled by the wiring. A signal is output from the circuit 100 to each of the wirings OUT[1] to [N]. The signals output to each of the terminals [1] to [N] (signal V OUT (also called [1] or [N]) As will be described later, the signal V OUT [1] to [N ] is the signal V SP1 Or signal V SP2 is a signal that is delayed with respect to

[0029] The circuit 100 has a function of controlling the potentials of the wirings OUT[1] to OUT[N]. , the circuit 100 receives the signal V SP1 The function to shift and the signal V SP2 It has the function to shift Then, the circuit 100 outputs the signal V SP1 A signal V that is delayed with respect to OUT [1]~[ N] to the wirings OUT[1] to [N], respectively, and a function of outputting the signal V SP2 Against Delayed signal V OUT [1] to [N] are output to wiring OUT[1] to [N], respectively. As shown in FIG. SP1 becomes high level (active) Then, the signal V SP1 is shifted in the direction from wiring OUT[1] to wiring OUT[N]. Therefore, the signal V OUT[1] is the signal V SP1 Delays the signal V OUT [i] (i is any one from 2 to N-1) is a signal V OUT [i-1], and the signal V O UT [N] is the signal V OUT [N-1]. Also, as shown in FIG. signal V SP2 When goes high (active), the signal V SP2 Is wiring OUT[N]? The signal V OUT [N] is the signal V SP2 Delays the signal V OUT [i] is the signal V OUT Delay for [i+1], signal V OUT [1] is the signal V OUT [2]. Thus, the circuit 100 , it functions as a shift register, particularly a bidirectional shift register. The shift direction is signal V SP1 Or signal V SP2 Select depending on which one is shifted. In addition, the signal V SP1 Or signal V SP2 Which of the signals is shifted depends on the signal V S P1 Or signal V SP2 However, the selection is made depending on which of the following is active. The functions of the path 100 are not limited to these.

[0030] Next, a configuration example of the circuit 100 will be described with reference to FIG. The circuit SR includes a plurality of circuits SR[1] to SR[N]. In the circuit SR[1], a terminal C1 is connected to wirings CK1 to CK2. The terminal C2 is connected to a corresponding one of the wirings CK1 to CK4. The terminal C3 is connected to a corresponding one of the wirings CK1 to CK4. Connected to one wire, terminal S1 is connected to wire SP1, and terminal S2 is connected to wire OUT[2] The circuit SR[i] is connected to the terminal S1, and the terminal O is connected to the wiring OUT[1]. The circuit SR[N] differs from the circuit SR[1] in that it is connected to the line OUT[i-1]. The point where the child S1 is connected to the wiring OUT[N-1], and the terminal S2 is connected to the wiring SP2 In this respect, the circuit SR[4m+1] (where m is 0 or a positive integer) differs from the circuit SR[1]. In this case, the terminal C1 is connected to the wiring CK1, the terminal C2 is connected to the wiring CK4, and the terminal C3 is connected to the wiring CK5. In the circuit SR[4m+2], the terminal C1 is connected to the wire CK2. The terminal C2 is connected to the wiring CK1, and the terminal C3 is connected to the wiring CK3. In R[4m+3], terminal C1 is connected to wire CK3, and terminal C2 is connected to wire CK2. The terminal C3 is connected to the wiring CK4. In this case, the terminal C1 is connected to the wiring CK4, the terminal C2 is connected to the wiring CK3, and the terminal C3 is connected to the wiring CK4. is connected to the wire CK1.

[0031] The circuit SR has a function of controlling the potential of the terminal O. Specifically, the circuit SR has a function of controlling the potential of the terminal S1 The circuit S R has the function of outputting a delayed signal from terminal O relative to the signal at terminal S1 and the function of outputting the signal at terminal S2. The function of the delay circuit is to output a delayed signal from terminal O relative to the signal. No. V SP1When the signal input to terminal S1 is shifted, the signal delayed with respect to the signal input to terminal S2 is shifted to terminal For example, in the circuit SR[i], the signal V OU T A signal V delayed with respect to [i-1] OUT [i] is output from terminal O. On the other hand, Fig. 3 As shown in the example, the signal V SP2 When the signal input to terminal S2 is shifted, For example, in the circuit SR[i], the terminal S2 is Input signal V OUT Signal V delayed with respect to [i+1] OUT [i] comes out of terminal O Thus, the circuit SR may be a sequential circuit, a flip-flop, or a shift register. However, the functions of the circuit SR are not limited to this. stomach.

[0032] Next, a specific example of the circuit SR will be described with reference to FIG. 101, transistor 102, transistor 103, transistor 104 and transistor The transistor 101 has a first terminal connected to the terminal C1 and a second terminal A first terminal of the transistor 102 is connected to the wiring VSS1. The first terminal of the transistor 103 is connected to the wiring VSS2. and a second terminal connected to the gate of the transistor 101. A first terminal of the transistor 4 is connected to the terminal S1, and a second terminal of the transistor 4 is connected to the gate of the transistor 101. The first terminal of the transistor 105 is connected to the terminal S2, and the gate of the transistor 105 is connected to the terminal S2. and a second terminal connected to the gate of the transistor 101, the gate of which is connected to the terminal C3. The gate of the transistor 101, the second terminal of the transistor 103, The second terminal of the transistor 104 or the second terminal of the transistor 105 is designated as a node ND1. vinegar.

[0033] Each of the transistors 101 to 105 has a first terminal (a source or drain The connection of the second terminal (also called the other of the source or drain) to the That is, the transistors 101 to 104 have a function of controlling electrical continuity between the transistors 101 to 104 and the connected terminals. Each of the transistors 105 functions as a switch. The functions of the transistors 01 to 105 are not limited to those described above.

[0034] Each of the wirings VSS1 and VSS2 has a function of transmitting a signal, a potential, or a current. In other words, each of the wiring VSS1 and the wiring VSS2 is a signal line, a power supply line, or a current supply line. For example, the wiring VSS1 and the wiring VSS2 each have a potential. The potential input to the wiring VSS1 and the wiring VSS2 is a signal V CK1 , signal V CK2 , signal V CK3 , or signal V CK4 Corresponding to low or high level of In particular, when the transistor 101 is an n-channel transistor, the wiring VSS1 and the wiring VSS2 is connected to the signal V CK1 , signal V CK2 , signal V CK3 , or signal V CK4 Rolex On the other hand, it is preferable that the transistor 101 is a P-channel In the case of a 1-type, the signal VSS1 and VSS2 are connected to the wiring CK1 , signal V CK2 ,signal V CK3 , or signal V CK4 It is preferable that a potential corresponding to the high level of the first input is input.

[0035] Note that the potential corresponding to the low level of the signal is equal to or approximately equal to the low level of the signal. However, the potential corresponding to the low level of the signal is lower than the high level of the signal. Alternatively, the potential may be lower than the intermediate potential between the high level and the low level of the signal. Similarly, the potential corresponding to the high level of the signal is a potential equal to or approximately equal to the high level of the signal. However, the potential corresponding to the high level of the signal is higher than the low level of the signal. Alternatively, the potential may be higher than the intermediate potential between the high level and the low level of the signal.

[0036] When the same potential is input to the wiring VSS1 and the wiring VSS2, SS2 may be integrated into one wiring. The first terminal of the transistor 103 may be connected to the same wiring.

[0037] Next, an example of the operation of the circuit SR illustrated in FIG. 4 will be described using the circuit SR[i] as an example. For convenience, the circuit SR[i] has a terminal C1 connected to the wire CK2, and a terminal C2 connected to the wire CK1. The terminal C1 is connected to the wiring CK2, and the terminal C2 is connected to the wiring CK3. The transistor 101, the transistor 104, and the transistor 105 are N-channel types. It shall be so.

[0038] When a signal delayed with respect to the signal at terminal S1 is output from terminal O, and when a signal delayed with respect to the signal at terminal S2 is output from terminal O, The case where a signal delayed by the delay is output from terminal O will be described separately.

[0039] First, let us consider an example of the operation when outputting a signal from terminal O that is delayed with respect to the signal from terminal S1. This will be described with reference to FIG.

[0040] An example of the operation of the circuit SR in the period A will be described. FIG. 1 is an example of a schematic diagram of an operation.

[0041] The signal at terminal C2 (signal V CK1 ) goes high, so transistor 104 is turned on. The signal at terminal C3 (signal V CK3 ) goes low, so transistor 105 Also, the transistor 103 is turned off. Therefore, the signal (high level) of the terminal S1 Bell Signal V OUT [i-1]) is supplied to node ND1, so the potential of node ND1 After that, the potential of the node ND1 becomes equal to the potential of the gate of the transistor 104 (terminal C 2 signal (high level signal V CK1 ) minus the threshold voltage of transistor 104 When node ND becomes equal to or approximately equal to 1 becomes floating.

[0042] Since the potential of the node ND1 becomes high, the transistor 101 is turned on. The transistor 102 is turned on. Therefore, the signal at the terminal C1 (the low-level signal V CK2 ) and Since the potential of the wiring VSS1 is supplied to the terminal O, the signal of the terminal O (signal V OUT [i]) becomes low level.

[0043] Note that a high potential value of the node ND1 means a potential value at which the transistor 101 is turned on. Specifically, the potential of the first terminal or the second terminal of the transistor 101 and the This is a value higher than the sum of the threshold voltage of the transistor 101 and the threshold voltage of the transistor 102.

[0044] Note that during the period A, the transistor 102 may be off.

[0045] An example of the operation of the circuit SR in the period B will be described. FIG. 1 is an example of a schematic diagram of an operation.

[0046] The signal at terminal C2 (signal V CK1 ) goes low, so transistor 104 is turned off. The signal at terminal C3 (signal V CK3 ) goes low, so transistor 105 The transistor 103 is turned off. Therefore, the node ND1 is in a floating state. Therefore, the potential of the node ND1 remains high.

[0047] Since the potential of the node ND1 becomes high, the transistor 101 is turned on. The transistor 102 is turned off. Therefore, the signal at the terminal C1 (the high-level signal V CK2 )but Since the voltage is supplied to the terminal O, the potential of the terminal O rises. The potential difference between the terminal O and the node ND1 is held by a parasitic capacitance between the gate and the second terminal of the transistor 101, and Therefore, when the potential of the terminal O rises, the node ND1 The potential of the node ND1 also rises. 1 signal (high level signal V CK2 )) and the threshold voltage of transistor 101. When the voltage at terminal O becomes high, the voltage at terminal C1 (high-level signal V CK2 ) Thus, the signal at terminal O (signal V OUT [i]) will be at a high level.

[0048] An example of the operation of the circuit SR in the period C will be described. FIG. 1 is an example of a schematic diagram of an operation.

[0049] The signal at terminal C2 (signal V CK1 ) goes low, so transistor 104 is turned off. The signal at terminal C3 (signal V CK3 ) goes high, so transistor 105 The transistor 103 is turned off. Therefore, the signal at the terminal S2 (high level Bell Signal V OUT [i+1]) is supplied to node ND1, so the potential of node ND1 After that, the potential of the node ND1 becomes equal to the potential of the gate of the transistor 105 (terminal C 3 signal (high level signal V CK3 ) minus the threshold voltage of transistor 105 When node ND becomes equal to or approximately equal to 1 becomes floating.

[0050] Since the potential of the node ND1 becomes high, the transistor 101 is turned on. The transistor 102 is turned on. Therefore, the signal at the terminal C1 (the low-level signal V CK2 ) and Since the potential of the wiring VSS1 is supplied to the terminal O, the signal of the terminal O (signal V OUT [i]) becomes low level.

[0051] During period C, the signal at terminal C1 (low-level signal V CK2 ) is supplied to a terminal O. Furthermore, the current supply capability of the transistor 101 is often large. Therefore, the signal at terminal O (signal V OUT [i]) can be made to have a shorter fall time.

[0052] In addition, the signal at terminal C1 (low-level signal V CK2 ) and the potential of the wiring VSS1 is When the potential of the terminal O drops due to the supply, the potential of the node ND1 also drops. The potential of the node ND1 becomes the potential of the gate of the transistor 105 (the signal of the terminal C3 (high level) signal V CK3 ) minus the threshold voltage of transistor 105, However, the transistor 105 is turned on so that the potential of the node ND1 is The potential of the gate of 105 (signal at terminal C3 (high-level signal V CK3 )) to Transis If the voltage Vcc is higher than the threshold voltage of transistor 105 minus the threshold voltage of transistor 105, transistor 105 will not turn on.

[0053] Note that during the period C, the transistor 102 may be off.

[0054] An example of the operation of the circuit SR in the period D will be described. FIG. 1 is an example of a schematic diagram of an operation.

[0055] The signal at terminal C2 (signal V CK1 ) goes low, so transistor 104 is turned off. The signal at terminal C3 (signal V CK3 ) goes low, so transistor 105 In addition, the transistor 103 is turned on. Since the potential at the node ND1 is supplied to the node ND1, the potential at the node ND1 drops.

[0056] Since the potential of the node ND1 becomes low, the transistor 101 is turned off. The transistor 102 is turned on. Therefore, the potential of the wiring VSS1 is supplied to the terminal O. The signal at terminal O (signal V OUT [i]) becomes low level.

[0057] Note that the low potential value of the node ND1 means a potential value at which the transistor 101 is turned off. Specifically, the potential of the first terminal or the second terminal of the transistor 101 and the The value is lower than the sum of the threshold voltage of the transistor 101 and the threshold voltage of the transistor 102.

[0058] In the period D, the transistor 102 may be off. In such a case, the terminal O Since it is floating, the signal at terminal O (signal V OUT [i]) remains at a low level.

[0059] In the period D, the transistor 103 may be turned off. In such a case, the node N Since D1 is in a floating state, the potential of the node ND1 remains high. Since the potential of the transistor 101 is high, the transistor 101 is turned on. CK2 is supplied to terminal O.

[0060] An example of the operation of the circuit SR in the period E will be described. FIG. 8A shows the operation of the circuit SR in the period E. 1 is an example of a schematic diagram of an operation.

[0061] The signal at terminal C2 (signal V CK1 ) goes high, so transistor 104 is turned on. The signal at terminal C3 (signal V CK3 ) goes low, so transistor 105 The transistor 103 is turned on. Therefore, the signal (low level) of the terminal S1 Bell Signal V OUT [i-1]) and the potential of the wiring VSS2 are supplied to the node ND1. Therefore, the potential of the node ND1 becomes a low value.

[0062] Since the potential of the node ND1 becomes low, the transistor 101 is turned off. The transistor 102 is turned on. Therefore, the potential of the wiring VSS1 is supplied to the terminal O. The signal at terminal O (signal V OUT [i]) becomes low level.

[0063] In the period E, the wiring VSS2 and the terminal S1 are connected to the transistors 103 and 104. Therefore, the potential of the wiring VSS2 is supplied to the wiring OUT[i-1]. Therefore, it is possible to reduce noise occurring in the wiring OUT[i-1].

[0064] Note that the transistor 102 may be off during the period E. In such a case, the terminal O Since it is floating, the signal at terminal O (signal V OUT [i]) remains at a low level.

[0065] Note that during the period E, the transistor 103 may be off.

[0066] An example of the operation of the circuit SR in the period F will be described. FIG. 8B shows the operation of the circuit SR in the period F. 1 is an example of a schematic diagram of an operation.

[0067] The signal at terminal C2 (signal V CK1 ) goes low, so transistor 104 is turned off. The signal at terminal C3 (signal V CK3 ) goes low, so transistor 105 In addition, the transistor 103 is turned on. Since the potential of the node ND1 is supplied to the node ND1, the potential of the node ND1 becomes a low value.

[0068] Since the potential of the node ND1 becomes low, the transistor 101 is turned off. The transistor 102 is turned on. Therefore, the potential of the wiring VSS1 is supplied to the terminal O. The signal at terminal O (signal V OUT [i]) becomes low level.

[0069] In the period F, the transistor 102 may be off. In such a case, the terminal O Since it is floating, the signal at terminal O (signal V OUT [i]) remains at a low level.

[0070] In the period F, the transistor 103 may be turned off. In such a case, the node N Since D1 is in a floating state, the potential of the node ND1 remains low.

[0071] An example of the operation of the circuit SR during the period G will be described. FIG. 9(A) shows the operation of the circuit SR during the period G. 1 is an example of a schematic diagram of an operation.

[0072] The signal at terminal C2 (signal V CK1 ) goes low, so transistor 104 is turned off. The signal at terminal C3 (signal V CK3 ) goes high, so transistor 105 Also, the transistor 103 is turned on. Therefore, the signal (low level) of the terminal S2 Bell Signal V OUT [i+1]) and the potential of the wiring VSS2 are supplied to the node ND1. Therefore, the potential of the node ND1 becomes a low value.

[0073] Since the potential of the node ND1 becomes low, the transistor 101 is turned off. The transistor 102 is turned on. Therefore, the potential of the wiring VSS1 is supplied to the terminal O. The signal at terminal O (signal V OUT [i]) becomes low level.

[0074] In the period G, the wiring VSS2 and the terminal S2 are connected to the transistors 103 and 105. Therefore, the potential of the wiring VSS2 is supplied to the wiring OUT[i+1]. Therefore, it is possible to reduce noise occurring in the wiring OUT[i+1].

[0075] In the period G, the transistor 102 may be off. In such a case, the terminal O Since it is floating, the signal at terminal O (signal V OUT [i]) remains at a low level.

[0076] Note that during the period G, the transistor 103 may be off.

[0077] An example of the operation of the circuit SR in the period H will be described. FIG. 9B shows the operation of the circuit SR in the period H. 1 is an example of a schematic diagram of an operation.

[0078] The signal at terminal C2 (signal V CK1 ) goes low, so transistor 104 is turned off. The signal at terminal C3 (signal V CK3 ) goes low, so transistor 105 In addition, the transistor 103 is turned on. Since the potential of the node ND1 is supplied to the node ND1, the potential of the node ND1 becomes a low value.

[0079] Since the potential of the node ND1 becomes low, the transistor 101 is turned off. Therefore, the potential of the wiring VSS1 is supplied to the terminal O. Signal (signal V OUT [i]) becomes low level.

[0080] In the period H, the transistor 102 may be off. In such a case, the terminal O Since it is floating, the signal at terminal O (signal V OUT [i]) remains at a low level.

[0081] In the period H, the transistor 103 may be turned off. In such a case, the node N Since D1 is in a floating state, the potential of the node ND1 remains low.

[0082] Next, an example of the operation when a signal delayed with respect to the signal at terminal S2 is output from terminal O will be described. The timing chart shown in FIG. 10 is a timing chart of the signal at the terminal S1. No. (Signal V OUT [i-1]) becomes high level during period C, and the signal at terminal S2 ( signal V OUT [i+1]) becomes high level in period A. The timing chart shown in FIG. 10 differs from the timing chart shown in FIG. No. (Signal V CK1 ) becomes high level during periods C and G, and the signal ( signal V CK3 ) is at a high level in periods A and E. However, a signal that is delayed with respect to the signal at terminal S1 is output from terminal O. The explanation of the operations common to those in the case of inputting is omitted here.

[0083] An example of the operation of the circuit SR in the period A will be described.

[0084] The signal at terminal C2 (signal V CK1 ) goes low, so transistor 104 is turned off. The signal at terminal C3 (signal V CK3 ) goes high, so transistor 105 The transistor 103 is turned off. Therefore, the signal at the terminal S2 (high level Bell Signal V OUT [i+1]) is supplied to node ND1, so the potential of node ND1 After that, the potential of the node ND1 becomes equal to the potential of the gate of the transistor 105 (terminal C 3 signal (high level signal V CK3 ) minus the threshold voltage of transistor 105 When node ND becomes equal to or approximately equal to 1 becomes floating.

[0085] Since the potential of the node ND1 becomes high, the transistor 101 is turned on. The transistor 102 is turned on. Therefore, the signal at the terminal C1 (the low-level signal V CK2 ) and Since the potential of the wiring VSS1 is supplied to the terminal O, the signal of the terminal O (signal V OUT [i]) becomes low level.

[0086] Note that during the period A, the transistor 102 may be off.

[0087] During period B, the circuit SR outputs a delayed signal from terminal O relative to the signal at terminal S1. The operation is the same as that in period B when inputting.

[0088] An example of the operation of the circuit SR in the period C will be described.

[0089] The signal at terminal C2 (signal V CK1 ) goes high, so transistor 104 is turned on. The signal at terminal C3 (signal V CK3 ) goes low, so transistor 105 Also, the transistor 103 is turned off. Therefore, the signal (high level) of the terminal S1 Bell Signal V OUT [i-1]) is supplied to node ND1, so the potential of node ND1 After that, the potential of the node ND1 becomes equal to the potential of the gate of the transistor 104 (terminal C 2 signal (high level signal V CK1 ) minus the threshold voltage of transistor 104 When node ND becomes equal to or approximately equal to 1 becomes floating.

[0090] Since the potential of the node ND1 becomes high, the transistor 101 is turned on. The transistor 102 is turned on. Therefore, the signal at the terminal C1 (the low-level signal V CK2 ) and Since the potential of the wiring VSS1 is supplied to the terminal O, the signal of the terminal O (signal V OUT [i]) becomes low level.

[0091] In addition, the signal at terminal C1 (low-level signal V CK2 ) and the potential of the wiring VSS1 is When the potential of the terminal O drops due to the supply, the potential of the node ND1 also drops. The potential of the node ND1 becomes equal to the potential of the gate of the transistor 104 (the signal (high level) of the terminal C2). signal V CK1 ) minus the threshold voltage of transistor 104, However, the transistor 104 is turned on so that the potential of the node ND1 is The potential of the gate of 104 (the signal at terminal C2 (high-level signal V CK1 )) to Transis If the voltage Vcc is higher than the threshold voltage of transistor 104 minus the threshold voltage of transistor 104, transistor 104 will not turn on.

[0092] Note that during the period C, the transistor 102 may be off.

[0093] During period D, the circuit SR outputs a delayed signal from terminal O relative to the signal at terminal S1. The operation is the same as that in period D when inputting.

[0094] During period E, the circuit SR operates by outputting a delayed signal from terminal O relative to the signal at terminal S1. The operation is the same as that in period G when inputting.

[0095] The operation of the circuit SR during the period F is to output a delayed signal from the terminal O with respect to the signal at the terminal S1. The operation is the same as that in period F or period H when the input is

[0096] During period G, the circuit SR operates by outputting a delayed signal from terminal O relative to the signal at terminal S1. The operation is the same as that in period E when inputting.

[0097] During period H, the circuit SR operates by outputting a delayed signal from terminal O relative to the signal at terminal S1. The operation is the same as that in period F or period H when the input is

[0098] Next, an example of a preferred embodiment of the device according to the present invention will be described.

[0099] It is preferable that the transistors 101 to 105 have the same polarity. Preferably, the transistors 101 to 105 are N-channel transistors. Alternatively, the transistors 101 to 105 are preferably P-channel transistors. This allows the manufacturing process to be simplified, improving yield and / or In particular, the transistors 101 to 105 can be In the case of an N-channel type, the transistors 101 to 105 are A transistor having an oxide semiconductor in a formation region (also called an OS transistor) is The OS transistor has amorphous silicon in the channel formation region. The mobility is higher and the off-state current is extremely small compared to that of a transistor having a The sizes of the transistors 101 to 105 can be reduced.

[0100] The first conductor (also referred to as a conductive film or a conductive layer) is a first The second conductor has a region that serves as a terminal (either a source electrode or a drain electrode). This serves as the second terminal (the other of the source electrode and the drain electrode) on the terminal O side of the transistor 101. The third conductor has a region that becomes the gate (gate electrode) of the transistor 101. The third conductor has a first region overlapping the first conductor and a second conductor. and a second region overlapping the first region. In such a case, the area of ​​the second region is This allows the second terminal of the transistor 101 to be connected to the gate Since the capacitance between the node ND1 and the The increase can be made larger.

[0101] The first region is an area where the third conductor and the first conductor overlap with each other without a semiconductor layer therebetween. The second region may be an area where the third conductor and the second conductor overlap without a semiconductor layer therebetween. The semiconductor layer is a semiconductor layer having a channel formation region of the transistor 101.

[0102] The W (channel width) / L (channel length) of the transistor 101 is It is preferable that W / L of transistor 101 is larger than W / L of transistor 103. It is preferable that the W / L of transistor 101 is greater than the W / L of transistor 104. The W / L of transistor 101 is preferably greater than the W / L of transistor 10 It is preferable that the W / L of the transistors 101 to 105 is larger than that of the transistors 101 to 105. It is preferable that the W / L of the transistor 101 is the largest among the transistors 105. Since the current supply capacity of the transistor 101 can be increased, the rising edge of the signal at the terminal O The rise and fall times can be shortened.

[0103] When a transistor is composed of multiple transistors, the W / L is the sum of the W / L of multiple transistors. For example, When transistors are connected in parallel, W is the sum of the W of the multiple transistors, and L is the sum of the W of the multiple This is the average value of the transistor's L.

[0104] The W / L of transistor 104 is equal or approximately equal to the W / L of transistor 105. It is preferable that the W / L of the transistor 104 is approximately equal to the W / L of the transistor 105. This means that the W / L of transistor 104 is 0.8 times or more than the W / L of transistor 105, and 1. It is more preferable that the ratio is 0.9 to 1.1 times. Therefore, the circuit SR shifts the signal at terminal S1 and the signal at terminal S2. However, the same operation can be performed.

[0105] Here, the circuit SR is not limited to the configuration illustrated in Fig. 4. Modifications of the circuit SR illustrated in Fig. 4 Here, the same reference numerals are used for the parts common to FIG. 4, and the explanation thereof is omitted. do.

[0106] In the circuit SR of this embodiment, which will be described with reference to FIG. 4 or the like, or which will be described without reference to the drawings, The first terminal of the transistor 103 is connected to the wiring VSS1, the terminal S1, the terminal S2, the terminal C1, and the terminal C 2, may be connected to terminal C3, terminal C4, terminal S3, terminal S4 or terminal O. Terminal C4 11A shows the terminal S3 and the terminal S4 in FIG. In the example shown in FIG. 11B, the first terminal of the resistor 103 is connected to the wiring VSS1. 4, the first terminal of the transistor 103 is connected to the terminal S2. In FIG. 12A, the first terminal of the transistor 103 in FIG. 4 is the terminal S1. The connected configuration is illustrated.

[0107] 4, 11(A), 11(B), 12(A), etc., or not shown in the drawings. In the circuit SR of the present embodiment described in , the first terminal of the transistor 104 is connected to the wiring V SS2, terminal S1, terminal S2, terminal C1, terminal C2, terminal C3, terminal C4, terminal S3 or 12B, the transistor 102 in FIG. FIG. 13A illustrates a configuration in which the first terminal is connected to the terminal S2. A configuration in which a first terminal of the transistor 102 is connected to a terminal S1 is illustrated.

[0108] In Figs. 4, 11(A), 11(B), 12(A), 12(B) and 13(A), etc. In the circuit SR of this embodiment, which may or may not be shown in the figure, the transistor The gate of the transistor 102 may be connected to the gate of the transistor 103. In FIG. 4, the gate of the transistor 102 is connected to the gate of the transistor 103. The following shows an example of such a configuration.

[0109] 4, 11(A), 11(B), 12(A), 12(B), 13(A) and In the circuit SR of this embodiment, which will be described as shown in FIG. 13(B) or described without being shown in FIG. At least one of a first terminal and a gate of the transistor 104 is connected to the terminal S1. In addition, at least one of the first terminal and the gate of the transistor 105 may be 14A shows the transistor 10 in FIG. The gate of transistor 4 is connected to terminal S1, and the gate of transistor 105 is connected to terminal S2. FIG. 14B shows a configuration in which the first terminal of the transistor 104 in FIG. The gate of the transistor 104 is connected to the terminal S1, and the gate of the transistor 105 is connected to the terminal C2. A first terminal of the transistor 105 is connected to the terminal C3, and a gate of the transistor 105 is connected to the terminal S2. The following configuration is illustrated.

[0110] 4, 11(A), 11(B), 12(A), 12(B), 13(A), and In the circuit SR of this embodiment, which will be described with reference to FIG. 13(B) or without reference to FIG. In addition, a configuration for controlling the potential of the gate of the transistor 104 may be added. A configuration for controlling the potential of the gate of the transistor 105 may be added. 4, transistors 106, 107, and 108 are The transistor 106 is connected to the first terminal of the The first terminal is connected to the terminal C4, the second terminal is connected to the gate of the transistor 104, and the gate A first terminal of the transistor 107 is connected to the wiring VSS3. , the second terminal is connected to the gate of the transistor 104, and the gate is connected to the terminal C1. The transistor 108 has a first terminal connected to the terminal C4 and a second terminal connected to the transistor The gate of the transistor 109 is connected to the gate of the first transistor 105 and the gate of the transistor 109 is connected to the terminal S4. The first terminal is connected to the wiring VSS4, and the second terminal is connected to the gate of the transistor 105. and the gate is connected to terminal C1.

[0111] Each of the wiring VSS3 and the wiring VSS4 has a function of transmitting a signal, a potential, or a current. In other words, each of the wiring VSS3 and the wiring VSS4 is a signal line, a power supply line, or a current supply line. For example, the wiring VSS3 and the wiring VSS4 each have a potential. The potential input to the wiring VSS3 and the wiring VSS4 is a signal V CK1 , signal V CK2 , signal V CK3 , or signal V CK4 Corresponding to low or high level of In particular, if the transistors 104 and 105 are N-channel transistors, , the wiring VSS3 and the wiring VSS4 are connected to the signal V CK1 , signal V CK2 , signal V CK3 ,also is the signal V CK4 It is preferable that a potential corresponding to the low level of the transistor is input. If the transistor 104 and the transistor 105 are P-channel type, the wiring VSS3 and the wiring V SS4 has a signal V CK1 , signal V CK2 , signal V CK3 , or signal V CK4 High level It is preferable that a potential corresponding to the voltage Vcc is input.

[0112] It is preferable that the terminal S3 is connected to the wiring OUT[i-2]. The terminal C4 is preferably connected to a corresponding one of the wirings CK1 to CK4. It is preferable to connect it to one wire. Specifically, the terminal C4 of the circuit SR[4m+1] is connected to the wire CK3, and the terminal C4 of the circuit SR[4m+2] is connected to the wire CK4, Terminal C4 of circuit SR[4m+3] is connected to wire CK1, and terminal C For example, the terminal C1 is connected to the wiring CK2, and the terminal C2 is connected to the wiring CK3. When terminal C3 is connected to line CK3, terminal C4 is connected to line CK4. Connected.

[0113] An example of the operation of the circuit SR shown in FIG. 15(A) will be described. Only one example of the operation when a signal delayed with respect to the signal is output from terminal O will be described.

[0114] An example of the operation of the circuit SR in the period H immediately before the period A will be described.

[0115] The signal at terminal S3 (signal V OUT [i-2]) goes high, so transistor 10 6 is turned on. Also, the signal at terminal C1 (signal V CK2 ) will be at a low level, Therefore, the signal at the terminal C4 (high-level signal V CK4 )but Since the potential of the gate of the transistor 104 is supplied to the gate of the transistor 104, The potential of the gate of the transistor 104 rises to the potential of the gate of the transistor 106 (terminal S3 signal (high level signal V OUT [i-2]) to the threshold voltage of transistor 106 When the voltage drops to a lower value, transistor 106 turns off. The gate of the transistor becomes floating.

[0116] The signal at terminal S4 (signal V OUT [i+2]) goes low, so transistor 10 8 is turned off. Also, the signal at terminal C1 (signal V CK2 ) will be at a low level, Transistor 109 is turned off, so the gate of transistor 105 is left floating. When the initial value of the potential of the gate of the transistor 105 is a low value, The gate potential remains low.

[0117] Since the potential of the gate of the transistor 104 becomes high, the transistor 104 is turned on. In addition, the potential of the gate of the transistor 105 becomes low. Therefore, the signal at terminal S1 (low-level signal V OUT [i-1]) is no The input is supplied to ND1.

[0118] An example of the operation of the circuit SR in the period A will be described.

[0119] The signal at terminal S3 (signal V OUT [i-2]) goes low, so transistor 10 6 is turned off. Also, the signal at terminal C1 (signal V CK2 ) will be at a low level, Therefore, the gate of the transistor 104 is floating. Therefore, the potential of the gate of the transistor 104 is maintained at a high value.

[0120] The signal at terminal S4 (signal V OUT [i+2]) goes low, so transistor 10 8 is turned off. The signal at terminal C1 (signal V CK2 ) goes low, so the transistor Therefore, the gate of the transistor 105 is in a floating state, and the transistor 109 is turned off. The potential of the gate of transistor 105 remains low.

[0121] Since the potential of the gate of the transistor 104 becomes high, the transistor 104 is turned on. In addition, the potential of the gate of the transistor 105 becomes low. Therefore, the signal at terminal S1 (high-level signal V OUT [i-1]) is no The potential of the node ND1 is increased. The potential difference between the second terminal and the gate of the transistor 104 is due to the parasitic capacitance between the gate of the transistor 104 and the second terminal. The gate of the transistor 104 is held in a floating state. When the potential of ND1 rises, the potential of the gate of transistor 104 also rises. The potential of the gate of the transistor 104 is equal to the potential of the first terminal of the transistor 104 (the signal ( A high-level signal V OUT [i-1]) and the threshold voltage of transistor 104. When this happens, the potential of the node ND1 becomes a high-level signal V OUT Increase to the same value as [i-1] This increases the potential difference between the gate and the second terminal of the transistor 104. Therefore, the drain current of the transistor 104 can be increased. This can shorten the rise time of the potential of the node ND1. Since the size of the capacitor 104 can be reduced, the layout area can be reduced. Cut.

[0122] An example of the operation of the circuit SR in the period B will be described.

[0123] The signal at terminal S3 (signal V OUT [i-2]) goes low, so transistor 10 6 is turned off. The signal at terminal C1 (signal V CK2 ) becomes high level, Therefore, the potential of the wiring VSS3 is supplied to the gate of the transistor 104. As a result, the potential at the gate of transistor 104 drops.

[0124] The signal at terminal S4 (signal V OUT [i+2]) goes low, so transistor 10 8 is turned off. The signal at terminal C1 (signal V CK2 ) becomes high level, Therefore, the potential of the wiring VSS4 is supplied to the gate of the transistor 105. Therefore, the potential of the gate of the transistor 105 becomes low.

[0125] The potential of the gate of the transistor 104 becomes low, so that the transistor 104 is turned off. Since the potential of the gate of the transistor 105 becomes low, the transistor 105 is turned off. become.

[0126] An example of the operation of the circuit SR in the period C will be described.

[0127] The signal at terminal S3 (signal V OUT [i-2]) goes low, so transistor 10 6 is turned off. The signal at terminal C1 (signal V CK2 ) goes low, so the transistor Therefore, the gate of the transistor 104 is in a floating state, and the transistor 107 is turned off. The potential of the gate of the transistor 104 remains low.

[0128] The signal at terminal S4 (signal V OUT[i+2]) goes low, so transistor 10 8 is turned off. The signal at terminal C1 (signal V CK2 ) goes low, so the transistor Therefore, the gate of the transistor 105 is floating, and the transistor The potential of the gate of transistor 105 remains low.

[0129] The potential of the gate of the transistor 104 becomes low, so that the transistor 104 is turned off. Since the potential of the gate of the transistor 105 becomes low, the transistor 105 is turned off. become.

[0130] An example of the operation of the circuit SR in the period D will be described.

[0131] The signal at terminal S3 (signal V OUT [i-2]) goes low, so transistor 10 6 is turned off. The signal at terminal C1 (signal V CK2 ) goes low, so the transistor Therefore, the gate of the transistor 104 is in a floating state, and the transistor 107 is turned off. The potential of the gate of the transistor 104 remains low.

[0132] The signal at terminal S4 (signal V OUT [i+2]) goes high, so transistor 10 8 is turned on. The signal at terminal C1 (signal V CK2 ) goes low, so the transistor Therefore, the signal at terminal C4 (high-level signal V CK4 ) is Tran Since the potential at the gate of transistor 105 is supplied to the gate of transistor 105, the potential at the gate of transistor 105 rises. .

[0133] The potential of the gate of the transistor 104 becomes low, so that the transistor 104 is turned off. Since the potential of the gate of the transistor 105 becomes high, the transistor 105 is turned on. Therefore, the signal at terminal S2 (low-level signal V OUT [i+1]) is the node ND 1 is supplied.

[0134] An example of the operation in period E immediately following period D will be described.

[0135] The signal at terminal S3 (signal V OUT [i-2]) goes low, so transistor 10 6 is turned off. The signal at terminal C1 (signal V CK2 ) goes low, so the transistor Therefore, the gate of the transistor 104 is in a floating state, and the transistor 107 is turned off. The potential of the gate of the transistor 104 remains low.

[0136] The signal at terminal S4 (signal V OUT [i+2]) goes low, so transistor 10 8 is turned off. The signal at terminal C1 (signal V CK2 ) goes low, so the transistor Therefore, the gate of the transistor 105 is floating, and the transistor The potential of the gate of transistor 105 remains high.

[0137] The potential of the gate of the transistor 104 becomes low, so that the transistor 104 is turned off. Since the potential of the gate of the transistor 105 becomes high, the transistor 105 is turned on. Therefore, the signal at terminal S2 (low-level signal V OUT [i+1]) is the node ND 1 is supplied.

[0138] The operations in period E, except for the period immediately following period D, are similar to those in period C.

[0139] The operation during period F is similar to the operation during period B.

[0140] The operation during period G is similar to the operation during period C.

[0141] The operations during period H, except for the period immediately before period A, are similar to those during period C.

[0142] At least one of the first terminal and the gate of the transistor 106 is connected to the terminal S3. In addition, the transistor 108 may have at least one of the first terminal and the gate. The only requirement is that the first terminal be connected to the terminal S4. A first terminal of the transistor 106 is connected to the terminal S3, and a first terminal of the transistor 108 is 16A shows an example of a configuration in which the transistor S1 shown in FIG. A first terminal of the transistor 106 is connected to the terminal S3, and a gate of the transistor 106 is connected to the terminal C4. A first terminal of the transistor 108 is connected to the terminal S4, and a second terminal of the transistor 108 is connected to the terminal S5. A configuration in which the gate is connected to terminal C4 is illustrated.

[0143] At least one of the first terminal and the gate of the transistor 106 is connected to the terminal S1. In addition, at least one of the first terminal and the gate of the transistor 108 may be connected to the terminal S 16B shows a case where the transistor 106 in FIG. A first terminal is connected to the terminal C2, and a gate of the transistor 106 is connected to the terminal S1. A first terminal of the transistor 108 is connected to the terminal C3, and a gate of the transistor 108 is FIG. 17(A) shows a configuration in which the transistor S1 is connected to the terminal S2 in FIG. A first terminal of the transistor 106 is connected to the terminal S1, and a gate of the transistor 106 is connected to the terminal a first terminal of the transistor 108 is connected to terminal S2; and a second terminal of the transistor 108 is connected to terminal S3. FIG. 17B illustrates a configuration in which the gate of 108 is connected to the terminal S2. ), a first terminal of the transistor 106 is connected to the terminal S1, and a second terminal of the transistor 10 A gate of transistor 6 is connected to terminal C2, and a first terminal of transistor 108 is connected to terminal S2. In this example, the gate of the transistor 108 is connected to the terminal C3.

[0144] The first terminal of the transistor 107 is connected to the wiring VSS1, the wiring VSS2, and the wiring VSS4. , terminal S1, terminal S2, terminal S3, terminal S4, terminal C2, terminal C3 or terminal C4. The first terminal of the transistor 109 may be connected to a wiring VSS1, a wiring VSS2, Wiring VSS3, terminal S1, terminal S2, terminal S3, terminal S4, terminal C2, terminal C3 or terminal 15A, the transistor 10 may be connected to the transistor C4. A first terminal of transistor 7 is connected to terminal S3, and a first terminal of transistor 109 is connected to terminal S4. FIG. 18B shows an example of a structure in which the transistor 10 in FIG. A first terminal of the transistor 7 is connected to the line VSS1, and a first terminal of the transistor 109 is connected to the line VS The following illustrates a configuration in which the S1 is connected:

[0145] Note that the W / L of the transistor 106 is equal or approximately equal to the W / L of the transistor 108. It is preferable that the W / L of the transistor 106 is approximately equal to the W / L of the transistor 108. The W / L of the transistor 106 is 0.8 times or more the W / L of the transistor 108. It means 1.2 times or less, and more preferably 0.9 times or more and 1.1 times or less.

[0146] The W / L of the transistor 107 is equal to or approximately equal to the W / L of the transistor 109. It is preferable that the W / L of the transistor 107 is approximately equal to the W / L of the transistor 109. By "correct," it is meant that the W / L of transistor 107 is approximately equal to the W / L of transistor 109. , the W / L of the transistor 107 is 0.8 times or more and 1.2 times the W / L of the transistor 109. More preferably, it is 0.9 times or more and 1.1 times or less.

[0147] The transistors 106 to 109 have the same polarity as the transistor 101. It is preferable that there is.

[0148] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), As shown in Figs. 16(B), 17(A), 17(B), 18(A) and 18(B), etc. In the circuit SR of this embodiment, which will be described below or will not be shown in the figure, a terminal O and a node ND 1. In FIG. 19(A), a transistor may be added between the transistor 1 in FIG. The transistor 110 has a first terminal connected to the terminal O. The first terminal is connected to the node ND1, and the gate is connected to the terminal C1.

[0149] Note that the transistor 110 preferably has the same polarity as the transistor 101 .

[0150] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), 16(B), 17(A), 17(B), 18(A), 18(B) and 19( In the circuit SR of this embodiment, which is described as shown in FIG. A transistor may be added between C1 and node ND1. In the example shown, a transistor 111 is added to the first The first terminal is connected to the terminal C1, and the second terminal is connected to the node ND1.

[0151] Note that the transistor 111 preferably has the same polarity as the transistor 101 .

[0152] In addition, a signal is input to the gate of the transistor 111, and the transistor 11 1 may be controlled to be on or off.

[0153] The gate of the transistor 111 may be connected to the gate of the transistor 102. Alternatively, the gate of the transistor 111 may be connected to the gate of the transistor 103. Alternatively, the gate of the transistor 111 may be connected to the gate of the transistor 102 and the It may be connected to the gate of the resistor 103.

[0154] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), Figure 16(B), Figure 17(A), Figure 17(B), Figure 18(A), Figure 18(B), Figure 19(A ) and the circuit SR In the example shown in FIG. 2, a transistor may be added that is connected in series with the transistor 103. 0(A) illustrates a configuration in which a transistor 112 is added to the configuration of FIG. The first terminal of the transistor 112 is connected to the second terminal of the transistor 103, and the second terminal of the transistor 112 is connected to the second terminal of the transistor 103. It is connected to node ND1.

[0155] Note that the transistor 112 preferably has the same polarity as the transistor 101 .

[0156] In addition, a signal is input to the gate of the transistor 112, and the transistor 11 2 may be controlled to be on or off.

[0157] The transistor 112 is connected between the first terminal of the transistor 101 and the wiring VSS1. It may be connected.

[0158] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), Figure 16(B), Figure 17(A), Figure 17(B), Figure 18(A), Figure 18(B), Figure 19(A 19(B) and 20(A) and the like, or the present embodiment described without being shown in the drawings. In the circuit SR of the above embodiment, a transistor connected in series with the transistor 102 is added. FIG. 20B illustrates a configuration in which a transistor 113 is added to the configuration in FIG. The first terminal of the transistor 113 is connected to the second terminal of the transistor 102. , the second terminal is connected to terminal O.

[0159] Note that the transistor 113 preferably has the same polarity as the transistor 101 .

[0160] In addition, a signal is input to the gate of the transistor 113, and the transistor 11 3 may be controlled to be on or off.

[0161] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), Figure 16(B), Figure 17(A), Figure 17(B), Figure 18(A), Figure 18(B), Figure 19(A 19(B), 20(A) and 20(B), etc., or In the circuit SR of the present embodiment, the gate of transistor 101 and the gate of transistor 1 A transistor connected between the connection point of the second terminal of transistor 104 and the second terminal of transistor 105. In FIG. 21A, the transistor 114 is added to the circuit shown in FIG. The transistor 114 has a first terminal connected to the gate of the transistor 101. The second terminal of the transistor 104 is connected to the first terminal of the transistor 105. 2 and the second terminal of the transistor 103.

[0162] Note that the transistor 114 preferably has the same polarity as the transistor 101 .

[0163] As illustrated in FIG. 21B, the second terminal of the transistor 103 is connected to a transistor 114。 114 may be connected to the first terminal.

[0164] The gate of the transistor 114 may be connected to the terminal C1. A potential corresponding to the high level of the signal at the terminal C1 may be input to the gate of the transistor 114.

[0165] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), Figure 16(B), Figure 17(A), Figure 17(B), Figure 18(A), Figure 18(B), Figure 19(A ), FIG. 19(B), FIG. 20(A), FIG. 20(B), FIG. 21(A) and FIG. 21(B), etc. In the circuit SR of the present embodiment, which may or may not be shown in the figure, transistor 1 The gate of MOSFET 03 may be connected to terminal S3, terminal S4, or terminal C4. 4, the gate of the transistor 103 is connected to the terminal C4. do.

[0166] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), Figure 16(B), Figure 17(A), Figure 17(B), Figure 18(A), Figure 18(B), Figure 19(A ), FIG. 19(B), FIG. 20(A), FIG. 20(B), FIG. 21(A), FIG. 21(B) and FIG. In the circuit SR of this embodiment, which will be described as shown in FIG. 2(A) or described without being shown in the figure, A configuration for controlling the gate potential of the transistor 103 may be added. In FIG. 4, a configuration in which a transistor 115 and a transistor 116 are added is illustrated. The transistor 115 has a first terminal connected to the terminal C4 and a second terminal connected to the The transistor 116 is connected to the gate of the transistor 103 and the gate of the transistor 116 is connected to the terminal C4. A first terminal of the second transistor is connected to the wiring VSS2 and a second terminal of the second transistor is connected to the gate of the transistor 103. The gate of the first transistor is connected to a node ND1.

[0167] During periods A, B, and C, the signal at terminal C4 (signal V CK4 ) becomes low level Therefore, the transistor 115 is turned off. The transistor 116 is turned on. Therefore, the potential of the wiring VSS2 is Since the potential of the gate of the transistor 103 is supplied to the Since the potential of the gate of the transistor 103 becomes low, the transistor 103 is turned off.

[0168] During period D, the signal at terminal C4 (signal V CK4 ) becomes high level, The potential of the node ND1 becomes low, so the transistor 116 turns on. Therefore, the signal at terminal C4 (high-level signal V CK4 ) is transistor 10 Since the potential of the gate of the transistor 103 is supplied to the gate of the transistor 103, the potential of the gate of the transistor 103 becomes high. Since the potential of the gate of the transistor 103 becomes high, the transistor 103 is turned on.

[0169] During periods E, F, and G, the signal at terminal C4 (signal V CK4 ) becomes low level Therefore, the transistor 115 is turned off. The transistor 116 is turned off. Therefore, the gate of the transistor 103 is in a floating state. Therefore, the potential of the gate of the transistor 103 is maintained at a high value. Since the potential of the gate becomes high, the transistor 103 is turned on.

[0170] During period H, the signal at terminal C4 (signal V CK4 ) becomes high level, The potential of the node ND1 becomes low, so the transistor 116 turns on. Therefore, the signal at terminal C4 (high-level signal V CK4 ) is transistor 10 Since the potential of the gate of the transistor 103 is supplied to the gate of the transistor 103, the potential of the gate of the transistor 103 becomes high. Since the potential of the gate of the transistor 103 becomes high, the transistor 103 is turned on.

[0171] At least one of the first terminal and the gate of the transistor 115 is connected to the terminal C4. For example, the first terminal of the transistor 115 may be connected to the terminal C4. The gate of transistor 115 is connected to the signal V CK1 , signal V CK2 , signal V CK3 , or signal V C K4 The high level of the input terminal 14 may be connected to a wiring (not shown) to which a potential corresponding to the high level of the input terminal 14 is input.

[0172] The gate of the transistor 116 is connected to the terminals C1, C2, C3, S1, and 22(B) may be connected to the terminal S2 or the terminal O. FIG. 23B shows a configuration in which the gate of the transistor 116 is connected to the terminal S1. 2(B), the gate of the transistor 116 is connected to the terminal C1. .

[0173] The first terminal of the transistor 116 is connected to the wiring VSS1, the wiring VSS3, and the wiring VSS4. , may be connected to terminal S3, terminal S4 or terminal C4.

[0174] The transistors 115 and 116 have the same polarity as the transistor 101. It is preferable that there is.

[0175] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), Figure 16(B), Figure 17(A), Figure 17(B), Figure 18(A), Figure 18(B), Figure 19(A ), Fig. 19(B), Fig. 20(A), Fig. 20(B), Fig. 21(A), Fig. 21(B), Fig. 22 22(B), 23(A), 23(B), etc., or In the circuit SR of the present embodiment, which will be described later, the gate of the transistor 102 is connected to the terminal S1. , terminal S2, terminal S3, terminal S4, terminal C2, terminal C3, or terminal C4. FIG. 24A shows a configuration in which the gate of the transistor 102 in FIG. 4 is connected to the terminal C4. FIG. 24B shows a structure in which the gate of the transistor 102 in FIG. The configuration in which the slave S1 is connected is illustrated.

[0176] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), Figure 16(B), Figure 17(A), Figure 17(B), Figure 18(A), Figure 18(B), Figure 19(A ), Fig. 19(B), Fig. 20(A), Fig. 20(B), Fig. 21(A), Fig. 21(B), Fig. 22 (A), Fig. 22(B), Fig. 23(A), Fig. 23(B), Fig. 24(A) and Fig. 24(B), etc. In the circuit SR of this embodiment, which is described with or without illustration, each transistor If multiple configurations are applicable to a server, the server must have a configuration that supports two or more of the multiple configurations. In other words, a transistor may have a first configuration and a second configuration. When the third configuration is applicable, the transistor corresponding to the first configuration, the transistor corresponding to the second configuration, Two or more of the transistors corresponding to the third configuration and the transistors corresponding to the third configuration A transistor may also be provided.

[0177] For example, the first terminal of the transistor 103 is connected to the wiring VSS2 ( 4), a configuration in which it is connected to the wiring VSS1 (see FIG. 11(A)), and a configuration in which it is connected to the terminal S2 (see FIG. 11B), (see FIG. 12A), and (see FIG. 12B) 1, a configuration connected to terminal C2, a configuration connected to terminal C3, and a configuration connected to terminal C4 A configuration connected to terminal S3, a configuration connected to terminal S4, a configuration connected to terminal O FIG. 25(A) shows a circuit SR shown in FIG. A transistor 103A corresponding to the transistor 103 having a first terminal connected to the terminal S2 , and a transistor 103 having a first terminal connected to the terminal S1. 03B is provided.

[0178] For example, the gate of the transistor 103 is connected to the terminal S3, and the gate of the transistor 104 is connected to the terminal S4. A configuration connected to terminal C1, a configuration connected to terminal C2, a configuration connected to terminal C3, and a configuration connected to terminal C 25(B) shows a configuration in which the circuit shown in FIG. In the circuit SR, a transistor corresponding to the transistor 103 whose gate is connected to the terminal S2 is A transistor 103C, and a transistor corresponding to the transistor 103 whose gate is connected to the terminal S1. 10 illustrates a configuration in which a resistor 103D is provided.

[0179] For example, the gate of the transistor 116 is connected to the node ND1 (see FIG. 2). 2(B)), a configuration in which the terminal C1 is connected (see FIG. 23(B)), a configuration in which the terminal C2 is connected (see FIG. 23(B)), a configuration connected to terminal C3; a configuration connected to terminal S1 (see FIG. 23(A)); There are two configurations: one for connection to terminal S2 and one for connection to terminal O. In the circuit SR illustrated in FIG. 1B, a transistor 116 having a gate connected to a terminal S1 and a transistor 116A having a gate connected to the terminal S2. 6 is provided.

[0180] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), Figure 16(B), Figure 17(A), Figure 17(B), Figure 18(A), Figure 18(B), Figure 19(A ), Fig. 19(B), Fig. 20(A), Fig. 20(B), Fig. 21(A), Fig. 21(B), Fig. 22 (A), Fig. 22(B), Fig. 23(A), Fig. 23(B), Fig. 24(A), Fig. 24(B), Fig. 25(A), 25(B), 26(A), etc., or described without being shown in the drawings. All or part of the circuits SR of this embodiment can be combined.

[0181] For example, in FIG. 26B, the transistor 103 in FIG. The first terminal is connected to the wiring VSS1, and the transistors 106 to 109 are connected to the wiring VSS2 as shown in FIG. A transistor 109 is added, and the first terminal of the transistor 107 is connected to the The first terminal of the transistor 109 is connected to the wiring VSS1 as shown in FIG. The configuration in which the signal is connected to VSS1 is illustrated.

[0182] For example, in FIG. 27A, the transistor 110 in FIG. 4 is replaced with the transistor 110 in FIG. 19B illustrates a configuration in which a transistor 111 is added.

[0183] For example, in FIG. 27B, the transistor 104 in FIG. The gate of the transistor 105 is connected to the terminal S1 as shown in FIG. S2, and a transistor 103A is provided as shown in FIG. 25(A). 10B is provided as an example.

[0184] Fig. 4, Fig. 11(A), Fig. 11(B), Fig. 12(A), Fig. 12(B), Fig. 13(A), Fig. 1 3(B), Fig. 14(A), Fig. 14(B), Fig. 15(A), Fig. 15(B), Fig. 16(A), Figure 16(B), Figure 17(A), Figure 17(B), Figure 18(A), Figure 18(B), Figure 19(A ), Fig. 19(B), Fig. 20(A), Fig. 20(B), Fig. 21(A), Fig. 21(B), Fig. 22 (A), Fig. 22(B), Fig. 23(A), Fig. 23(B), Fig. 24(A), Fig. 24(B), Fig. 25(A), 25(B), 26(A), 26(B), 27(A) and 27(B) In the circuit SR of the present embodiment, which is described as being illustrated in FIG. All or at least one of the transistors may have a double gate structure. The transistor of the structure has a first gate and a second gate. The channel formation region or the semiconductor layer having the channel formation region of the transistor having the first structure is The first gate is located below the second gate. The first gate may be provided at or above the The first gate corresponds to the first gate, and the first gate corresponds to the second gate. The second gate may be connected to the first gate or to a dedicated wiring. When the first gate is connected to the second gate, the mobility of the transistor is increased, and the Therefore, the W / L ratio of the transistor can be reduced. When the gate of transistor 2 is connected to a dedicated wiring, the transistor is turned on by the potential or signal of the dedicated wiring. The electrical properties of the stator can be controlled.

[0185] For example, in FIG. 38A, the transistors 101 to 105 in FIG. The semiconductor device has a double gate structure, and the first gate and the second gate are connected to each other. For example:

[0186] For example, in FIG. 38B, the transistors 101 to 105 in FIG. The first gate has a double gate structure, and the second gate is connected to the wiring BG. do.

[0187] In this specification, various types of switches can be used. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. For example, it is possible to allow current to flow through path 1, or to allow current to flow through path It has the function of selecting and switching whether to allow current to flow to 2. An example of the switch that can be used is an electrical switch or a mechanical switch. In other words, the switch is not limited to a specific one as long as it can control the current. An example of a switch is a transistor (e.g., a bipolar transistor, a MOS transistor, transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky -Diode, MIM (Metal Insulator Metal) diode, M IS (Metal Insulator Semiconductor) Diode, These include transistors with diode connections, or logic circuits that combine these. An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has an electrode that can be mechanically moved, and the movement of the electrode causes The transistor operates by controlling conduction and non-conduction.

[0188] When a transistor is used as a switch, the transistor is treated as a simple switch. Since the transistor operates as a gate, the polarity (conductivity type) of the transistor is not particularly limited. In order to suppress the current, it is desirable to use a transistor having a polarity with a smaller off-state current. An example of a transistor with low off-state current is a transistor having an LDD region or There are transistors having a multi-gate structure.

[0189] When using transistors as switches, the transistors that operate as switches The source potential of the capacitor operates at a value close to the potential of the low-potential power supply (Vss, GND, 0V, etc.). In this case, it is preferable to use an N-channel transistor as the switch. If the source potential is close to the potential of the high-potential power supply (such as Vdd), the switching It is desirable to use P-channel transistors as switches because N-channel When a transistor operates with its source at a potential close to the low-potential power supply, it is called a P-channel transistor. In a transistor, when the source operates at a potential close to that of the high-potential power supply, the gate and source This is because the absolute value of the voltage between the Or, the transistor can operate as a source follower. This is because the output voltage is less likely to become small because the do.

[0190] In addition, both N-channel and P-channel transistors are used as switches. A CMOS switch may be used. If either the N-channel transistor or the N-channel transistor is conductive, the current Therefore, the voltage of the input signal to the switch Even if the voltage is high or low, the voltage can be output appropriately. This allows the voltage amplitude value of the signal for turning the switch on and off to be reduced, reducing power consumption. The force can be reduced.

[0191] When using a transistor as a switch, the switch is connected to the input terminal (source or One of the drain terminals), the output terminal (the other of the source or drain), and the terminal that controls conduction On the other hand, when a diode is used as a switch, A switch may not have a terminal that controls conduction. Using a diode as a switch reduces the amount of wiring required to control the terminal. It is possible.

[0192] For example, in this specification, transistors having various structures are used as transistors. Therefore, there is no limitation on the type of transistor to be used. Examples of such transistors include transistors having single crystal silicon, or transistors having amorphous silicon or polycrystalline silicon. Amorphous silicon, microcrystalline (also called microcrystal, nanocrystal, or semi-amorphous) A transistor having a non-single crystal semiconductor film, such as a single crystal semiconductor film, can be used. Alternatively, thin-film transistors (TFTs) made from these semiconductors can be used. There are various advantages to using TFTs. For example, they are smaller than single crystal silicon. Since it can be manufactured at a very low temperature, it is possible to reduce manufacturing costs and to increase the size of manufacturing equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Since a large number of display devices can be manufactured, the manufacturing cost can be reduced. Therefore, a substrate having low heat resistance can be used. Alternatively, a display element can be manufactured using a transistor on a light-transmitting substrate. It is possible to control the transmission of light. Also, because the film thickness of the transistor is thin, A part of the film that forms the photodiode can transmit light, which improves the aperture ratio. It is possible.

[0193] In addition, when manufacturing polycrystalline silicon, a catalyst (such as nickel) is used to form the crystals. This will further improve the crystallinity and make it possible to manufacture transistors with good electrical characteristics. As a result, the gate driver circuit (scanning line driver circuit) and the source driver circuit (signal line driver circuit) and signal processing circuits (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) on the board. You can form a body.

[0194] In addition, when manufacturing microcrystalline silicon, a catalyst (such as nickel) is used to form the crystal. This makes it possible to further improve the crystallinity and manufacture transistors with good electrical characteristics. In some cases, the crystallinity can be improved by simply applying heat treatment without laser irradiation. As a result, part of the source driver circuit (analog switch, etc.) and the gate The driver circuit (scanning line driving circuit) can be formed integrally on the substrate. Therefore, when laser irradiation is not performed, unevenness in the crystallinity of silicon can be suppressed. Therefore, it is possible to display images with improved quality. However, catalysts (such as nickel) It is possible to produce polycrystalline silicon or microcrystalline silicon without using

[0195] In addition, improving the crystallinity of silicon to polycrystalline or microcrystalline can reduce the overall size of the panel. It is preferable, but not limited to, to perform the above. The crystallinity of the silicon may be improved by selectively irradiating the silicon with laser light. For example, the peripheral circuit area, which is an area other than the pixels, can be irradiated with light. Only in the area of ​​the gate driver circuit and the source driver circuit, or only in the area of ​​the source driver circuit, It is also possible to irradiate only a part of the buffer circuit (e.g., an analog switch) with laser light. As a result, silicon crystallization is improved only in areas where high-speed circuitry is required. Since there is little need for high-speed operation in the pixel region, the crystallinity is improved. Even if the pixel circuit is not connected to the crystal, it can still operate without any problems. Since the area where the performance needs to be improved is small, the manufacturing process can be shortened. Throughput can be increased and manufacturing costs can be reduced. Since a small number of manufacturing devices are required, manufacturing costs can be reduced.

[0196] An example of a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). , or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, In -Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), In A transistor having a Zn-Zn-O or the like can be used. These compound semiconductors or thin film transistors made of these oxide semiconductors are used. This allows the manufacturing temperature to be lowered, so that, for example, transistors can be manufactured at room temperature. As a result, it is possible to manufacture a substrate having low heat resistance, such as a plastic substrate. It is possible to form transistors directly on a plate or film substrate. Compound semiconductors or oxide semiconductors are used not only for the channel portion of a transistor, but also for For example, these compound semiconductors or oxide semiconductors can be used for other purposes. It can be used as a line, a resistor element, a pixel electrode, or an electrode having light transmission properties. Since these can be deposited or formed simultaneously with the transistors, costs can be reduced.

[0197] Note that an example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, manufacturing at a low vacuum, or It can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This allows the transistor layout to be easily changed. Alternatively, it can be manufactured without using resist, which reduces material costs and the number of processes. Or, since it is possible to apply the film only to the necessary parts, it is possible to apply the film after forming the film on the entire surface. This method wastes less material and is less costly than etching.

[0198] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. These can be used to fabricate transistors on a flexible substrate. It is possible to form transistors using organic semiconductors and carbon nanotubes. The device used can be made shock resistant.

[0199] Note that as the transistor, transistors having various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A MOS transistor is used as the transistor. This allows the size of the transistors to be reduced. It is possible to mount a bipolar transistor as a transistor. This allows a large current to flow, which allows the circuit to operate at high speed. It is also possible to mix MOS transistors and bipolar transistors on a single substrate. This can realize low power consumption, small size, high speed operation, etc. come.

[0200] For example, in this specification, an example of a transistor is a transistor having two or more gate electrodes. A multi-gate transistor can be used. Since the panel regions are connected in series, a structure in which multiple transistors are connected in series is obtained. Therefore, the multi-gate structure reduces the off-current and improves the breakdown voltage of the transistor (reliability). Or, by using a multi-gate structure, it is possible to improve the efficiency when operating in the saturation region. Even if the voltage between the drain and source changes, the current between the drain and source does not change much. The voltage-current characteristic does not change and has a flat slope. By using certain voltage-current characteristics, it is possible to create an ideal current source circuit or a circuit with a very high resistance. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized. It is possible to achieve the following:

[0201] An example of a transistor is a structure in which gate electrodes are arranged above and below a channel. A transistor having a structure in which gate electrodes are arranged above and below the channel can be applied. By doing so, the circuit configuration becomes like multiple transistors connected in parallel. As a result, the channel area increases, and the current value can be increased. A structure in which gate electrodes are arranged above and below makes it easier for a depletion layer to form. , the S value can be improved.

[0202] An example of a transistor is a transistor having a structure in which a gate electrode is disposed above a channel region. a structure in which the gate electrode is disposed under the channel region; a positive staggered structure; and a reverse staggered structure. A structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or A transistor having a structure in which the channel regions are connected in series can be used. Transistors are available in planar, FIN, and TRI-GATE types. gate type), top gate type, bottom gate type, double gate type (gates above and below the channel) The configuration can be various, such as

[0203] An example of a transistor is a transistor having a source electrode or a A transistor with an overlapping drain electrode can be used. By making the structure such that the source electrode and drain electrode overlap the This can prevent the operation from becoming unstable due to charge accumulating in a portion of the panel region.

[0204] As an example of a transistor, a structure in which an LDD region is provided can be applied. By providing a gate, the off-state current can be reduced or the withstand voltage of the transistor can be improved (reliability can be improved). Alternatively, by providing an LDD region, when operating in the saturation region, Even if the voltage between the drain and source is changed, the drain current does not change much and the slope is flat. A stable voltage-current characteristic can be obtained.

[0205] For example, in this specification, it is possible to form transistors using various substrates. The type of substrate is not limited to a specific one. An example of the substrate is a semiconductor substrate. Solid substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Includes plastic substrates, metal substrates, stainless steel substrates, and stainless steel foil. Substrates for bonding, tungsten substrates, substrates with tungsten foil, flexible substrates, bonding Examples of glass substrates include laminated films, paper containing fibrous materials, and base films. Examples of the glass include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of flexible substrates, laminated films, and base films include: Examples include polyethylene terephthalate (PET), polyethylene Plastics such as polyphenylene naphthalate (PEN) and polyethersulfone (PES) For example, synthetic resin such as acrylic resin may be used. For example, Examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Alternatively, for example, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, In particular, semiconductor substrates, single crystal substrates, and SOI substrates are used. By manufacturing transistors using this method, the variation in characteristics, size, shape, etc. is reduced. This makes it possible to manufacture small-sized transistors with high current capability. By constructing a circuit using such transistors, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit. It is possible to plan this.

[0206] In addition, a flexible substrate may be used as the substrate, and a transistor may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate having poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be, for example, an inorganic film of a tungsten film and a silicon oxide film. The laminated structure of the above-mentioned, or a structure in which an organic resin film such as polyimide is formed on a substrate, etc. may be used. This can be done.

[0207] That is, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one substrate and the transistor may be placed on another substrate. Examples include substrates on which the above-mentioned transistors can be formed, as well as paper substrates, ceramic substrates, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth board Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or Mostly recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), leather The substrates used are leather and rubber. By using these substrates, Formation of transistors with low power consumption, fabrication of durable devices, heat resistance It is possible to provide a lighter or thinner device.

[0208] All of the circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate, a plastic substrate, a single crystal substrate, an SOI substrate, etc. This reduces the number of components, thereby reducing costs, and reduces the number of connections to circuit components. This can improve reliability.

[0209] It is possible that all of the circuits required to realize a given function are not formed on the same substrate. In other words, part of the circuitry required to realize a given function is formed on a certain substrate. Another part of the circuitry required to realize a given function is formed on a different substrate. For example, some of the circuits required to realize a certain function can be made of glass. Another part of the circuitry required to realize a given function is formed on the single crystal substrate. (or SOI substrate). The single crystal substrate (also called IC chip) on which another part of the circuitry required for the semiconductor device is formed is called COG ( By using the Chip On Glass (Chip On Glass) method, the IC is connected to the glass substrate and then attached to the glass substrate. It is possible to place the chip on the board. Or, the IC chip can be placed on the board using TAB (Tape Auto) omated Bonding), COF(Chip On Film), SMT(Su Surface Mount Technology, or a printed circuit board, etc. In this way, part of the circuit is formed on the same substrate as the pixel section. This reduces the number of components, resulting in lower costs, and the number of connections to the circuit components. This reduces the power consumption and improves the reliability of the circuit. In many cases, circuits with high drive frequencies consume a lot of power. Then, such a circuit is formed on a substrate (such as a single crystal substrate) separate from the pixel section, and By using this IC chip, it is possible to prevent an increase in power consumption. do.

[0210] For example, in this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. Here, the source and drain are determined by the structure or operating conditions of the transistor. It is difficult to determine which is the source and which is the drain because it depends on the conditions. Therefore, the part that functions as the source and the part that functions as the drain are called the source. In some cases, the term "source" or "drain" is not used. In such cases, for example, The first terminal, the first electrode, or the first region is referred to as the first terminal, the first electrode, or the first region, and the other of the source and the drain is referred to as the second terminal. It may be referred to as a terminal, a second electrode, or a second region.

[0211] A transistor has at least three terminals including a base, an emitter, and a collector. In this case, the element may be, for example, an element having one of an emitter and a collector. The first terminal, the first electrode, or the first region is referred to as the first terminal, the first electrode, or the first region, and the other of the emitter and the collector is referred to as the second terminal. It may be written as a terminal, a second electrode, or a second region. When a polarized transistor is used, the term "gate" can be replaced with "base." It is.

[0212] For example, in this specification, when it is explicitly stated that X and Y are connected, When X and Y are electrically connected, when X and Y are functionally connected, This includes the case where X and Y are directly connected. Therefore, a given connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, and may be modified in any way without departing from the spirit or scope of the present invention. This also includes matters other than those involved.

[0213] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0214] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. It has the function of switching between these modes.

[0215] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if

[0216] In addition, when it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (That is, there is another element or circuit between X and Y.) (i.e., there is no other element or device between X and Y) and (i.e., X and Y are functionally connected). (X and Y are functionally connected via another circuit) and (X and Y are directly connected) (i.e., when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that they are electrically connected, it is not enough to simply It is the same as if it were explicitly stated that the item is connected.

[0217] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0218] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the object (e.g., the device , elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0219] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0220] Note that this embodiment mode can be appropriately combined with the description of other embodiment modes. The contents described in this embodiment (or a part of the contents) may be used in conjunction with another embodiment. The content (or a portion of the content) and / or one or more other embodiments described herein. To apply, combine, or replace the content (or even a part of the content) The contents described in the embodiments are various in each embodiment. This refers to content described using figures or content described using text in the specification. In addition, a figure (or a part of a figure) described in a certain embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part of it) described in another embodiment of the present invention This also applies to the following embodiments. It is.

[0221] (Embodiment 2) In this embodiment, a display device including a device according to one embodiment of the present invention will be described.

[0222] The display device illustrated in FIG. 28A includes a circuit 100 and a pixel portion 130. 0 has N (N is a natural number greater than or equal to 3) wires OUT and M (M is a natural number) wires SL( Wirings SL[1] to SL[M] are provided. The pixel 131 is provided corresponding to M lines SL. The gate signal line driver circuit also functions as a gate signal line driver circuit, a scanning line driver circuit, etc. The N wirings OUT function as gate lines (also called gate signal lines or scanning lines). The M wirings SL have a function of transmitting a video signal. The M wirings function as source lines (also called source signal lines or signal lines). The line SL is connected to a source driver (a source line driving circuit, a source signal line driving circuit, or a signal line driving circuit). It is connected to a circuit that functions as a signal processing circuit (also called a path).

[0223] The selection or non-selection of the pixel 131 is controlled based on the potential of the wiring OUT. The selection or non-selection of pixel 131 is controlled by circuit 100. When pixel 131 is selected, A video signal is written to the pixel 131 from the line SL. The pixel 131 displays the video signal. When the pixel 131 is deselected, the pixel 131 continues to display according to the held video signal.

[0224] Next, a specific example of the configuration of the pixel 131 will be described.

[0225] The pixel 131 illustrated in FIG. 28B includes a transistor 132, a liquid crystal element 133, and a capacitor. The transistor 132 has a first terminal connected to the line SL and a second terminal The first electrode of the liquid crystal element 133 and the first electrode of the capacitor element 134 (also called a pixel electrode) The second electrode ( The common electrode (also called a common electrode) is common to all or two or more of the multiple pixels 131. That is, the conductor having a region that becomes the second electrode of the liquid crystal element 133 of the first pixel 131 is The second electrode of the liquid crystal element 133 of the second pixel 131 is provided. The second electrode of the capacitor 134 is connected to a wiring that functions as a capacitor line. The electrodes are connected to the same wiring in all or two or more of the pixels 131. The second electrode of the liquid crystal element 134 may be connected to the second electrode of the liquid crystal element 133. The transistor 132 is turned on or off depending on the potential of the wiring OUT. When the liquid crystal element 32 is turned on, the video signal on the line SL is input to the pixel 131. The liquid crystal material is aligned by the first electrode of the liquid crystal element 133 and the liquid crystal element 13 The capacitance element 134 is controlled by a potential difference between the first electrode of the first transistor and the second electrode of the second transistor. That is, the capacitor 134 has a function of storing electric charge. The potential of the pixel is maintained at a value according to the video signal.

[0226] The pixel 131 illustrated in FIG. 28C includes a transistor 135, a transistor 136, and an EL The transistor 135 has a first terminal connected to the wiring SL and a second terminal connected to the The terminal is connected to the gate of the transistor 136, and the gate is connected to the wiring OUT. The first terminal of the transistor 136 is a wiring having a function of supplying a current to the EL element 137. The first terminal is connected to a line, and the second terminal is connected to a first electrode (also called a pixel electrode) of the EL element 137. The second electrode (also called a common electrode) of the EL element 137 is connected to all or a part of the pixels 131. That is, the second electrode of the EL element 137 of the first pixel 131 is common to two or more pixels. The conductor having the polarized region serves as the second electrode of the EL element 137 of the second pixel 131. The transistor 135 is turned on or off depending on the potential of the wiring OUT. When the transistor 135 is turned on, the video signal of the wiring SL is input to the pixel 131. The transistor 136 has a function of supplying a current to the EL element 137. The current supplied from the stator 136 to the EL element 137 has a value according to the video signal. The transistor 137 has a function of emitting light in response to a current supplied from the transistor 136 .

[0227] The configuration of the pixel 131 is not limited to that shown in FIG. 28(B) and FIG. 28(C). a transistor having a first terminal connected to a line OUT and a second terminal connected to a line SL; A display element that performs display based on a video signal input via a transistor. Alternatively, the pixel 131 may have a gate connected to the wiring OUT and a first terminal connected to the wiring A transistor connected to SL and a video signal input through the transistor and a pixel electrode to which a potential or current based on the pixel voltage is supplied. is a transistor having a gate connected to the wiring OUT and a first terminal connected to the wiring SL. A current based on a video signal input through the transistor is supplied to a display element or a pixel electrode. and a transistor for supplying a voltage to the first electrode.

[0228] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. can be done.

[0229] (Embodiment 3) In this embodiment, a configuration example of a transistor will be described with reference to the drawings. The transistors described in this embodiment are the transistors 101 to 116 described in the first embodiment. The transistors 132, 135, and 136 described in the second embodiment are It is possible to use.

[0230] <Example of transistor configuration> FIG. 29(A) is a schematic top view of a transistor 600 to be described below. FIG. 29B is a schematic cross-sectional view of the transistor 600 taken along the line AB in FIG. The transistor 600 illustrated in FIGS. 29(A) and 29(B) is a bottom-gate transistor. It is.

[0231] The transistor 600 includes a gate electrode 602 provided on a substrate 601 and a An insulating layer 603 is provided on the gate electrode 602, and the gate electrode 602 is provided on the insulating layer 603. The oxide semiconductor layer 604 provided so as to overlap with the oxide semiconductor layer 604 The pair of electrodes 605a and 605b are provided. The insulating layer 603 and the oxide semiconductor layer 604 are provided. An insulating layer 606 covers the pair of electrodes 605a and 605b, and an insulating layer 607 is formed on the insulating layer 606. is provided.

[0232] There is no particular restriction on the material of the substrate 601, but it should be at least strong enough to withstand the subsequent heat treatment. Use heat-resistant materials. For example, glass substrate, ceramic substrate, quartz substrate, safa A ceramic substrate, a YSZ (yttria stabilized zirconia) substrate, etc. may be used as the substrate 601. In addition, a single crystal semiconductor substrate having silicon or silicon carbide, a polycrystalline semiconductor substrate, It is also possible to apply a compound semiconductor substrate having silicon germanium, an SOI substrate, etc. In addition, a substrate having a semiconductor element formed thereon may be used as the substrate 601. good.

[0233] In addition, a flexible substrate such as plastic is used as the substrate 601, and the substrate is directly formed on the flexible substrate. Alternatively, the transistor 600 may be formed between the substrate 601 and the transistor 600. A peeling layer may be provided on the upper layer of the transistor. After that, it can be separated from the substrate 601 and used for transfer to another substrate. Therefore, the transistor 600 can be transferred to a substrate having low heat resistance or a flexible substrate.

[0234] The gate electrode 602 may be made of any of aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, etc. A metal selected from the group consisting of tin, tin, tin alloys, and tin alloys containing the above-mentioned metals. In addition, it can be formed by using an alloy of manganese and zirconium. The gate electrode 602 may be a single layer. For example, a silicon-containing aluminum film may be used. Single layer structure, two-layer structure with titanium layer laminated on aluminum layer, titanium layer on titanium nitride layer a two-layer structure in which a tungsten film is laminated on a titanium nitride film; A two-layer structure in which a tungsten film is laminated on a titanium film or a tungsten nitride film, and a titanium film and A three-layer structure in which an aluminum film is laminated on a titanium film, and a titanium film is further formed on the aluminum film. In addition, titanium, tantalum, tungsten, molybdenum, chromium, , neodymium, scandium or a combination of two or more of these. A film containing fluorine may also be used.

[0235] The gate electrode 602 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal may also be used.

[0236] In addition, an In-Ga-Zn-based oxynitride semiconductor film is formed between the gate electrode 602 and the insulating layer 603. , In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride Semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN, These films have a specification of 5 eV or more, preferably 5.5 eV or more. Since the electron affinity of the oxide semiconductor is larger than that of the oxide semiconductor, The threshold voltage of the transistor can be shifted to the positive side, resulting in a so-called normally-off transistor. For example, an In-Ga-Zn oxynitride semiconductor film can be used In the case of using the oxide semiconductor layer 604, the nitrogen concentration is at least higher than that of the oxide semiconductor layer 604, specifically, 7 atomic % or more. The above In-Ga-Zn-based oxynitride semiconductor film is used.

[0237] The insulating layer 603 functions as a gate insulating film. The edge layer 603 is preferably an insulating oxide film.

[0238] The insulating layer 603 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Copper, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide The above may be used, and the layer may be a laminate or a single layer.

[0239] The insulating layer 603 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide By using this, the gate leakage of the transistor can be reduced.

[0240] The pair of electrodes 605a and 605b serve as source and drain electrodes of the transistor. It works like this.

[0241] The pair of electrodes 605a and 605b are made of a conductive material such as aluminum, titanium, chromium, or nickel. Nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten Metals such as zinc or alloys containing these as the main component are used in a single layer structure or a laminated structure. For example, a single layer structure of an aluminum film containing silicon, Two-layer structure with titanium film laminated, two-layer structure with titanium film laminated on tungsten film, copper-ma A two-layer structure in which a copper film is laminated on a magnesium-aluminum alloy film, a titanium film or a titanium nitride film A titanium film or titanium nitride film is laminated with an aluminum film or a copper film. a three-layer structure in which a titanium film or a titanium nitride film is formed on the first layer; Molybdenum nitride film and aluminum layer on the molybdenum film or molybdenum nitride film A molybdenum film or a molybdenum nitride film is then formed on the copper film. There are three-layer structures. Transparent conductive materials containing indium oxide, tin oxide, or zinc oxide are used. It may be used.

[0242] The insulating layer 606 is formed using an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. It is preferable that the oxide insulating film contains more oxygen than the oxygen required for the stoichiometric composition. When heated, some oxygen is released. The oxide insulating film, including the On-line Spectroscopy analysis showed that the amount of oxygen released, calculated as oxygen atoms, was 1. 0×10 18 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 The oxide insulating film is as described above. The surface temperature of the film during the TDS analysis was The range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 500° C. or lower, is preferred.

[0243] The insulating layer 606 can be made of silicon oxide, silicon oxynitride, or the like.

[0244] The insulating layer 606 is formed so as to cover the oxide semiconductor layer 60 when the insulating layer 607 is formed later. It also functions as a damage mitigation membrane for 4.

[0245] Alternatively, an oxide film that transmits oxygen may be provided between the insulating layer 606 and the oxide semiconductor layer 604. good.

[0246] As the oxide film that transmits oxygen, silicon oxide, silicon oxynitride, etc. can be used. In this specification, the silicon oxynitride film is a film containing less than or equal to nitrogen. A silicon nitride film is a film that contains more oxygen than silicon dioxide. This refers to a film with a high nitrogen content.

[0247] The insulating layer 607 can be made of an insulating film having a blocking effect against oxygen, hydrogen, water, and the like. By providing the insulating layer 607 over the insulating layer 606, oxygen from the oxide semiconductor layer 604 can be prevented. Therefore, the diffusion of hydrogen, water, and the like to the outside and the intrusion of hydrogen, water, and the like into the oxide semiconductor layer 604 from the outside can be prevented. Examples of insulating films that have a blocking effect against oxygen, hydrogen, water, etc. include silicon nitride, Silicon oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride Yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Examples include

[0248] <Example of how to fabricate a transistor> Next, an example of a method for manufacturing the transistor 600 illustrated in FIGS.

[0249] First, as shown in FIG. 30(A), a gate electrode 602 is formed on a substrate 601. An insulating layer 603 is formed on the electrode 602 .

[0250] Here, a glass substrate is used as the substrate 601 .

[0251] The method of forming the gate electrode 602 will be described below. First, the sputtering method, the CVD method, and the evaporation method are used. A conductive film is formed by deposition or the like, and a first photomask is used to perform photolithography on the conductive film. A resist mask is formed by a deposition process. Next, a part of the conductive film is The resist mask is then etched to form a gate electrode 602. After that, the resist mask is removed.

[0252] The gate electrode 602 may be formed by electrolytic plating, printing, inkjet printing, or the like instead of the above-mentioned method. It may be formed by a jet method or the like.

[0253] The insulating layer 603 is formed by a sputtering method, a PECVD method, a vapor deposition method, or the like.

[0254] As the insulating layer 603, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film is used. In the case of forming the silicon-containing film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen oxides.

[0255] In addition, when forming a silicon nitride film as the insulating layer 603, a two-stage formation method is used. First, a mixture of silane, nitrogen, and ammonia is used as a raw material gas. A first silicon nitride film with few defects is formed by the plasma CVD method using the same material. The fuel gas was changed to a mixture of silane and nitrogen, and the hydrogen concentration was low and hydrogen was not blown. A second silicon nitride film capable of being coated is formed. As the insulating layer 603, a silicon nitride film having few defects and a hydrogen blocking property is used. can be formed.

[0256] In addition, when a gallium oxide film is formed as the insulating layer 603, MOCVD (Metal O Formed using the organic chemical vapor deposition (OCVD) method It is possible.

[0257] Next, as shown in FIG. 30B, an oxide semiconductor layer 604 is formed over the insulating layer 603.

[0258] A method for forming the oxide semiconductor layer 604 is described below. First, an oxide semiconductor film is formed. Subsequently, a second photomask is used to form a photoresist film on the oxide semiconductor film through a photolithography process. A resist mask is formed. Next, part of the oxide semiconductor film is etched using the resist mask. Then, etching is performed to form the oxide semiconductor layer 604. After that, the resist mask is removed.

[0259] After this, a heat treatment may be performed. When the heat treatment is performed, it is performed in an atmosphere containing oxygen. The temperature of the heat treatment is preferably, for example, 150° C. or higher and 600° C. or lower. and preferably, the heating temperature is set to 200° C. or higher and 500° C. or lower.

[0260] Next, as shown in FIG. 30(C), a pair of electrodes 605a and 605b are formed.

[0261] The method for forming the pair of electrodes 605a and 605b will be described below. First, a sputtering method is used. A conductive film is formed by a PECVD method, a vapor deposition method, etc. Next, a third photomask is applied to the conductive film. A resist mask is formed by a photolithography process using the resist mask. The conductive film is partially etched using a etch mask to form a pair of electrodes 605a and 605b. Thereafter, the resist mask is removed.

[0262] Note that as shown in FIG. 30C, when the conductive film is etched, the upper part of the oxide semiconductor layer 604 is Therefore, the oxide semiconductor layer 604 may be partially etched and thinned. When the oxide semiconductor film is formed, the thickness of the oxide semiconductor film is preferably set to be large in advance.

[0263] Next, as shown in FIG. 30D, the oxide semiconductor layer 604 and the pair of electrodes 605a and 60 An insulating layer 606 is formed on 5b, and then an insulating layer 607 is formed on the insulating layer 606.

[0264] When a silicon oxide film or a silicon oxynitride film is formed as the insulating layer 606, the source gas As the gas, a deposition gas containing silicon and an oxidizing gas are preferably used. Representative examples of deposition gases containing silane include silane, disilane, trisilane, and fluorosilane. The oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0265] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180° C. or higher. The temperature is kept at 260° C. or less, more preferably at 200° C. or more and 240° C. or less, and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is adjusted to 100 Pa or more and 250 Pa or less, more preferably 1 00 Pa to 200 Pa, and 0.17 W / cm2 to the electrode installed in the treatment chamber 2 End 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 More than 0.35W / cm 2 Below Silicon oxide film or silicon oxynitride film is formed by supplying high frequency power under the following conditions. do.

[0266] As a film formation condition, high frequency power with the above power density is supplied in a processing chamber with the above pressure. In the plasma, the decomposition efficiency of the source gas increases, oxygen radicals increase, and the source gas is oxidized. As a result, the oxygen content in the oxide insulating film becomes higher than the stoichiometric ratio. However, when the substrate temperature is above this level, the bond between silicon and oxygen is weak, and the A portion of the oxygen is released. As a result, the mixture contains more oxygen than the stoichiometric composition. In this case, an oxide insulating film from which part of oxygen is released by heating can be formed.

[0267] In addition, in the case where an oxide insulating film is provided between the oxide semiconductor layer 604 and the insulating layer 606, In the step of forming the layer 606 , the oxide insulating film serves as a protective film for the oxide semiconductor layer 604 . As a result, damage to the oxide semiconductor layer 604 is reduced, and high-frequency power density is achieved. A force may be used to form the insulating layer 606 .

[0268] For example, a substrate placed in an evacuated processing chamber of a PECVD apparatus is heated to 180° C. or higher for 40 The temperature is kept at 0° C. or lower, more preferably at 200° C. or higher and 370° C. or lower, and the raw material gas is introduced into the processing chamber. The pressure in the processing chamber is set to 20 Pa or more and 250 Pa or less, and more preferably 100 Pa or less. a or more and 250 Pa or less, and high-frequency power is supplied to the electrode installed in the treatment chamber. As a result, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film. In addition, by setting the pressure in the treatment chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film When the oxide semiconductor layer 604 is formed, damage to the oxide semiconductor layer 604 can be reduced.

[0269] As the source gas for the oxide insulating film, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen oxides.

[0270] The insulating layer 607 can be formed by a sputtering method, a PECVD method, or the like.

[0271] When a silicon nitride film or a silicon nitride oxide film is formed as the insulating layer 607, the raw material gas The gas used may be a deposition gas containing silicon, an oxidizing gas, or a gas containing nitrogen. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and fluorinated silane. Nitrogen, etc. Nitrogen-containing gases include nitrogen and ammonia.

[0272] Through the above steps, the transistor 600 can be formed.

[0273] <Modifications of Transistor> An example of a configuration of a transistor that is partially different from the transistor 600 will be described below.

[0274] FIG. 31A is a schematic cross-sectional view of a transistor 610, which will be described below. The transistor 610 differs from the transistor 600 in the structure of the oxide semiconductor layer.

[0275] The oxide semiconductor layer 614 in the transistor 610 includes an oxide semiconductor layer 614a and an oxide The semiconductor layer 614b is laminated thereon.

[0276] Note that the boundary between the oxide semiconductor layer 614a and the oxide semiconductor layer 614b may be unclear. Therefore, in figures such as FIG. 31(A), these boundaries are shown by dashed lines.

[0277] The oxide semiconductor layer 614a is typically made of In-Ga oxide, In-Zn oxide, or In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) When the oxide semiconductor layer 614a is an In-M-Zn oxide, Zn and O The atomic ratio of In and M excluding the above is preferably less than 50 atomic % In, M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is For example, the oxide semiconductor layer 614a has an energy A material having a gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. is used.

[0278] The oxide semiconductor layer 614b contains In or Ga, and is typically In-Ga oxide, I n-Zn oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce) , Nd, or Hf) and has a lower energy of the conduction band than the oxide semiconductor layer 614a. is close to the vacuum level, and typically, the energy level of the conduction band of the oxide semiconductor layer 614b is and the energy difference between the conduction band minimum of the oxide semiconductor layer 614a and the conduction band minimum of the oxide semiconductor layer 614b is 0.05 eV or more. 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV It is preferably 0.5 eV or less, or 0.4 eV or less.

[0279] When the oxide semiconductor layer 614b is an In-M-Zn oxide, the The atomic ratio of In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. %, more preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than ic%.

[0280] For example, the oxide semiconductor layer 614a may be made of In:Ga:Zn=1:1:1, In:Ga:Z In-Ga-Z with an atomic ratio of n=1:1:1.2 or In:Ga:Zn=3:1:2 The oxide semiconductor layer 614b may be made of In:Ga:Zn In-Ga-Zn oxide with atomic ratios of 1:3:2, 1:6:4, or 1:9:6 was used. Note that the atoms of the oxide semiconductor layer 614a and the oxide semiconductor layer 614b can be The atomic ratios each include a margin of error of plus or minus 20% from the atomic ratios listed above.

[0281] The oxide semiconductor layer 614b provided on the upper layer contains Ga, which functions as a stabilizer. By using an oxide having a large amount, the oxide semiconductor layer 614a and the oxide semiconductor layer 61 The release of oxygen from 4b can be suppressed.

[0282] In addition, the semiconductor characteristics and electrical characteristics (field effect The appropriate composition should be used depending on the required properties (mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the oxide semiconductor layer 614a and the oxide semiconductor layer 61 4b Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, It is preferable to make the density etc. appropriate.

[0283] Note that in the above description, the oxide semiconductor layer 614 has a structure in which two oxide semiconductor layers are stacked. Although this is illustrated as an example, a structure in which three or more oxide semiconductor layers are stacked may be used.

[0284] FIG. 31B is a schematic cross-sectional view of a transistor 620, which will be described below. The transistor 620 is different from the transistor 600 in the structure of the oxide semiconductor layer. It is different from 10.

[0285] The oxide semiconductor layer 624 in the transistor 620 includes an oxide semiconductor layer 624a, an oxide The semiconductor layer 624b and the oxide semiconductor layer 624c are laminated in this order.

[0286] The oxide semiconductor layer 624a and the oxide semiconductor layer 624b are stacked over the insulating layer 603. The oxide semiconductor layer 624c is formed on a top surface of the oxide semiconductor layer 624b and a pair of The electrodes 605a and 605b are provided in contact with the upper and side surfaces thereof.

[0287] For example, the oxide semiconductor layer 624b may be the oxide semiconductor layer 614 shown in the first modification. For example, the oxide semiconductor layers 624a and 624c may have a similar structure to that of the oxide semiconductor layers 624a and 624c. As the oxide semiconductor layer 614b, a structure similar to that of the oxide semiconductor layer 614b illustrated in the first modification can be used. Cut.

[0288] For example, the oxide semiconductor layer 624a provided under the oxide semiconductor layer 624b and the oxide semiconductor layer The oxide semiconductor layer 624c provided in the second insulating layer 624 has a Ga content functioning as a stabilizer. By using a large amount of oxide, the oxide semiconductor layer 624a, the oxide semiconductor layer 624b, and In addition, release of oxygen from the oxide semiconductor layer 624c can be suppressed.

[0289] In addition, when a channel is mainly formed in the oxide semiconductor layer 624b, for example, The conductor layer 624b is made of an oxide containing a large amount of In. By providing a pair of electrodes 605a and 605b, the on-current of the transistor 620 is increased. It can be done.

[0290] <Other examples of transistor configurations> A top-gate transistor to which the oxide semiconductor film of one embodiment of the present invention can be applied will be described below. A configuration example of the data recorder will be described below.

[0291] In the following, components having the same configuration or function as those described above will be referred to as the same. Each component will be given the same reference symbol, and duplicated explanations will be omitted.

[0292] FIG. 32A is a schematic cross-sectional view of a top-gate transistor 650, which will be described below. vinegar.

[0293] The transistor 650 is an oxide semiconductor provided on a substrate 601 on which an insulating layer 651 is provided. a pair of electrodes 605a and 605b in contact with an upper surface of the oxide semiconductor layer 604; an insulating layer 603 provided over an oxide semiconductor layer 604 and a pair of electrodes 605 a and 605 b; A gate electrode 602 is provided over the insulating layer 603 so as to overlap with the oxide semiconductor layer 604. In addition, an insulating layer 652 is provided to cover the insulating layer 603 and the gate electrode 602. do.

[0294] The insulating layer 651 has a function of suppressing diffusion of impurities from the substrate 601 to the oxide semiconductor layer 604. For example, the insulating layer 607 may have the same structure as the insulating layer 607. 651 does not have to be provided if it is not necessary.

[0295] The insulating layer 652 has a blocking effect against oxygen, hydrogen, water, etc., similar to the insulating layer 607. Note that the insulating layer 607 is not required if it is not necessary. stomach.

[0296] An example of the structure of a transistor that is partially different from the transistor 650 will be described below.

[0297] FIG. 32B is a schematic cross-sectional view of a transistor 660, which is described below. The transistor 660 differs from the transistor 650 in the structure of the oxide semiconductor layer.

[0298] The oxide semiconductor layer 664 in the transistor 660 includes an oxide semiconductor layer 664a, an oxide The semiconductor layer 664b and the oxide semiconductor layer 664c are stacked in this order.

[0299] Among the oxide semiconductor layer 664a, the oxide semiconductor layer 664b, and the oxide semiconductor layer 664c, The oxide semiconductor film described above may be used for any one, any two, or all of the above. This can be done.

[0300] For example, the oxide semiconductor layer 664b may be the oxide semiconductor layer 614 shown in the first modification. For example, the oxide semiconductor layers 664a and 664c may have a similar structure to that of the oxide semiconductor layers 664a and 664c. As the oxide semiconductor layer 614b, a structure similar to that of the oxide semiconductor layer 614b illustrated in the first modification can be used. Cut.

[0301] In addition, the oxide semiconductor layer 664a provided under the oxide semiconductor layer 664b and the oxide semiconductor layer The oxide semiconductor layer 664c to be provided has a high content of Ga functioning as a stabilizer. By using a thin oxide, the oxide semiconductor layer 664a, the oxide semiconductor layer 664b, and the oxide This can suppress the release of oxygen from the organic semiconductor layer 664c.

[0302] An example of the structure of a transistor that is partially different from the transistor 650 will be described below.

[0303] FIG. 32C is a schematic cross-sectional view of a transistor 670, which is described below. The shape of the pair of electrodes 605a and 605b in contact with the oxide semiconductor layer 604 and the gate The transistor 602 differs from the transistor 650 in terms of the shape of the port electrode 602 and the like.

[0304] The transistor 670 is an oxide semiconductor provided on a substrate 601 on which an insulating layer 651 is provided. a gate electrode on the insulating layer 603; 602, an insulating layer 654 over the insulating layer 651 and the oxide semiconductor layer 604, The insulating layer 654 and the oxide semiconductor layer 6 A pair of electrodes 605a and 605b electrically connected to the insulating layer 656 and the pair of electrodes and an insulating layer 652 on the poles 605a, 605b.

[0305] The insulating layer 654 is formed of, for example, an insulating film containing hydrogen. An example of the insulating layer 654 is a silicon nitride film. The oxygen vacancies in the oxide semiconductor layer 604 are bonded to the oxygen vacancies, and the oxygen vacancies in the oxide semiconductor layer 604 become carriers. Therefore, in the structure shown in FIG. 32C, the oxide semiconductor layer 604 and the insulating layer 654 are in contact with each other. The regions corresponding to the n-type region 604b and the n-type region 604c are shown. The region between n-type region 604b and n-type region 604c becomes channel region 604a.

[0306] By providing n-type regions 604b and 604c in the oxide semiconductor layer 604, a pair of electrodes 60 The contact resistance between the n-type regions 604b and 605a can be reduced. As for 4c, when the gate electrode 602 is formed and when the insulating layer 654 covering the gate electrode 602 is formed, The transistor 670 shown in FIG. This is a so-called self-aligned top-gate transistor. By forming a p-gate type transistor structure, the gate electrode 602 and the source and drain electrodes Since there is no overlap between the pair of electrodes 605a and 605b that function as in-electrodes, The parasitic capacitance occurring between the electrodes can be reduced.

[0307] The insulating layer 656 of the transistor 670 is, for example, a silicon oxynitride film. etc.

[0308] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. can be done.

[0309] (Embodiment 4) In this embodiment, a semiconductor layer of the transistor with low off-state current described in the above embodiment is An oxide semiconductor layer that can be used will be described.

[0310] The oxide semiconductor used for the channel formation region in the semiconductor layer of the transistor is at least It is preferable that the alloy contains indium (In) or zinc (Zn). In particular, the alloy contains In and Zn. In addition, it is preferable to have a stabilizer that strongly binds oxygen. The stabilizer is preferably gallium (Ga), tin (Sn), zirconium (Zr), or the like. Contains at least one of Zr, Hafnium, and Aluminum. Just do that.

[0311] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of tetraethynyl ions (Te).

[0312] Examples of oxide semiconductors used for the semiconductor layer of a transistor include indium oxide. Tin oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, S n-Al-Zn oxide, In-Hf-Zn oxide, In-Zr-Zn oxide, In -Ti-Zn oxide, In-Sc-Zn oxide, In-Y-Zn oxide, In-L a-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd -Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd- Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Z n-type oxides, In-Er-Zn-type oxides, In-Tm-Zn-type oxides, In-Yb-Zn In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In-Hf- Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides, etc.

[0313] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In In-Ga-Zn oxides with an atomic ratio of Ga:Zn=2:1:3 and oxides with similar compositions It is a good idea to use compounds.

[0314] When a large amount of hydrogen is contained in the oxide semiconductor film constituting the semiconductor layer, hydrogen is bonded to the oxide semiconductor. By this, some of the hydrogen atoms become donors, generating electrons that act as carriers. As a result, the threshold voltage of the transistor is shifted in the negative direction. After the conductive film is formed, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen from the oxide semiconductor film. Alternatively, it is preferable to highly purify the mixture by removing moisture so that impurities are contained as little as possible.

[0315] Note that the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film causes the oxide semiconductor film to lose its oxygen. Therefore, the oxide semiconductor film is preferably subjected to a dehydration treatment (dehydrogenation treatment) In order to compensate for oxygen vacancies increased by the above-mentioned treatment, oxygen is added to the oxide semiconductor film. In this specification and the like, the case where oxygen is supplied to an oxide semiconductor film is referred to as an oxygen-added Alternatively, oxygen contained in the oxide semiconductor film may be increased to a level higher than the stoichiometric composition. When this is done, it is sometimes referred to as hyperoxygenation treatment.

[0316] In this manner, hydrogen or moisture is removed from the oxide semiconductor film by the dehydration treatment (dehydrogenation treatment). By adding oxygen to compensate for the oxygen deficiency, the material becomes i-type (intrinsic) or i-type. The oxide semiconductor film can be substantially i-type (intrinsic). The term "substantially intrinsic" means that there are very few carriers derived from donors in the oxide semiconductor film (zero ), and the carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 Below, 1x 10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 The following is It is said.

[0317] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film as described above can be For example, a transistor using an oxide semiconductor film can be The drain current when the capacitor is off is 1×10 -18 Below A, Preferably 1 x 10 -21 A or less, more preferably 1×10 -24 A or below, or 85℃ 1×10 -15 A or less, preferably 1×10 -18 A or less, more preferably 1×10 - 21 A or less. Note that the off state of a transistor is an n-channel transistor. In the case of a transistor, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. If the gate voltage is more than 1V, 2V, or 3V less than the threshold voltage, the transistor It becomes the off state.

[0318] The structure of the oxide semiconductor film will be described below.

[0319] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). Talline Oxide Semiconductor film, polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0320] First, we will explain the CAAC-OS film.

[0321] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0322] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0323] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0324] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0325] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0326] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0327] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0328] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0329] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0330] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0331] Next, a microcrystalline oxide semiconductor film will be described.

[0332] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0333] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. When this is done, a circular (ring-shaped) area of ​​high brightness may be observed. Nanobeam electron diffraction of the nc-OS film revealed multiple spots within the ring-shaped region. It may be observed.

[0334] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0335] Next, the amorphous oxide semiconductor film will be described.

[0336] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0337] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0338] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0339] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Ox The resulting film is called an ide semiconductor membrane.

[0340] The amorphous-like OS membrane appears as voids in high-resolution TEM images. In addition, crystals may be clearly observed in high-resolution TEM images. There are areas where crystals can be seen and areas where crystals cannot be seen. The phos-like OS film is formed by irradiating a small amount of electrons, which is the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, if the nc-OS film is of good quality, However, crystallization due to minute amounts of electron irradiation, such as that observed by TEM, is hardly observed.

[0341] The size of the crystals in the amorphous-like OS film and the nc-OS film was calculated. Measurements can be performed using high-resolution TEM images. For example, the crystal of InGaZnO4 It has a layered structure, with two Ga-Zn-O layers between In-O layers. InGaZnO4 The unit cell of this crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers. The layers are stacked in the c-axis direction. Therefore, the spacing between adjacent layers is is approximately the same as the lattice spacing (also called the d value) of the (009) plane, and crystal structure analysis has revealed that The value is expected to be 0.29 nm. Therefore, we focus on the lattice fringes in the high-resolution TEM image. In the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less, The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0342] The oxide semiconductor film is, for example, an amorphous oxide semiconductor film. e. A stacked film including two or more of an OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. may be also possible.

[0343] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. " refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0344] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0345] Note that the structures and methods described in this embodiment may be different from the structures and methods described in other embodiments. can be used in appropriate combination.

[0346] (Embodiment 5) In this embodiment, an example of a display module will be described below with reference to FIGS. 33 and 34. The explanation is given below.

[0347] FIG. 33 is a top view showing an example of a display module. The display module 700 shown in FIG. The pixel portion 702 is provided on the first substrate 701, and the semiconductor device 702 is provided on the first substrate 701. A source driver circuit section 704 and a gate driver circuit section 706, a pixel section 702, a source driver circuit section 706, and a gate driver circuit section 706. A sealant is disposed to surround the gate driver circuit section 704 and the gate driver circuit section 706. 712 and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 is sealed by a first substrate 701, a sealant 712, and a second substrate 705. Although not shown in FIG. 33, a display is provided between the first substrate 701 and the second substrate 705. An element is provided.

[0348] The display module 700 is surrounded by a sealant 712 on the first substrate 701. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 705 are arranged in a region different from the region where the pixel is located. An FPC terminal portion 708 (FPC: Flexible Printed Circuit) electrically connected to the driver circuit portion 706 In addition, the FPC terminal portion 708 is provided with The FPC 716 is connected to the pixel section 702 and the source driver circuit section 7 Various signals are supplied to the pixel portion 702 and the gate driver circuit portion 706. , a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal section 708 A signal line 710 is connected to each of the FPC 716. , through a signal line 710, a pixel section 702, a source driver circuit section 704, a gate driver It is provided to a circuit portion 706 and an FPC terminal portion 708 .

[0349] In addition, the display module 700 may be provided with a plurality of gate driver circuits 706. The display module 700 includes a source driver circuit section 704 and a gate driver circuit section In the example shown, the pixel portion 702 and the pixel portion 706 are formed on the same first substrate 701. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit section 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (e.g. For example, a driving circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film is placed on the first substrate 70. The method of connecting the separately formed drive circuit board is not particularly limited. The method is not specified, and may be COG (Chip On Glass) or wire bonding. A method such as a tagging method can be used.

[0350] The display module 700 includes a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 705. The gate driver circuit section 706 includes a plurality of transistors. The transistor described in the above embodiment can be used as the gate electrode.

[0351] The display module 700 can also include various elements. Liquid crystal elements, EL (electroluminescence) elements (EL elements including organic and inorganic materials) LED (white LED, red LED, green LED, blue LED), organic EL element, inorganic EL element), color LEDs, transistors (transistors that emit light according to current), electron emitters, Electronic ink, electrophoretic element, grating light valve (GLV), plasma display Using PDP and MEMS (Micro Electro Mechanical Systems) Display elements, digital micromirror devices (DMDs), digital micromirror devices (DMSs) shutter), IMOD (Interference Modulation) element, shutter MEMS display element using the optical interferometer method, MEMS display element using the optical interference method, electrowetting display elements using carbon nanotubes, piezoelectric ceramic displays, etc. In addition to these, there are also other types of sensors that can be used to control the electrical or magnetic fields. The display medium may have a variable resistance, brightness, reflectance, transmittance, etc. An example of such a display device is an EL display. An example of the device is a field emission display (FED) or SED type flat panel display. Surface-conduction Electron (SED) Examples of display devices using liquid crystal elements include the LCD (LCD-emitter Display). For LCDs (transmissive LCDs, semi-transmissive LCDs, reflective LCDs, etc.), LCD, direct-view LCD, projection LCD, etc. An example of a display device using ink or electrophoretic elements is electronic paper. In order to realize a semi-transmissive or reflective LCD, the pixel voltage must be A part or the whole of the electrode may function as a reflective electrode. For example, A part or the whole of the pixel electrode may be made of aluminum, silver, or the like. In this case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. This makes it possible to further reduce power consumption. A configuration in which a liquid crystal element is used as a display element will be described below.

[0352] The display method of the display module 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying colors are , RGB (R stands for red, G stands for green, B stands for blue) are not limited to three colors. For example, R pixel and It may be made up of four pixels: a G pixel, a B pixel, and a W (white) pixel. Like the pixel array, one color element is made up of two colors of RGB, and different colors are Alternatively, yellow, cyan, magenta, etc. may be added to the RGB. You can add more than one color. Note that the size of the display area for each dot of the color element is different. However, the disclosed invention is not limited to color display devices, and may be used in monolithic display devices. It can also be applied to a display device with a black display.

[0353] In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is white light (W In order to make a display device display full color, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B), Yellow (Y) and other colors can be used in combination. The color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light from the colored layer may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the light emission by about 30% when using self-luminous elements such as organic EL elements and inorganic EL elements. When using a full-color display, R, G, B, Y, and white (W) are generated by It is also possible to emit light from an element having a certain color. In this embodiment, the power consumption can be further reduced. The following describes a configuration that does not include a backlight, i.e., a so-called reflective liquid crystal display module. Do the following.

[0354] A cross-sectional view taken along the dashed line QR in FIG. 33 is shown in FIG. The details of the rule are explained below.

[0355] <Explanation about the display module> The display module 700 shown in FIG. 34 includes a wiring section 711, a pixel section 702, and a The wiring section 702 includes a driver circuit section 704 and an FPC terminal section 708. 11 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor. The source driver circuit portion 704 also includes a transistor 752. .

[0356] The transistors 750 and 752 can be the transistors shown above. Cut.

[0357] The transistor used in this embodiment is a highly purified oxide semiconductor in which the formation of oxygen vacancies is suppressed. The transistor has a conductive film, and the current value in the off state (off-state current value) is reduced. Therefore, the retention time of electrical signals such as image signals can be extended, and the power can be turned off. In the ON state, the write interval can be set longer. This reduces the frequency of refresh operations. This has the effect of reducing power consumption.

[0358] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of high speed driving is used in a display device. By using this, the switching transistor in the pixel section and the driver used in the driver circuit section can be The transistors can be formed on the same substrate. Since there is no need to use semiconductor devices formed from silicon wafers, etc., The number of points can be reduced. Also, in the pixel area, transistors that can be driven at high speed can be used. By using this, high quality images can be provided.

[0359] The capacitor 790 has a structure having a dielectric between a pair of electrodes. One electrode of the transistor 790 is a conductive film that functions as a gate electrode of the transistor 750. The other electrode of the capacitor 790 is formed using a conductive film formed in the same process. A conductive film is used to function as the source electrode and the drain electrode of the capacitor 750. The dielectric sandwiched between the electrodes is an insulating film that functions as a gate insulating film of the transistor 750. Use the velum.

[0360] 34, a transistor 750, a transistor 752, and a capacitor 790 Over the top of this, insulating films 764 and 768 and a planarizing insulating film 770 are provided.

[0361] The insulating film 764 is, for example, a silicon oxide film, a silicon oxynitride film, or the like, which is formed by using a PECVD apparatus. The insulating film 768 may be formed by, for example, a PECVD apparatus. A silicon nitride film or the like may be formed using the planarization insulating film 770. Imide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide Organic materials having heat resistance, such as olefin resin and epoxy resin, can be used. The planarization insulating film 770 may be formed by stacking a plurality of insulating films made of the above material. The planarization insulating film 770 does not necessarily have to be provided.

[0362] The signal line 710 serves as the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed in the same process as the conductive film that functions as the transistor 750. 752, a conductive film formed in a process different from the source electrode and drain electrode, e.g., a gate The conductive film may be formed in the same process as the conductive film that functions as the electrode. For example, when a material containing copper is used, signal delays caused by wiring resistance are reduced. , making it possible to display on a large screen.

[0363] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed in the same process as the conductive film that functions as the FPC. It is electrically connected to a terminal of C716 via an anisotropic conductive film 780.

[0364] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. .

[0365] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The body 778 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the first substrate 701 and the second substrate 705 is controlled by a In addition, a spherical spacer may be used as the structure 778. In the embodiment, the structure 778 is provided on the first substrate 701 side. For example, a structure 778 may be provided on the second substrate 705 side. A structure in which the structures 778 are provided on both the first substrate 701 and the second substrate 705 may be used.

[0366] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and a A colored film 736 which functions as a color filter, a light-shielding film 738 and an insulating film in contact with the colored film 736 A veil 734 is provided.

[0367] <Example of configuration using liquid crystal elements as display elements> The display module 700 shown in FIG. 34 includes a liquid crystal element 775. The liquid crystal element 775 is a conductive The liquid crystal layer 776 includes the conductive film 772, the conductive film 774, and the liquid crystal layer 776. The liquid crystal material has a dielectric constant anisotropy of 2 or more and 3.8 or less. The display module shown in FIG. In the liquid crystal layer 776, the liquid crystal layer 776 is turned on and off by a voltage applied to the conductive film 772 and the conductive film 774. By changing the orientation state, light transmission or non-transmission can be controlled, allowing images to be displayed. .

[0368] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed on the planarization insulating film 770. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display module 700 shown in FIG. The light is reflected by the colored film 736 and displayed on the screen. .

[0369] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a light-transmitting property in visible light can be used. For example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) As a conductive film having a reflectivity in visible light, for example, aluminum, Alternatively, a material containing silver may be used. In this embodiment, the conductive film 772 may be a A conductive film that is reflective in visible light is used.

[0370] In addition, when a conductive film that is reflective to visible light is used as the conductive film 772, the conductive film For example, an aluminum film having a thickness of 100 nm may be formed as a lower layer, and A 30 nm thick silver alloy film (e.g., an alloy film containing silver, palladium, and copper) is formed on the layer. The above-mentioned structure provides the following excellent effects.

[0371] (1) The adhesiveness between the base film and the conductive film 772 can be improved. (2) By using a chemical solution, It is possible to etch the aluminum film and the silver alloy film at the same time. (3) Conductivity The cross-sectional shape of the membrane 772 can be made to have a good shape (for example, a tapered shape). (3) The reason is that the etching rate of the aluminum film by the chemical solution is slower than that of the silver alloy film. Or, when the lower aluminum film is exposed after etching the upper silver alloy film, the silver alloy The electrons are drawn from aluminum, which is a metal that is less noble than the membrane, in other words, has a high ionization tendency. Therefore, etching of the silver alloy film is suppressed and etching of the underlying aluminum film progresses. This is because the journey will be faster.

[0372] In the display module 700 shown in FIG. The unevenness is formed, for example, by forming the planarization insulating film 770 with an organic resin film. The organic resin film is formed of a material such as a resin, and the surface of the organic resin film is provided with irregularities. The conductive film 772, which functions as a reflective electrode, is formed along the above-mentioned unevenness. When light enters the conductive film 772, the light may be diffusely reflected on the surface of the conductive film 772. As shown in Figure 34, a reflective color LCD By using it as a display device, it is possible to display without using a backlight, so the power consumption is The force can be reduced.

[0373] The display module 700 shown in FIG. 34 is a reflective color liquid crystal display module. For example, the conductive film 772 may be a transparent film that transmits visible light. By using a conductive film, a transmissive color liquid crystal display module can be formed. In the case of a liquid crystal display module, the unevenness provided on the planarization insulating film 770 is not provided. Alternatively, a different configuration may be used.

[0374] Although not shown in FIG. 34, the conductive films 772 and 774 are provided on the side in contact with the liquid crystal layer 776. Although not shown in FIG. Optical members (optical substrates) such as a member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. In the case of a module or a transflective display module, a backlight, sidelight, etc. are used as a light source. A gate or the like may also be provided.

[0375] Liquid crystal elements include thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, and polymer dispersed liquid crystal. The liquid crystal material may be a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like. Therefore, cholesteric phase, smectic phase, cubic phase, chiral nematic phase, etc. Shows dimensions etc.

[0376] In addition, when the in-plane switching system is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the crystalline phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. It has a short response time, is optically isotropic, so alignment treatment is unnecessary, and viewing angle dependency is small. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. It is possible to prevent electrostatic damage caused by electrostatic discharge, and thus to prevent defects in liquid crystal display devices during the manufacturing process. Damage can be reduced.

[0377] When liquid crystal elements are used as display elements, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fring e Field Switching) mode, ASM (Axially Symmet ric aligned Micro-cell) mode, OCB (Optical C ompensated birefringence mode, FLC (Ferroel etric Liquid Crystal) mode, AFLC (AntiFerro You can use modes such as electric Liquid Crystal.

[0378] In addition, normally black type liquid crystal display devices, such as those using a vertical alignment (VA) mode, The liquid crystal display device may be a transmission type liquid crystal display device. There are several types of vertical alignment modes, including: For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV mode, etc. can be used.

[0379] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0380] (Embodiment 6) In this embodiment, a touch sensor ( By providing a touch detection device, it functions as an input / output device (also called a touch panel). A configuration that can achieve the above will be described with reference to Figs. 35 and 36. Descriptions of parts that overlap with the embodiment may be omitted.

[0381] FIG. 35 is a projection diagram for explaining the configuration of the input / output device.

[0382] FIG. 35(A) is a projection view of the input / output device 800, and FIG. 35(B) is a projection view of the input / output device 800. 13 is a projection diagram illustrating the configuration of a detection unit 820U provided. FIG.

[0383] FIG. 36 is a cross-sectional view of the input / output device 800 shown in FIG. 35(A) taken along the line Z1-Z2.

[0384] <Example 1 of I / O device configuration> The input / output device 800 described in this embodiment has a window 834 that transmits visible light, and A plurality of detection units 820U are arranged in a matrix. ) and a scanning line G1 electrically connected to a plurality of detection units 820U arranged in a row direction (FIG. A signal line electrically connecting the detection units 820U arranged in the detection unit 820U (indicated by arrows Ry in the figure) line DL, and a first supporting the detection unit 820U, the scanning line G1, and the signal line DL. An input device 850 having a base material 836 and a matrix-shaped arrangement overlapping the window portion 834. A display module including a plurality of pixels 802 and a second substrate 810 supporting the pixels 802. 801 (see FIG. 35(A) to FIG. 35(C)).

[0385] The detection unit 820U is electrically connected to the detection element Ca that overlaps the window portion 834 and the detection element Ca. (See FIG. 35B).

[0386] The sensing element Ca has an insulating layer 823 and an insulating layer 823 (not shown in FIG. 35(B)) sandwiched therebetween. It includes a first electrode 821 and a second electrode 822 (see FIG. 35(B)).

[0387] The detection circuit 839 is supplied with a selection signal and generates a detection signal based on a change in the capacitance of the detection element Ca. Supply the number DATA.

[0388] The scanning line G1 can supply a selection signal, and the signal line DL supplies a detection signal DATA. The detection circuit 839 is disposed so as to overlap the gaps between the windows 834. .

[0389] The input / output device 800 described in this embodiment includes a detection unit 820U and a detection unit A colored layer is provided between the window portion 834 of the unit 820U and the pixel 802 that overlaps it.

[0390] The input / output device 800 described in this embodiment is a detector having a window 834 that transmits visible light. An input device 850 having a plurality of sensing units 820U and a pixel 802 overlapping a window portion 834 are overlapped. A display module 801 including a plurality of pixels 802 and a color layer between the window portion 834 and the pixel 802. It is composed of:

[0391] In this way, the input / output device receives a detection signal based on the change in capacitance and a detection unit that supplies the detection signal. and providing position information of the sensing unit, and image information associated with the position information of the sensing unit. As a result, a novel input / output device with excellent convenience and reliability can be provided. can be provided.

[0392] The input / output device 800 is also a flexible board that receives signals from the input device 850. A flexible printed circuit board (FPC) 1 or / and a flexible printed circuit board (FPC) 2 that supplies a signal including image information to the display module 801 It may also include a flexible substrate FPC2.

[0393] In addition, a protective substrate 837 and a protective layer 837p are provided to protect the input / output device 800 by preventing scratches. Or / and the input / output device 800 is provided with an anti-reflection layer 867p that reduces the intensity of reflected external light. It is also possible to do so.

[0394] The input / output device 800 also includes a scanning line for supplying a selection signal to the scanning line of the display module 801. The driving circuit 803g, the wiring 811 for supplying signals, and the flexible substrate FPC2 are electrically The input terminal 819 is connected to the

[0395] The individual elements constituting the input / output device 800 will be described below. are not clearly separable, and one component may also be part of another. For example, the input device 850 having a colored layer at a position overlapping the multiple window portions 834 is The device 850 is also a color filter.

[0396] The input / output device 800 includes an input device 850 and a display module 801 (see FIG. 35). See A).

[0397] The input device 850 supports a plurality of detection units 820U and A first substrate 836 is provided. For example, a plurality of detection units are arranged in a matrix of 40 rows and 15 columns. 820U is disposed on a first substrate 836.

[0398] The window 834 transmits visible light.

[0399] A colored layer that transmits light of a predetermined color is provided at a position overlapping the window portion 834. For example, A transparent colored layer CFB, a green light transparent colored layer CFG or a red light transparent colored layer It has a layer CFR (see FIG. 35(B)).

[0400] In addition to blue, green and / or red, a colored layer that transmits white light or a yellow Colored layers that transmit light of various colors may be provided.

[0401] The colored layer may contain a metal material, a pigment, a dye, or the like.

[0402] A light-shielding layer BM is provided so as to surround the window portion 834. The light-shielding layer BM prevents light from passing through the window portion 834. Hard to penetrate.

[0403] Carbon black, metal oxides, and composite oxides including solid solutions of multiple metal oxides are used as light-shielding materials. It can be used for the layer BM.

[0404] At positions overlapping the light-shielding layer BM, the scanning line G1, the signal line DL, the wiring VPI, the wiring RES, and A wiring VRES and a detection circuit 839 are provided.

[0405] In addition, a light-transmitting overcoat layer that covers the colored layer and the light-shielding layer BM may be provided. do.

[0406] The sensing element Ca has a first electrode 821, a second electrode 822, and a pair of electrodes An insulating layer 823 is provided between the electrodes 822 (see FIG. 36).

[0407] The first electrode 821 is formed, for example, in an island shape so as to be separated from other regions. The first electrode 821 and the second electrode 822 are connected to each other so that the first electrode 821 cannot be identified by a user of the output device 800. A configuration in which a layer that can be fabricated in the same process is disposed adjacent to the first electrode 821 is preferred. More preferably, the first electrode 821 and a layer disposed adjacent to the first electrode 821 It is preferable to minimize the number of windows 834 arranged in the gap. A configuration without 834 is preferable.

[0408] For example, the first electrode 821 or the second electrode 822 of the sensing element Ca placed in the air is When something with a dielectric constant different from that of the air approaches, the capacitance of the sensing element Ca changes. When a finger or other object approaches the sensing element Ca, the capacitance of the sensing element Ca changes. This means that it can be used as a proximity detector.

[0409] The first electrode 821 and the second electrode 822 include a conductive material.

[0410] For example, inorganic conductive materials, organic conductive materials, metals, conductive ceramics, etc. It can be used for the electrode 821 and the second electrode 822.

[0411] Specifically, the first electrode 821 and the second electrode 822 are made of aluminum, chromium, copper, etc. , tantalum, titanium, molybdenum, tungsten, nickel, silver or manganese The metal elements, alloys containing the above-mentioned metal elements, or combinations of the above-mentioned metal elements An alloy thereof can be used.

[0412] Alternatively, the first electrode 821 and the second electrode 822 may be made of indium oxide or indium tin. Conductive acids such as oxide, indium zinc oxide, zinc oxide, and zinc oxide doped with gallium Compounds such as fluorine-containing fluorine compounds can be used.

[0413] Alternatively, the first electrode 821 and the second electrode 822 may be made of graphene or graphite. The graphene-containing film can be, for example, a graphene oxide film. The film can be formed by reducing the film containing the compound. The reduction method includes applying heat or reducing the compound. A method using a base agent, etc. can be mentioned.

[0414] Alternatively, a conductive polymer may be used for the first electrode 821 and the second electrode 822. Cut.

[0415] The detection circuit 839 includes, for example, transistors M1 to M3. 839 includes wiring for supplying a power supply potential and a signal. For example, the signal line DL, the wiring VPI, This includes wiring CS, scanning line G1, wiring RES, and wiring VRES.

[0416] The detection circuit 839 may be disposed in a region that does not overlap with the window portion 834 .

[0417] Conductive materials are wired (for example, signal lines DL, wiring VPI, wiring CS, scanning lines G1, For example, inorganic conductive materials, organic conductive materials, etc. Conductive materials, metals, conductive ceramics, etc. can be used for the wiring. The same material as that which can be used for the first electrode 821 and the second electrode 822 is used as the wiring. may be applied.

[0418] Also, aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum Metal materials such as tin, iron, cobalt, copper, or palladium, or alloy materials containing such metal materials. It can be used for the scanning line G1, the signal line DL, the wiring VPI, the wiring RES, and the wiring VRES. Cut.

[0419] The detection circuit 839 may be formed on the first base material 836. Alternatively, the detection circuit 839 may be formed on another base material. The assembled sensing circuit 839 may then be transferred to the first substrate 836 .

[0420] The first substrate 836 and the second substrate 810 may be a glass substrate or a flexible material (e.g. For example, a resin, a resin film, a plastic film, or the like can be used.

[0421] More specifically, the first substrate 836 and the second substrate 810 are made of non-alkali glass. Soda-lime glass, potash glass, crystal glass, etc. can be used. The first base material 836 may be polyester, polyolefin, polyamide, polyimide, or the like. Use a resin film or plate such as polycarbonate, acrylic resin, etc. can be done.

[0422] The protective substrate 837 and / or the protective layer 837p may be, for example, glass or polyester. , polyolefin, polyamide, polyimide, polycarbonate, acrylic resin, etc. A resin film, a resin plate or a laminate thereof can be used.

[0423] The protective layer 837p may be, for example, a hard coat layer or a ceramic coat layer. Specifically, a layer containing a UV curable resin or aluminum oxide can be formed on the second electrode 8. It may be formed at a position overlapping with 22.

[0424] The display module 801 includes a plurality of pixels 802 arranged in a matrix (see FIG. 35). (See (C)).

[0425] For example, pixel 802 includes subpixel 802B, subpixel 802G, and subpixel 802R, Each sub-pixel comprises a display element and a pixel circuit for driving the display element.

[0426] The subpixel 802B of the pixel 802 is disposed at a position overlapping the colored layer CFB, and the subpixel 80 The subpixel 2G is disposed at a position overlapping the colored layer CFG, and the subpixel 802R is disposed at a position overlapping the colored layer CFR. The equipment is placed in a suitable location.

[0427] The colored layer CFR is located so as to overlap the liquid crystal element 880. As a result, the light reflected by the reflective electrode 872 is A part of the reflected light is transmitted through the colored layer CFR and emitted in the direction of the arrow shown in the figure. The electrode 872 may be a conductive film similar to the conductive film 772 functioning as a reflective electrode in the above embodiment. The liquid crystal element 880 may have a dielectric constant anisotropy of 2 or more and 3.8 or less. The liquid crystal layer has a

[0428] In addition, a light-shielding layer BM is provided so as to surround the colored layer (for example, the colored layer CFR).

[0429] The scanning line driver circuit 803g includes a transistor 803t and a capacitor 803c (see FIG. 36). (see).

[0430] The detection signal DATA supplied by the detection unit 820U is converted and then fed to the flexible substrate FPC1 Various circuits that can be used for the converter CONV (FIG. 3) 5(A) and Figure 36).

[0431] For example, transistor M4 can be used for converter CONV.

[0432] The display module 801 includes an anti-reflection layer 867p at a position overlapping the pixel. For example, a circular polarizing plate can be used as 867p.

[0433] As shown in FIG. 35(A), the display module 801 includes wiring that can supply signals. A terminal 819 is provided on the wiring 811. A flexible circuit board FPC2 that can supply signals such as This is being continued.

[0434] In addition, a printed wiring board (PWB) is attached to the flexible board FPC2. is also good.

[0435] The display module 801 has wiring such as scanning lines, signal lines, and power lines. can be used for wiring.

[0436] The wiring of the display module 801 is made of, for example, aluminum, chromium, copper, tin, etc. Ta, titanium, molybdenum, tungsten, nickel, yttrium, zirconium, silver or manganese; an alloy containing the above-mentioned metal element; or In particular, alloys of aluminum, chromium, Contains one or more elements selected from copper, tantalum, titanium, molybdenum, and tungsten. In particular, an alloy of copper and manganese is suitable for microfabrication using a wet etching method. It is appropriate.

[0437] The specific structure of the wiring of the display module 801 is titanium on an aluminum film. A two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film is laminated on a tantalum nitride film. A two-layer structure in which a titanium film is laminated with an tungsten film, and an aluminum film is laminated on the titanium film. A three-layer structure can be used in which a titanium film is formed on the aluminum film. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, sca A laminated layer of an alloy film or a nitride film made of one or more selected from tin, nickel, tin, or tin. Alternatively, a light-transmitting material containing indium oxide, tin oxide, or zinc oxide can be used. Alternatively, a conductive material having such properties may be used.

[0438] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0439] (Embodiment 7) In this embodiment mode, electronic devices manufactured using the liquid crystal display device described in the above embodiment mode will be described. A specific example of this will be described with reference to FIG.

[0440] As an example of an electronic device to which the present invention can be applied, a television device (television or television (also called television receivers), computer monitors, digital cameras, digital video Cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, music players These include video game devices, gaming machines (pachinko machines, slot machines, etc.), and game cabinets. A specific example of electronic equipment is shown in FIG.

[0441] FIG. 37(A) shows a portable information terminal 1400 having a display unit. The 00 has a display unit 1402 and an operation button 1403 built into a housing 1401. The liquid crystal display device of one embodiment of the present invention can be used for the display portion 1402.

[0442] FIG. 37B shows a mobile phone 1410. The mobile phone 1410 has a housing 141 1, a display unit 1412, operation buttons 1413, a speaker 1414, and a microphone 1415. The liquid crystal display device of one embodiment of the present invention can be used for the display portion 1412. Cut.

[0443] FIG. 37C shows a music playback device 1420. The music playback device 1420 has a housing 1 A display unit 1422, an operation button 1423, and an antenna 1424 are incorporated in 421. Moreover, the antenna 1424 can transmit and receive information by radio signals. The liquid crystal display device of one embodiment can be used for the display portion 1422.

[0444] The display unit 1402, the display unit 1412, and the display unit 1422 each have a touch input function. Display buttons (not shown) displayed on the display units 1402, 1412, and 1422 ) you can operate the screen and input information by touching it with your finger or other object.

[0445] The liquid crystal display device shown in the above embodiment includes a display portion 1402, a display portion 1412, and a display portion 14 22, the display unit 1402, the display unit 1412, and the display It can be a display unit 1422.

[0446] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0447] In addition, regarding the contents not specified in the drawings or text in the specification, Alternatively, the upper limit of a certain value may be set. If a numerical range is listed, such as a lower limit, you can narrow the range arbitrarily. Or, by excluding one point within the scope, a mode of the invention that excludes a part of the scope is specified. As a result, for example, the prior art can be considered to be within the technical scope of one aspect of the present invention. It may be stipulated that no entry will be allowed.

[0448] As a specific example, a circuit diagram in which first to fifth transistors are used in a circuit is shown below. In that case, the circuit does not have a sixth transistor. Alternatively, the circuit does not have a capacitance element. Furthermore, it is possible to specify that the circuit has a certain connection structure. The invention can be configured by specifying that the semiconductor device does not have a sixth transistor. Alternatively, it is specified that the circuit does not have a capacitive element having a specific connection structure. For example, the gate of the third transistor may be connected to the gate of the third transistor. It is possible to specify the invention as not having a sixth transistor. Alternatively, for example, a capacitor element having a first electrode connected to the gate of the third transistor may be provided. It is possible to define the invention as not having

[0449] As another specific example, for a certain value, for example, "a certain voltage is 3 V or more and 10 V or less. In that case, for example, if a certain voltage is -2V It is possible to specify one aspect of the invention as "excluding cases where the voltage is greater than or equal to 1 V and less than or equal to 1 V." Or, For example, it is possible to define one aspect of the invention as excluding cases where a certain voltage is 13 V or higher. For example, the invention may be stipulated that the voltage is between 5V and 8V. It is possible. For example, it is also possible to specify the invention as having a voltage of approximately 9V. For example, the voltage is between 3V and 10V, but does not include the case where the voltage is 9V. It is also possible to define the invention as follows: Even if it is described that "it is preferable that these conditions are satisfied" or "it is preferable that these conditions are satisfied," , Certain values ​​are not limited to those descriptions. That is, "preferably", "preferably", etc. However, even if the following description is given, the present invention is not necessarily limited to the above description.

[0450] As another specific example, for a certain value, for example, "It is preferable that a certain voltage is 10 V" In that case, for example, if a certain voltage is between -2V and 1V, It is possible to define an aspect of the invention as "except when It is possible to provide an aspect of the invention that excludes cases where the voltage is 13V or greater.

[0451] As another specific example, when describing the properties of a certain substance, for example, "a certain film is an insulating film," In that case, the insulating film is, for example, an organic insulating film. Alternatively, the insulating film may be an inorganic insulating film. It is possible to define an embodiment of the invention as excluding the case of a velum. Or, for example, It is possible to specify one embodiment of the invention so that the film does not include a conductive film. For example, one aspect of the invention can be stipulated as excluding the case where the film is a semiconductor film. It is Noh.

[0452] As another specific example, regarding a certain laminated structure, for example, "between film A and film B, a certain film is In that case, for example, if the membrane is a laminate of four or more layers, Or, for example, the invention can be defined as "excluding the case where the film is a multi-layer film." It is possible to define the invention as excluding the case where a conductive film is provided between the film and the .

[0453] It should be noted that one aspect of the invention described in this specification etc. may be carried out by various people. However, the implementation may involve multiple people. For example, in the case of a transmitting and receiving system, Company A manufactures and sells the transmitter, and Company B manufactures the receiver. Another example is a light-emitting device having a TFT and a light-emitting element. In the case of a device, the semiconductor device on which the TFT is formed is manufactured and sold by Company A. Company B then purchases the semiconductor device, deposits light-emitting elements on the semiconductor device, and produces light-emitting devices. In some cases, the project is completed as a set piece.

[0454] In such a case, the inventor must be able to assert patent infringement against either Company A or Company B. In other words, it is possible to construct an embodiment of the invention that is implemented only by Company A. It is possible to construct an invention that is implemented only by Company B as a separate invention. In addition, it is possible to assert a patent infringement claim against Company A or Company B. It can be determined that one aspect of the invention that can be used is clear and described in the present specification, etc. For example, in the case of a transmission and reception system, there are descriptions for only the transmitter and for only the receiver. Even if the description of the above case is not included in the present specification, the transmitter alone constitutes one aspect of the invention. The receiver alone can constitute one aspect of another invention, and one aspect of those inventions can be is clear and can be judged to be described in the present specification. In the case of a light-emitting device having a TFT and a light-emitting element, the semiconductor device in which the TFT is formed The present specification does not include any description of only the device or only the light emitting device having the light emitting element. However, one embodiment of the present invention can be constituted only by a semiconductor device having a TFT formed thereon. One embodiment of the invention can be constituted by only a light-emitting device having a light-emitting element. One aspect can be considered clear and described herein.

[0455] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of devices (capacitive elements, resistive elements, etc.), the connection destination is not specified. However, a person skilled in the art may be able to configure one aspect of the invention. Even if the destination is not specified, one aspect of the invention is clear. When the contents are described in this specification, etc., one aspect of the invention that does not specify a connection destination is the same as the embodiment of the present specification. In particular, when the terminals are connected to multiple If such a case is considered, there is no need to limit the connection destination of the terminal to a specific location. Therefore, there are active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistive elements, etc.) By specifying the connection destinations of only some of the terminals of a device (e.g., It may be possible to configure one embodiment.

[0456] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art can identify an invention by at least specifying the function. In other words, if a function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0457] In this specification, etc., in a drawing or text described in a certain embodiment, It is possible to extract a part of the invention and use it as an embodiment of the invention. If a figure or text describing a certain part is included, the figure or text of that part will be taken out. The above-mentioned contents are disclosed as one aspect of the invention and constitute one aspect of the invention. It is possible to say that one aspect of the invention is clear. Well, for example, in a drawing or text that describes a single or multiple active elements (such as transistors, diodes), wirings, passive elements (such as capacitor elements, resistor elements), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc., it is assumed that a part thereof can be extracted to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitor elements), M ( M is an integer and M < N) circuit elements (such as transistors, capacitor elements) can be extracted to constitute an aspect of the invention. Another example is that from a cross-sectional view composed of N (N is an integer) layers, M (M is an integer and M < N) layers can be extracted to constitute an aspect of the invention. Still another example is that from a flowchart composed of N (N is an integer) elements, M (M is an integer and M < N) elements can be extracted to constitute an aspect of the invention. Yet another example is that from a text described as "A has B, C, D, E, or F", by arbitrarily extracting some elements, aspects of the invention such as "A has B and E", "A has E and F", "A has C, E, and F", or "A has B, C, D, and E" can be constituted. It should be noted that in this specification, etc., when at least one specific example is described in a drawing or text described in a certain embodiment, deriving the upper concept of the specific example is easily understood by those skilled in the art. Therefore, when at least one specific example is described in a drawing or text described in a certain embodiment, the upper concept of the specific example

[0458] In addition, in this specification, etc., in a drawing or text described in a certain embodiment, when at least one specific example is described, deriving the upper concept of the specific example is easily understood by those skilled in the art. Thus, when at least one specific example is described in a drawing or text described in a certain embodiment, the upper concept of the specific example The invention is also disclosed as an embodiment of the invention and may constitute an embodiment of the invention. And one aspect of the invention can be said to be clear.

[0459] In this specification, at least the contents shown in the drawings (or even a part of the drawings) This is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if something is shown in a diagram, it does not need to be explained in words. However, the contents are disclosed as one aspect of the invention and constitute one aspect of the invention. Similarly, a part of the drawings may be regarded as an embodiment of the invention. This is disclosed as one embodiment of the present invention. It can be said that one aspect of the invention is clear. [Explanation of symbols]

[0460] C1 terminal C2 terminal C3 Terminal C4 terminal CK1 wiring CK2 Wiring CK3 Wiring CK4 Wiring G1 scan line M1 Transistor M3 Transistor M4 Transistor ND1 Node S1 terminal S2 terminal S3 Terminal S4 Terminal SP1 Wiring SP2 Wiring VSS1 wiring VSS2 wiring VSS3 wiring VSS4 wiring FPC1 Flexible Circuit Board FPC2 Flexible Circuit Board SR circuit Period A B period C period D Period E Period F period G Period H period OUT wiring O terminal SL Wiring DL signal line CS wiring RES wiring VPI Wiring VRES wiring Ca sensing element BG wiring 100 circuits 101 Transistor 102 Transistor 103 Transistor 103A Transistor 103B Transistor 103C Transistor 103D Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 113 Transistor 114 Transistor 115 Transistor 116 Transistor 116A Transistor 116B Transistor 130 Pixel section 131 pixels 132 Transistor 133 Liquid crystal element 134 Capacitive element 135 Transistor 136 Transistor 137 EL element 600 Transistors 601 Substrate 602 Gate electrode 603 Insulation Layer 604 Oxide semiconductor layer 604a Channel Region 604b n-type region 604c n-type region 605a electrode 605b electrode 606 Insulating layer 607 Insulating Layer 610 Transistor 614 Oxide semiconductor layer 614a Oxide semiconductor layer 614b Oxide semiconductor layer 620 Transistor 624 Oxide Semiconductor Layer 624a Oxide semiconductor layer 624b Oxide semiconductor layer 624c Oxide semiconductor layer 650 Transistors 651 Insulation Layer 652 Insulating layer 654 Insulating layer 656 Insulating Layer 660 Transistor 664 Oxide Semiconductor Layer 664a Oxide semiconductor layer 664b Oxide semiconductor layer 664c Oxide semiconductor layer 670 Transistors 700 Display Module 701 Substrate 702 Pixel section 704 Source driver circuit section 705 Substrate 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 734 Insulating film 736 Colored film 738 Light-shielding film 750 Transistors 752 Transistor 760 Connection electrode 764 Insulating film 768 Insulating Film 770 Planarizing Insulating Film 772 Conductive Film 774 Conductive Film 775 Liquid crystal elements 776 Liquid crystal layer 778 Structure 780 Anisotropic Conductive Film 790 Capacitive element 800 I / O devices 801 Display module 802 pixels 802B subpixel 802G subpixel 802R subpixel 803c capacity 803g Scanning line driver circuit 803t Transistor 810 Base material 811 Wiring 819 Terminal 820U Detection Unit 821 Electrode 822 Electrode 823 Insulating layer 834 Window 836 Base material 837 Protective base material 837p protective layer 839 Detection circuit 850 Input Device 867p anti-reflection layer 872 Reflecting electrode 880 Liquid crystal element 1400 Mobile Information Terminal 1401 Case 1402 Display section 1403 Operation button 1410 Mobile Phones 1411 Case 1412 Display section 1413 Operation button 1414 Speaker 1415 Mike 1420 Music player 1421 Case 1422 Display section 1423 Operation button 1424 Antenna

Claims

1. The semiconductor device includes first to seventh transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a gate signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; the other of the source and the drain of the second transistor is always electrically connected to a power supply line; one of a source and a drain of the third transistor is always electrically connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the third transistor is always electrically connected to one of a source and a drain of the fifth transistor; a gate of the third transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a first signal line; the gate of the fourth transistor is always electrically connected to the second signal line; the other of the source and the drain of the fifth transistor is always electrically connected to a third signal line; the gate of the fifth transistor is always electrically connected to a fourth signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the third transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a fifth signal line; a gate of the sixth transistor is always electrically connected to the fifth signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the third transistor; a gate of the seventh transistor is always electrically connected to one of the source and the drain of the third transistor; when the other of the source and the drain of the third transistor is in a conductive state with the gate of the first transistor and the gate of the seventh transistor through at least a channel formation region of the third transistor, a potential at which the first transistor is turned off and a potential at which the seventh transistor is turned off are input to the gate of the first transistor through at least a channel formation region of the third transistor, when the other of the source and the drain of the seventh transistor is in a conductive state with the gate of the third transistor at least through a channel formation region of the seventh transistor, a potential at which the third transistor is turned off is input to the gate of the third transistor at least through the channel formation region of the seventh transistor, when the first signal line is in a conductive state with the gate of the first transistor via at least a channel formation region of the fourth transistor, a potential at which the first transistor is turned on is input to the gate of the first transistor via at least a channel formation region of the fourth transistor, a gate of the first transistor through a channel formation region of the fifth transistor, and a potential at which the first transistor is turned on is input to the gate of the first transistor through the channel formation region of the fifth transistor.

2. The semiconductor device includes first to seventh transistors, one of the source and the drain of the first transistor is always electrically connected to a clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a gate signal line; one of the source and the drain of the second transistor is always electrically connected to the gate signal line; the other of the source and the drain of the second transistor is always electrically connected to a power supply line; one of a source and a drain of the third transistor is always electrically connected to one of a source and a drain of the fourth transistor; one of a source and a drain of the third transistor is always electrically connected to one of a source and a drain of the fifth transistor; a gate of the third transistor is always electrically connected to a gate of the second transistor; the other of the source and the drain of the fourth transistor is always electrically connected to a first signal line; the gate of the fourth transistor is always electrically connected to the second signal line; the other of the source and the drain of the fifth transistor is always electrically connected to a third signal line; the gate of the fifth transistor is always electrically connected to a fourth signal line; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the third transistor; the other of the source and the drain of the sixth transistor is always electrically connected to a fifth signal line; a gate of the sixth transistor is always electrically connected to the fifth signal line; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the third transistor; a gate of the seventh transistor is always electrically connected to one of the source and the drain of the third transistor; when the other of the source and the drain of the third transistor is in a conductive state with the gate of the first transistor and the gate of the seventh transistor through at least a channel formation region of the third transistor, a potential at which the first transistor is turned off and a potential at which the seventh transistor is turned off are input to the gate of the first transistor through at least a channel formation region of the third transistor, when the other of the source and the drain of the seventh transistor is in a conductive state with the gate of the third transistor at least through a channel formation region of the seventh transistor, a potential at which the third transistor is turned off is input to the gate of the third transistor at least through the channel formation region of the seventh transistor, when the first signal line is in a conductive state with the gate of the first transistor via at least a channel formation region of the fourth transistor, a potential at which the first transistor is turned on is input to the gate of the first transistor via at least a channel formation region of the fourth transistor, when the third signal line is in a conductive state with the gate of the first transistor via at least a channel formation region of the fifth transistor, a potential at which the first transistor is turned on is input to the gate of the first transistor via at least a channel formation region of the fifth transistor, W (channel width) / L (channel length) of the first transistor is larger than W / L of the second transistor, the W / L of the first transistor is greater than the W / L of the third transistor; the W / L of the first transistor is greater than the W / L of the fourth transistor; A semiconductor device in which the W / L of the first transistor is larger than the W / L of the fifth transistor.

3. A semiconductor device according to claim 1 or 2, and a pixel, the pixel includes an eighth transistor; One of the source and the drain of the eighth transistor is always electrically connected to the liquid crystal element; the other of the source and the drain of the eighth transistor is always electrically connected to a source signal line; the gate of the eighth transistor is always electrically connected to the gate signal line; A display device in which the drive mode of the liquid crystal element is an FFS mode.

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