Signal processing device and program

Abstract

To reduce the standby time when processing a plurality of color signals in a band unit.SOLUTION: An image processing unit includes a module A10, a module B12 and a shared buffer memory 18. The module A10 executes first processing of processing a plurality of color signals at a time and outputting the color signals in parallel with each other. The buffer memory 18 temporarily stores the plurality of color signals output from the module A10. The module B12 performs processing by reading out the plurality of color signals in order by the number in which the processing can be performed once from the buffer memory 18. The module A10 starts processing of the second band at timing at which the color signal of the first band is left in the buffer memory 18 and before completion of processing of the first band in the module B12.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a signal processing device and a program. [Background technology]

[0002] Patent Document 1 describes an information processing device that prevents waiting time from occurring in the processing operation of the latter-stage processing means even when the number of color signals that the latter-stage processing means can process at one time is smaller than the number of color signals that the former-stage processing means can process at one time. The information processing device has a first processing means that processes multiple color signals at one time and outputs them in parallel, a storage means that temporarily stores the multiple color signals output in parallel from the first processing means, and a second processing means that reads out the multiple color signals from the storage means in sequence in the number that can be processed at one time and processes them, and is capable of processing a smaller number of color signals at one time than the first processing means, and the speed at which the signals are read from the storage means is faster than the speed at which the signals are written to the storage means. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-81321 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, when processing multiple color signals in bands consisting of multiple lines, if the first and second processors finish processing a band before moving on to processing the next band, a time lag equivalent to the transfer unit in the storage means will occur, resulting in a waiting time for each band.

[0005] The present invention aims to provide a technology that can reduce waiting time when processing multiple color signals on a band-by-band basis when transferring multiple color signals using two processing means and a storage means, compared to a method in which processing of a band is completed before moving on to processing the next band. [Means for solving the problem]

[0006] The invention described in claim 1 includes a first processor and a second processor that read and execute a program, and a storage means, wherein the first processor processes a plurality of color signals at once and outputs them in parallel, the storage means temporarily stores the plurality of color signals output from the first processor, the second processor reads out and processes the plurality of color signals from the storage means in sequence in the number that can be processed at one time, and the first processor and the second processor store the plurality of color signals in a , consisting of image width × N lines (N is an integer greater than or equal to 2) The processing is performed in band units, and after the processing of the first band is completed, the processing of the next second band is started, and the first processor starts the processing of the second band at a timing before the processing of the first band is completed by the second processor and while the color signal of the first band remains in the storage means. and the second processor starts processing the second band before reading out the color signal of the last line of the first band from the storage means. It is a signal processing device.

[0008] Claim 2 The invention described in claim 1 is characterized in that the first processor writes one line of color signals constituting the first band into the storage means and then notifies the second processor of the completion of writing, and the second processor, after receiving the completion of writing, reads the color signals processed by the first processor from the storage means and notifies the first processor of the completion of reading. 1 The present invention relates to a signal processing device.

[0009] Claim 3The invention described in claim 1 is characterized in that the first processor writes the color signals of the last line constituting the first band into the storage means and then notifies the second processor of the completion of writing, the second processor reads the color signals of the line before the last line from the storage means and notifies the first processor of the completion of reading after receiving the completion of the writing from the first processor, and the first processor processes the color signals of the first line constituting the second band and writes them into the storage means without overwriting the color signals of the last line. 2 The present invention relates to a signal processing device.

[0010] Claim 4 The invention described in claim 1 is characterized in that the second processor writes the color signals of the first line constituting the second band in the first processor to the storage means without overwriting the color signals of the last line, and reads the color signals of the last line from the storage means after receiving a notification of the completion of the writing. 3 The present invention relates to a signal processing device.

[0011] Claim 5 The invention described in claim 1 is characterized in that the first processor writes the color signals of the last line of the last band constituting a page into the storage means and then notifies the second processor of the completion of writing, and the second processor reads the color signals of the line before the last line of the last band from the storage means after receiving the completion of writing from the first processor, and further reads the color signals of the last line of the last band from the storage means and notifies the first processor of the completion of reading. 4 The present invention relates to a signal processing device.

[0012] Claim 6 In the invention described in the above, a plurality of the second processors are provided, signal The different color signals among the above are read out from the storage means and processed. 5The present invention relates to a signal processing device.

[0013] The invention described in claim 7 causes a processor to function as a first processing means for processing a plurality of color signals at once and outputting them in parallel, and a second processing means for reading out and processing the plurality of color signals in sequence, in the number that can be processed at once, from a storage device that temporarily stores the plurality of color signals output from the first processing means, and the first processing means and the second processing means process the plurality of color signals in band units consisting of an image width×N lines (N is an integer of 2 or more) and start processing the next second band after the processing of the first band is completed, and the first processing means starts processing the second band at a timing before the processing of the first band is completed by the second processing means and when the color signals of the first band remain in the storage device, and the second processing means Processing Means to start processing the second band before the color signal of the last line of the first band is read from the storage device. Effect of the Invention

[0014] Claim 1~ 7 According to the invention described in the item 2, when a plurality of color signals are transferred, the waiting time when the plurality of color signals are processed in units of bands can be reduced. [Brief description of the drawings]

[0015] [Figure 1] 1 is an overall configuration diagram of an image forming apparatus. [Diagram 2] FIG. 4 is a configuration block diagram of an image processing unit of a comparative example. [Diagram 3] 3 is a timing chart of a comparative example of FIG. 2. [Figure 4] FIG. 13 is a configuration block diagram of an image processing unit of another comparative example. [Diagram 5] 5 is a timing chart of a comparative example of FIG. 4. [Figure 6] FIG. 13 is a configuration block diagram of an image processing unit of still another comparative example. [Figure 7]7 is a timing chart of a comparative example of FIG. 6. [Figure 8] 4 is a timing chart of the image processing unit according to the embodiment. [Figure 9] 13 is another timing chart of the image processing unit of the embodiment. [Figure 10] FIG. 2 is a configuration block diagram of a DMAC of a module A in the embodiment. [Figure 11] FIG. 2 is a configuration block diagram of a DMAC of a module B in the embodiment. [Figure 12] 11 is a process flowchart of a write counter unit and a read counter unit according to the embodiment. [Figure 13] 13 is a flowchart showing a process of the DMAC of module A in the embodiment. [Figure 14] 13 is a flowchart illustrating a process of the DMAC of module B in the embodiment. [Figure 15] 5 is a processing timing chart of a first band and a second band according to an embodiment. [Figure 16] 13 is a process timing chart of the third band according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking an image forming apparatus as an example.

[0017] First, a configuration of a comparative example that is a premise of this embodiment will be described.

[0018] An image forming apparatus is an apparatus that forms an image on a recording material, and has a copy function, a scanner function, a fax sending / receiving function, a printing function, and the like.

[0019] FIG. 1 is a diagram showing an example of the appearance of an image forming apparatus 1 described in, for example, Patent Document 1. As shown in FIG.

[0020] The image forming apparatus 1 includes an image reading device 100 that reads an image of a document, and an image recording device 200 that records an image on a sheet of paper.

[0021] The image forming apparatus 1 also includes a user interface (UI) 300 that is used to accept operations by a user and to present various types of information to the user. The image forming apparatus 1 also includes a control device that controls the overall operation of the image forming apparatus 1.

[0022] Image reading device 100 is attached on top of image recording device 200 which constitutes the main body of the device. Image reading device 100 includes image reading section 110 which optically reads an image formed on a document, and document transport section 120 which transports the document to image reading section 110. Document transport section 120 has document storage section 121 which stores documents, and document discharge section 122 to which documents pulled out from document storage section 121 are discharged, and transports the documents from document storage section 121 to document discharge section 122 using a transport mechanism.

[0023] The image recording device 200 includes a mechanism for forming an image on the surface of a sheet of paper, a mechanism for transporting the sheet of paper, and the like.

[0024] The image recording device 200 includes an image forming unit that forms an image on paper pulled out from a paper tray 250, a paper supply unit that supplies paper to the image forming unit, a paper discharge unit that discharges the paper on which the image has been formed by the image forming unit, and an inversion transport unit that inverts the paper output from the image forming unit and transports it again toward the image forming unit.

[0025] In the image forming section, recording units corresponding to each color of yellow (Y), magenta (M), cyan (C), and black (K) are arranged along the paper transport path.

[0026] Each recording unit includes a photoconductor drum, a charger that charges the surface of the photoconductor drum, an exposure unit that irradiates the charged photoconductor drum with laser light to draw an image, a developer that develops the drawn image into a toner image, and a transfer unit that transfers the toner image to a transfer belt. The toner images corresponding to each color transferred to the transfer belt are finally transferred to the surface of a sheet of paper and fixed by a fixing unit.

[0027] A paper tray 250 for storing paper is disposed at the bottom of the image recording device 200, and a plurality of discharge trays 260 for discharging paper on which images have been formed are provided at the top of the image recording device 200.

[0028] The user interface 300 is disposed on the front side of the image reading device 100 so that its operation surface faces the user who operates the image forming device 1.

[0029] The user interface 300 has an operation unit that accepts instructions from a user and a display unit that provides information to the user. The operation unit has a function to detect operations on, for example, hardware keys or software keys. The display unit displays software keys, etc. as an operation screen.

[0030] The control device is provided inside the housing of the image recording device 200. The control device has a CPU (Central Processing Unit), a ROM (Read Only Memory) in which firmware, a BIOS (Basic Input / Output System), etc. are stored, and a DDR SDRAM used as a work area for the CPU, which together constitute a general computer.

[0031] The control device has an image processing unit that executes various processes required for image formation (e.g., color correction, gradation correction, etc.) The image processing executed by the image processing unit includes a circuit unit that processes all of the print data corresponding to the four colors of cyan (C), magenta (M), yellow (Y), and black (K) in parallel, and a circuit unit that processes the print data output from the circuit unit one color at a time in sequence.

[0032] 2 shows the configuration of an image processing unit of a comparative example. The image processing unit includes, for example, two modules, a module A10 and a module B12, and these modules 10 and 12 are connected to a DDR16 via a bus 14. Both the module A10 and the module B12 are modules that simultaneously process four colors, CMYK, in parallel, and include a color-specific DMAC (Direct Memory Access Controller) that reads print data for four colors, CMYK, from the DDR16 without going through a CPU (not shown), and a color-specific DMAC that writes print data for four colors, CMYK, to the DDR without going through a CPU. Although the module A10 and the DMAC are functionally separate members, for convenience of explanation, in this embodiment, the module A10 and the DMAC are described as being one unit.

[0033] Module A10 reads the print data for four colors, CMYK, from DDR 16 via bus 14 using DMAC, executes predetermined processing, and stores the data in DDR 16. Module B12 reads the print data for four colors, CMYK, that has been processed by module A10 from DDR 16 via bus 14, executes predetermined processing, and stores the data in DDR 16.

[0034] Module A10 and module B12 divide the print data into bands and execute processing for each band. Here, one band is composed of image width×N lines (N is an integer of 2 or more).

[0035] Fig. 3 shows a timing chart of processing in the configuration of Fig. 2. Fig. 3(a) is a timing chart of module A10, and Fig. 3(b) is a timing chart of module B12. It is assumed that the print data is composed of a first band, a second band, and a third band. For convenience of explanation, the print data processed by module A10 will be referred to as A-processed print data.

[0036] First, the module A 10 reads and processes the print data of the first band of four colors, CMYK, from the DDR 16. Next, the module B 12 reads and processes the A-processed print data of the first band of four colors, CMYK, from the DDR 16.

[0037] Module A10 reads and processes the next second band of CMYK four-color print data from DDR 16 in parallel with the processing of the first band of CMYK four-color print data that has been A-processed in module B12. Module B12 then reads the second band of CMYK four-color print data that has been A-processed from DDR 16 and processes it.

[0038] Module A10 reads and processes the next, third band of CMYK four-color print data from DDR 16 in parallel with module B12 processing the second band of CMYK four-color A-processed print data. Module B12 then reads the third band of CMYK four-color A-processed print data from DDR 16 and processes it.

[0039] However, in such processing, the amount of data read / written from / to the DDR16 increases, causing the DDR16 to become a bottleneck, making it difficult to increase the processing speed. Therefore, it is desirable to be able to transfer the A-processed print data directly from the module A 10 to the module B 12 without passing through the bus 14 and the DDR 16.

[0040] Fig. 4 shows the configuration of an image processing section of another comparative example. The configurations of module A10 and module B12 are the same as those in Fig. 2, but a buffer memory 18 capable of high speed operation is provided for each color of CMYK between module A10 and module B12. That is, a buffer memory for C, a buffer memory for M, a buffer memory for Y, and a buffer memory for K are provided between module A10 and module B12. In the figure, these buffer memories for each color of CMYK are collectively referred to as buffer memory 18.

[0041] When the module A 10 processes the print data for four colors, CMYK, the print data that has been A-processed is temporarily stored in these buffer memories 18 by the DMAC, and the DMAC of the module B 12 reads out the A-processed print data from the buffer memories 18 and processes it, thereby reducing the transfer of print data via the DDR 16. The buffer memories 18 are configured as ping-pong buffers or ring buffers, and each color only needs to have a capacity of at least two lines. The buffer memories 18 can be buffer memories originally provided inside the LSI, and may have a capacity of, for example, about 512 MB.

[0042] Fig. 5 shows a process flow chart in the configuration of Fig. 4. Fig. 5(a) is a timing chart of the module A10, and Fig. 5(b) is a timing chart of the module B12.

[0043] The module A10 reads and processes the first band of four-color CMYK print data from the DDR 16. Then, every time processing of one line of print data is completed, the data is transferred to the buffer memory 18 by the DMAC.

[0044] When module A10 completes processing of the print data for the last line of the first band and transfers it to buffer memory 18, it waits for the downstream module B12 to complete processing of the A-processed print data of the first band, and after processing in module B12 is completed, it begins processing the four-color CMYK print data of the next second band.

[0045] Module B12 sequentially reads and processes the A-processed print data of the first band of four colors, CMYK, from buffer memory 18. Then, when processing of the A-processed print data of the last line of the first band is completed, next, it reads and processes the A-processed print data of the first line of the second band stored in buffer memory 18.

[0046] In this way, by providing a shared buffer memory 18 that directly connects module A10 and module B12, print data can be transferred from module A10 to module B12 without going through DDR16, thereby eliminating the bottleneck problem of DDR16.

[0047] However, since module A10 moves on to processing the next second band after module B12 has also completed processing the first band, there is always a waiting time for each band, which is the transfer unit (in this case, one line) of the shared buffer memory 18. In other words, module A cannot start processing the next band until module B has read all of the A-processed print data stored in buffer memory 18, and must wait until module B has finished reading the A-processed print data stored in buffer memory 18.

[0048] Although the configuration in FIG. 3 to FIG. 5 includes two modules, module A10 and module B, the same problem may occur in a configuration including more modules.

[0049] 6 shows a configuration of three modules, module A10, module B-0, and module B-1, with module B12 being divided into two modules, module B-0 and module B-1. For example, this corresponds to a case where module A10 is configured with one core (single core) and module B12 is configured with two cores (dual core), and module A10 processes the four colors of CMYK in parallel and simultaneously, while module B12 processes the four colors of CMYK one color at a time in two separate processes. Specifically, module B-0 processes C and M alternately one color at a time, and module B-1 processes Y and K alternately one color at a time.

[0050] Fig. 7 shows a processing timing chart in the configuration of Fig. 6. Fig. 7(a) is a timing chart for module A10, Fig. 7(b) is a timing chart for module B-0, and Fig. 7(c) is a timing chart for module B-1.

[0051] Module A10 reads the first band of four-color CMYK print data from DDR 16 and processes it. Then, every time processing of one line of print data is completed, it transfers it to buffer memory 18. When processing of the last line of print data of the first band is completed, module A10 waits for the subsequent modules B-0 and B-1 to complete processing of the A-processed print data of the first band, and after processing in modules B-0 and B-1 is completed, starts processing the next second band of four-color CMYK print data.

[0052] The module B-0 reads out the A-processed print data C from the buffer memory 18 and processes it out of the A-processed print data of the first band of four colors, CMYK. When the processing of the A-processed print data C is completed, the module B-0 next reads out the A-processed print data M from the buffer memory 18 and processes it out. When the processing of the A-processed print data M is completed, the module B-0 again reads out the A-processed print data C from the buffer memory 18 and processes it out. When the processing of the A-processed print data C is completed, the module B-0 again reads out the A-processed print data M from the buffer memory 18 and processes it out. That is, the module B-0 alternately repeats the processing of the A-processed print data C and M twice.

[0053] Furthermore, in parallel with the processing of module B-0, module B-1 reads out the A-processed print data of Y from the buffer memory 18 and processes it out of the A-processed print data of the four colors CMYK of the first band. When the processing of the A-processed print data of Y is completed, it then reads out the A-processed print data of K from the buffer memory 18 and processes it out. When the processing of the A-processed print data of K is completed, it again reads out the A-processed print data of Y from the buffer memory 18 and processes it out. When the processing of the A-processed print data of Y is completed, it again reads out the A-processed print data of K from the buffer memory 18 and processes it out. That is, module B-1 alternately repeats the processing of the A-processed print data of Y and K twice.

[0054] Even in this case, module A10 completes processing of the first band, and then proceeds to processing of the next second band after modules B-0 and B-1 have completed processing of the first band, so there is always a waiting time for each band that is the transfer unit in buffer memory 18 (in this case, one line).

[0055] In consideration of the problem of occurrence of the above-mentioned waiting time, in this embodiment, the writing timing and reading timing to the shared buffer memory 18 are adjusted to further reduce the waiting time occurring in the comparative example.

[0056] Next, the processing of this embodiment will be described.

[0057] FIG. 8 shows a timing chart of this embodiment. The configuration of this embodiment is the same as that shown in FIG. 4, and the image processing unit as a signal processing device includes a module A10, a module B12, and a buffer memory 18 that directly connects these two modules A10 and B12. In this embodiment, the module A10 functions as a first processor, and the module B12 functions as a second processor, and each of them realizes various functions by reading and executing a program. Note that the DMAC of the module A10 and the DMAC of the module B12 are dedicated controllers that execute DMA (Direct Memory Access), and are separate from the processor that executes the processing of the module A10, but in this embodiment, they are collectively referred to as a processor for convenience. In addition, the buffer memory 18 functions as a storage means. Here, the processor refers to a processor in a broad sense, and includes a general-purpose processor (e.g., a CPU Central Processing Unit, etc.) and a dedicated processor (e.g., a GPU Graphics Processing Unit, an ASIC Application Specific Integrated Circuit, an FPGA Field Programmable Gate Array, a programmable logic device, etc.). In addition, the operations of the processor may not only be performed by a single processor, but may be performed by multiple processors located at physically separate locations in cooperation with each other. Also, the order of the operations of the processor may be changed as appropriate.

[0058] The upper part of Fig. 8 shows a timing chart of a comparative example, which is the same as the timing chart shown in Fig. 5. On the other hand, the lower part of Fig. 8 shows a timing chart of this embodiment.

[0059] In the comparative example, the module A10 starts processing the next second band after the module B12 has completed processing all the lines of the first band, but in this embodiment, the module A10 starts processing the next second band before the module B12 has completed processing all the lines of the first band. More specifically, in the comparative example, the module A10 starts processing the next second band after the module B12 has completed processing the last line of the first band and there is no A-processed print data remaining in the buffer memory 18, but in this embodiment, the module A10 starts processing the next second band when the A-processed print data still remains in the buffer memory 18, that is, when the print data of the last line of the first band remains because it has not yet been read out. If the first band is composed of N lines, the process starts when the A-processed print process of (N-1) lines is completed and N lines of A-processed print data still remain in the buffer memory 18.

[0060] In the lower timing chart of FIG. 8, the module A10 reads out the first band of CMYK four-color print data from the DDR 16 and processes it. Then, each time processing of one line of print data is completed, it transfers it to the buffer memory 18. When the module A10 completes processing of the print data of the Nth line, which is the last line of the first band, the module A10 starts processing the next second band of CMYK four-color print data with the Nth line of A-processed print data remaining in the buffer memory 18 after the subsequent module B12 completes processing of the (N-1)th line of the first band of A-processed print data. Then, when processing of the first line of the second band of CMYK print data is completed, the module A10 writes the A-processed print data to the buffer memory 18.

[0061] However, the write start position is adjusted based on the amount of remaining data in the buffer memory 18 so as not to overwrite the A-processed print data of the first band that still remains in the buffer memory 18 and has not yet been read out by module B.

[0062] Meanwhile, in parallel with this, module B12 reads and processes the A-processed print data of N lines of the first band remaining in buffer memory 18, and when that processing is completed, reads and processes the A-processed print data of the CMYK four-color print data of the second band at the read start position corresponding to the write start command specified based on the amount of remaining data in buffer memory 18. Thereafter, processing continues in the same manner in module A10 and module B12 in sequence.

[0063] According to this process, module A10 does not need to wait for module B12 to complete processing on a band-by-band basis, and can start processing the next band while the A-processed print data remains in the buffer memory 18, so the waiting time for each band can be reduced compared to the comparative example. In this embodiment, since the waiting time for each band can be reduced, the reduction effect becomes more noticeable as the number of bands increases.

[0064] A timing chart of another embodiment is shown in Fig. 9. The configuration is the same as that shown in Fig. 6, and includes a module A10, modules B-0 and B-1, and a buffer memory 18 that directly connects these three modules A10, B-0 and B-1.

[0065] The upper part of Fig. 9 shows a timing chart of a comparative example, which is the same as the timing chart shown in Fig. 7. On the other hand, the lower part of Fig. 9 shows a timing chart of this embodiment.

[0066] In the comparative example, as described above, the module A10 starts processing the next second band after the modules B-0 and B-1 have completed processing all the lines of the first band, but in this embodiment, the module A10 starts processing the next second band before the modules B-0 and B-1 have completed processing all the lines of the first band. More specifically, in the comparative example, the module A10 starts processing the next second band after the modules B-0 and B-1 have completed processing the last line of the first band and no A-processed print data remains in the buffer memory 18, but in this embodiment, the module A10 starts processing the next second band when A-processed print data still remains in the buffer memory 18, that is, when the last line of the first band still remains. If the first band is composed of N lines, the process starts when the A-processed print process of (N-1) lines is completed and N lines of A-processed print data remain in the buffer memory.

[0067] In the lower timing chart of Fig. 9, the module A10 reads out and processes the first band of four-color CMYK print data from the DDR 16. Then, each time processing of one line of print data is completed, the module A10 transfers it to the buffer memory 18. When processing of the print data of the Nth line, which is the last line of the first band, is completed, the module A10 waits for the subsequent modules B-0 and B-1 to complete processing of the A-processed print data of the (N-1)th line of the first band, and after the modules B-0 and B-1 have completed processing of the A-processed print data of the (N-1)th line, the module A10 starts processing the next second band of four-color CMYK print data while leaving the A-processed print data of the Nth line in the buffer memory 18. Then, when processing of the first line of the four-color CMYK print data of the second band is completed, the A-processed print data is written to buffer memory 18, but at this time, the write start position is adjusted based on the amount of remaining data in buffer memory 18 so as not to overwrite the A-processed print data of the first band that still remains in buffer memory 18 and has not been read out by modules B-0, B-1.

[0068] On the other hand, modules B-0 and B-1 read and process the A-processed print data of N lines of the first band remaining in buffer memory 18, and when that processing is completed, read and process the A-processed print data of the CMYK four-color print data of the second band at the read start position corresponding to the write start command specified based on the amount of remaining data in buffer memory 18. Thereafter, processing continues in the same manner in module A10 and modules B-0 and B-1 in sequence.

[0069] Even in this process, module A10 does not need to wait for modules B-0 and B-1 to complete band-by-band processing, and can start processing the next band while the A-processed print data is present in buffer memory 18, thereby reducing the waiting time compared to the comparative example.

[0070] Writing of A-processed print data processed in module A to buffer memory 18 and reading of A-processed print data from buffer memory 18 are controlled by the DMAC of each module.

[0071] 10 shows the configuration of the DMAC 20 of the module A10. A DMAC 20 is provided for each color, and the configuration of the DMAC 20 for a specific color (e.g., Y) is shown as an example. The DMAC 20 of the module A10 includes a buffer manager 22, a write counter 24, a CMD (command) manager 26, and a DATA (data) manager 28.

[0072] The buffer management unit 22 includes a start buffer designation unit and a band management unit. The start buffer designation unit outputs the start position of each band in two or more buffer memories 18 (in the case of a ping-pong buffer) to the CMD management unit 26, and the band management unit generates a start address to be used by the CMD management unit 26 according to the current number of bands and number of lines.

[0073] The write counter unit 24 sets a count value by counting up in response to a notification of write completion (output of a write completion signal) and counting down in response to a notification of read completion (input of a read completion signal). The initial value of the write counter unit 24 is 0, and it counts up by 1 when it receives a notification of write completion and counts down by 1 when it receives a notification of read completion. The write counter unit 24 manages the number of lines being used in the buffer memory 18.

[0074] The CMD management unit 26 calculates an address, a burst, and the like from the specified top address and a predetermined image width, and issues a write command. In addition, the CMD management unit 26 outputs a write completion notification (write completion signal) to the DMAC of module B 12 every time writing of one line of print data to the buffer memory 18 is completed. The CMD management unit 26 controls the write operation to the buffer memory 18 based on the count value of the write counter unit 24.

[0075] The DATA management unit 28 issues the print data processed by the module A10 as write data in cooperation with the CMD management unit 26. The write command from the CMD management unit 26 and the write data from the DATA management unit 28 constitute a DMA signal.

[0076] 11 shows the configuration of the DMAC 30 of the module B 12. The DMAC 30 of the module B 12 includes a buffer management unit 32, a read counter unit 34, a CMD management unit 36, and a DATA management unit 38.

[0077] The buffer management unit 32 includes a start buffer designation unit and a band management unit, and generates a start address to be used by the CMD management unit 36 ​​according to the current number of bands and number of lines.

[0078] The read counter unit 34, like the write counter unit 24, sets a count value by counting up in response to a write completion notification (output of a write completion signal) and counting down in response to a read completion notification (input of a read completion signal). The initial value of the read counter unit 34 is 0, and it counts up by 1 when it receives a write completion notification and counts down by 1 when it receives a read completion notification.

[0079] The CMD management unit 36 ​​calculates an address, a burst, etc. from the specified top address and a predetermined image width, and issues a read command. The CMD management unit 36 ​​outputs a read completion notification (read completion signal) to the DMAC of the module A10 every time it reads one line of print data from the buffer memory 18. The CMD management unit 36 ​​controls the read operation from the buffer memory 18 based on the count value of the read counter unit 34. Specifically, as described below, when the count value of the read counter unit 34 is a value other than 0 (for example, 1), it reads print data from the buffer memory 18, and when the count value of the read counter unit 34 becomes 0, it stops reading from the buffer memory 18 and goes into a standby state.

[0080] The data management unit 38 outputs to the module B the print data that has undergone the A process and that has been read out from the buffer memory 18 in response to a read command.

[0081] FIG. 12 shows a processing flowchart of the write counter unit 24 of the DMAC 20 of the module A10 and the read counter unit 34 of the DMAC 30 of the module B12.

[0082] The write counter unit 24 determines whether or not there is a notification of completion of writing (S101). When the processing of one line of print data is completed, the module A10 notifies the module B12 and the write counter unit 24 of the completion of writing, and if there is a notification of the completion of writing (YES in S101), the count value is incremented (S102). Therefore, the count value of the write counter unit 24 is the initial value of 0 until the processing of the first line of the first band is completed, and when the processing of the first line is completed and output to the buffer memory 18, the count value of the write counter unit 24 becomes 1, and if there is a further notification of the completion of writing, the count value of the write counter unit 24 becomes 2.

[0083] Furthermore, if there is no write completion notification (NO in S101), the write counter unit 24 next judges whether there is a read completion notification (S103). When the module B12 completes reading one line of print data from the buffer memory 18, it notifies the completion of reading, and if there is a read completion notification (YES in S103), the count value is counted down (S104). Therefore, when the count value is 2 and reading of the first line is completed, the count value of the write counter unit 24 becomes 1 from 2.

[0084] The process of the read counter unit 34 is similar, and the read counter unit 34 judges whether or not there is a notice of completion of writing (S101). When the processing of one line of print data is completed, the module A10 notifies the module B12 and the write counter unit 24 of the completion of writing, and if there is a notice of the completion of writing (YES in S101), the count value is counted up (S102). Therefore, the count value of the read counter unit 34 is the initial value of 0 until the processing of the first line of the first band is completed, and when the processing of the first line is completed and output to the buffer memory 18, the count value of the read counter unit 34 becomes 1, and if there is a notice of the completion of writing, the count value of the read counter unit 34 becomes 2.

[0085] Furthermore, if there is no write completion notification (NO in S101), the read counter unit 34 next judges whether there is a read completion notification (S103). When the module B12 completes reading one line of print data from the buffer memory 18, it notifies the completion of reading, and if there is a read completion notification (YES in S103), the count value is counted down (S104). Therefore, when the count value is 2 and reading of the first line is completed, the count value of the read counter unit 34 becomes 1 from 2.

[0086] FIG. 13 shows a flowchart of the overall process of the DMAC 20 of the module A10.

[0087] First, the buffer management unit 22 of the DMAC 20 of the module A10 determines a start address according to the current band information and data position information in the buffer memory (S201).

[0088] Next, the CMD management unit 26 and the DATA management unit 28 compare the count value of the write counter unit 24 with the number of lines in the buffer memory 18 (S202), and if the count value of the write counter unit 24 has not reached the number of lines in the buffer memory 18 (YES in S202), output the A-processed print data to the designated output buffer, i.e., the buffer memory 18 (S203). If the count value of the write counter unit 24 has reached the number of lines in the buffer memory 18 (NO in S202), the process goes to a standby state without outputting the data to the buffer memory 18. Then, it is determined whether or not one line of A-processed print data has been output (S204), and the process is repeated until one line of A-processed print data has been output to the buffer memory 18 (NO in S204).

[0089] When the output of the A-processed print data for one line to the buffer memory 18 is completed (YES in S204), the CMD management unit 26 notifies the subsequent stage, that is, the module B12 and the write counter unit 24, of the completion of the write (S205). The write counter unit 24 counts up the count value by one by receiving the write completion notification from the CMD management unit 26 (see FIG. 12). Therefore, when the A-processed print data for the first line of the first band is output to the buffer memory 18, the count value of the write counter unit 24 counts up from 0 to 1, and when the A-processed print data for the second line is further output to the buffer memory 18, the count value of the write counter unit 24 counts up from 1 to 2. Also, when the DMAC 30 of the module B12 reads out the A-processed print data for one line from the buffer memory 18, the completion of the read is notified, so when the write counter unit 24 receives this read completion notification, it counts down the count value by one by one. Therefore, when the count value reaches 2, if a read completion notification is received, the count value will count down from 2 to 1.

[0090] The above process is repeatedly performed for the A-processed print data of all lines of the band (NO in S206), and when processing of all lines of the band is completed (YES in S206), the buffer management unit 22 retains the amount of data in the buffer memory 18 (S207).

[0091] FIG. 14 shows a flowchart of the overall process of the DMAC 30 of the module B12.

[0092] First, the buffer management unit 32 of the DMAC 30 of the module B 12 determines a start address according to the current band information and data position information in the buffer memory (S301).

[0093] Next, it is determined whether the count value of the read counter unit 34 for the relevant color, i.e., the target color to be processed, is greater than 0 (S302). The count value of the read counter unit 34 is incremented by one when a write completion notice is received, and decremented by one when a read completion notice is received (see FIG. 12). Therefore, if the count value is greater than 0, it means that the A-processed print data has been written to the buffer memory 18 and has not yet been read out. Therefore, when the count value is greater than 0 (YES in S302), the A-processed print data is read out from the designated input buffer, i.e., the buffer memory 18 (S303). Then, it is determined whether one line's worth of print data has been read out (S304), and this is repeated until one line's worth of print data has been read out (NO in S304).

[0094] When one line of print data is read and input (YES in S304), the CMD management unit 36 ​​notifies the previous stage, that is, the module A10 and the read counter unit 34, of the completion of reading (S305).

[0095] After the above process is performed for the relevant color, the target color is switched and the same process is repeated (S308), then the process is repeated for the number of input colors (S306), and further repeated for the print data for all lines of the band (S307).

[0096] In addition, when module B12 processes the four colors of CMYK in parallel simultaneously as shown in Figure 4, the relevant color is not a specific color but the four colors of CMYK simultaneously, so S306 always returns YES, and the target color switching process in S308 is not executed.

[0097] More detailed timing charts are shown in Figures 15 and 16. It is assumed that the first to third bands are processed, and each band is made up of the first to third lines.

[0098] Fig. 15 shows the processing timing of the first and second bands. Fig. 15(a) shows the output line of module A10, Fig. 15(b) shows the count value of the write counter unit 24 of the DMAC 20 of module A10, Fig. 15(c) shows the color processing timing of module A10, and Fig. 15(d) shows the color processing timing of module B12.

[0099] When processing of the first band is started, module A10 reads the print data of the first line of the first band from DDR16, processes the four colors of CMYK simultaneously, and outputs the A-processed print data of the first line of the four colors of CMYK to buffer memory 18. At this time, the count value of write counter unit 24 is the initial value of 0.

[0100] When module A10 completes processing of the first line of print data and completes output of the first line of print data to buffer memory 18, write counter unit 24 is notified of the completion of writing, and so the count value of write counter unit 24 counts up from 0 to 1. Also, read counter unit 34 of DMAC 30 in module B12 is notified of the completion of writing, and so the count value of read counter unit 34 counts up from the initial value of 0 to 1.

[0101] Next, the module A 10 reads the print data for the second line of the first band from the DDR 16, processes the four colors, CMYK, simultaneously, and outputs the A-processed print data for the second line of the four colors, CMYK, to the buffer memory 18. At this time, the count value of the write counter unit 24 remains at 1.

[0102] On the other hand, in module B, as the output of the first line of print data to the buffer memory 18 is completed, the count value of the read counter unit 34 is incremented from 0 to 1, and module B starts reading the A-processed print data of the first line from the buffer memory 18, and processes the four colors, CMYK, simultaneously.

[0103] When processing of the print data of the second line of the first band is completed in module A10 and output of the print data of the second line to buffer memory 18 is completed, the write counter unit 24 is notified of the completion of writing, and the count values ​​of the write counter unit 24 and the read counter unit 34 count up from 1 to 2.

[0104] Then, when module B12 has completed reading all of the A-processed print data of the first line of the first band, the completion of reading is notified to the read counter unit 34 and the write counter unit 24, so that the count values ​​of the write counter unit 24 and the read counter unit 34 count down from 2 to 1. Note that while the count value of the write counter unit 24 is 2, module A10 does not read the next line of print data from DDR16 and enters a standby state.

[0105] When module B12 has completed reading the A-processed print data of the first line and the count value of the write counter unit 24 reaches 1, module A10 reads the print data of the third line of the first band from DDR16 and processes the four colors, CMYK, simultaneously, and outputs the A-processed print data of the third line of the four colors, CMYK, to the buffer memory 18.

[0106] In response to the count value of the read counter section 34 being 1, the module B 12 starts reading out the A-processed print data of the second line of the first band from the buffer memory 18, and processes the four colors, CMYK, simultaneously.

[0107] When processing of the print data of the third line of the first band is completed in module A10 and output of the print data of the third line to buffer memory 18 is completed, the write counter unit 24 and the read counter unit 34 are notified of the completion of writing, so that the count values ​​of the write counter unit 24 and the read counter unit 34 again count up from 1 to 2.

[0108] In addition, when module B12 has completed reading all of the A-processed print data of the second line, the completion of reading is notified to the read counter unit 34 and the write counter unit 24, and the count values ​​of the write counter unit 24 and the read counter unit 34 count down from 2 to 1.

[0109] At this point in time, module A10 has completed simultaneous processing of the four colors CMYK for the first line to the third line of the first band, and output to buffer memory 18 has been completed; however, the A-processed print data for the third line of the first band remains in buffer memory 18, and the count values ​​of write counter unit 24 and read counter unit 34 remain at 1.

[0110] Even though one line of A-processed print data that has not yet been read by module B12 remains in buffer memory 18, module A10 proceeds to processing of the next second band, reads the print data of the first line of the second band from DDR16, and processes the four colors, CMYK, simultaneously.

[0111] On the other hand, module B12 starts reading out the A-processed print data of the third line of the first band from the buffer memory 18 in response to the count value of the read counter unit 34 being 1, and processes the four colors CMYK simultaneously. Thereafter, the same process is repeated. FIG. 16 shows the processing timing for the last band, the third band.

[0112] Similar to the first and second bands, the print data for the first to third lines are processed in sequence in module A10 and module B12.

[0113] Module A10 reads the print data for the third line from DDR 16 and processes the four colors, CMYK, simultaneously. When output to buffer memory 18 is complete, write completion is notified to write counter unit 24 and read counter unit 34, and the count values ​​of write counter unit 24 and read counter unit 34 count up from 1 to 2.

[0114] Module B12 reads out the A-processed print data of the second line of the third band from the buffer memory 18 and processes the four colors, CMYK, simultaneously. Then, when all the A-processed print data of the second line of the third band has been read out, it notifies the read counter unit 34 and the write counter unit 24 of the completion of reading, so that the count values ​​of the write counter unit 24 and the read counter unit 34 count down from 2 to 1.

[0115] After this, module A10 goes into a standby state because all processing of the print data of the first to third lines of the third band has been completed, but since the count value of the read counter unit 34 of module B12 is still 1 even after all processing of the second line of the third band has been completed, module B12 reads the A-processed print data of the third line from the buffer memory 18 in response to this and processes the four colors of CMYK simultaneously. Then, when all the A-processed print data of the third line has been read, the read counter unit 34 and the write counter unit 24 are notified of the completion of reading, so the count values ​​of the write counter unit 24 and the read counter unit 34 count down from 1 to 0 and all processing ends.

[0116] Please note that, as shown in FIG. 16(d), in module B12, after reading out all of the A-processed print data of the second line, it subsequently reads out and processes the A-processed print data of the third line remaining in the buffer memory 18.

[0117] 15 and 16 show an example in which the four colors CMYK are processed simultaneously in module A10 and module B12. However, the same can be said for a case in which module B12 is composed of modules B-0 and B-1 as shown in FIG. 6, in which module B-0 processes C and M alternately as single colors, and module B-1 processes Y and K alternately as single colors, and a write counter unit 24 and a read counter unit 34 are provided for each color and the count values ​​are increased or decreased. [Explanation of symbols]

[0118] 1 image forming apparatus, 10 module A, 12 module B, 14 bus, 16 DDR, 18 buffer memory, 20 DMAC (module A), 24 write counter unit, 30 DMAC (module B), 34 read counter unit.

Claims

1. a first processor and a second processor for reading and executing a program; A storage means; the first processor processes a plurality of color signals at a time and outputs them in parallel; the storage means temporarily stores a plurality of color signals output from the first processor; the second processor reads out and processes a plurality of color signals from the storage means in sequence, the number of color signals being able to be processed at one time; the first processor and the second processor process the plurality of color signals in band units each consisting of an image width×N lines (N is an integer of 2 or more) and start processing the next second band after the processing of the first band is completed, the first processor starts processing the second band at a timing before the processing of the first band is completed by the second processor and the color signals of the first band remain in the storage means, and the second processor starts processing the second band before reading out the color signals of the last line of the first band from the storage means. Signal processing device.

2. the first processor writes one line of color signals constituting the first band into the storage means, and then notifies the second processor of completion of the writing; the second processor, after receiving the completion of the writing, reads out the color signal processed by the first processor from the storage means and notifies the first processor of the completion of the reading; The signal processing device according to claim 1 .

3. the first processor notifies the second processor of completion of writing after writing the color signals of the last line constituting the first band into the storage means; the second processor, after receiving the completion of the writing from the first processor, reads out color signals for a line previous to the last line from the storage means and notifies the first processor of the completion of the reading; the first processor processes the color signals of the first line constituting the second band after receiving the completion of the reading from the second processor, and writes the color signals of the first line into the storage means without overwriting the color signals of the last line; The signal processing device according to claim 2 .

4. the second processor writes the color signals of the first line constituting the second band into the storage means without overwriting the color signals of the last line by the first processor, and reads the color signals of the last line from the storage means after receiving a notification of the completion of the writing. The signal processing device according to claim 3 .

5. the first processor notifies the second processor of completion of writing after writing the color signals of the last line of the last band constituting a page into the storage means; the second processor reads color signals of the line before the last line of the last band from the storage means after receiving the completion of the writing from the first processor, and further reads color signals of the last line of the last band from the storage means and notifies the first processor of the completion of the reading. The signal processing device according to any one of claims 1 to 4.

6. a plurality of the second processors are provided, each of the second processors reading out a different one of the plurality of color signals from the storage means and processing the different one; The signal processing device according to any one of claims 1 to 5.

7. The processor, a first processing means for processing a plurality of color signals at once and outputting the processed signals in parallel; a second processing means for reading out and processing the plurality of color signals in sequence, the number of which can be processed at one time, from a storage device that temporarily stores the plurality of color signals output from the first processing means; Function as a The first processing means and the second processing means process the multiple color signals in bands consisting of an image width x N lines (N is an integer greater than or equal to 2), and start processing the next second band after processing of the first band is completed, and the first processing means starts processing of the second band at a timing before processing of the first band is completed by the second processing means and while the color signals of the first band remain in the storage device, and the program causes the second processing means to function to start processing of the second band before reading out the color signals of the last line of the first band from the storage device.

Images