Ultra-Low Clamping Voltage Surge Protection Module Using Depletion-Mode MOSFETs

Abstract

To provide an ultra-low clamping voltage Surge Protection Module (SPM) that uses a depletion mode MOSFET (D MOSFET).SOLUTION: A SPM 200A may be part of a circuit or a device and includes a primary protection stage provided by a gas discharge tube (GDT) 210 and a secondary protection stage provided by a TVS diode 220. D MOSFETs 224 and 226 are connected between the primary protection stage and the secondary protection stage. The SPM includes a single D MOSFET, dual D MOSFETs, or a plurality of D MOSFETs. The primary and secondary protection stages are implemented with a number of different components.EFFECT: The SPM using D MOSFET(s) exhibits improved surge protection over circuits using inductors.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate to surge protection for circuits, and more particularly, to techniques for surge protection using depletion mode MOSFETs. [Background technology]

[0002] Surge protection modules (SPMs), which are made up of protection components with different topologies, are considered as an effective means to clamp and divert external transient surges entering the system to be protected. SPMs can also be built with multi-stage protection devices against electrical surges or transient voltage events. SPMs may have primary, secondary and even tertiary protection components. These protection modules employ either overcurrent protection components such as fuses and positive temperature coefficient devices (PTCs) or overvoltage protection components such as gas discharge tubes (GDTs) and metal oxide varistors (MOVs). Inductors or common mode chokes are typically placed between the primary and secondary protection components of SPMs.

[0003] Electronic systems or devices are particularly susceptible to surge events such as lightning surges, induced surges from other power lines and systems, switching on and off inductive loads, crossing of power lines, etc. It is difficult to design a protection module that will allow normal operating power or signals while suppressing or diverting undesirable overvoltage spikes or currents.

[0004] It is with respect to these and other considerations that the present improvements may be useful. Summary of the Invention

[0005] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended as an aid in determining the scope of the claimed subject matter.

[0006] An exemplary embodiment of a circuit for providing overcurrent protection is disclosed. The circuit is comprised of a primary protection device, a secondary protection device, and a depletion-mode metal-oxide-semiconductor field-effect transistor (D MOSFET). The primary protection device diverts a first portion of an external transient surge entering the circuit to ground. The secondary protection device diverts a second portion of an external transient surge entering the circuit to ground. The D MOSFET absorbs surge energy between the primary protection device and the secondary protection device.

[0007] An exemplary embodiment of a device connected to a circuit is disclosed. The device provides overcurrent protection to a circuit element in the circuit and is comprised of a primary protection device, a secondary protection device, and a D MOSFET. The primary protection device diverts to ground a first portion of an external transient surge that enters the circuit. The secondary protection device diverts to ground a second portion of the external transient surge that enters the circuit. The D MOSFET blocks a residual surge of the external transient surge that is not completely suppressed by the primary protection device. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1 is a representative diagram of an SPM circuit according to the prior art. [Figure 1B] FIG. 1 is a representative diagram of an SPM circuit according to the prior art.

[0009] [Figure 2A] FIG. 1 is a representation of a novel SPM circuit according to an example embodiment. [Figure 2B] FIG. 1 is a representation of a novel SPM circuit according to an example embodiment.

[0010] [Diagram 3] FIG. 1 is a representation of a novel SPM circuit according to an example embodiment.

[0011] [Figure 4] FIG. 1 is a representation of a novel SPM circuit according to an example embodiment.

[0012] [Diagram 5] FIG. 2C illustrates response waveforms for a test performed on the circuit of FIG. 2B according to an exemplary embodiment. [Figure 6] FIG. 2C illustrates response waveforms for a test performed on the circuit of FIG. 2B according to an exemplary embodiment. [Figure 7] FIG. 2C illustrates response waveforms for a test performed on the circuit of FIG. 2B according to an exemplary embodiment. [Figure 8] FIG. 2C illustrates response waveforms for a test performed on the circuit of FIG. 2B according to an exemplary embodiment.

[0013] [Figure 9] FIG. 1 is a representation of a novel device used for surge protection of a circuit according to an exemplary embodiment.

[0014] [Figure 10] 2C is an image of test results performed on the circuit of FIG. 2B according to an example embodiment.

[0015] [Figure 11] FIG. 1 is a representative diagram of a circuit for testing the surge tolerance of a single D MOSFET according to an exemplary embodiment.

[0016] [Figure 12A] 4 is a waveform illustrating the response of a forward-biased D MOSFET to surge energy and saturation current in the safe operating area in accordance with an example embodiment. [Figure 12B] 4 is a waveform illustrating the response of a forward-biased D MOSFET to surge energy and saturation current in the safe operating area in accordance with an example embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] According to embodiments described herein, an ultra-low clamp voltage surge protection module (SPM) utilizing one or more depletion mode MOSFETs (D MOSFETs) is disclosed. The SPM may be part of a circuit or device and includes a primary protection stage and a secondary protection stage, with the D MOSFET connected between the two stages. The SPM may include a single D MOSFET, dual D MOSFETs, or multiple D MOSFETs, and the primary and secondary protection stages may be implemented with a number of different components. The SPM using D MOSFETs has shown improved surge protection performance over circuits using inductors.

[0018] A Metal Oxide Semiconductor Field Effect Transistor device, known as a MOSFET, is a semiconductor device used to switch and amplify electronic signals in electronic devices. Adjusting the voltage on its gate changes the width of the channel located between the source and drain of the MOSFET. MOSFETs come in various configurations depending on whether they are P-channel devices built on an N-type substrate, N-channel devices built on a P-type substrate, vertically arranged semiconductors, horizontally arranged semiconductors, depletion mode, or enhancement mode.

[0019] Unlike enhancement-mode MOSFETs, which are activated by applying a voltage across the gate, depletion-mode MOSFETs are activated when the gate terminal is at 0 volts (V GS = 0V), they are known as "normally-on" devices. In addition to having a thin gate oxide between the source and drain regions, a conductive channel is formed under the gate oxide and between the source and drain regions by ion implantation. The concentration of active dopants in the substrate-channel region is used to determine the threshold voltage (V Th ) to the desired value. Despite their name, many modern MOSFETs can be fabricated with a polysilicon gate rather than a metal gate on an insulating gate oxide.

[0020] A varistor is an electronic component whose electrical resistance changes with an applied voltage. Varistors are used as control or compensation devices in circuits to provide optimal operating conditions or to protect against excessive voltage transients. When used as a protection device, a varistor, when triggered, shunts current caused by excessive voltage away from sensitive components. Metal oxide varistors (MOVs) are a type of varistor that uses a sintered body of ceramic metal oxide material.

[0021] Transient voltage suppression (TVS) diodes are electronic components used to protect electronic devices from voltage spikes that occur on connected electrical lines. TVS diodes operate by shunting excess current when an induced voltage exceeds the avalanche breakdown potential. TVS diodes are clamping devices that suppress all overvoltages above their breakdown voltage. TVS diodes automatically reset when the overvoltage condition is removed, but they internally absorb much more transient energy than comparable crowbar devices.

[0022] Gas discharge tubes (GDTs) are overvoltage protection devices that dissipate voltage transients with plasma gas. Characteristically, one of the GDT configurations is a ceramic tube sandwiched between metal electrodes and sealed with a rare gas. GDTs are used to divert overvoltages to lower, safer levels when an external surge exceeds the sparkover voltage (operating voltage). GDTs have high insulation resistance and low capacitance and leakage to ensure minimal impact on the normal operation of the device. GDTs are designed to dissipate large amounts of energy, such as lightning surge protection, as they provide high voltage transient surge protection for small devices, and are widely applied in outdoor communication devices as an example. Generally, the trigger / turn-on speed of GDT devices is much slower compared to semiconductor-based protection devices such as TVS diodes.

[0023] As mentioned above, a circuit called a surge protection module (SPM) is composed of protection components of different topologies and is designed to clamp and divert external transient surges entering the system (components downstream of the SPM circuit). SPMs achieve "protection coordination" by using different stages of protection, e.g., primary, secondary, and tertiary protection. Protection coordination describes the "matching" of different stages of protection components (including both overvoltage and overcurrent) to form a functional protection module.

[0024] 1A and 1B are representative diagrams of prior art surge protection module (SPM) circuits 100A and 100B, respectively. SPM circuit 100A (FIG. 1A) features a metal oxide varistor (MOV) 102, an inductor 104, and a transient voltage suppression (TVS) diode 106, such that SPM circuit 100A represents a MOV plus TVS combination. The MOV varistor provides high energy withstand capability, while the TVS diode exhibits a low clamping voltage.

[0025] SPM circuit 100B (FIG. 1B) features an MOV 112, two chokes 114, 116, a capacitor 118, and a TVS diode 120, so that SPM circuit 100B represents a MOV, plus choke, plus TVS combination. SPM circuit 100B receives 24VDC, and the MOV varistor 112 in this embodiment is a V33ZA70PX manufactured by Littelfuse®, a special low voltage 20mm diameter MOV (3KA@8 / 20μsec(1 time)), while TVS diode 120 may be any one of the SMBJ or SMCJ series TVS diodes, such as the SMBJ28A, SMBJ30A, SMCJ28A, or SMCJ30A, also manufactured by Littelfuse®.

[0026] Circuits 100A and 100B represent two different conventional designs of surge protection modules. Inductors and common mode chokes are often used between the primary protection device (MOV or Gas Discharge Tube (GDT)) and the secondary protection device (TVS diode). Circuit 100A places an inductor 104 between the MOV 102 (primary protection) and the TVS diode 106 (secondary protection). Circuit 100B places chokes 114, 116 between the MOV 112 (primary protection) and the TVS diode 120 (secondary protection). Thus, these circuits 100A and 100B are used as "low pass filters" by filtering all high speed or switching frequency spikes but allowing DC or low frequency AC to pass through the respective circuits.

[0027] As shown in the conventional SPM circuit 100A (FIG. 1A), following the primary protection device MOV 102 (which may alternatively be a GDT), the inductor 104 is large enough to help block any residual surges that were not fully suppressed by the primary protection device. However, including such a large inductor in the circuit 100A may result in other side effects, such as energy loss and high voltage spikes during fast transient events. Furthermore, the presence of such a large inductor results in larger let-through voltages and currents reaching the secondary protection devices (e.g., TVS diode 106 in circuit 100A), requiring higher power TVS diodes to clamp the large let-through voltages. Furthermore, inductors are frequency-dependent components that may perform well in one particular frequency band but not perform as well in other signal frequency ranges. Such situations may exist especially when the circuit 100A is faced with unexpected external surge conditions, where it is difficult to predict the frequency and response time (or ramp-up time vs. decay time) of the surge waveform.

[0028] [Two-way design]

[0029] 2A and 2B are representative diagrams of novel SPM circuits 200A and 200B, respectively, according to an exemplary embodiment. The SPM circuit 200A includes an input gas discharge tube (GDT) 210 with four capacitors 212, 214, 216, 218, followed by two D MOSFETs 224, 226, and one TVS diode 220. In one embodiment, the GDT 210 is a GDT DC60 device manufactured by Littelfuse®. The numbers indicate the pin-out assignments of the GDT DC60 components. Optionally, the TVS diode 220 is combined with a second TVS diode 222, as shown in the circuit 200B (FIG. 2B). Hereinafter, the notation "SPM circuit 200" may refer to either the circuit 200A with one TVS diode 220 or the circuit 200B with two TVS diodes 220, 222. Thanks to the strong current limiting / blocking characteristics of the D MOSFETs 224 and 226, the SPM circuit 200 thus provides an overall ultra-low clamping voltage that cannot be achieved by conventional methods on the market in some embodiments, such as the above SPM circuits 100A and 100B, which employ conventional methods such as MOV or GDT devices as the first protection device in the circuit, followed by an inductor, and then a second stage protection device. Clamping voltage is a performance indicator that indicates the ability of a surge protection device to attenuate a surge (reduce the surge to a manageable level). The clamping voltage of a surge protection device that limits a 6000V surge so that only 600V is seen by the load is 600V.

[0030] The D MOSFET is a normally-on switch. In a source-follower configuration in which the gate and source terminals of the D MOSFET are connected (short-circuited), the D MOSFET operates as a current limiter with a saturation mode. The gate-source voltage V GS When goes negative with respect to the gate, the D MOSFET begins to pinch off, blocking the voltage and current passing through the D MOSFET switch. In an exemplary embodiment, as disclosed herein, these properties of the D MOSFET make it suitable for providing surge protection.

[0031] In an exemplary embodiment, the D MOSFETs 224 and 226 in the circuit 200 cooperate with the primary protection GDT 210 and the secondary protection TVS diodes 220 and 222 (or a single secondary protection TVS diode 220) to form a functional surge protection module. In one embodiment, the depletion mode MOSFETs 224 and 226 overcome the above-mentioned deficiencies of the inductor 104 of FIG. 1A. In an exemplary embodiment, the circuit 200 provides bidirectional protection using two 1000V D MOSFETs 224 and 226 configured as shown in FIG. 2A and FIG. 2B.

[0032] [Anti-serial bidirectional design]

[0033] FIG. 3 is a representative diagram of a novel SPM circuit 300 for providing bidirectional protection according to an example embodiment. The SPM circuit 300 features an input-side GDT 310 with four capacitors 312, 314, 316, 318, and one TVS diode 320 (optionally, the circuit may include two TVS diodes; this time, the circuit 300 features four D MOSFETs 324, 326, 328, 330 instead of two. The four D MOSFETs 324, 326, 328, 330 configuration is referred to as an "anti-series" connection because current can pass in both directions, providing bidirectional protection. When current flows from the left side of the circuit 300, the first D MOSFET 324 is forward biased in saturation mode, while the second D MOSFET 326 is reverse biased. However, the body diode inside the second D MOSFET 326 is now forward biased and acts as a conductive path. The same principle applies when current flows from the reverse direction. In the exemplary embodiment, four D MOSFETs 324, 326, 328, 330 are connected in series. MOSFETs 324, 326, 328, and 330 are 500V MOSFETs.

[0034] [One-way design]

[0035] FIG. 4 is a representative diagram of a novel SPM circuit 400 for providing unidirectional protection according to an exemplary embodiment. The circuit 400 features a GDT 410 with four capacitors 412, 414, 416, 418, a D MOSFET 424, a diode 426, and a TVS diode 428. In contrast to circuits 200 and 300, the circuit 400 features fewer components with similar functionality and is suitable for unidirectional surge protection in some embodiments. The SPM circuit 400 may provide protection for, for example, DC lines, single signal transmissions, etc. In such circumstances, the simpler design of the SPM circuit 400 may be preferred over the more complex design of the SPM circuits 200 or 300.

[0036] Thus, the various D MOSFET configurations presented herein disclose an innovative way to dramatically suppress the let-through transient voltage to a much lower level before the voltage reaches the secondary protection portion of each circuit 200, 300, 400. The circuit 200b (including both TVS diodes 224 and 226) of the bidirectional MOSFET design (FIG. 2B) was subjected to various tests to demonstrate the superior clamping performance of the surge protection module in the exemplary embodiment. Tests performed with the anti-series bidirectional circuit 300 and the unidirectional circuit 400 yield similarly encouraging results in some embodiments.

[0037] Returning to FIG. 2B, to test circuit 200, the function of this module is to provide protection for a -48V telecom / server power supply. GDT 210 is a GDT GD60: 60V Sparkover voltage device manufactured by Littelfuse®. D MOSFETs 224, 226 are IXTH16N100D2 (1000V, 10A, 1.3Ω). TVS diodes 224, 226 are "20KPA60CA" also manufactured by Littelfuse® with a standoff voltage of 60V and a power rating of 20kW. Two arrows 230, 232 are shown in circuit 200B (FIG. 2B). Arrow 230 indicates that the primary protection provided by the GDT clamps a portion of the surge current and allows the current to pass to ground. Arrow 232 indicates the clamping of additional surge current with the secondary protection provided by TVS diodes 220, 222, and MOSFETs 224, 226 help absorb some of the surge energy that was not completely suppressed by the primary protection devices, with the residual surge energy going to the TVS diodes 220, 222 for further clamping.

[0038] The test results presented below were conducted in the area of ​​telecom / server power protection, however, these results are not intended to be limiting as the SPM circuit 200B may have a variety of different applications for providing surge protection.

[0039] In an exemplary embodiment, the SPM circuit 200B of FIG. 2B was subjected to the following surge conditions. 1. Surge test: 20kA 8 / 20 Waveform D MOSFET 500V 2.Surge test: 4kA 10 / 350 Waveform D MOSFET 500V 3.D MOSFET 1000V 20kA 8 / 20 Waveform Surge Test 4.D MOSFET 1000V 4kA 10 / 350 Waveform Surge Test 5. Continuous current, 48V, 3A test on 500VD MOSFET

[0040] Furthermore, this surge current / voltage waveform was measured 1) across the GDT210 (DC60) and 2) across the TVS220, 222 (20KPA60CA), and captured in the following multiple response waveforms (Figures 5 to 8).

[0041] The circuit 200B of FIG. 2B provides an exemplary embodiment of the surge protection ideas disclosed herein. These tests can also be applied to anti-series bidirectional circuit 300 (FIG. 3) and unidirectional circuit 400 (FIG. 4). For example, the circuit 300 can use a GDT DC60 as the primary protection device and four IXTH16N50D2 D MOSFETs (500V) connected in anti-series for current interruption in bidirectional mode. The two sets of D MOSFETs 324, 326, 328, 330 are described herein as "anti-series" because the first two D MOSFETs 324, 326 are in a forward biased position while the other two D MOSFETs 328, 330 are in a reverse biased position. In this specification, the D MOSFETs in a reverse biased position means that the integrated body diodes conduct current in a forward direction.

[0042] 5 is a response waveform 500 showing surge test results for Test 1 (20kA 8 / 20 surge test) on circuit 200B (FIG. 2B) according to an example embodiment. The numbers to the left of the waveform 500 indicate the channel (channels 1, 2, 3, 4) of the resulting waveform that was generated. Channel 1 shows the surge current through the DC60 GDT 210. Channel 2 shows the surge current through the 20KPA60CA TVS diode 220 with Vc=78V. Channel 3 shows the surge current through the 20KPA60CA (<30A) TVS diode 222. Channel 4 shows the voltage (200V) through the GDT 210.

[0043] Channel 1 shows a very stressful and fast surge waveform. The GDT 210 responds by removing a portion of the surge energy, and the remaining let-through energy (see channel 4) is further absorbed by the D MOSFETs 224 and 226. The first MOSFET 224 acts as a surge current sink, while the second MOSFET 226 passes the current through its body diode as previously described. By placing the two MOSFETs in an anti-series configuration, the circuit 200B can provide bidirectional surge protection. The resulting energy level is precisely clamped to 78V by the TVS diodes 220 and 222 (channel 2). The final clamp voltage is 78V, which is a very low level in some embodiments considering the surge current. The surge current level passing through the TVS diodes 220, 222 is relatively low (<30A, channel 3). In one embodiment, this first surge test shows excellent clamping characteristics, even with the inrush surge current reaching up to 20kA in this example. In the exemplary embodiment, the clamp voltage remained at the same level no matter how high the inrush surge level was.

[0044] 6 is a response waveform 600 showing surge test results for Test 2 (4kA 10 / 350 surge test) on circuit 200B (FIG. 2B) according to an exemplary embodiment. The numbers to the left of the waveform 600 indicate the channels (channels 1, 2, 3, 4) of the resulting waveforms that were generated. Channel 1 shows the surge current through the DC60 GDT 210. Channel 2 shows the surge current through the 5KPA60CA TVS diode 220 with Vc=78V. Channel 3 shows the surge current through the 5KPA60CA (<20A) TVS diode 222. Channel 4 shows the voltage (130V) through the GDT 210.

[0045] Compared with the 8 / 20 surge test (waveform 600), the 10 / 350 surge test is considered a longer and more energetic surge waveform. In other words, the 10 / 350 surge test is slower than the 8 / 20 surge test for testing and compliance of some modern communication equipment. As shown in waveform 600 of FIG. 6, the anti-series D MOSFETs 224 and 226 absorb the let-through energy of the GDT 210 (channel 4), and the surge energy is further clamped by the TVS diodes 220 and 222 (channel 2). In one embodiment, the resulting clamped voltage remains at 78V (channel 2).

[0046] 7 is a response waveform 700 showing surge test results for Test 3 (20kA 8 / 20 surge test) on circuit 200B (FIG. 2B) according to an example embodiment. The numbers to the left of the waveform 700 indicate the channel (channels 1, 2, 3, 4) of the resulting waveform that was generated. Channel 1 shows the surge current through the DC60 GDT 210. Channel 2 shows the surge current through the 5KPA60CA TVS diode 220, with Vc=98V. Channel 3 shows the surge current through the 5KPA60CA (<16A) TVS diode 222. Channel 4 shows the voltage (856V) across the GDT 210.

[0047] In Test 3, the D MOSFETs 224 and 226 are IXTT10N100D2 manufactured by Littelfuse®. Compared to Tests 1 and 2, the surge waveform in Test 3 (20kA 8 / 20) is considered to be a very stressful fast surge waveform in one embodiment. The GDT 210 responds to remove some of the surge energy (channel 4). The let-through energy is then further absorbed by the D MOSFETs 224, 226. In one embodiment, the final clamp voltage in Test 3 is 78V, which is also a very low level compared to using a conventional inductor. Tests 1 (FIG. 5), 2 (FIG. 6), and 3 (FIG. 7) all show that the D MOSFET provides a much better clamp voltage than a conventional inductor. If an inductor were used here, the resulting clamp voltage would be in the range of 140-200V or higher, even if a TVS diode was used. Also, the surge current increases, for example from 10kA to 20kA, so the clamp voltage also increases dramatically. In the exemplary embodiment, the excellent clamping characteristics of Test 3 are maintained even as the surge current increases up to 20 kA, and the clamping voltage of about 78 V is maintained no matter how high the inrush surge level.

[0048] 8 is a response waveform 800 showing surge test results for Test 4 (4kA 10 / 350 surge test) on circuit 200B (FIG. 2B) according to an exemplary embodiment. The numbers to the left of the waveform 900 indicate the channel (channels 1, 2, 3, 4) of the generated waveform. Channel 1 shows the surge current through the DC60 GDT 210. Channel 2 shows the surge current through the 5KPA60CA TVS diode 220 with Vc=76V. Channel 3 shows the surge current through the 5KPA60CA (<12A) TVS diode 222. Channel 4 shows the voltage (160V) across the GDT 210.

[0049] For Test 4, the 10 / 350 surge test is intended to be a longer, more energetic surge waveform (i.e., slower than the 8 / 20 waveforms of Tests 1 and 3 above), making it suitable for testing and compliance of some modern communication devices. As shown in waveform 800, the spike voltage appearing at the GDT 210 is 160V (Channel 4). The D MOSFETs 224 and 226 absorb the let-through energy through the GDT 210, and then the surge energy is further clamped by the TVS diodes 220 and 222 (Channel 2). As a result, in the exemplary embodiment, the clamping voltage is maintained at 76V (Channel 2).

[0050] In an exemplary embodiment, Test 3 (waveform 700) and Test 4 (waveform 800) show the results of using a 1000V D MOSFET instead of a 500V D MOSFET, which have very similar clamping voltages. However, in some fast surge environments, the GDT has limitations in its ability to respond quickly, resulting in very high spikes and high voltage surge waveforms, and the drain-source voltage V of the D MOSFET DS This may exceed the rating of the drain-source voltage V DS A D MOSFET having a TSSOP MOSFET can, in some embodiments, help solve such problems, providing better surge absorption and allowing circuit 200B to still provide a low clamping voltage after the TVS diode stage.

[0051] Circuits 200A, 200B, 300, 400 may be connected to other downstream circuit elements to protect those circuit elements. Additionally, each of circuits 200A, 200B, 300, and 400 may be implemented in exemplary embodiments as a standalone device commercially available for connection to and protection of those circuits. For example, FIG. 9 illustrates a device 900 implementing a unidirectional embodiment of circuit 400 (FIG. 4). In particular, device 900 includes a GDT 910 with four capacitors 912, 914, 916, and 918 representing a primary protection stage, a diode 926 and a TVS diode 928 representing a secondary protection stage, and a D MOSFET 924 sandwiched between them to further suppress surge voltages. In other embodiments, the GDT may be replaced with a MOV, a thyristor, or another TVS diode. In yet other embodiments, based on the application for which the device is to provide surge protection, the primary protection stage may be eliminated entirely, with no GDT or capacitors present. Device 900 may be connected to other circuits to provide the surge protection functionality described herein. The other circuits 200A, 200B, and 300 may also be implemented as devices in an exemplary embodiment.

[0052] FIG. 10 is an image 1000 showing information related to test 5 (48V, 3A continuous test) of the circuit 200B (FIG. 2B) according to an exemplary embodiment. In test 5, a continuous current of 3A was applied to the protection module circuit 200B, and the D MOSFETs 224, 226 showed a temperature rise of about 101° C. inside the case (package), as shown in image 1000. In this test, the D MOSFETs 224, 226 were not attached with a heat sink. Thus, under normal operating conditions, the protection module circuit 200B can pass normal operating current through the circuit without protection intervention. In an exemplary embodiment, this shows that the D MOSFETs 224 and 226 operating in saturation mode can provide a current sending function that is different from the surge absorption and blocking function during oversurge conditions.

[0053] [D MOSFET Safe Operating Area (SOA)]

[0054] In the protection circuit 200B, when the GDT 210 responds to an external surge current, it results in a surge voltage and current passing through the GDT. However, in general, the triggering speed of the GDT to an overvoltage event is slower than that of a semiconductor-type overvoltage protection device, such as a thyristor-type protection device, such as a TVS diode. This is despite the GDT having a relatively high energy handling capability. To have a regulated current interruption element to absorb more surge energy before going to the secondary protection device, in the exemplary embodiment, the D MOSFETs 224 and 226 have the capability to interrupt that level of surge energy following the GDT stage. The safe operating area means that the D MOSFETs 224, 226 can safely withstand the residual energy passing through the GDT without exceeding their safe operating area (SOA). In this case, the SOA of the MOSFET is determined by the minimum operating voltage V DS and current I DS Condition vs time scale. This is usually plotted when different surge waveforms are applied to the MOSFET. Table 1 below provides details of the SOA of the MOSFET.

[0055] FIG. 11 is a representative diagram of a circuit 1100 for testing the surge tolerance of a single D MOSFET, according to an exemplary embodiment. The circuit 1100 includes a D MOSFET 1102 and allows for evaluation of the safe operating area (SOA) for a particular waveform. Table 1 shows the results of a current surge for the circuit of FIG. 11, according to an exemplary embodiment. In this test, the D MOSFET 1102 is a Littelfuse IXTH10N100D2, and a gate-source short circuit (SOA) of the D MOSFET occurs. This is a surge test result in which a dedicated surge waveform and peak voltages (500V, 1000V) are directly applied to the D MOSFET, and it is confirmed that the D MOSFET can operate without chip failure under such input voltage and current conditions. For the D MOSFET in Table 1, the resulting detected voltage V DS(464V, 1000V) is the maximum V listed in the datasheet DS (IXTH10N100D2 is 1000V). In addition, in this surge test, the maximum current I sat It is also possible to verify the above.

[0056] [Table 1] Table 1 shows that the IXTH10N100D2 D MOSFET can safely pass a 1000V 1.2 / 50μsec surge test.

[0057] Table 2 shows the results of a current surge for the circuit of Fig. 11 according to an exemplary embodiment. In this test, the D MOSFET 1102 is a Littelfuse IXTH10N100D2, and a gate-source short circuit (SOA) of the D MOSFET occurs.

[0058] [Table 2] Table 2 shows that the IXTH10N100D2 D MOSFET can safely pass the 700V 10 / 1000μsec surge test.

[0059] Table 3 shows the current surge results for the circuit of Figure 11 according to an exemplary embodiment. In this test, the D MOSFET 1102 is a Littelfuse IXTH16N50D2, and the D MOSFET is shorted from gate to source.

[0060] [Table 3] Table 3 shows that the IXTH16N50D2 D MOSFET can safely pass a 500V 1.2 / 50μsec surge test with a maximum saturation current of 24A.

[0061] Table 4 shows the current surge results for the circuit of Figure 11 according to an exemplary embodiment. In this test, the D MOSFET 1102 is a Littelfuse IXTH16N50D2, and the D MOSFET is shorted from gate to source.

[0062] [Table 4] Table 4 shows that the IXTH16N50D2 D MOSFET can safely pass the 700V 10 / 1000μsec surge test with a maximum saturation value of 43.2A.

[0063] 12A and 12B are waveforms illustrating the response of a forward biased D MOSFET to surge energy and saturation current in the safe operating area of ​​circuit 400 (FIG. 4) or device 900 (FIG. 9) in accordance with an example embodiment. In the first waveform 1200A, the D MOSFET is an IXTH10N100D2 manufactured by Littelfuse®. In the second waveform 1200B, the D MOSFET is an IXTH16N50D2 also manufactured by Littelfuse®. Waveform 1200A shows the saturation current I of a forward biased 1000V D MOSFET to measure the safe operating area (SOA). sat and the drain-source voltage V DS Waveform 1200B shows a time plot of the saturation current, I, of a forward-biased 500V D MOSFET to measure the SOA. sat and the drain-source voltage V DS The waveforms 1200A and 1200B show the saturation current I sat The saturation state of the D MOSFET is in a steady state when the D MOSFET is exposed to surge energy and can respond to block the surge energy.

[0064] Based on the 1.2 / 50μs surge test, in the exemplary embodiment, a 1000V D MOSFET can safely pass a 1000V 21.6A surge test. Converting the current specification to rated power, the D MOSFET can withstand at least 1000V×21.6A=21.6kW with a current waveform of 8 / 20μs. (1.2 / 50 is a voltage waveform. Converting to a current waveform results in 8 / 20. Thus, the two notations are the same, but one represents a voltage waveform and the other represents a current waveform. Incidentally, at 10 / 1000, both the current waveform and the voltage waveform are 10 / 1000. These are standards for communication surges established by UL and IEC.) Therefore, in order to pass the above 20kA surge, the D MOSFET must be able to withstand a rated power of at least 1000V×21.6A=21.6kW with a current waveform of 8 / 20μs. sat = (200 - 98) x 16 = 1.63 kW, which is significantly lower than the 21.6 kW of the D MOSFET.

[0065] Similarly, based on the 1.2 / 50 μs surge test, in an exemplary embodiment, a 500V D MOSFET can safely pass a 500V 24A surge test. Converting the current specification to a power rating, the D MOSFET can withstand at least 500V x 24A = 12kW with a 8 / 20 μs current waveform. Therefore, in an exemplary embodiment, the D MOSFET can safely handle such energy levels. Similar calculations can be performed to estimate the SOA of a D MOSFET under different surge waveforms and conditions, since the energy handling capabilities of D MOSFETs tend to be similar per wafer area.

[0066] In some embodiments, the D MOSFET configurations shown and described herein provide a new way to absorb surge energy instead of traditional wire inductors. Because chokes are inductors with a magnetic core, they suffer from similar drawbacks as inductors. In exemplary embodiments, ultra-low clamping voltages are achieved by using the D MOSFET implementations described herein. Additionally, in some embodiments, a smaller rated secondary protection device, such as the illustrated TVS diode, can be used to provide a cost-effective solution by the D MOSFET blocking some of the surge energy before it reaches the secondary protection stage. In other words, in some embodiments, a higher rated TVS diode may be required in the secondary protection stage without the D MOSFET contributing to the suppression of the surge energy.

[0067] In an exemplary embodiment, fast ramp surges, from medium-speed surges of moderate energy to long-duration surges of high energy, can be absorbed more effectively by D MOSFETs than the prior art because the response time of D MOSFETs is much faster than other passive components such as inductors.

[0068] Also, the GDT used in the primary protection stage of the above circuit is just one example. The GDT can be replaced with various components such as, but not limited to, MOVs, TVS diodes, and thyristor protection devices. In some embodiments, depending on the application and surge protection level, it is also possible to use D MOSFETs for surge protection even without the primary protection stage (in some embodiments).

[0069] Thus, a new protection module circuit is disclosed that features one or more D MOSFETs as shown and described herein. Unlike the use of traditional inductors, the one or more D MOSFETs, in an exemplary embodiment, provide superior surge energy blocking and absorption capabilities as part of a coordinated protection circuit having multiple stages (primary and secondary). In contrast, inductors are bulky and provide a high impedance path for high frequency signals, resulting in power loss. The use of inductors may result in unwanted overshoots or an inability to accommodate fast transient events.

[0070] In contrast to the inductor model, one or more D MOSFETs, as illustrated in the various circuits herein, can handle a wide range of different ramp rates and magnitudes of surge energy levels within their safe operating area. Thus, D MOSFETs, in exemplary embodiments, are particularly well suited to absorb surge energy in modern electronic devices as electronic designs demand increasingly sophisticated protection schemes.

[0071] As used herein, elements or steps described in the singular and preceded by the words "a" or "an" are to be understood as not excluding a plurality of elements or steps, unless the plural exclusion is expressly stated. Moreover, references to "one embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments incorporating the same recited features.

[0072] Although the present disclosure refers to specific embodiments, numerous variations, substitutions, and modifications to the described embodiments are possible without departing from the scope of the present disclosure, as defined in the appended claims. Accordingly, it is intended that the present disclosure not be limited to the described embodiments, but rather have its full scope defined by the following claims and equivalents thereof.

Claims

1. 1. A circuit operable to provide overcurrent protection, comprising: a primary protection device for diverting to ground a first portion of an external transient surge entering the circuit; a secondary protection device that diverts a second portion of the external transient surge entering the circuit to the ground; a first depletion-mode metal-oxide-semiconductor field effect transistor (first D MOSFET), a second D MOSFET, a third D MOSFET, and a fourth D MOSFET connected in anti-series; Equipped with the first D MOSFET, the second D MOSFET, the third D MOSFET, and the fourth D MOSFET absorb residual surge energy between the primary protection device and the secondary protection device that is not completely suppressed or diverted by the primary protection device.

2. 2. The circuit of claim 1, wherein the primary protection device is a gas discharge tube (GDT).

3. 2. The circuit of claim 1, wherein the primary protection device is a metal oxide varistor (MOV).

4. 4. The circuit of claim 1, wherein the secondary protection device is a transient voltage suppression (TVS) diode.

5. 4. The circuit of claim 1, wherein the secondary protection device is two transient voltage suppression (TVS) diodes connected in parallel.

6. 6. The circuit of claim 1, wherein the first D MOSFET, the second D MOSFET, the third D MOSFET, and the fourth D MOSFET provide bidirectional protection.

7. 7. The circuit of claim 1, wherein the primary protection device is a first transient voltage suppression (TVS) diode and the secondary protection device is a second TVS diode.

8. a device coupled to a circuit, the device operable to provide overcurrent protection to the circuit; a primary protection device for diverting to ground a first portion of an external transient surge entering the circuit; a secondary protection device that diverts a second portion of the external transient surge entering the circuit to the ground; a first depletion-mode metal-oxide-semiconductor field effect transistor (first D MOSFET), a second D MOSFET, a third D MOSFET, and a fourth D MOSFET connected in anti-series; Equipped with the first D MOSFET, the second D MOSFET, the third D MOSFET, and the fourth D MOSFET block residual surge energy of the external transient surge that was not completely suppressed or bypassed by the primary protection device.

9. The device of claim 8 , wherein the primary protection device is a gas discharge tube (GDT).

10. The device of claim 8 , wherein the primary protection device is a metal oxide varistor (MOV).

11. 11. The device of claim 8, wherein the secondary protection device is a transient voltage suppression (TVS) diode.

12. 11. The device of claim 8, wherein the secondary protection device is two transient voltage suppression (TVS) diodes connected in parallel.

13. 13. The device of claim 8, wherein the first D MOSFET, the second D MOSFET, the third D MOSFET, and the fourth D MOSFET provide bidirectional protection.

14. 14. The device of claim 8, wherein the primary protection device is a first transient voltage suppression (TVS) diode and the secondary protection device is a second TVS diode.

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