Memory Controller

Abstract

To provide a memory controller configured to suppress reduction in access performance.SOLUTION: A memory controller 100 issues a command to a semiconductor memory device in response to an access request from arithmetic units 210, 220, 230 to the semiconductor memory device 300 having multiple ranks R0, R1, R2. The memory controller includes an access request holder 110, an access request selector 130, a command generator 120, a refresh interval counter 140 and refresh counters 150, 151, 152. The access request selector calculates total processing time for each of the ranks, selects multiple access requests, as an access request group, for an access target rank, and determines the order of processing the access requests in the selected access request group. The command generator issues an access command to the access target rank in order, and issues a refresh command to a refresh target rank.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a memory controller. [Background technology]

[0002] There is a memory system including a DRAM (Dynamic Random Access Memory) with multiple ranks as a semiconductor memory. Such a semiconductor memory device needs to be refreshed periodically to retain data. The memory controller described in Patent Document 1 refreshes the semiconductor memory at regular intervals and may postpone the execution of the refresh for each rank depending on the amount of access requests. In addition, if the execution of the refresh for that rank is postponed for a certain period of time, the refresh for that rank is forcibly executed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2020-517024 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the memory controller described in Patent Document 1, when access requests are concentrated in a particular rank, if a refresh is forcibly performed on the rank where the access requests are concentrated, access to that rank is not executed. In addition, although access is possible to other ranks, access is not executed because there is no access request. This causes a problem of reduced access efficiency in the entire memory system. [Means for solving the problem]

[0005] The present disclosure can be realized in the following forms.

[0006] According to one embodiment of the present disclosure, there is provided a memory controller (100), which issues a command to a semiconductor memory device (300) having a plurality of ranks (R0, R1, R2) in response to an access request from an arithmetic device (210, 220, 230) to the semiconductor memory device, and includes an access request holding unit (110) that holds a plurality of the access requests and holds an access target address, an access type, and a data length for each of the plurality of access requests, an access request selection unit (130) that calculates an estimated processing time for the access request from the data length and determines a processing order for the access requests in accordance with the estimated processing time and the access target address and the access type held in the access request holding unit, a command generation unit (120) that converts each of the access requests held in the access request holding unit into an access command that is a command instructing an access indicated by the access request held in the access request holding unit and issues the access command to the semiconductor memory device in accordance with the processing order, and a notification is generated at each refresh interval of the semiconductor memory device. the access request selection unit calculates a total processing time which is the sum of the expected processing times of the plurality of access requests for each of the plurality of ranks, selects, as an access request group, the plurality of access requests for an access target rank which is a rank having a total processing time longer than a refresh processing time which is the time required for refreshing, and determines an order of processing the access requests in the selected access request group, and the command generation unit issues the access commands to the access target ranks in order, and issues a refresh command which is a command instructing the execution of a refresh to a refresh target rank which is a rank other than the access target rank and has a counter value greater than a first threshold value. According to this embodiment of the memory controller, an access command is issued to a rank that is the target of an access request group whose processing time exceeds the refresh processing time among the multiple ranks, and refresh is executed to the other ranks while the access command is being issued. Therefore, since each rank is refreshed more frequently than when refresh is executed periodically, even if access requests are unevenly distributed to some ranks, it is possible to prevent refresh from being forcibly executed in the rank to which the access requests are unevenly distributed, and to prevent a decrease in access efficiency. [Brief description of the drawings]

[0007] [Figure 1] 1 is an explanatory diagram showing a schematic configuration of a memory controller according to an embodiment of the present invention; [Diagram 2] 11 is a flowchart showing the processing procedure of the first half of an access request selection process according to the present embodiment. [Diagram 3] 13 is a flowchart showing the processing procedure of a second half of the access request selection process according to the present embodiment. [Figure 4] 10 is a flowchart showing a procedure of a counting operation of a refresh counter according to the present embodiment. [Diagram 5] 5 is a flowchart showing a procedure of a memory access process according to the present embodiment. [Figure 6] 10 is a flowchart illustrating a procedure for a refresh process according to the present embodiment. [Figure 7] 10 is a flowchart showing the procedure of an access command issuing process according to the present embodiment. [Figure 8] 13 is a flowchart showing a procedure of a process performed in an access command issuing process when a counter value is equal to or greater than a second threshold value. [Figure 9] 13 is a flowchart showing a procedure of a process performed in an access command issuing process when a counter value is equal to or greater than a third threshold value. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A. Embodiment: A-1. System configuration: As shown in FIG. 1, the memory controller 100 is connected to the arithmetic devices 210 to 230 via a bus 400. The arithmetic devices 210 to 230 are, for example, CPUs or GPUs (Graphics Processing Units). The memory controller 100 may be connected to one arithmetic device instead of a plurality of arithmetic devices. The memory controller 100 is connected to the semiconductor memory device 300 via a bus 500. The semiconductor memory device 300 of this embodiment is a DRAM having a plurality of ranks R0 to R2. The number of ranks included in the semiconductor memory device 300 may be two or four or more. The semiconductor memory device 300 is configured to be able to read and write data for any storage unit specified by a command issued by the memory controller 100, and each of the ranks R0 to R2 includes a plurality of banks. The memory controller 100 issues a command to the semiconductor memory device 300 in response to an access request issued by the arithmetic devices 210 to 230, and causes the semiconductor memory device 300 to read and write data. In this embodiment, commands issued by the memory controller 100 include a read command for instructing the semiconductor memory device 300 to read data, a write command for instructing the semiconductor memory device 300 to write data, and a refresh command for instructing a refresh.

[0009] The memory controller 100 includes an access request holding unit 110, a command generating unit 120, an access request selecting unit 130, a refresh interval counter 140, and refresh counters 150-152. The access request holding unit 110 holds access requests issued by the arithmetic units 210-230 and information related to the access requests (hereinafter also referred to as "access request information"). The access request information includes an access target address, an access type, and a data length of the held access request. The "access target address" means a logical address of the access target data. In this embodiment, the "access type" indicates whether the access request is a read access request indicating data reading from the semiconductor memory device 300 or a write access request indicating data writing to the semiconductor memory device 300. The "data length" indicates the length of data that the read access request or the write access request requests to read or write. When an access command, which will be described later, is issued, the access request holding unit 110 erases the access request, assuming that the processing of the access request corresponding to the issued access command has ended.

[0010] The command generating unit 120 converts the access target address of the access request held in the access request holding unit 110 into a physical address indicating the data storage area on the semiconductor memory device 300 in which the access target data is stored. In this embodiment, the command generating unit 120 determines the bits specifying the rank in the physical address by referring to the lower bits of the logical address. The "lower bits" refer to a bit string indicating a logical address that includes the least significant bit and has a sufficient number of consecutive bits to specify the rank. In this way, by determining the bits specifying the rank in the physical address by referring to the lower bits of the logical address, it becomes easier to distribute the access destinations, and it is possible to prevent access requests from being concentrated in a specific rank.

[0011] Furthermore, the command generating unit 120 generates an access command including the converted physical address. An "access command" refers to a read command that instructs reading of data indicated by a read access request and a write command that instructs writing of data indicated by a write access request. The command generating unit 120 issues the access commands to the semiconductor memory device 300 in accordance with the command issuing order determined by the access request selecting unit 130, which will be described later. In addition, when causing the semiconductor memory device 300 to execute a refresh, the command generating unit 120 issues a refresh command to the semiconductor memory device 300.

[0012] The access request selection unit 130 executes an access request selection process, which will be described later, and determines the processing order of the access requests held in the access request holding unit 110. In other words, the processing order of the access requests means the order in which the access commands are issued.

[0013] Refresh interval counter 140 issues a notification at each refresh interval to refresh counters 150 to 152. The "refresh interval" refers to the longest time allowed for executing a refresh on all rows, as defined by the standard of semiconductor memory device 300, divided by the number of rows that make up a bank.

[0014] The refresh counters 150-152 correspond to the ranks R0-R2, respectively, of the semiconductor memory device 300, and execute counting operations, which will be described later, to hold counter values ​​Cnt0-Cnt2, respectively. The counter values ​​Cnt0-Cnt2 are expressed as positive or negative integers.

[0015] A-2. Access Request Selection Process: The access request selection process shown in Fig. 2 and Fig. 3 will be described. As shown in Fig. 2, the access request selection unit 130 judges whether or not there is an access request held by the access request holding unit 110 (step S110). If it is judged that there is no access request held by the access request holding unit 110 (step S110: No), the access request selection unit 130 waits until an access request is held in the access request holding unit 110.

[0016] If it is determined that there is an access request held in the access request holding unit 110 (step S110: Yes), the access request selection unit 130 acquires the access request information held in the access request holding unit 110 (step S120).

[0017] The access request selection unit 130 calculates an estimated processing time for each access request (step S130). The "estimated processing time" refers to the time estimated to be required to process an access request, calculated based on the data length of the acquired access request information.

[0018] The access request selection unit 130 calculates the total processing time for each access request group candidate (step S140). An "access request group candidate" refers to a plurality of access requests that specify the same rank and that specify a common row address for each bank. Also, the "total processing time" refers to the sum of the estimated processing times of the access requests that form the access request group candidate.

[0019] The access request selection unit 130 determines an access request group for each rank (step S150). An "access request group" refers to an access request group candidate that has the longest total processing time among a plurality of access request group candidates.

[0020] 3, the access request selection unit 130 determines whether or not there is a rank that corresponds to the access target rank among the ranks that are the targets of the access request group (step S160). The "access target rank" refers to a rank for which the total processing time of the access request group to that rank is longer than the time required for refreshing (hereinafter also referred to as the "refresh processing time").

[0021] If it is determined that there is an access target rank (step S160: Yes), the access request selection unit 130 determines the order of issuing access commands so that the access request group for the access target rank is processed next (step S170), and ends the access request selection process. The access request selection unit 130 determines the processing order of the access requests included in the access request group so as to improve access efficiency, for example, by continuously processing command requests of the same access type. Furthermore, when there are multiple ranks corresponding to the access target rank, the access request selection unit 130 determines the order of issuing access commands so as to give priority to processing of the access request group including an access request with a high priority set in advance by the arithmetic devices 210 to 230. Furthermore, the priority may be set so that the priority becomes higher as the time elapsed since the access request was issued becomes longer.

[0022] If it is determined that there is no access target rank (step S160: No), the access request selection unit 130 determines whether there is a combination of multiple ranks that corresponds to an access target rank group (step S162). An "access target rank group" refers to a combination of multiple ranks in which the sum of the total processing times of the access request groups for each rank is longer than the refresh processing time.

[0023] If it is determined that there is an access target rank group (step S162: Yes), the access request selection unit 130 determines the order of issuing access commands so that the access request group for the access target rank group is processed next (step S172), and ends the access request selection process. If there are multiple combinations of multiple ranks corresponding to the access target rank group, the order of issuing access commands is determined so that processing is prioritized from the access request group including the access request with the high set priority, as in the process when there are multiple ranks corresponding to the access target ranks described above.

[0024] If it is determined that there is no access target rank group (step S162: No), the access request selection unit 130 determines the access command issuing order so that the access request group including the access request with the set high priority is processed next (step S174). After step S174 is completed, the access request selection unit 130 ends the access request selection process.

[0025] A-3.Counting operation: The counting operation shown in Fig. 4 will be described. The counting operations performed in the refresh counters 150 to 152 are similar, so the counting operation in the refresh counter 150 will be described as an example. When the refresh counter 150 receives a notification issued from the refresh interval counter 140 (step S210: Yes), the refresh counter 150 adds 1 to the counter value Cnt0 (step S220). When a refresh is executed in the rank R0 (step S212: Yes), the refresh counter 150 subtracts 1 from the counter value Cnt0 (step S222). In this way, the refresh counter 150 continues to execute the addition process executed each time a notification is issued from the refresh interval counter 140 and the subtraction process executed each time a refresh is executed in the corresponding rank R0 in parallel while the memory controller 100 is in operation.

[0026] A-4.Memory access processing: The memory controller 100 executes memory access processing in response to access requests issued by the arithmetic devices 210-230, and issues refresh commands and access commands. The memory access processing shown in FIG. 5 will be described. The memory controller 100 executes the above-mentioned access request selection processing (step S300). The memory controller 100 executes refresh processing for each of the ranks R0-R2 in accordance with the access command issuing order determined in step S300 (steps S400-S420), and also executes access command issuing processing (step S500). The memory controller 100 continues to execute each refresh processing and access command issuing processing while the memory controller 100 is in operation.

[0027] The refresh process shown in FIG. 6 will be described. The refresh processes executed in ranks R0 to R2 are similar, so the refresh process in rank R0 will be described as an example. The command generation unit 120 judges whether rank R0 is scheduled to be accessed or is currently being accessed (step S402). In other words, the command generation unit 120 judges whether rank R0 is a rank to be accessed or is included in a group of ranks to be accessed. If it is judged that rank R0 is scheduled to be accessed or is currently being accessed (step S402: Yes), the command generation unit 120 waits until rank R0 is no longer scheduled to be accessed or is no longer currently being accessed. Note that "access" refers to a state in which the issuance of an access command is continuously performed.

[0028] If it is determined that rank R0 is not scheduled to be accessed or is not being accessed (step S402: No), the command generator 120 determines whether the counter value Cnt0 of the refresh counter 150 is greater than the threshold value TH1 (step S404). The threshold value TH1 is set according to the maximum number of times that the semiconductor memory device 300 can execute refresh prior to the refresh interval, which is determined by the standard of the semiconductor memory device 300. The semiconductor memory device 300 of this embodiment can execute refresh prior to the refresh interval up to eight times, and the threshold value TH1 is set to -8. The threshold value TH1 corresponds to the "first threshold value" in this disclosure.

[0029] If it is determined that the counter value Cnt0 is equal to or less than the threshold value TH1 (step S404: No), the command generating unit 120 performs the process of step S402 again. If it is determined that the counter value Cnt0 is greater than the threshold value TH1 (step S404: Yes), the command generating unit 120 issues a refresh command and causes all banks belonging to rank R0 to be refreshed (step S406). In this embodiment, when performing the process of step S406, if other ranks are also in a state where they can be refreshed, refresh is performed in order from the rank with the largest counter value of the refresh counter corresponding to each rank. Note that a rank that is not an access target rank or a rank included in the access target rank group and has a counter value greater than the threshold value TH1 corresponds to a "refresh target rank" in this disclosure.

[0030] After the refresh is completed, the access request selection unit 130 executes the access request selection process described above (step S408). That is, the access request selection unit 130 executes the access request selection process each time the refresh is completed in any rank, and updates the access command issuing order. After the step S408 is completed, the process returns to step S402, and the memory controller 100 repeatedly executes the processes of steps S402 to S408.

[0031] A description will now be given of the access command issuing process shown in Fig. 7 to Fig. 9. As shown in Fig. 7, the command generating unit 120 obtains the access command issuing order determined by the above-mentioned access request selection process (step S510).

[0032] The command generating unit 120 determines whether the counter value CntN of the refresh counter corresponding to the rank N for which the next access command is to be issued is smaller than a threshold value TH2 (step S520). The threshold value TH2 is set to an arbitrary value equal to or greater than 0. The threshold value TH2 corresponds to the "second threshold value" in this disclosure.

[0033] If it is determined that the counter value CntN is smaller than the threshold value TH2 (step S520: Yes), the command generator 120 determines whether the counter value CntN is smaller than a threshold value TH3 (step S530). The threshold value TH3 is set to an arbitrary value larger than the threshold value TH2. The threshold value TH3 corresponds to the "third threshold value" in this disclosure.

[0034] If it is determined that the counter value CntN is smaller than the threshold value TH3 (step S530: Yes), the command generating unit 120 issues an access command instructing an access of the access type indicated by one access request in accordance with the access command issuing order (step S540).

[0035] The command generating unit 120 determines whether or not the issuance of all access commands has been completed for each access request group (step S550). If the issuance of all access commands has not been completed (step S550: No), the command generating unit 120 repeatedly executes the processes of steps S520 to S540 until the issuance of all access commands has been completed. If the issuance of all access commands has been completed (step S550: Yes), the memory controller 100 executes step S510 again, and repeatedly executes the processes of steps S520 to S540 again for the access request group for which the next access command is to be issued and processed.

[0036] If it is determined in step S520 that the counter value CntN is equal to or greater than the threshold value TH2 (step S520: No), the access request selection unit 130 acquires the access request information held in the access request holding unit 110 (step S522), as shown in Fig. 8. The rank where the counter value is equal to or greater than the threshold value TH2 corresponds to the "first priority refresh rank" in this disclosure.

[0037] Using the acquired access request information, the command generation unit 120 determines whether or not there is an accessible rank (step S532). An "accessible rank" refers to a rank other than the currently accessed rank, which has already been refreshed, and for which there is an access request. If it is determined that there is no accessible rank (step S532: No), the command generation unit 120 executes the process of step S530 in FIG. 7.

[0038] As shown in FIG. 8, if it is determined that there is an accessible rank (step S532: Yes), the command generating unit 120 interrupts access to the currently accessed rank and causes the rank whose access has been interrupted to perform a refresh (step S542).

[0039] The command generating section 120 determines the command issuing order so that the access request for the accessible rank is processed next (step S552), and executes the process of step S520 in FIG.

[0040] If it is determined in step S530 shown in Fig. 7 that the counter value CntN is equal to or greater than the threshold value TH3 (step S530: No), the command generator 120 interrupts access to the currently accessed rank and causes the rank whose access has been interrupted to execute a refresh (step S534), as shown in Fig. 9. The rank whose counter value is equal to or greater than the threshold value TH3 corresponds to the "second priority refresh rank" in this disclosure.

[0041] The access request selection unit 130 acquires the access request information stored in the access request storage unit 110 (step S544). Using the acquired access request information, the command generation unit 120 determines whether or not there is an accessible rank (step S554).

[0042] If it is determined that there is no accessible rank (step S554: No), command generation unit 120 repeatedly executes steps S544 and S554 until an accessible rank appears. If it is determined that there is an accessible rank (step S554: Yes), command generation unit 120 executes the process of step S552 in FIG.

[0043] According to the memory controller 100 of the embodiment described above, an access command is issued to the access target rank, and while the access command is being issued to the access target rank, refresh is executed for the other ranks. Therefore, since each rank is refreshed more frequently than when refresh is executed periodically, even if access requests are unevenly distributed to the access target rank, it is possible to prevent the refresh from being forcibly executed in the access target rank, and to prevent a decrease in access efficiency.

[0044] Furthermore, the memory controller 100 selects, for each bank, a plurality of access requests that specify a common row address as an access request group, so that the number of times the row address needs to be changed can be reduced, and a decrease in access efficiency can be further reduced.

[0045] In addition, when there are multiple ranks to be refreshed, the memory controller 100 issues refresh commands in order of rank with the largest counter value, so that refresh can be performed preferentially in order of rank with the greatest need for refresh, thereby suppressing a decrease in the stability of data retention in the semiconductor memory device 300.

[0046] Furthermore, when there are multiple access target ranks, the memory controller 100 processes the access requests in order starting from the rank including the access request with the highest priority level, thereby enabling efficient processing of the access requests.

[0047] Furthermore, when there is no access target rank, the memory controller 100 issues an access command to the access target rank group, and executes refresh for other ranks while issuing the access command to the access target rank group. Therefore, in the same way as issuing an access command to the access target rank, it is possible to suppress a decrease in access efficiency.

[0048] Furthermore, when the counter value of the rank to be accessed becomes equal to or greater than the threshold value TH2 and there is another accessible rank other than the rank in question, the memory controller 100 interrupts the issuance of an access command to the rank being accessed, issues a refresh command, and issues an access command to the accessible rank. This allows the memory system as a whole to perform refresh without stopping the issuance of access commands, thereby suppressing a decrease in access efficiency.

[0049] Furthermore, when the counter value of the rank to be accessed becomes equal to or greater than the threshold value TH3, the memory controller 100 stops issuing the access command to that rank and issues a refresh command, thereby ensuring that refresh can be performed even on the rank to be accessed, and preventing a decrease in the stability of data retention in the semiconductor memory device 300.

[0050] In addition, when converting a logical address to a physical address, the memory controller 100 determines the rank address of the physical address by referring to the lower bits of the logical address, making it easier to distribute access destinations and preventing access requests from being concentrated in a specific rank.

[0051] B. Other embodiments: (B1) In the above embodiment, when there are multiple refresh target ranks, the command generating unit 120 issues refresh commands in descending order of the counter value, but the present disclosure is not limited to this. The command generating unit 120 may issue refresh commands in any order regardless of the counter value.

[0052] (B2) In the above embodiment, the access request selection unit 130 selects, as an access request group, a plurality of access requests that specify a common row address for each bank, but the present disclosure is not limited to this. The access request selection unit 130 may select, as an access request group, a plurality of access requests that specify different row addresses for each bank. When selecting access requests in this way, it is preferable to process the access requests in an order that can suppress a decrease in access efficiency, for example, when there are sufficient access requests to other banks, to process an access request to another bank between the processing of two access requests that specify different row addresses.

[0053] (B3) In the above embodiment, when there are multiple access target ranks or access target rank groups, the access request selection unit 130 determines the order of issuing access commands so as to give priority to processing of an access request group including an access request with a high set priority, but the present disclosure is not limited to this. The access request selection unit 130 may process the access request groups in any order, regardless of priority.

[0054] (B4) In the above embodiment, when converting the access target address from a logical address to a physical address, the command generation unit 120 determines the bit that specifies the rank address in the physical address by referring to the lower bits of the logical address, but the present disclosure is not limited to this. The command generation unit 120 may determine the bit that specifies the rank address in the physical address by referring to the upper bits of the logical address.

[0055] The present disclosure is not limited to the above-mentioned embodiment, and can be realized in various configurations without departing from the spirit of the present disclosure. For example, the technical features in each embodiment corresponding to the technical features in the form described in the Summary of the Invention column can be appropriately replaced or combined in order to solve some or all of the above-mentioned problems or to achieve some or all of the above-mentioned effects. Furthermore, if the technical feature is not described as essential in this specification, it can be appropriately deleted.

[0056] The control unit and the method described in the present disclosure may be realized by a special-purpose computer provided by configuring a processor and a memory programmed to execute one or more functions embodied in a computer program. Alternatively, the control unit and the method described in the present disclosure may be realized by a special-purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit and the method described in the present disclosure may be realized by one or more special-purpose computers configured by a combination of a processor and a memory programmed to execute one or more functions and a processor configured with one or more hardware logic circuits. In addition, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions executed by a computer. [Explanation of symbols]

[0057] R0, R1, R2...rank, 100...memory controller, 110...access request holding unit, 120...command generation unit, 130...access request selection unit, 140...refresh interval counter, 150, 151, 152...refresh counter, 210...arithmetic unit, 300...semiconductor memory device

Claims

1. A memory controller (100) that issues a command to a semiconductor memory device (300) having a plurality of ranks (R0, R1, R2) in response to an access request from an arithmetic unit (210, 220, 230) to the semiconductor memory device, an access request storage unit (110) that stores a plurality of the access requests and stores an access target address, an access type, and a data length for each of the plurality of access requests; an access request selection unit (130) that calculates an estimated processing time for the access request from the data length, and determines a processing order for the access requests according to the estimated processing time, the access target address, and the access type stored in the access request storage unit; a command generating unit (120) that converts the access requests held in the access request holding unit into access commands that instruct the access of the access type indicated by the access requests, and issues the access commands to the semiconductor memory device in accordance with the processing order; a refresh interval counter (140) for issuing a notification at each refresh interval of the semiconductor memory device; A refresh counter (150, 151, 152) that holds a counter value for each of the plurality of ranks, the counter value being incremented each time the notification is issued and decremented each time a refresh is executed; Equipped with the access request selection unit calculates a total processing time, which is a sum of the estimated processing times of the plurality of access requests, for each of the plurality of ranks, selects, as an access request group, the plurality of access requests for an access target rank, which is a rank whose total processing time is longer than a refresh processing time, which is a time required for refreshing, and determines an order of processing the access requests in the selected access request group; the command generation unit issues the access commands to the access target ranks in order, and issues a refresh command, which is a command instructing the execution of a refresh, to a refresh target rank that is a rank other than the access target rank and has the counter value greater than a first threshold value; Memory controller.

2. 2. The memory controller of claim 1, The semiconductor memory device has a plurality of banks, In the access request group, the access requests specifying each bank specify a common row address. Memory controller.

3. 3. The memory controller according to claim 1, When there are a plurality of refresh target ranks, the command generation unit issues the refresh commands in descending order of the rank having the largest counter value. Memory controller.

4. 3. The memory controller according to claim 1, When there are a plurality of access target ranks, the command generation unit issues the access commands in order from the rank including the access request having the highest priority. Memory controller.

5. 5. The memory controller of claim 4, The priority is preset by the computing device. Memory controller.

6. 5. The memory controller of claim 4, the access request selection unit sets the priority such that the priority becomes higher as the time elapsed since the issuance of the access request becomes longer. Memory controller.

7. 3. The memory controller according to claim 1, When the semiconductor memory device includes three or more ranks and there is no rank corresponding to the access target rank, the command generation unit issues the access command to an access target rank group which is a combination of a plurality of ranks whose sum of the total processing times of the respective ranks is greater than the refresh processing time, and issues the refresh command to a rank other than the access target rank group and whose counter value is greater than the first threshold value. Memory controller.

8. 3. The memory controller according to claim 1, When the access target rank becomes a first-priority refresh rank, which is a rank at which the counter value is equal to or greater than a second threshold value, and when there is an accessible rank other than the first-priority refresh rank, which is a rank for which the access request has occurred and for which refresh has already been completed, the command generation unit suspends issuance of the access command to the first-priority refresh rank, issues the refresh command to the first-priority refresh rank, and issues the access command to the accessible rank. Memory controller.

9. 9. The memory controller of claim 8, when the access target rank becomes a second-priority refresh rank, which is a rank for which the counter value is equal to or greater than a third threshold value greater than the second threshold value, the command generation unit suspends issuance of the access command to the second-priority refresh rank and issues the refresh command to the second-priority refresh rank, and when there is an accessible rank other than the second-priority refresh rank, which is a rank for which the access request has occurred and for which refresh has already been completed, issues the access command to the accessible rank. Memory controller.

10. 3. The memory controller according to claim 1, When converting a logical address into a physical address, the rank address is determined by referring to the lower bits of the logical address. Memory controller.

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