Power-on reset circuit and integrated circuit including the same

Abstract

The power-on reset circuit includes a terminal (101) for a reference potential (VSS) and a terminal (102) for a supply potential (VDD), and a voltage divider (130) coupled therebetween. First and second transistors (110, 120) of the bandgap circuit are each resistively coupled to the reference potential terminal (101) and have their bases connected to the voltage divider (130). A current mirror (150, 160, 170) couples the collectors of the first and second transistors (110, 120) to an output terminal (103) that provides an output signal (POR) indicative of a power-on reset state. A first compensating transistor (180) is coupled between the collector of one of the transistors (120) and the reference potential terminal (101), and a second compensating transistor (190) is coupled between the output terminal (103) and the reference potential terminal (101) to compensate for the effects of parasitic substrate currents in response to external interference.

Description

[Technical field]

[0001] The present disclosure relates to a power-on reset circuit. More specifically, the present disclosure relates to a power-on reset circuit having first and second transistors forming a bandgap circuit and a current mirror for coupling the collectors of the transistors to an output terminal. The present disclosure also relates to an integrated circuit having a power-on reset circuit for controlling a portion of the integrated circuit.

[0002] This patent application claims priority to European Patent Application No. 20172116.4, filed April 29, 2020, the disclosure of which is incorporated herein by reference. [Background technology]

[0003] Power-on reset (POR) circuits are widely used in electronic devices to monitor the current level of a power supply voltage and hold a functional unit of the electronic device in a reset state when the power supply voltage falls below a threshold level and release the reset state when the power supply voltage rises above the threshold level. A conventional POR circuit has a bandgap arrangement that determines the trip point based on the bandgap voltage of silicon, which can be reliably reproduced with a corresponding arrangement of bipolar transistors. As long as the power supply voltage level is above the threshold, the POR circuit operates to always remain powered on. POR circuits may be provided in integrated circuits that are subject to external interference, such as high temperatures or electromagnetic fields when the circuit is used in an industrial or automotive environment, or stray light incident on the POR circuit when the integrated circuit is used as an optoelectronic device. Such interference may induce parasitic substrate currents in the semiconductor substrate incorporating the POR circuit and the integrated circuit. Parasitic substrate currents may act on the collectors of the bipolar transistors of the POR circuit and flow vertically and laterally. The substrate current may be caused as a leakage current or a photocurrent between the collector of the bipolar transistor of the POR circuit and the semiconductor substrate, or through a parasitic transistor established in the substrate with the collector of the bipolar transistor of the POR circuit.

[0004] The switching action of the bandgap current switch in the POR circuit is based on the ratio of substantially different currents flowing through the bipolar transistors of the bandgap circuit forming the current switch. The currents are mirrored to the output terminals, which pull the output terminals to the high-side or low-side voltage supply terminals. When external interference causes a parasitic substrate current, a corresponding current is induced in the bipolar transistors of the bandgap current switch, and the mirror ratio of the current mirror causes an asymmetric parasitic contribution to the pull-up and pull-down currents at the output terminals. As a result, the POR circuit may exhibit a tendency to exhibit a power-on reset condition in response to an external interference event, even though the supply voltage level is still at a sufficient and acceptable voltage level. It is desirable to avoid such fail-reset switching of the POR circuit, since the circuit may be interrupted and reset, resulting in loss of data.

[0005] There is a need for a POR circuit that can operate in an environment where external interference occurs. There is a need for a POR circuit for industrial, automotive and optoelectronic applications that operates more robustly and is less susceptible to external interference such as high temperature, EMI and light. The POR circuit needs to avoid fail reset in response to external interference such as high temperature, EMI and stray light that may generate parasitic currents such as leakage current, lateral current and photocurrent. It is an object of the present disclosure to provide a power-on reset circuit that operates more robustly in an environment with external interference.

[0006] Another object of the present disclosure is to provide a power-on reset circuit that provides a stable trip point, even under external interference.

[0007] Yet another object of the present disclosure is to provide a POR circuit that does not experience reset failure even under harsh environmental conditions and operates accurately.

[0008] It is yet another object of the present disclosure to provide an optoelectronic integrated circuit or integrated circuit with ESD protected external terminals that operate more accurately. Summary of the Invention

[0009] According to the present disclosure, one or more of the above mentioned objects are achieved by a power-on reset circuit comprising the features of claim 1.

[0010] According to one embodiment, the power-on reset circuit comprises a reference potential terminal and a supply potential terminal that can be operably coupled to a power supply voltage source. A voltage divider connected between the reference potential terminal and the supply potential terminal senses the level of the supply voltage. First and second transistors have bases connected to an output node of the voltage divider and emitters coupled via a resistive network to the reference potential terminal. A first current mirror is coupled to the collector of the first transistor and to the output terminal, the output terminal being configured to provide an output signal in response to a voltage between the reference potential terminal and the supply potential terminal. A second current mirror is connected to the collector of the second transistor and further coupled to the output terminal via a third current mirror. The power-on reset circuit further comprises first and second compensation transistors, the first compensation transistor coupled between a collector of one of the first and second transistors and the reference potential terminal, and the second compensation transistor coupled between the output terminal and the reference potential terminal.

[0011] The first and second compensating transistor devices compensate for parasitic currents in a semiconductor substrate incorporating the power-on reset circuit. For example, the parasitic substrate current may be a leakage current through a collector-substrate diode of a bipolar transistor caused by external interference such as high temperature. The parasitic substrate current may be a photoelectric current through a collector-substrate diode of a bipolar transistor that may act as a parasitic photodiode when stray light couples to the backside of an integrated circuit, which may occur if the power-on reset circuit is included in an optoelectronic device. The parasitic current may be a lateral current that flows through a parasitic transistor parasitically formed by the collector of the bipolar transistor, the semiconductor substrate and other doped regions when the other doped regions are biased by an electromagnetic event. This may be the case when the doped regions are connected to an external terminal, such as a pad region in a circuit used in an electromagnetic environment. Such circuits are often equipped with electrostatic discharge (ESD) structures with such doped regions to induce EMI impulses into the substrate and prevent them from entering the circuit. In this case, the doped regions of the ESD structure may be negatively biased. The first and second compensating transistors compensate for such parasitic currents in that they generate an additional current from the collector to the substrate of one of the bipolar transistors of the bandgap circuit and another additional current from the output terminal to the substrate. The substrate may be connected to a reference potential. In another embodiment, the substrate may be connected to another potential different from the reference potential. The other potential may be lower than the reference potential. The effect of the first compensating transistor on the bandgap current switch formed by the first and second transistors and the effect of the second compensating transistor on the output terminal are transformed via a current mirror, such that the parasitic asymmetric effect due to external interference is substantially compensated for.

[0012] The first and second compensation transistors make the circuit more robust against external interference in that the trip point of the POR circuit is stabilized. The first and second compensation transistors generate symmetrical parasitic pull-up and pull-down current contributions at the output terminal of the POR circuit, thereby maintaining the stability of the trip point and avoiding a fail reset.

[0013] The first and second compensation transistors may be matched to bipolar transistors forming the bandgap current switch. The first and second compensation transistors may each be formed from a bipolar transistor having a base region, a collector region, and an emitter region, with the base connected to the collector or the emitter. The base and emitter regions of the first and second compensation transistors are connected to each other, whereby a substrate diode is formed from the collector region of the compensation transistor to the semiconductor substrate. The semiconductor substrate may be P-conductive or P-doped, and the transistor is an NPN transistor having N-doped collector and emitter regions and a P-doped base region. Since the first and second compensation transistors use the same building blocks used to form the first and second bipolar transistors of the bandgap current switch, the bandgap transistor and the compensation transistor may be assumed to be matched in structure, matched in dimensions, and therefore matched in electrical behavior.

[0014] The first and second transistors of the current switch form a bandgap circuit with a switch point at the base of the transistor of approximately 1.2V. The bandgap function is achieved by having the collector area of ​​one transistor, such as the first transistor, be a multiple of the collector area of ​​the second transistor. For example, the collector area of ​​the first transistor may be an integer multiple of the collector area of ​​the second transistor, such as 4:1. Other integer multiples or other relationships may also be used. Typically, the integer multiple is achieved by connecting bipolar transistor units in parallel with each other. As an example, four units may be connected to provide a collector area of ​​four units for the first transistor, and one collector unit may be used for the second transistor to provide a collector area ratio of 4:1.

[0015] In addition, the first compensation transistor may be connected to a transistor of the bandgap current switch having a smaller collector area, such as an area of ​​one unit of the second transistor, and a base and an emitter of the first compensation transistor may be connected to each other and to a reference potential terminal.

[0016] The collector of the first bipolar transistor of the bandgap current switch is coupled to the output terminal through a first current mirror. The first current mirror includes an input path having a diode-connected transistor coupled between the collector of the first transistor and a supply potential terminal. The first current mirror further includes an output path having another transistor, and the control terminals of the transistors in the input path and output path of the first current mirror are connected to each other such that a potential from the diode-connected transistor in the input path controls a current through the transistor in the output path. The transistor in the output path is connected between the output terminal and the supply potential terminal. The first current mirror has a defined current conversion ratio between the current through the input path and the current through the output path such that an output signal at the output terminal provides a reliable trip point under normal operating conditions. In one embodiment, the current conversion ratio of the first current mirror may be M1:1. M1 may be an integer value. In one embodiment, the current conversion ratio of the first current mirror may be 6:1. The current transfer ratio is achieved by the width-to-length (W / L) ratio of the transistors in the input path to the output path, which are field effect transistors.

[0017] In a corresponding method, a second current mirror includes an input path having a diode-connected transistor connected to the collector of the second transistor of the bandgap current switch and to the supply potential terminal. An output path includes another transistor, and control terminals of the transistors in the input / output path of the second current mirror are connected to each other. The output path of the second current mirror is coupled to the output terminal via a third current mirror including an input path having a diode-connected transistor connected between the output path transistor of the second current mirror and a reference potential terminal, and an output path having another transistor connected between the output terminal and the reference potential terminal. Control terminals of the transistors in the input / output path of the third current mirror are connected to each other.

[0018] The second and third current mirrors each have an individual current conversion ratio that forms a combined current conversion ratio of the second and third current mirrors. The current conversion ratios may be integers, but may also be rational numbers. For example, the current mirror ratio of the second current mirror may be M2:1 and the current conversion ratio of the third current mirror may be M3:1. In one embodiment, M2:1 may be 3:1 and M3:1 may be 1:1, resulting in a combined conversion ratio of 3:1. Other ratios may be used.

[0019] A second compensation transistor connected between the output terminal and the reference potential terminal is connected in parallel with the output path transistor of the third current mirror. In one embodiment, the base-collector path of the second compensation transistor is connected in parallel with the output path transistor of the third current mirror.

[0020] Matching elements in the POR circuit, such as bipolar transistors and transistors of the current mirrors, which may be field effect transistors with width / length (W / L) ratios defined to establish current conversion ratios of the corresponding current mirrors, are set so that vertical or lateral parasitic substrate currents in the substrate generated by external events such as high temperature, EMI, stray light, etc., generate substantially equal contributions to the parasitic pull-up and pull-down currents at the output terminals. The collector areas of the first and second transistors are N1 and N2, respectively, the collector areas of the first and second compensating transistors are N3 and N4, respectively, and the current mirror conversion ratios of the first, second and third current mirrors are M1:1, M2:1 and M3:1, respectively. To equalize the contributions of the parasitic currents at the output terminals, these collector areas and current conversion ratios must satisfy the following equation: N1 / M1=(N2+N3) / (M2×M3)+N4

[0021] In one embodiment, the collector areas of the first and second transistors are 4:1, the current conversion ratio of the first current mirror is 3:1, the current conversion ratio of the second current mirror is 6:1, the current conversion ratio of the third current mirror is 1:1, and the collector area ratio between the second transistor of the bandgap current switch and the first and second compensation transistors is 1:1. Therefore, the above formula is satisfied as follows: 4 / 3=(1+1) / (6x1)+1

[0022] In one embodiment, the transistors of the bandgap current switch may be bipolar transistors such that the trip point of the current switch is approximately 1.2V at the bandgap voltage supplied to the transistor base. The first and second compensation transistors are also realized by bipolar transistors in order to realize a sufficient match with the bipolar transistors of the bandgap current switch. The transistors of the current mirror are composed of field effect transistors with a PCHMOS transistor for the current mirror connected to the power supply potential terminal and an NCHMOS transistor for the current mirror connected to the reference potential terminal. The width / length (W / L) ratios of the field effect transistors are reproducible and match each other, so that the current conversion ratio can be reliably set with the field effect transistors. Overall, the combination of bipolar and field effect transistors with one of the transistors of the bandgap current switch and a compensation transistor at the output terminal realizes a POR circuit with a defined and robust trip point even in case of external interference. The trip point of the bandgap current switch is defined by a bandgap reference voltage of a silicon diode, such as a base-emitter diode of a bipolar NPN transistor, while the switching threshold with respect to a supply voltage level between the supply potential terminal and the reference potential terminal can be set by a voltage divider connected between the supply voltage terminals. The voltage divider has an output node or an intermediate node connected to the bases of the first and second transistors of the bandgap current switch. The voltage divider may be a resistive voltage divider, particularly an ohmic voltage divider with ohmic resistors.

[0023] Another voltage divider may be provided between the emitter of the bipolar transistor of the bandgap current switch and the reference potential terminal, the external terminal of which may be connected between the emitter of the first bipolar transistor and the reference potential terminal, and the emitter of the second bipolar transistor may be connected to an intermediate node between the resistors of the voltage divider, the voltage divider may be a resistive voltage divider, in particular an ohmic voltage divider with ohmic resistors.

[0024] The POR circuit may be embedded in a semiconductor substrate of a first conductivity type, such as a P-substrate. The substrate has a deep well doping of another conductivity type, such as an N-well, which forms the collector of one of the bandgap current switch transistors. Another doped region of a second conductivity type, such as an N-well, may be disposed in the semiconductor substrate. In the case of a negatively biased N-well, a lateral substrate current may be generated from the N-well doped region through the P-substrate to the N-well collector region forming a parasitic lateral transistor. This may be the case, for example, when the N-well doped region is connected to an external terminal that may receive EMI impulses. According to the principles of the present disclosure, the effect of the substrate current is compensated by the first and second compensation transistors, as described above, so that an additional lateral substrate current is generated that compensates for the EMI event in that it equalizes the contribution of the pull-up and pull-down currents at the output terminal. Since the first and second compensation transistors generate such a current only under external interference conditions, their power consumption is very low and almost negligible. In normal operating mode, there is substantially no power consumption by the first and second compensation transistors.

[0025] An optoelectronic integrated circuit which solves one or more of the above mentioned objects comprises the features of claim 14.

[0026] The optoelectronic integrated circuit includes a circuit portion having one or more photodiodes. The photodiodes generate a current in response to an optical signal received by the circuit portion. The POR circuit provides a reset signal to the circuit portion of the integrated circuit having the photodiodes. The reset signal keeps the circuit portion in a reset state when the power supply voltage falls below a threshold, and releases the reset of the circuit portion and enables the circuit portion when the power supply voltage rises above the threshold. Since optoelectronic integrated circuits are often illuminated from the back side of the integrated circuit, stray light incident on the POR circuit may parasitically form a photodiode for stray light by a substrate diode between a collector region of a bipolar transistor and a semiconductor substrate, generating unwanted current. The power-on reset circuit according to the principles of the present disclosure includes a compensation transistor, whereby asymmetric optoelectronic effects caused by a parasitic photodiode of a bipolar transistor of a bandgap current switch are compensated by first and second compensation transistors that maintain a stable trip point.

[0027] One or more of the above mentioned objects are also achieved by an integrated circuit comprising the features of claim 15.

[0028] According to one embodiment, an integrated circuit has a circuit portion with at least one pad area, such as a metal pad, disposed on a surface of the integrated circuit. The POR circuit enables the circuit portion by releasing a reset of the circuit portion of the integrated circuit having the pad area. The pad area may be used to receive a bond wire for receiving or transmitting an external electrical signal. Such a pad area may be provided with an electrostatic discharge structure to prevent external interference, such as electromagnetic interference (EMI), from entering the electronic circuit. ESD structures are often used in industrial or automotive integrated circuits where EMI events may occur. The ESD structure may include a doped region disposed in a semiconductor substrate of the integrated circuit, the doped region being connected to the pad area. The POR circuit according to the principles of the present disclosure may generate a lateral substrate current between the collector of the bipolar transistor and the doped region of the ESD structure. The first and second compensation transistors generate additional parasitic currents at the output terminals that compensate for the parasitic currents generated by the bipolar transistor of the bandgap current switch, thereby maintaining a stable trip point of the POR circuit even during ESD operation due to an EMI impulse.

[0029] It should be understood that both the foregoing general description and the following detailed description are merely exemplary and are intended to provide an overview or framework for understanding the nature and features of the claims. The accompanying drawings are included to provide a further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate one or more embodiments, and together with the description, serve to explain the principles and operation of the various embodiments. In the drawings, the same elements in different figures are designated with the same reference numerals. [Brief description of the drawings]

[0030] [Figure 1] 1 is a schematic diagram of a power-on reset circuit in accordance with the principles of the present disclosure; [Diagram 2] FIG. 1 shows a conventional POR circuit. [Diagram 3]2 is a cross-sectional view of a portion of a semiconductor substrate and an external terminal of the power-on reset circuit of FIG. 1. [Figure 4] 2 is a diagram showing an integrated circuit having the power-on reset circuit of FIG. 1 and a functional circuit portion having a photodiode and an external terminal. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The present disclosure will now be described in more detail with reference to the accompanying drawings showing embodiments of the present disclosure. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure will fully convey the scope of the disclosure to those skilled in the art. The drawings are not necessarily drawn to scale and are designed to clearly illustrate the present disclosure.

[0032] 2 shows a conventional power-on reset (POR) circuit. The conventional circuit comprises a bandgap current switch with two bipolar transistors 210, 220 controlled by a voltage divider 230 supplied with supply voltages VDD, VSS. When the supply voltages VDD, VSS fall below a threshold, a current flows through the transistor 210 and is mirrored through the current mirror 250 to pull up the current IPU at the output terminal 230 and supply the supply potential VDD. The output signal POR is high (POR=1), indicating a power-on reset state. When the supply voltages VDD, VSS exceed the threshold, the current switches from the transistor 210 to the transistor 220. The collector current of the transistor 220 is mirrored through the current mirrors 260, 270 to pull down the current IPD at the output terminal 203 and pull down the output signal POR to a low level (POR=0), causing the output signal POR to change from a reset state to an on state indicating normal operation, allowing the supply voltage to be supplied to the functional circuit.

[0033] When an energy strike such as high temperature, electromagnetic waves, stray light, etc. occurs in the POR circuit and generates a substrate current in the chip, the collector areas of transistors 210, 220 draw parasitic currents from the collectors to ground potential VSS, such as currents IDNA, IDNB, from the collectors to the substrate of the integrated circuit. In one conventional embodiment, the collector area of ​​transistor 210 is four times the collector area of ​​transistor 220, and current mirror 250 has a current conversion ratio of 3:1, current mirror 260 has a current conversion ratio of 6:1, and current mirror 270 has a current conversion ratio of 1:1. The parasitic current IDNB of transistor 220 is mirrored to output node 203 with a ratio of 1 / 6, while the parasitic current IDNA of transistor 210 is mirrored to output node 203 with a ratio of 4 / 3. The trip point of the output node occurs when currents IPU and IPD are equal such that in the event of an energy strike that creates a parasitic substrate current, there is an increased tendency to pull output terminal 203 high and revert to a power-on reset condition. If the POR circuit exhibits a normal non-reset operating condition with an output signal POR=0, parasitic currents from external interference can cause the circuit to switch generating the reset condition POR=1, which can result in the operational circuit controlled by the power-on-reset circuit being reset and its operation being unintentionally interrupted and all operational data being lost. External interference that can cause such POR failures can occur, for example, in industrial and automotive environments and in photoelectric applications.

[0034] FIG. 1 illustrates a POR circuit according to the principles of the present disclosure. The POR circuit is robust against external influences that generate parasitic substrate currents in that it compensates for the effects of the parasitic substrate currents. The POR circuit of FIG. 1 includes a bandgap circuit with bipolar transistors 110, 120 with their base terminals connected together and to an output node of a resistive ohmic voltage divider 130. The voltage divider 130 includes ohmic resistors 131, 132 connected between terminals 101, 102 for reference potential VSS and supply potential VDD, respectively. The emitters of the transistors 110, 120 are resistively coupled to the terminal 101 for reference potential VSS. A voltage divider 140 is connected between the emitters of the transistors 110, 120 and the reference potential terminal 101. The voltage divider 140 includes ohmic resistors 141, 142 connected between the emitter of the transistor 110 and the reference potential terminal 101. The intermediate or middle node, which is the output node of the voltage divider 140, is connected to the emitter of the transistor 120. The transistor 110 has a larger collector area than the transistor 120. The transistor 110 has a collector area of ​​N1 units, and the transistor 120 has a collector of N2 units. The arrangement of the voltage dividers and transistors described above constitutes a bandgap circuit with a trip point at the bandgap voltage of silicon, for example, 1.2V. When the base potential of the transistors 110, 120 is below the bandgap voltage, a current flows through the transistor 110. When the base potential is higher than the bandgap voltage, a current flows through the transistor 120, and the transistors 110, 120 establish a bandgap current switch. The resistors 131, 132 of the voltage divider 130 can be designed so that the trip point of the bandgap current switch occurs at the desired level of the power supply voltages VDD, VSS.

[0035] The collector current of transistor 110 is mirrored to output terminal 103 via current mirror 150 to provide a pull-up current IPU at output terminal 103. The collector current of transistor 120 is mirrored to output terminal 103 via high-side current mirror 106 and low-side current mirror 170 to provide a pull-down current IPD at output terminal 103. Current mirror 150 comprises an input path with diode-connected transistor 151 connected between the collector of transistor 110 and supply potential terminal 102. Current mirror 150 further comprises an output path with transistor 152 connected between output terminal 103 and supply potential terminal 102. The control terminals of transistors 151, 152 are connected to each other. The control terminal of transistor 151 is connected to its drain terminal to form a diode. The current flowing through transistor 151 controls a corresponding current flowing through transistor 152. Depending on the dimensions of transistors 151, 152, the currents flowing through these transistors have a ratio of M1:1. The current conversion ratio is set by the relationship of the sizes of the transistors 151, 152, which is represented by the relationship between the width and length (W / L) of the gate areas of the transistors 151, 152.

[0036] The transistors 151, 152 are P-channel MOSFETs, while the transistors 110, 120 in the bandgap section are bipolar NPN transistors. Bipolar transistors provide defined switching points that can be manufactured reproducibly. The W / L ratio of the field effect transistors can be manufactured with sufficient control to obtain the desired current in the field effect transistors. The circuit of FIG. 1 can be realized on an integrated chip dedicated to mainly bipolar CMOS devices, such as P-channel and N-channel MOSFETs, and additionally to form at least one type of bipolar transistor, such as an NPN transistor.

[0037] The current mirror 160 comprises an input path having a diode-connected transistor 161 connected between the collector of the transistor 120 and the supply potential terminal 102, and an output path having a transistor 162 connected to the supply potential terminal 102. The transistors 161, 162 are P-channel MOSFETs with their gate terminals connected to each other. The current flowing through the transistor 162 is further mirrored to the output terminal 103 by the current mirror 170. The current mirror 170 has an input path having a diode-connected transistor 171 connected between the drain of the transistor 162 and the reference potential terminal 101. The output path of the current mirror 170 has a transistor 172 connected between the output terminal 103 and the reference potential terminal 101. The gate terminals of the N-channel MOSFETs 171, 172 are connected to each other. The current mirror 160 has a current conversion ratio of M2:1, and the current mirror 170 has a current conversion ratio of M3:1.

[0038] In one embodiment, the collector areas of transistors 110, 120 and the current conversion ratios of current mirrors 150, 160, 170 can be as follows: Transistor 110 has a collector area of ​​N1 units, which may be 4 units; Transistor 210 has a collector area of ​​N2 units, which may be 1 unit; Current mirror 150 may have a current ratio of 3:1, current mirror 160 may have a current ratio of 6:1, and current mirror 170 may have a current ratio of 1:1. Other ratios that produce a similar or identical effect are also possible. In one embodiment, transistor 110 is made of an integer number of bipolar units, which are connected in parallel with each other to achieve the desired collector area. By collecting bipolar units in parallel, a collector of the desired size can be defined and manufactured in a well-controlled manner.

[0039] The functionality of the circuit of Figure 1 in normal operating mode is the same as that described for the conventional circuit of Figure 2, since transistors 180, 190 do not conduct any appreciable current in normal operating mode. In the event of external interference that induces substrate current, such as high temperature, electromagnetic interference, stray light, etc., a predominantly vertical or predominantly lateral substrate current may be generated, as will be described with reference to Figure 3.

[0040] FIG. 3 is a cross-sectional view of one of the bipolar transistors, such as transistors 110, 120. A doped region of one of the transistors is disposed in a semiconductor substrate 300 of P conductivity type. A deep doped well 311 forms the collector of the bipolar transistor of N conductivity type. The collector well has a doped region 312 of P conductivity type forming the base of the bipolar transistor. A doped region 313 of N conductivity type in the P doped region 312 constitutes the emitter of the bipolar transistor. A parasitic substrate diode 330 is formed by the deep N well doped region 311 of the collector and the P substrate 300. At high temperatures, the leakage current 341 through the parasitic substrate diode 330 increases and may not be negligible with respect to the contribution of a mirrored version of said leakage current at the output terminal 103. Also, stray light coupled into the semiconductor chip, for example through the backside of the chip, may generate a photocurrent such as 341 due to a parasitic photodiode acting as a parasitic substrate diode. Stray light may be incident on the backside of the portion of the chip carrying the POR circuitry if the chip is a backside illuminated optoelectronic chip.

[0041] Additionally, the semiconductor substrate 300 may have an N-well such as 320, which may be a deep N-well for other electrical reasons. The N-well 320 may be part of an ESD protection structure that may be coupled to a metal pad 321 that forms a connection area for receiving or transmitting an electrical signal via a bond wire connected to the pad area 321. A parasitic transistor 340 is established by the deep N-well doped region 311 of the bipolar transistor, the P-substrate 300, and the N-well 320 of the ESD protection structure. The substrate 300 is typically biased by a ground potential VSS and a connected ground potential terminal 101. An electromagnetic interference (EMI) impulse may negatively bias the deep N-well doped region 320 to a potential below the reference potential VSS such that the parasitic transistor 340 may conduct and generate a lateral parasitic current 342. As discussed above with reference to FIG. 2, vertical and lateral substrate currents generate currents in the collectors of transistors 110, 120 that are asymmetrically mirrored to the output nodes via current mirrors 150, 160 and 170, creating the risk that external interference may reset the output signal POR high, causing a POR failure.

[0042] To avoid such failures and to make the POR circuit robust against substrate currents and against the above-mentioned external shocks, compensation transistors 180, 190 are provided. The compensation transistor 180 is connected to the collector of the transistor 120 and to the ground potential terminal 101. In the embodiment shown, the compensation transistor 180 is connected to the one of the transistors 110, 120 having the smaller collector area, the transistor 120 having a collector area of ​​1 unit compared to the transistor 110 having a collector area of ​​1 unit or more, for example 4 units. A situation may arise where the compensation transistor 180 is connected to another transistor having a larger collector area, such as the transistor 110. The compensation transistor 190 is connected between the output terminal 103 and the reference potential terminal 101. At the same time, the compensation transistor 190 is connected in parallel to the output path of the third current mirror 170, such as the transistor 172. The compensation transistors 180, 190 are determined so that the total contributions of the parasitic pull-up and pull-down currents at the output terminal 103 are substantially the same so that they are equal to each other and avoid the tendency of the POR output signal towards the supply voltage or the reference voltage. The compensation transistors 180, 190 are designed to compensate for the above-mentioned asymmetry created by the substrate currents of the bipolar transistors of the bandgap circuit with respect to the output signal POR at the terminal 103. The arrangement of doping regions shown in FIG. 3 also corresponds to the compensation transistors 180, 190.

[0043] In one embodiment, the compensation transistors 180, 190 may comprise a substrate diode comprising an N-well doping region and a semiconductor substrate. In this regard, the transistors 180, 190 may be implemented as bipolar transistors with the base connected to the emitter. In the embodiment shown in FIG. 1, the transistor 180 is implemented as a bipolar transistor with the base terminal 181 connected to the emitter terminal 183, both connected to the ground potential terminal 101. Similarly, the transistor 190 is implemented as a bipolar transistor with the base terminal and the emitter terminal connected to each other and to the ground potential terminal 101. Furthermore, the collector areas of the compensation transistors 180, 190 are such that the contributions to the pull-up and pull-down currents at the output node 103 to external interference are substantially equalized. For the collector areas of transistors 110, 120 and the current conversion ratios of current mirrors 150, 160, 170 as described above, it is useful to have a collector area of ​​N3 of 1 unit for compensation transistor 180 and a collector area of ​​N4 of compensation transistor 190 of 1 unit. Compensation transistors 180, 190 are bipolar transistor units and therefore matched to the transistor units forming transistors 110, 120. The above-mentioned transistors 180, 190 are realized as substrate diodes using bipolar transistors with shorted base terminals and are in the off state during normal operating mode, so they do not contribute to the current consumption during normal operation. They only pass substrate current during external interference, so their current consumption is negligible.

[0044] In case of external interference, the collector of transistor 110 generates a parasitic substrate current IDN1. The joint collector of transistors 120, 180 generates another substrate current IDN2. Transistor 190 generates another substrate current IDN3. The contribution of the parasitic substrate current IDN1 to the pull-up current IPU at the output terminal 103 is 4 / 3 current units, considering that the collector area of ​​transistor 110 is 4 units and the current mirror ratio of current mirror 150 is 3:1. The contribution of the parasitic currents IDN2, IDN3 to the pull-down current at the output terminal 103 is (1+1) / (6x1)+1=4 / 3, considering that the collector areas of transistors 120, 180 are 1 unit each, the mirror ratio of current mirror 160 is 6:1, the mirror ratio of current mirror 170 is 1:1, and the collector unit of transistor 190 is 1. Thus, the contributions of the pull-up and pull-down currents at output terminal 103 to the parasitic substrate current in the circuit of FIG. 1 are 4 / 3 in each case, thereby being equalized.

[0045] More generally, for any collector area of ​​the bipolar transistors, and any current ratio of the current mirrors, transistors 110, 120, 180, 190 having collector areas of N1, N2, N3, N4, respectively, and current mirrors 150, 160, 170 having current conversion ratios of M1:1, M2:1, M3:1, respectively, the area and ratio values ​​should obey the following equation such that the pull-up and pull-down contributions of the substrate current at output terminal 103 are equal: N1 / M1=(N2+N3) / (M2×M3)+N4

[0046] The POR circuit of FIG. 1 according to the principles of the present disclosure may be useful in connection with integrated circuits targeted for industrial, automotive, or photovoltaic applications, as will be described with reference to FIG.

[0047] 4 shows an integrated circuit 400 having the POR circuit 410 of FIG. 1 generating a POR signal to control a power-on reset of a circuit portion 420 monolithically integrated on the same chip 400. The circuit portion 420 has a photodiode 421 and a pad area 422 to which an electrostatic discharge (ESD) structure 423 is connected. The circuit portion 420 may include only one of the elements, such as the photodiode 421 or the pad / ESD structure 422, 423, as shown in FIG. 4, or may include both of them.

[0048] The photodiode 421 generates a current in response to the incidence of optically visible and / or invisible light, including infrared or UV light. Photodiodes are often implemented for backside illumination, where light incident from the backside of the chip generates a photocurrent. Stray light may also be incident on the backside of the POR circuit portion 410 and generate a parasitic photocurrent via a parasitic substrate diode that may act parasitically as a photodiode. The POR circuit 410 of FIG. 1 is robust against the generation of substrate current due to the above stray light in that the contribution of the substrate current to the switching point is symmetrical and the trip point of the signal POR at the output terminal 103 is compensated to remain unchanged.

[0049] Use of the chip 400 in an industrial or automotive environment may require the chip to operate under high temperature conditions or be exposed to electromagnetic interference (EMI) events. High temperatures may increase leakage currents through parasitic substrate diodes. The EMI events may affect ESD structures 423, which may be connected to pad regions 422. The pad regions 422 are externally accessible metal regions provided on the top surface of the chip so that bond wires 424 can be attached to the pad regions 422. The pad regions 422 and / or bond wires may have the function of a parasitic antenna in the event of an EMI impulse, such that the ESD structures 423 dump parasitic EMI signals to ground. The ESD structures 423 may include doped regions, such as 320 shown in FIG. 3, designed to dump relatively large EMI energy. In this case, a parasitic lateral transistor, such as 340 shown in FIG. 3, may generate a lateral substrate current 342. The POR circuit 410 of FIG. 1 is robust to high temperature and EMI conditions because it compensates and equalizes parasitic substrate currents in the POR circuit without changing the trip point of the POR output signal.

[0050] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present disclosure as set forth in the appended claims. Since modifications, combinations, subcombinations and variations of the disclosed embodiments incorporating the spirit and substance of the present disclosure may occur to those skilled in the art, the present disclosure should be construed as including all within the scope of the appended claims.

Claims

1. A terminal (101) for a reference potential (VSS) and a terminal (102) for a supply potential (VDD); a voltage divider (130) connected between the terminal for the reference potential (VSS) (101) and the terminal for the supply potential (VDD) (102); a first transistor (110) and a second transistor (120) each having a base connected to said voltage divider (130), an emitter resistively coupled to said terminal for reference potential (VSS) (101), and a collector connected to said terminal for supply potential (VDD) (102); a first current mirror (150) having an input path connected to the collector of the first transistor (110) and an output path connected to an output terminal (103), the output terminal being configured to provide an output signal (POR) in response to a voltage between the terminal for reference potential (VSS) (101) and the terminal for supply potential (VDD) (102); a second current mirror (160) and a third current mirror (170), the second current mirror (160) being connected to the output terminal (103) via an input path connected to the collector of the second transistor (120) and an output path of the third current mirror (170); a first compensation transistor (180) connected between the collector of one of the first and second transistors (120) and the reference potential (VSS) terminal (101); a second compensation transistor (190) connected between the output terminal (103) and the reference potential (VSS) terminal (101); Equipped with The first compensation transistor (180) and the second compensation transistor (190) each comprise a bipolar transistor having a base, a collector, and an emitter, the base being connected to the emitter; the collectors of the first transistor (110) and the second transistor (120) each have a collector area, the collector area of ​​the first transistor (110) being a multiple of the collector area of ​​the second transistor (120); The collector of the first compensation transistor (180) is connected to the collector of the second transistor (120), and the base and emitter of the first compensation transistor are connected to the reference potential (VSS) terminal (101); The collector of the second compensation transistor (190) is connected to the output terminal (103), and the base and the emitter of the second compensation transistor (190) are connected to the terminal for reference potential (VSS) (101); A power-on reset circuit, wherein the collector areas of the first compensation transistor (180) and the second compensation transistor (190) are such that their contributions to the pull-up current (IPU) and the pull-down current (IPD) at the output terminal (103) are substantially equalized in the event of external interference.

2. 2. The power-on reset circuit of claim 1, wherein the input path of the first current mirror (150) includes a diode-connected transistor (151) connected to the collector of the first transistor (110) and to the terminal for the supply potential (VDD), and the output path of the first current mirror (150) includes a transistor (152) having a control terminal connected to a control terminal of the transistor (151), and a first current mirror (150) output path, the transistor (152) of the output path being connected between the output terminal (103) and the terminal for the supply potential (VDD).

3. the input path of the second current mirror (160) includes a diode-connected transistor (161) connected to the collector of the second transistor (120) and to the terminal (102) for the supply potential (VDD), and the output path of the second current mirror (160) includes a transistor (162) having a control terminal connected to a control terminal of the transistor (161) of the input path of the second current mirror (160); the input path of the third current mirror (170) includes a diode-connected transistor (171) connected to the collector of the transistor (162) in the output path of the second current mirror (160); the output path of the third current mirror (170) includes a transistor (172) having a control terminal connected to a control terminal of the transistor (171) of the input path of the third current mirror (170); 3. The power-on reset circuit of claim 1, wherein the transistor (172) of the output path of the third current mirror (170) has a collector connected to the output terminal (103) and an emitter connected to the terminal (102) for the reference potential (VSS).

4. 4. The power-on reset circuit of claim 3, wherein the base-collector path of the second compensation transistor (190) is connected in parallel with a transistor (172) in the output path of the third current mirror (170).

5. The first transistor (110) has a collector area of ​​N1 units, the second transistor (120) has a collector area of ​​N2 units, the first compensation transistor (180) has a collector area of ​​N3 units, the second compensation transistor (190) has a collector area of ​​N4 units, the first current mirror (150) has a current conversion ratio of M1:1, the second current mirror (160) has a current conversion ratio of M2:1, and the third current mirror (170) has a current conversion ratio of M3:1, the collector areas and the current conversion ratios being expressed by the following equations: N1 / M1=(N2+N3) / (M2×M3)+N4 5. The power-on reset circuit according to claim 3.

6. 6. The power-on reset circuit of claim 1, wherein a collector area ratio between the first transistor (110) and the second transistor (120) is 4:1, a current conversion ratio of the first current mirror (150) is 3:1, a current conversion ratio of the second current mirror (160) is 6:1, a collector area ratio between the second transistor (120) and the first compensation transistor (180) is 1:1, and a collector area ratio between the second transistor (120) and the second compensation transistor (190) is 1:

1.

7. 7. The power-on reset circuit according to claim 1, wherein the first and second transistors (110, 120) are bipolar transistors and the transistors (151, 152, 161, 162, 171, 172) of the first, second and third current mirrors (150, 160, 170) are field effect transistors.

8. 8. The power-on reset circuit according to claim 1, further comprising a voltage divider (140) comprising a resistor (141) connected to the emitter of the first transistor (110) and another resistor (142) connected to the terminal for reference potential (VSS), and the emitter of the second transistor (120) is connected to a node located between the resistors (141, 142) of the voltage divider (140).

9. a semiconductor substrate (300) of a first conductivity type (P), the semiconductor substrate (300) having a deep well (311) of a second conductivity type (N) different from the first conductivity type (P), the deep well (311) forming the collector of at least one of the first and second transistors (110, 120); a doped region (320) of the second conductivity type (N) disposed within the semiconductor substrate (300), 9. The power-on reset circuit according to claim 1.

10. 10. The power-on reset circuit of claim 9, wherein the power-on reset circuit is disposed within an integrated circuit (400), and the doped regions (320, 423) are connected to terminals (422) of the integrated circuit configured to receive or transmit external signals.

11. a circuit portion (420) having at least one photodiode (421) and configured to operate in response to an optical signal received by said at least one photodiode (421); A power-on reset circuit (410) according to any one of claims 1 to 10, comprising: a power-on reset circuit (410) configured to be enabled by an output signal (POR) of the power-on reset circuit (410) depending on a voltage between the terminal (101) for the reference potential (VSS) and the terminal (102) for the supply potential (VDD); An optoelectronic integrated circuit (400).

12. a circuit portion (420) having at least one pad area (422) configured to receive and / or transmit an external electrical signal and an electrostatic discharge structure (423) connected to said pad area (422), said electrostatic discharge structure (423) having a doped region (320) connected to said pad area (422) and disposed on a substrate (300) of the integrated circuit (400); A power-on reset circuit (410) according to any one of claims 1 to 10, wherein the circuit portion (420) is configured to be enabled by an output signal (POR) of the power-on reset circuit (410) depending on a voltage between the terminal (101) for the reference potential (VSS) and the terminal (102) for a supply potential (VDD). An integrated circuit (400).

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