Method, device and system for including alternative memory access operations through a memory interface - Patents.com

Abstract

To provide a method, a memory device, and a system that satisfy the requirement for a fast initial response (i.e., boot) system and at the same time provide a memory device with a fast interface speed.SOLUTION: A method decodes command data received on a one-way command address (CA) bus of a memory interface in a default mode of a memory device according to a first standard. In response to a mode enter command, the method places the memory device into an alternate management mode, receives alternate command data on the CA bus, decodes the alternate command data according to a second standard, executes the alternate command, and returns the memory device to the default mode in response to decoding mode exit commands received on the CA bus according to the first standard. The memory interface comprises a CA bus and a data bus, and the CA bus and data bus comprise multiple parallel input connections.SELECTED DRAWING: Figure 23

Description

[Technical Field]

[0001] The present disclosure relates generally to memory devices and systems, and more particularly to memory devices and systems having a command-address bus and a data bus. [Background technology]

[0002] Some memory device applications require non-volatility as well as fast access speeds, especially read access. While high-speed interfaces exist, such as those described in JEDEC standard JESD209-4D (i.e., LPDDR4), these interfaces do not support many nonvolatile memory (NVM) operations. To address these requirements, memory devices can include two interfaces. As just one example, a conventional NVM device can include an established NVM serial interface (e.g., Serial Peripheral Interface, SPI) in addition to an LPDDR4-compatible interface. This type of dual-interface device allows for high-speed read operations via the LPDDR4 interface while also allowing NVM operations (e.g., program, erase, read, Serial Flash Discovery Protocol (SFDP) register access, and Secure Silicon Register (SSR) access) through the SPI interface.

[0003] The JEDEC standard JESD209-2F (i.e., LPDDR2) includes the ability to use an "overlay window" that allows memory addresses to overlap an existing array area with a target register in the memory device. Therefore, when write data is written to this type of overlay window, the write data can be redirected, for example, to a mode register. However, write operations through an LPDDR2 / 4 interface require read / write training before a read or write operation. This type of read / write training can include write training. Write training requires a certain amount of time (e.g., >200 ms). The involvement of this type of write training time is incompatible with applications that require the bus to be available within a relatively short period of time. As two of many possible examples, some versions of the Controller Area Network (CAN) bus may require the bus to be operational within 50 ms, and some IEEE 802.11 standards (i.e., Ethernet) may require the bus to be operational in less than 200 ms. Therefore, if data needs to be read from or written to (e.g., programmed into) a memory device for the first time in a relatively short amount of time, conventional LPDDR4-only devices are not suitable.

[0004] While dual-interface memory devices (e.g., LPDDR2 / 4 and SPI) can meet the requirements for this type of fast boot, this type of memory device is not without drawbacks. A system with a host and a dual-interface memory device must include two buses, two controllers, and two memory mappings. Two buses may require more interface pins than a single-interface memory device. Two controllers may require valuable device area to accommodate logic circuits and may require two separate software stacks to execute commands received through the different interfaces (i.e., commands of two different standards). Two memory mappings may arise because the command address format may change between the two standards.

[0005] It would be desirable to arrive at some way to provide memory devices with fast interface speeds while meeting the demands of fast initial response (ie, boot) systems. Summary of the Invention [Means for solving the problem]

[0006]

[0005] Embodiments may include a memory device having an interface and a memory controller circuit. The interface may include a unidirectional command and address (CA) bus and a data bus. The memory controller circuit may have a default mode of operation in which command data is received on the CA bus and decoded according to a first standard. In response to decoding a mode enter command, the memory device may be placed in an alternate management mode. In the alternate management mode, alternate command data may be received on the CA bus. In response to a command execution instruction, the alternate command data may be decoded according to a second standard to execute the alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, the memory device may be returned to the default mode. Corresponding methods and apparatus are also disclosed.

[0007] In some embodiments, write or read operations can occur on the CA bus, while read operations can occur but not write operations can occur on the data bus. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a memory device according to one embodiment. [Figure 2] FIG. 2 is a timing diagram illustrating memory device operation according to one embodiment. [Figure 3A] FIG. 10 is a block diagram of a memory device according to another embodiment. [Figure 3B] FIG. 2 illustrates a memory device address space according to one embodiment. [Figure 4] 4 is a state diagram of a memory device operation according to an embodiment. [Figure 5] FIG. 10 is a timing diagram illustrating a memory device entering an alternate management mode according to one embodiment. [Figure 6A]FIG. 10 illustrates possible LPDDR4 format commands that can place a memory device into an alternate management mode, according to an embodiment. [Figure 6B] FIG. 10 illustrates possible LPDDR4 format commands that can place a memory device into an alternate management mode, according to an embodiment. [Figure 6C] FIG. 10 illustrates possible LPDDR4 format commands that can place a memory device into an alternate management mode, according to an embodiment. [Figure 6D] FIG. 10 illustrates possible LPDDR4 format commands that can place a memory device into an alternate management mode, according to an embodiment. [Figure 6E] FIG. 10 illustrates possible LPDDR4 format commands that can place a memory device into an alternate management mode, according to an embodiment. [Figure 7] FIG. 10 illustrates possible LPDDR4 commands that can place a memory device into an alternate management mode, according to an embodiment. [Figure 8] FIG. 10 is a timing diagram illustrating alternate command data received over a command address (CA) bus according to one embodiment. [Figure 9] FIG. 10 is a timing diagram illustrating alternative command data received as data packets over the CA bus according to one embodiment. [Figure 10] FIG. 1 is a diagram of a conventional system that utilizes an overlay state to write command data to a register of a memory device. [Figure 11] FIG. 1 is a diagram of a system and operation according to one embodiment. [Figure 12] FIG. 10 is a diagram of a system and operation according to another embodiment. [Figure 13] FIG. 10 is a diagram of a system and operation according to a further embodiment. [Figure 14] FIG. 10 is a diagram of a system and operation according to a further embodiment. [Figure 15] FIG. 1 illustrates processing of alternate command data in a memory device according to an embodiment. [Figure 16] FIG. 1 illustrates processing of alternate command data in a memory device according to an embodiment. [Figure 17] FIG. 1 illustrates processing of alternate command data in a memory device according to an embodiment. [Figure 18] FIG. 2 illustrates the processing of program data in a memory device, according to an embodiment. [Figure 19] FIG. 1 is a diagram of a memory cell array that can be included within an embodiment. [Figure 20] FIG. 1 is a diagram of an integrated circuit device according to one embodiment. [Figure 21] FIG. 2 is a block diagram of a host device according to one embodiment. [Figure 22] FIG. 1 is a diagram of an automobile system according to an embodiment. [Figure 23] FIG. 2 is a flow diagram of a method according to one embodiment. [Figure 24] FIG. 10 is a flow diagram of a method according to another embodiment. [Figure 25] FIG. 6 is a flow diagram of a method according to a further embodiment. [Figure 26] FIG. 10 is a flow diagram of a method according to another embodiment. [Figure 27] FIG. 10 is a flow diagram of a method according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiments may provide a memory device having a single interface that conforms to an existing standard, allowing for fast access (e.g., reads) to memory locations. In response to predetermined inputs through the interface, the memory device may be placed into an alternate control mode, in which additional capabilities (i.e., capabilities not supported by the existing standard) may be mapped to inputs at the interface.

[0010] In some embodiments, the existing interface can be compatible with one or more LPDDR standards (e.g., LPDDR2 / 4), and in an alternate control mode, the additional capability can be serial interface commands (e.g., SPI) that are mapped to the LPDDR inputs. This type of configuration allows the NVM device to provide LPDDR functionality and serial port access functionality through one interface.

[0011] In some embodiments, accesses in the alternate control mode may include write operations that can be performed without requiring write training of the data (DQ) bus, thus allowing the device to meet fast boot time requirements. In some embodiments, write data may be received on the CA bus but not on the data bus.

[0012] In some embodiments, additional functionality can be mapped to an existing interface by register operations on any suitable memory and / or CA bus. In some embodiments, this can include using mode register transactions that are compatible with existing standards. Existing standards for interfaces (e.g., LPDDR4) can map transactions to a predefined register address space. According to embodiments, additional mode registers can be added (i.e., beyond those defined by the standard), and such additional mode registers can be accessed in additional capabilities.

[0013] In some embodiments, the interface may be compatible with the LPDDR4 standard. The host system may use any suitable method to enter the alternate control mode, including, but not limited to, a read command to a predetermined address (which may not be a valid location in the memory cell array), a multipurpose command (MPC), a mode register write (MRW) command, or even a mode register read (MRR) command.

[0014] In some embodiments, when the memory device is in the alternate control mode, the mode register space can be repurposed to access additional registers used in embedded operations. Such extended mode registers can implement command-based protocols such as legacy SPI transactions and / or packet-based protocols. In the alternate control mode, standard (legacy) MPC / MRR / MRW operations are disabled, and any appropriate memory and / or register accesses are also performed using the MPC / MRR / MRW functions. When the memory device exits the alternate control mode, such standard (legacy) MPC / MRR / MRW operations can be re-enabled.

[0015] In the described embodiment, similar items are referred to by reference numbers that have the same reference number but whose first digit corresponds to the drawing number.

[0016] 1 is a block diagram of a memory device 100 according to one embodiment. The memory device 100 may include an interface 102, a controller circuit 104, and one or more memory cell arrays 106. The interface 102 may include a unidirectional CA bus, a clock (CLK) input, and a bidirectional data bus (DQ). Both the CA bus and the DQ bus may be multiple bit buses. The memory cell array 106 may include memory cells for storing data, including non-volatile memory cells, volatile memory cells, and combinations thereof.

[0017] The controller circuit 104 can control the operation of the memory device 100, including a default mode 108 and an alternate mode 110. The memory device 100 can begin operation in the default mode 108. In the default mode 108, the controller circuit can decode command and address data received on the CA bus according to a default standard to enable access to the memory cell array 106. However, certain commands that are decoded according to the default standard can place the memory device into an alternate operating mode 110.

[0018] In the alternate mode 110, command and address data received at the interface 102 can be decoded according to a second standard that differs from the default standard. As a result of the alternate mode 110, command data can be received and stored differently than in the default mode. Additionally, command bit values ​​for various memory access functions can differ from the default mode. In some embodiments, in the alternate mode 110, data (e.g., write data) can be transferred on the CA bus rather than on the DQ bus. Additionally or alternatively, in the alternate mode, command data can be stored differently (e.g., in a particular register or buffer) than in the default mode. During the alternate mode, the controller circuit 104 can continue to decode command and address data according to the default standard and can return the memory device to the default operating mode in response to receiving a particular command.

[0019] Note that during the default mode 108, the controller circuit 104 may disable decoding according to the second standard.

[0020] In some embodiments, the first standard can correspond to a parallel data interface, and the second standard can provide functionality for another interface or standard. In some embodiments, this can be functionality for a serial data interface. The first or second standard can identify command values ​​and corresponding data and can also identify how such commands are processed. The first or second standard may or may not be a standard promulgated by a standards organization. For example, the first standard can be a DDR standard, such as the LPDDR4 standard.

[0021] In this manner, by operation of one or more commands, memory device 100 can be switched from a default operating mode to an alternate operating mode, in which different types of communication channels can be provided to the memory device over the same interface.

[0022] 2A and 2B are timing diagrams illustrating various memory device operations according to embodiments, showing waveforms for a timing clock (CLK), a unidirectional CA bus (CA), and a data bus (DQ).

[0023] 2A illustrates the operation of alternate modes that allow commands and data values ​​to be received on the CA bus. Referring to FIG. 2A, it is assumed that prior to time t0, the memory device is in a first mode of operation decoding command, address, and data according to a first standard (Standard 1).

[0024] At time t0, a command can be received on the CA bus. The command can include bit values ​​indicating the type of command as well as other bits (i.e., arguments, addresses) that specify how the command is to be executed. This type of command and associated data can be decoded according to a first standard and indicate a switch to an alternate mode. In response, the memory device can enter the alternate mode, which allows for a different communication channel, capable of decoding data received according to a second standard (Standard 2).

[0025] At time t1, once the memory device is in the alternate mode, the memory device can receive alternate command data on the CA bus. Note that the alternate command data can include a bit value indicating the alternate command as well as associated data. For example, if the alternate command is a write operation (e.g., to an array or register), it can include write data. Note that in the illustrated embodiment, this type of data is not provided on the DQ bus. The alternate command can be decoded according to a second standard to determine the type of memory device operation to be performed. In the illustrated embodiment, the alternate command and any associated data can be received at a single data rate (e.g., a parallel data bit set is received once per CLK cycle on the CA bus). In some embodiments, the DQ bus can be a unidirectional bus that provides output data from the memory device but does not receive input data for the memory device.

[0026] At time t2, another command may be received on the CA bus. This type of command may be decoded according to the first standard and indicate an exit from the alternate mode. In response, the memory device may return to the first operating mode. This may disable the alternate communication path provided in the alternate mode. That is, received values ​​are no longer processed according to the second standard.

[0027] In this manner, the memory device can be placed into an alternate mode in which commands (with arguments and / or data) can be received on the CA bus and decoded according to an alternate standard.

[0028] 2B illustrates operations in which data writing can include receiving write data on the CA bus in an alternate mode and providing read data on the DQ bus in a first mode. Figure 2B can generally follow the operations described in Figure 2A, but can differ in the following respects.

[0029] At time t1, once the memory device is in the alternate mode, the memory device can receive an alternate command on the CA bus, which is decoded into a write command having a corresponding write address and write data according to an alternate protocol. Such alternate write command and write data can be received at a single data rate (SDR). As a result of the write command, the write data can be written to the memory device.

[0030] At time t2, the memory device exits the alternate mode.

[0031] At time t3, once the memory device returns to the first mode, the memory device can receive a command on the CA bus, which is decoded according to the first standard as a read command with a corresponding read address.

[0032] At time t4, in response to the read command, read data can be output on the DQ bus. In the illustrated embodiment, such read data can be output at double data rate (DDR).

[0033] In this manner, the memory device is switchable from a first mode to an alternate mode in which write operations (e.g., write commands and write data) can occur on the CA bus at a single data rate relative to the timing clock. In the first mode, read operations can occur with read commands received on the CA bus and read data output on the DQ bus at double data rate relative to the timing clock.

[0034] 3A is a block diagram of a memory device 300 according to another embodiment. The memory device 300 may be a non-volatile memory device having an LPDDR4 interface (IF) 302, a controller circuit 304, a non-volatile memory cell array 306, and a register 312. The LPDDR4 IF 302 may have inputs / outputs (IOs) compatible with JEDEC standard JESD209-4D. Such IOs may include, but are not limited to, complementary clock inputs (CK_t, CK_c), a clock enable input (CKE), a chip select input (CS), a CA bus (CA[5:0]), complementary data strobes (DQS_t, DQS_c), a data bus DQ, and a data mask / inverted IO (DMI).

[0035] The controller circuit 304 can process transactions through the LPDDR4 IF 302 in accordance with the LPDDR4 standard. In addition, however, the controller circuit 304 can also include an alternate mode 310 in which data values ​​received through the LPDDR4 IF 302 are decodable according to a second standard 314 that, in some embodiments, can provide the functionality of the SPI standard. That is, bit values ​​of the received data are decodable as commands of a different standard (i.e., rather than LPDDR4 commands). The controller circuit 304 can be placed into the alternate mode in any suitable manner, including, but not limited to, the specific LPDDR4-type commands and equivalents described herein.

[0036] The registers 312 may include additional registers used to receive data in alternate modes of operation, such as a mode register, in some embodiments, the registers 312 may include a mode register compatible with the LPDDR4 standard.

[0037] The nonvolatile array 306 may include one or more memory cell arrays capable of storing data in the absence of power. A write operation may include programming the memory cells. The nonvolatile memory cells may include any suitable technology, including those relying on charge storage (e.g., EPROM, EEPROM, flash EEPROM), ferroelectric, magnetoresistive, phase change, and oxidation-reduction with the application of an electric field. The memory cell arrays may have any suitable organization, including NOR and NAND types.

[0038] In this manner, the non-volatile memory device may include an LPDDR4-compatible interface capable of executing LPDDR4 commands as well as alternate commands when alternate modes are enabled. In some embodiments, such alternate commands may provide functionality of other standards (e.g., SPI).

[0039] Figure 3B is a diagram similar to Figure 3A illustrating a device address space 316 for one embodiment. The device address space 316 can include a memory array region 316-0 accessible by array read and write operations, an identification register 316-1, a Serial Flash Discoverable Parameter (SFDP) register 316-2, a Secure Silicon Register (SSR) 316-3, and a mode register 316-4.

[0040] According to an embodiment, memory accesses and / or register accesses can cause the memory device to enter an alternate mode. Memory accesses and / or register accesses can also cause the memory device to exit an alternate mode. In the illustrated embodiment, an LPDDR4 read command (318-0) addressed to memory array address space 316-0 can read stored data. Additionally, an LPDDR4 array read and / or write command (318-1) to mode switch address space 316-0a can cause the memory device to enter / exit an alternate mode. Similarly, an LPDDR4 register read and / or write command (318-2) can cause the memory device to enter / exit an alternate mode.

[0041] Still referring to FIG. 3B, when the device is in alternate mode, array locations can be written to by alternate write (e.g., program) commands 318-3 received through the LPDDR4 interface. This type of alternate write command can provide the same functionality as an SPI write command. In alternate mode, registers (316-1, 316-2, 316-3, and 316-4) are accessible by alternate register read / write commands 318-4 embedded within commands received through the LPDDR4 interface. Note that in some embodiments, the register space accessed by the alternate register read / write can be larger than that accessed by the LPDDR4 register read / write.

[0042] In this manner, a portion of the memory device address space can be dedicated to commands compatible with the first standard that enable the memory device to enter and exit an alternate mode of operation in which memory device operation is controllable by commands that provide the same functionality as the second standard.

[0043] In this way, the functionality of the second standard (eg, SPI) can be mapped to the interface of the first standard (eg, LPDDR4) using the existing first standard infrastructure.

[0044] FIG. 4 is a state diagram 400 of memory device operation according to one embodiment. Memory device operation can include conventional actions compatible with the first standard (e.g., LPDDR4), including power on or reset to enter an idle state. From the idle state, the memory device can enter a training state (MPC Train 423), a mode register write (MRW), a mode register read (MRR), or a CA bus training state (CA Bus Train) via a multi-purpose command. Using an activate command (ACT), the memory device can activate a bank (Bank Active) and execute a read (LPDDR4 Read) command. In some embodiments, MPC training may not include write training, allowing the memory device to have a relatively fast initial power on / reset time.

[0045] 4, in response to one or more specialized commands 422, the memory device can enter (Alt_Mode_Enter) or exit (Alt_Mode_Exit) an alternate management mode 424. The specialized commands 422 can take any suitable form, and in the illustrated embodiment, can include one or more commands compatible with the first standard, including, but not limited to, a special array read command (LPDDR4 Read), a special MRR command, or a special MRW command. Such commands can be “special” in that they can include involving addresses and / or arguments that are not otherwise assigned or valid according to the first standard.

[0046] In the alternate mode 424, the memory device can enter a mode management state 424-0 in which the memory device can be controlled by alternate access. In the illustrated embodiment, the alternate access can include alternate access via a register access operation 424-2 and / or alternate access via a packet access operation 424-1. In some embodiments, the register access operation 424-2 can include a register operation (e.g., MRW, MRR) according to a first standard that transfers data to and / or from the memory device, where the transferred data includes command data having addresses and / or arguments according to another standard (e.g., SPI). In some embodiments, the packet access operation 424-1 can include receiving a packet, parsing the packet, and determining an operation to be performed. This type of packet processing can determine command data having addresses and / or arguments according to another standard (e.g., SPI).

[0047] In this manner, the memory device may include logic that enables it to transition to an alternate management state upon receipt of a specialized command through the interface, in which memory device operation is controllable by an alternate set of instructions received through the same interface.

[0048] Figure 5 is a timing diagram illustrating how an LPDDR4 compatible memory device can be placed into an alternate management mode. Figure 5 includes waveforms for the timing clock (CK_t), chip select signal (CS), CA bus (CA), a description of the command or operation to be performed (Command / Operation), and data bus (DQ).

[0049] At time t1, the memory device may receive a "mode enter" command pair (Cmd-1 / Cmd-2) that may place the device into an alternate mode or equivalent described herein. In some embodiments, the command pair (Cmd-1 / Cmd-2) may have an LPDDR4 format, with each command being received over two clock cycles.

[0050] At time t3, after receiving a mode enter command (Cmd-1 / Cmd-2), the memory device can switch to an alternate mode, allowing access (ACCESS NOVO, i.e., access to non-volatile) using an alternate communication method / path. This type of alternate communication can occur on the CA bus. In some embodiments, some delay (tsw-alt) can exist between receiving the mode switch command (Cmd-1 / Cmd-2) and the ability to perform operations in the alternate mode. However, in other embodiments, the alternate communication can include a continuous sequence of values ​​on the CA bus.

[0051] Optionally, a mode enter command pair may occur after an activate command (Activate1 / Activate2). This type of optional configuration is illustrated in FIG. 5 by the activate commands (Activate1 / Activate2) occurring at time t0. In some embodiments, the mode enter commands (Cmd-1 / Cmd-2) can be issued after a minimum delay (e.g., tRCD) after ACT1 / ACT2. However, it should be understood that embodiments contemplate the ability to enter an alternate mode without a preceding activate command.

[0052] It should also be understood that the timing presented in Figure 5 can be used for mode exit commands (i.e., command pairs that bring the memory device out of an alternate mode) as well. Additionally, although Figure 5 illustrates entering or exiting an alternate mode with a command pair, other embodiments may enter and / or exit an alternate mode in response to receiving a single command (i.e., Cmd-1 alone or Cmd-2 alone).

[0053] In this manner, LPDDR4 commands can be used to enter and exit alternate modes in which the memory device can be controlled by one or more other sets of commands received over the same LPDDR4 interface.

[0054] 6A-6E illustrate command pairs that can be used to enter and / or exit alternate modes. The command pairs may be compatible with the LPDDR4 format, but may include arguments not defined by the standard in its current form.

[0055] FIG. 6A shows an array read command pair for entering or exiting an alternate mode. Various bit values ​​"H," "L," "BL," and "AP" can define the command as a read command. An argument bit value denoted as "V" can indicate that the command is a mode enter or mode exit command. In some embodiments, the bit value "V" can represent an undefined value or can be a defined value (i.e., replaces an existing command) according to the LPDDR4 standard.

[0056] Figure 6B shows an array write command pair for entering or exiting an alternate mode, the format of which can be understood from the description of Figure 6A.

[0057] FIG. 6C shows a mode register write command pair for entering or exiting an alternate mode. Various bit values ​​"H," "L," "BL," and "AP" can define the command as a mode register write command. Argument bit values ​​"Op0:Op7" can indicate that the command is a mode enter command or a mode exit command. In some embodiments, the bit values ​​"Op0:Op7" can exhibit undefined values ​​or can be defined values ​​(i.e., replace an existing command) according to the LPDDR4 standard.

[0058] Figure 6D shows a Mode Register Read command pair for entering or exiting an Alternate Mode, the format of which can be understood from the description of Figure 6A.

[0059] Figure 6E shows a general-purpose command pair for entering or exiting an alternate mode, the format of which can be understood from the description of Figure 6A.

[0060] In this manner, a memory device can be placed into an alternate mode of operation using commands that are compatible with existing standards (e.g., LPDDR4). As noted above, in some embodiments, a single command (as opposed to a command pair) can result in the memory device entering / exiting an alternate mode.

[0061] 7 is a diagram showing other possible commands that can be used to enter or exit an alternate mode. The commands shown may be compatible with the LPDDR4 format, but may occupy command space (bit combinations) that are not currently defined by the standard. The format of the commands shown in FIG. 7 can be understood from the description of FIG. 6A.

[0062] In this way, an alternate mode can be entered or exited using a combination of command bits in the unused command space.

[0063] 8 and 9 are timing diagrams illustrating alternate path communication on the CA bus according to embodiments. Figures 8 and 9 include waveforms for the clock signal (CK), chip select signal (CS), CA bus inputs (CA0 through CA5), and data IO (DQ). In some embodiments, the operation of Figures 8 and 9 is compatible with an LPDDR4 interface.

[0064] 8 illustrates operations in which a memory device can receive an alternate command (and associated data) on the CA bus. Initially, the memory device can be placed into an alternate mode 826. Such actions can include any suitable command input or equivalent described herein.

[0065] After entering alternate mode 826, alternate mode data 828A can be received on the CA bus (CA0 to CA5). The alternate mode data 828A can include command data and optionally additional data, such as argument data and / or address data. In some embodiments, the alternate mode data 828A can be compatible with other standards 830 and is reformatted for the CA bus. In the illustrated embodiment, the other standard can be the SPI standard, and the alternate data 828A can include SPI command bits (CMD[0] to CMD[7]) and corresponding argument or address data according to the command type.

[0066] FIG. 9 illustrates an operation in which a memory device can receive a data packet on the CA bus. The data packet can take any suitable form and can include a command and associated data. FIG. 9 illustrates receipt of packet data 832 on the CA bus. The packet data 832 can include a command value (OP[7:0]), a packet length value (PL[15:0]), packet data (PACKET DATA), and, optionally, error detection and / or correction data (ECC). Such packet values ​​can be received on the CA bus as alternate data 828B in an alternate mode of operation.

[0067] It should be understood that the alternative command data shown in Figures 8 and 9 is decoded and / or processed differently than in the default mode of operation.

[0068] In this way, when switched into an alternate mode of operation, the memory device can receive alternate command data on the CA bus.

[0069] To better understand the various features of the embodiments, a conventional overlay window operation is described. Figure 10 shows a conventional LPDDR4 system 1001 that can place an NVM device in an overlay mode, where data values, such as commands, can be included in NVM device registers by data write operations on DQ.

[0070] System 1001 can include a host device 1003 and a non-volatile memory (NVM) device 1007 that communicate over an LPDDR4 bus. Host device 1003 can include an LPDDR4 port 1005 and can issue LPDDR4 compatible commands to NVM device 1007. NVM device 1007 can include an LPDDR4 port 1009 and registers 1011.

[0071] FIG. 10 illustrates performing a program operation of NVM device 1007 using overlay mode. Because data is transferred on DQ, NVM device 1007 must first undergo training 1013, which can include read and write training. Write training can include receiving a sequence of commands and entering write training mode (1013-0). Once in write training mode, write and read operations can occur on the DQ bus (1013-1 and 1013-3). In response to such operations, timing adjustments can be made (1013-2). It should be understood that write training can include multiple iterations of write / read and adjustment operations (1013-0 / 1 / 2). As discussed above, this and other write training operations can require a significant amount of time (e.g., >200 ms).

[0072] After write training occurs, NVM device 1007 can be programmed with write overlay state 1023. A sequence of commands can enable the overlay state (1023-0). In the overlay state, NVM device 1007 can receive commands from host device 1003 to do the following: write a program command to register 1011-0 via the DQ bus (1023-1), write address data to register 1011-1 via the DQ bus (1023-2), and write program data to one or more registers 1011-2 via the DQ bus (1023-3). A program operation can then be initiated by writing command-go register 1011-3 via DQ (1023-4). After the program execute operation, device status register 1011-4 can be read (1023-5) to determine the status of the program operation. Such status data is readable on DQ. Next, a sequence of commands can disable the overlay state (1023-6).

[0073] Thus, overlay window operations require write training and provide data values ​​along with array write and read commands at predetermined addresses that may overlap existing array addresses.

[0074] 11 is a block diagram of a system 1130 and operation according to one embodiment. System 1130 may include an NVM device 1100 and a host device 1132 connected to each other by an LPDDR4-compatible bus. Host device 1132 may include a host LPDDR4 port 1134 that allows a host to send data over the LPDDR4 bus to an LPDDR4 port 1136 of NVM device 1100. NVM device 1100 may include registers 1138, a command decoder 1140, and a controller circuit 1142. NVM device 1100 may also include NV memory locations (not shown) accessible in alternate management modes. Registers 1138 may include registers accessible according to the existing LPDDR4 standard (i.e., mode registers) but may also include additional registers to provide a larger register space than dictated by the LPDDR4 standard.

[0075] FIG. 11 shows an NVM device 1100 that can be placed into an alternate management mode, which can execute alternate commands (i.e., non-LPDDR4 commands) for managing the NVM device via write operations to register locations on the NVM device.

[0076] Unlike conventional methods, such as the method of Figure 10, alternate mode operation can occur 1144 without write training. This can enable NVM device management operations (e.g., program) in applications where the device requires fast data input soon after power-up (e.g., boot operation), which may not be possible when write training is required.

[0077] In the illustrated embodiment, the host device 1132 can issue an MRW command in accordance with the LPDDR4 standard to place the NVM device 1100 in an alternate (management) state (1146-0). The alternate state can establish an alternate communication channel on the LPDDR4 bus, which allows the operation of the NVM device 1100 to be controlled by command data not included in the LPDDR4 standard.

[0078] The alternate NVM control command can be issued by a command sequence that can include LPDDR4 commands ACT1 / ACT2 / WRITE1 / CAS2, which can have a specialized argument bit to indicate alternate command 1146-1. In contrast to traditional overlay window methods, this type of command sequence may not involve data on the DQ bus. Alternate command 1146-1 can include any suitable NVM device management command, including array program, array erase, and register access, as a few of many possible examples. In response to alternate command sequence 1146-1, a command value can be stored in register 1138-0 of NVM device 1100.

[0079] In the illustrated embodiment, after the command data, a corresponding address value can be provided with a command sequence that can include the LPDDR4 commands ACT1 / ACT2 / WRITE1 / CAS2 (1146-2). In response, the address value can be stored in register 1138-1 of NVM device 1100.

[0080] In the illustrated embodiment, after the address value, corresponding data can be provided with an initial command sequence that can include LPDDR4 commands ACT1 / ACT2 / WRITE1 / CAS2 (1146-3). Additional data can be provided after the WRITE1 / CAS2 command. This type of data can be provided on the CA bus, the DQ bus, or a combination thereof. In response, the data value can be stored in one or more registers 1138-2 of the NVM device 1100. The data can accompany some alternative commands (e.g., array program, register write), while other alternative commands can include accompanying data (e.g., array read, register read).

[0081] In the illustrated embodiment, execution of the alternative command can be initiated by a command execution instruction. The command execution instruction can take any suitable form, and Figure 11 includes a command sequence that can include LPDDR4 commands ACT1 / ACT2 / WRITE1 / CAS2 (1146-4). As a result of such a sequence, a "command go" value can be stored in register 1138-3 of NVM device 1100.

[0082] In response to the command-go value being written into register 1138-3, command decoder 1140 can generate interrupt 1148-0. In response to interrupt 1148-0, controller circuit 1142 can access registers 1138-0 through 1138-2, call (1148-1) the indicated alternate command, and execute the alternate command.

[0083] After execution of the alternate command, the controller circuit 1142 may generate a state value in register 1138-4 that may indicate the result of the execution of the alternate command. Such state data may then be retrieved from the NVM device 1100 by a command sequence that may include the LPDDR4 commands ACT1 / ACT2 / READ1 / CAS2 (1146-5). In some embodiments, such state data may be transferred over the DQ bus.

[0084] When all desired alternate command operations have been performed, the alternate state may be exited with an MRW command (1146-6). NVM device 1100 may then interpret commands received from the host in accordance with the LPDDR4 standard.

[0085] In this way, a system having a host that communicates with an NVM device through a standardized interface can enable an alternate communication path to perform NVM device management functions not covered by the standard. This type of operation can be performed without write-discipline of the data bus.

[0086] FIG. 12 is a block diagram of a system 1230 and operation according to another embodiment. System 1230 may include items similar to those of FIG. 11. FIG. 12 may differ from FIG. 11 in that the NVM device may include a buffer 1250 that can store received data values ​​at addressable locations 1250-0 through 1250-3. Such locations are distinct from the NVM memory locations of NVM device 1200. Buffer 1250 may be formed by a memory circuit that offers faster read and write speeds than the main memory of NVM device 1200, such as, by way of example only, an SRAM.

[0087] FIG. 12 illustrates an NVM device 1200 that can be placed into an alternate management mode, in which the NVM device 1200 receives packet data that can include alternate commands for managing the NVM device.

[0088] As in FIG. 11, alternate mode operation can occur without write training (1244), and the host device 1232 can issue an MRW command to place the NVM device 1200 into the alternate state (1246-0).

[0089] Once in the alternate state, the host device 1232 can indicate a data packet transmission with a command sequence that can include LPDDR4 commands ACT1 / ACT2 / WRITE1 / CAS2 (1252-0). Such command sequences can include argument values ​​that can indicate the packet communication, including the size of the packet (PKT LEN). In response, packet capabilities can be stored in register 1238-0a of the NVM device 1200.

[0090] After the packet data write indication, packet data having a sequence of commands, which may be LPDDR4 compatible commands ACT1 / ACT2 / WRITE1 / CAS2 (1252-1), may be provided by host device 1232. In response, the packet data may be stored in buffer 1250 of NVM device 1100. The packet data may include data for executing an alternative command for the NVM device, and in the illustrated embodiment, may include a command, an address, and data.

[0091] In response to receiving the packet indication in register 1238-0a and / or the packet data in buffer 1250, command decoder 1240 can generate interrupt 1248-0. In response to interrupt 1248-0, controller circuit 1242 can analyze the packet data stored in buffer 1250 to determine an alternative command and corresponding values ​​(e.g., address and data). Such analysis can include accessing a particular address in buffer 1250. Such an address can be predetermined or can be indicated by the packet data in register 1238-0a. From analyzing the packet data, controller circuit 1242 can invoke (1248-1) the indicated command and execute the alternative command.

[0092] After execution of the alternate command, controller circuit 1242 can generate a state value in register 1238-4 or at a predetermined address 1250-3 of buffer 1250. Such state data can then be retrieved from NVM device 1100 by a command sequence that can include LPDDR4 commands ACT1 / ACT2 / READ1 / CAS2 (1246-5) addressed to the appropriate register or buffer address. In some embodiments, such state data can be transferred on the DQ bus.

[0093] When all desired alternate command actions have been performed, the alternate state may be exited with the MRW command (1246-6).

[0094] In this way, a system having a host that communicates with an NVM device through a standardized interface can enable an alternate communication path for receiving packet data, which can include NVM device management functions not covered by the standard. This type of operation can be performed without write training of the data bus.

[0095] 13 is a block diagram of a system 1330 and operation according to a further embodiment. The system 1330 can include items similar to those in FIG.

[0096] FIG. 13 illustrates an NVM device 1300 that can be placed into an alternate mode to receive command data through a sequence of register write operations.

[0097] As in Figure 11, alternate mode operation can occur without write training (1344). The host device 1332 can issue an MPC to place the NVM device 1300 in the alternate state (1358-0). This type of MPC can have arguments that are not defined by the current LPDDR4 standard and therefore can be considered a specialized MPC.

[0098] Once in the alternate state, the host device 1332 can perform MRW operations in accordance with the LPDDR4 standard to load alternate command data into NVM device registers 1338. In the illustrated embodiment, this type of action can include the following: an MRW can load register 1338-0 with alternate command data (e.g., an op code) (1356-0), one or more MRWs can load register 1338-1 with address data (e.g., array address, if appropriate for the command) (1356-1), and one or more MRWs can load register 1338-2 with data (e.g., program data, if appropriate for the command) (1356-2).

[0099] In the illustrated embodiment, execution of an alternative command can be initiated by the MRW to a "command go" type register 1338-3 of NVM device 1300. In response, command decoder 1340 can generate interrupt 1348-0, and the alternative command stored in registers 1338-0 through 1338-4 can be executed.

[0100] After execution of the alternate command, the controller circuit 1342 can generate a state value in register 1338-4, which can then be retrieved (1356-4) from the NVM device 1300 with a mode register read (MRR) command. In some embodiments, this type of state data can be transferred on the DQ bus.

[0101] When all desired alternate command actions have been performed, the alternate state can be exited by another specialized MPC (1358-1).

[0102] In this way, a system having a host that communicates with an NVM device through a standardized interface can use register write and read operations as an alternative communication channel to perform NVM device management functions not covered by the standard. These types of operations can be performed without data bus write discipline.

[0103] 14 is a block diagram of a system 1430 and operation according to a further embodiment. The system 1430 can include items similar to those in FIG.

[0104] 14 illustrates an NVM device 1400 that can be placed in an alternate mode to receive data packets through a sequence of register write operations over an alternate communication channel. Such data packets can contain alternate command data for performing NVM operations.

[0105] As in Figure 11, alternate mode operation can occur without write training (1444). As in Figure 13, host device 1432 can issue a special MPC (1458-0) to place NVM device 1400 into the alternate state.

[0106] Once in the alternate state, host device 1432 can perform a sequence of MRW operations in accordance with the LPDDR4 standard to transfer data packets to buffer 1450 within NVM device 1400. The data packets in buffer 1450 can have various values ​​accessible at buffer addresses. In the illustrated embodiment, such data can include a packet write instruction and packet length at address 1450-0a, an alternate command at address 1450-0b, address data (if appropriate for the command) at address 1450-1, and corresponding data (if appropriate for the command) at address 1450-2.

[0107] In response to receiving a data packet, the command decoder 1440 can generate an interrupt 1448-0, the packet data can be parsed, and alternative commands stored in the buffer 1450 can be executed.

[0108] After execution of the alternate command, controller circuit 1442 can write state values ​​to buffer 1450 at address 1450-3, which can then be retrieved (1446-5) from NVM device 1400 by one or more MRR commands. In some embodiments, this type of state data can be transferred on the DQ bus.

[0109] When all desired alternate command actions have been performed, the alternate state can be exited by another specialized MPC (1458-1).

[0110] In this way, a system having a host that communicates with an NVM device through a standardized interface can use register write and read operations as an alternate communication channel for transferring data packets with alternate device management commands. This type of operation can be performed without write discipline on the data bus.

[0111] Although embodiments herein disclose a buffer for storing packets with randomly addressable locations, alternative embodiments may include a buffer that can determine the type of data (e.g., command, address, data) using a storage order (e.g., FIFO, LIFO).

[0112] 15-17 illustrate processing of alternate command data in a memory device according to various embodiments. FIGS. 15-17 illustrate a memory device 1500 that may include banks 1506-0 to 1506-3 with corresponding access circuits 1566-0 to 1566-3, alternate command storage circuits 1538 / 50, controller circuits 1542, data IO paths 1570, and a DDR interface 1536. Each bank (1506-0 to 1506-3) may include one or more memory cell arrays including non-volatile and / or volatile memory cells. The access circuits (1566-0 to 1566-3) may enable access to the banks (1506-0 to 1506-3) and may include row / column decoders and various other circuits (e.g., sense / write amplifiers, program / erase circuits).

[0113] The controller circuit 1542 may include a first decode function 1540 and a second decode function 1514. The first decode function 1540 may decode command data according to one standard (e.g., LPDDR4), while the second decode function 1514 may decode command data according to a second standard (e.g., SPI), which may be considered an “embedded operation.” The storage circuit 1538 / 50 may receive and store alternative command data. The alternative command data may be for an embedded operation. The storage circuit 1538 / 50 may take any suitable form, including registers and / or buffers. A data IO path 1570 may provide a data path between the DQ bus, the banks (1506-0 to 1506-3), and the storage circuit 1538 / 50.

[0114] 15 and 16 show alternative commands for processing actions according to one embodiment.

[0115] FIG. 15 illustrates, at (1), receipt of command-address data on the CA bus (CA). At (2), the received command-address data is decoded by a first decode function 1540, and alternative command data 1568 can be stored in the storage circuit 1538 / 50. This type of operation can take any suitable form, including, but not limited to, a register write operation or a specialized array write operation. The alternative command data 1568 can include a command and associated values ​​(e.g., address, data). The alternative command data 1568 can have any suitable format, including separate values ​​(command, address, data) or contiguous values ​​(packet) that must be parsed.

[0116] 16 shows that, at (3), second decode function 1514 accesses storage circuit 1538 / 50 and decodes alternate command data 1568. Such alternate decode may include accessing a register to retrieve a value and / or parsing data stored in a buffer to retrieve a value. At (4), in response to such decode, controller 1524 may generate array / register access control signals that may execute alternate commands (e.g., array program, register write, array read, register read).

[0117] In this way, a memory device can receive a command according to one standard and store the resulting alternate command data, which can then be decoded according to a second standard to perform an operation on the memory device.

[0118] Figure 17 illustrates processing of alternate command data in a memory device according to a further embodiment. Figure 17 illustrates a memory device 1500 similar to that of Figure 15. Figure 17 may differ from that of Figure 15 in that the alternate command data is not stored in the memory circuitry, but rather is decoded "on the fly" from the CA bus.

[0119] FIG. 17 illustrates, at (1), receipt of command-address data on the CA bus. However, such command-address data does not include alternate command data. Rather, such command-address data may configure the controller circuit 1542 to begin decoding the received data according to a second standard. At (2), alternate command data 1568 may be received on the CA bus. Such alternate command data 1568 may be decodable by the second decode function 1514, as described with reference to FIG. 16.

[0120] In this way, the memory device can receive commands according to one standard and be placed into a mode that allows alternate command data on the command-address bus to be decoded according to a second standard to perform operations on the memory device.

[0121] Figures 18A and 18B illustrate the processing of program data in a memory device according to an embodiment. Figures 18A / B show a memory device 1500 similar to that of Figure 15. However, it should be understood that the banks (1506-0 through 1506-3) contain non-volatile memory cells.

[0122] FIG. 18A illustrates how an alternate command can program write data 1872 previously stored in the storage circuits into memory cells of bank 1506-0. The operations of FIG. 18A can be followed by operations that decode the alternate command data to determine if a program operation occurs. For example, the operations of FIG. 18A can be followed by the operations shown in FIG. 16. As a result of such a previous operation, write data 1872 has been stored in storage circuits 1538 / 50. Such write data can be stored in a sequence of registers or can be included as a field in a data packet stored in a buffer.

[0123] The second decode operation 1514 may generate an access signal that causes the write data 1872 to be programmed at an address indicated by the substitute command data (not shown).

[0124] Figure 18B shows how alternate program write data 1872 is received on the CA bus and stored in memory cells of bank 1506-0. The operations of Figure 18B may follow operations that decode the alternate command data on the fly. For example, the operations of Figure 18B may follow operations shown in Figure 17. A second decode operation 1514 may generate access signals to enable the write data 1872 arriving on the CA bus to be programmed at the address indicated by the alternate command data (not shown).

[0125] In this manner, the alternate command data (embedded operations) can be used to program data into the non-volatile memory cells of the memory device.

[0126] While embodiments can include any suitable memory cell array structure, some embodiments can include a one-transistor (1T) NOR type array. FIG. 19A is a schematic diagram of a 1T NOR array 1906A that can be included within an embodiment. The array 1906A can include memory cells (one shown as 1974-0) arranged in rows and columns, with memory cells in the same row connected to the same word line (one shown as 1974-1) and memory cells in the same column connected to the same bit line (one shown as 1974-2). In some embodiments, the memory cells (1974-0) can be formed with a single transistor structure and have a charge storage structure 1976 between the control gate and the channel. The charge storage structure 1976 can store one or more bits of data as a charge (including the absence of a charge). The charge storage structure 1976 can take any suitable form, including, but not limited to, a floating gate, a charge storage dielectric (e.g., a replacement gate), or a combination thereof.

[0127] While embodiments may include non-volatile memory cells, embodiments may also include any suitable volatile array structure or volatile memory cell type. FIG. 19B is a schematic diagram of a possible volatile memory cell array that may be included within an embodiment. FIG. 19B illustrates an array 1906B that may include volatile memory cells (one shown as 1974-0V) arranged in rows and columns and connected to one or more bit lines (e.g., 1974-2) and word lines (e.g., 1974-1). The volatile memory cells may take any suitable form, including, but not limited to, DRAM cells 1974-0V1 and / or SRAM cells 1974-0V2. SRAM cells 1974-0V2 include, but are not limited to, 4-transistor (4T), 6T, and / or 8T variations.

[0128] Of course, other embodiments may include any other suitable volatile or non-volatile cell types and / or array architectures.

[0129] Although embodiments can include a system with a memory device that operates in conjunction with a host device, embodiments can also include a standalone memory device. This type of device can provide memory device operation according to two standards (e.g., LPDDR4 and SPI), but can also include an interface according to only one standard (e.g., LPDDR4). This can provide a memory device with desired features but with a reduced pin count (e.g., no SPI interface). An embodiment of this type is shown in FIG. 20.

[0130] 20 illustrates a perspective top view of a packaged memory device 2000. The memory device 2000 can take the form of any of those described herein or equivalents. In some embodiments, the memory device 2000 can include a single integrated circuit die. The memory device 2000 can include many physical connections (e.g., pins), one of which is shown as 2078.

[0131] In this way, a memory device can provide functionality according to two different standards (e.g., SPI and LPDDR4), but also include connections for only one type of standard (LPDDR4) due to its relatively low pin count.

[0132] 21 is a block diagram of a host device 2132 according to one embodiment. The host device 2132 can embed any suitable functions for controlling a memory device (e.g., array read, array write, register read, register write) within the command sequence of the other standard (e.g., LPDDR4), thereby allowing operations to be performed according to two different standards. The host device 2132 can include an LPDDR4 interface 2134, a first command encoding function 2180, and a second command encoding function 2182. Such command encoding functions 2180 / 82 can be implemented in any suitable manner, including, but not limited to, processor-executed instructions, custom logic, programmable logic, or a combination thereof.

[0133] The first encoding function 2180 can encode commands in accordance with the first standard (LPDDR4). The first encoding function 2180 can encode memory access requests (array read, array write, register read, register write) into memory access commands in a conventional manner. In addition, the first encoding function 2180 can encode requests to enter and exit alternate mode 2180-0. Such requests can take the form of any of those described herein or equivalents, including a special MRW command, a special MRR command, a special array read or array write command, or an MPC. Such commands can be special in that they can include additional data (arguments, addresses) that do not correspond to commands in accordance with the first standard.

[0134] The second encoding function 2182 can encode commands according to the second standard 2182-0 into a format compatible with the first standard. In some embodiments, this type of encoding can provide functionality for an existing standard (e.g., SPI). For example, this type of format can be a bit value included in a command according to the second standard (e.g., a bit value in a mode register write command).

[0135] In this way, the host device can embed one standard command within another standard command (providing an embedded operation).

[0136] 22, a diagram of an automobile system 2230 according to one embodiment is shown. The automobile system 2230 can have multiple subsystems (two shown as 2230-0 and 2230-1). The subsystems 2230-0 / 1 can be operated by a host device (e.g., a CPU subsystem) that communicates with one or more memory devices. Such subsystems 2230-0 / 1 can include an electronic control unit (ECU) and / or an advanced driver assistance system (ADAS). However, in other embodiments, such subsystems can include a dashboard display / control subsystem and / or an infotainment subsystem, as two of many possible examples.

[0137] Subsystem 2230-0 / 1 may include a host device capable of accessing a memory device using embedded functions described herein or equivalents. In some embodiments, such memory devices may be non-volatile memory devices accessed by the host device over an LPDDR4 bus. The embedded functions may include non-volatile memory functions such as SPI-compatible programmability. According to embodiments, such embedded functions may be performed without requiring write training, enabling fast response to power-on timing requirements, for example, as required by CAN (and CAN-like) buses.

[0138] In this way, the automotive system can have fast boot capability from a non-volatile memory device.

[0139] While various devices and systems have disclosed methods, additional methods are described below with reference to flow diagrams. Such methods can be performed by processors executing instructions, custom logic, programmable logic, and combinations thereof. Such methods can be performed by various devices and equivalents described herein.

[0140] 23 illustrates a method 2390 for providing embedded operations according to one embodiment. The method 2390 may include receiving a command on a unidirectional CA bus of a memory interface. The received command is decodable according to a first standard (2390-0). If the decoded command does not indicate an alternate mode (N at 2390-1), the command is executable according to the first standard (2390-2).

[0141] If the decoded command indicates an alternate mode (Y at 2930-1), one or more alternate commands may be received and stored (2390-3). Such action may include storing the alternate commands with corresponding data (e.g., arguments, addresses). The alternate commands are decoded and executable according to a second standard (2390-4). Such action may include accessing the alternate commands from a memory location, including any accompanying data.

[0142] The method 2390 may include receiving a command on a CA bus of the memory interface. The received command is decodable according to a first standard (2390-5). If the decoded command does not indicate an exit from the alternate mode (N at 2390-6), the method 2390 may continue receiving and executing alternate commands (returning to 2390-3).

[0143] If the decoded command indicates exiting the alternate mode (Y at 2390-6), the method may return to receiving commands on the CA bus (2390-0).

[0144] In this way, commands according to the first standard can put the device into an alternate mode, where it can decode alternate commands according to the second standard.

[0145] Figure 24 shows a method 2490 for providing embedded operations according to a further embodiment. Method 2490 may include actions similar to those of Figure 23. Method 2490 may differ from the method of Figure 23 in that receiving an alternate command (2490-3A) may include receiving an alternate command on a CA bus (2490-30) and / or receiving an alternate command on a bidirectional data bus of a memory interface (2490-31).

[0146] In this way, commands according to the first standard can place the device in an alternate mode, where alternate commands received on the unidirectional CA bus or the bidirectional DQ bus can be stored according to the second standard.

[0147] Figure 25 shows a method 2590 for providing an embedded operation according to another embodiment. Method 2590 may include actions similar to those of Figure 23. Method 2590 may differ from the method of Figure 23 in that receiving the alternative command may include receiving the alternative command according to a first standard as a sequence of commands (2590-3A). Such actions may include receiving an alternative command bit value (and any associated data) embedded within the command (e.g., argument bits of the first standard command) according to the first standard.

[0148] Such alternate command values ​​may be stored in registers (2590-3B). Such registers may include registers accessible according to the first standard and / or additional registers not used in the first standard but used in the alternate mode.

[0149] In this way, commands conforming to the second standard can be included within commands conforming to the first standard.

[0150] FIG. 26 illustrates a method 2690 for providing embedded operations according to another embodiment. Method 2690 may include actions similar to those of FIG. 23. Method 2690 may differ from the method of FIG. 23 in that once the first standard command indicates an alternate mode (Y at 2690-1), method 2690 may receive a data packet on the memory interface (2690-7A). Such actions may include receiving packet data on the CA bus and / or DQ bus. The received packet data may be stored in a buffer (2690-7B). Such actions may include storing the packet data in a buffer via a sequence of buffer write operations or storing the packet in a register via a sequence of register write transactions.

[0151] The stored packet data can be analyzed to determine alternative commands (2690-7C). Such actions can include accessing the stored packet data by memory location indicating the type of data stored (command, argument, address, data).

[0152] In this way, a command according to the first standard can put the device into an alternate mode, in which it can receive data packets containing alternate command data.

[0153] FIG. 27 is a diagram 2790 of a command processing method according to one embodiment. FIG. 27 illustrates actions for the host device 2732 and the memory device 2700. The method 2790 may include powering up, resetting, waking, or similar actions for the memory device (2790-10). Such actions may include the memory device receiving power, a command, or a predetermined signal (2790-10). The memory device may perform CA bus training and read training (e.g., Read-DQ training) (2790-11). However, the memory device 2700 does not perform write training (2790-12). Thus, the memory device 2700 is ready for access without having to consume the time associated with write training.

[0154] The host device 2732 may perform various operations (2790-13). Such actions may include generating an LPDDR4 compatible command in response to a system request that is not a write operation to the memory device 2700. In response to receiving a write operation request (Y at 2790-14), the host device may place the memory device in an alternate mode with an LPDDR4 command (2790-15). Such actions may include any appropriate LPDDR4 command having an argument indicating the alternate mode, including, but not limited to, a special array read (Read ADDx), a special array write (Write ADDx), MPC, MRW, or MRR (2790-15A).

[0155] The host device 2732 can generate an alternate write command (2790-16). This type of alternate command can be a command that is not compatible with the LPDDR4 standard. By way of example only, this type of command is equivalent to an SPI program command. The host device 2732 can format the alternate command (and any associated data) (2790-17). This type of action can include bit values ​​for the alternate command (and associated data) within one or more LPDDR4 commands (e.g., LPDDR4 command arguments) (2790-17A) or within a data packet (2790-17B).

[0156] The host device 2732 can send alternate command data using LPDDR4 commands at a single data rate on the CA bus (2790-18).

[0157] The memory device 2700 can receive and store the alternate command data (2790-19). Such actions can include storing the alternate command data in a register (2790-19A) or in a packet buffer (2790-19B). Once stored, the alternate command data can be decoded (2790-20) according to a second (i.e., not LPDDR4) standard to derive the program command. Such actions can include accessing a register (2790-20A) using knowledge of which register stores which data. Such actions can also include parsing the received packet data (2720-20B).

[0158] Upon decoding the alternate command, write data can be programmed into the array at the address indicated by the alternate command (2790-21). A write status register can be set according to the result of such a program operation (2790-22). Such a register can be read by the host device (not shown).

[0159] Method 2790 also illustrates a response to a read operation request. In some embodiments, this type of read request can occur after an LPDDR4 command from the host exiting an alternate mode (not shown).

[0160] If a read operation request is received (Y at 2790-23), the host 2732 can send an LPDDR4 read command on the CA bus (2790-24). This type of read command can include a read address. The memory device 2700 can decode the LPDDR4 command (2790-25). Data can be read from the array at the address indicated by the read command, and this type of read data can be driven at double data rate on the DQ bus (2790-26). This type of read data can be received by the host device (2790-27). A read status register can be set according to the result of this type of read operation (2790-28). This type of register can be read by the host device (not shown).

[0161] In this manner, the host device 2732 can embed a non-LPDDR4 program command within an LPDDR4 command and send such a program command over the CA bus to the memory device 2700. The memory device 2700 can decode the program command and perform the program operation.

[0162] Embodiments may include a method in which, in a default mode of the memory device, command data received on the unidirectional CA bus is decodable according to a first standard. In response to decoding a mode enter command according to the first decoding standard, the memory device may enter an alternate management mode. In the alternate management mode, alternate command data is receivable on the CA bus. In response to receiving a command execution instruction on the CA bus, the alternate command data is decoded according to a second standard to execute the alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, the memory device may return to the default mode. The CA bus and the data bus may include multiple parallel input connections.

[0163] An embodiment may include a memory device having at least one non-volatile memory cell array and an interface including a unidirectional CA bus with a plurality of CA inputs, a data bus with a plurality of data inputs / outputs (IOs), and a timing clock input. The memory device may further include a memory controller circuit configured, in a default operating mode, to decode command data received on the CA bus according to a first standard and, in response to decoding a mode enter command according to the first standard, to place the memory device in an alternate management mode. In the alternate management mode, the memory controller circuit may receive alternate command data on the CA bus and, in response to receiving a command execution instruction on the CA bus, decode the alternate command data according to a second standard and execute the alternate command. In response to decoding a mode exit command received on the CA bus according to the first command decode protocol, the memory controller circuit may return the memory device to the default mode.

[0164] An embodiment may include a system including a memory device, the memory device including an interface having a unidirectional command and address (CA) bus, a data bus, and a clock input configured to receive a clock. The memory device may further include a memory controller circuit configured, in a default operating mode, to decode command data received on the CA bus according to a first standard and to place the memory device in an alternate management mode in response to decoding a mode enter command according to the first standard. In the alternate management mode, the memory controller circuit may receive alternate command data on the CA bus and, in response to receiving a command execution instruction on the CA bus, decode the alternate command data and execute the alternate command. The first standard may include at least one read command, the at least one read command outputting read data to be stored in at least one memory cell array on the data bus at double data rate relative to the clock. The at least one alternate command may include a write command, the write command writing data into the at least one memory cell array, the write data being received on the CA bus at a single data rate relative to the clock.

[0165] Methods, devices, and systems according to embodiments can read data from at least one memory cell array in both a default mode and an alternate mode.

[0166] Methods, devices and systems according to embodiments include storing memory device configuration data in configuration registers in a default mode, and alternate command data can be stored in the configuration registers in an alternate management mode.

[0167] Methods, devices and systems according to embodiments may include configuration registers having a first register address space in a default mode, and in an alternate management mode, the configuration registers have a second register address space that is larger than the first register address space.

[0168] In an alternate management mode, methods, devices, and systems according to embodiments may include receiving alternate command data on the CA bus, including receiving a program command, a program address, and program data on the CA bus configured to program non-volatile memory cells with the write data, and executing the alternate command includes programming the write data at the program address.

[0169] In an alternate management mode, methods, devices, and systems according to embodiments may include receiving alternate command data on the CA bus, which includes receiving a register read command and a register address on the CA bus, and executing the alternate command includes providing the register data to the register address as output data on the data bus.

[0170] In an alternate management mode, methods, devices, and systems according to embodiments receive alternate command data in at least one data packet and, in response to receiving a command execution instruction, parse the at least one data packet to access the alternate command data.

[0171] Methods, devices and systems according to embodiments may include a first standard that is a double data rate (DDR) standard, transmitting data on a data bus at DDR and receiving command and address data at a single data rate, and a second standard that enables execution of commands with the functionality of a serial bus standard that transmits command, address and data values ​​on at least one serial line.

[0172] Methods, devices and systems according to embodiments may include a first standard which is a low power DDR standard and a Serial Bus standard which is a Serial Peripheral Interface standard.

[0173] Methods, devices and systems according to embodiments may include a packet buffer circuit, and in an alternate management mode of operation, the controller circuit is configured to store received data packets in the packet buffer circuit, analyze the data packets and determine alternate command data.

[0174] Methods, devices and systems according to embodiments may include alternative command data including any selected from the group of a length value indicating the amount of data stored by the data packet, an error detection or correction code for the data contained within the data packet, and a security value for authenticating the sender of the data packet.

[0175] Methods, devices and systems according to embodiments may include a data bus that is unidirectional, providing output data from the device.

[0176] Methods, devices, and systems according to embodiments may include at least one memory cell array comprising non-volatile memory cells, and a write command configured to program data received on the CA bus into the at least one memory cell array.

[0177] Methods, devices, and systems according to embodiments can include at least one alternative command, including a register write command configured to write write data received on the CA bus into a register of a memory device, and a register read command configured to output data stored in a register of the memory device onto a data bus, wherein the register of the memory device can be different from the at least one memory array.

[0178] According to embodiments, the method, device, and system may include a plurality of registers distinct from the memory cell array. The memory cell array may comprise non-volatile memory cells. In the alternate management mode, the memory controller circuit is configured to execute register write commands decoded according to a first standard, store alternate program commands and write data in the registers, and decode alternate write commands according to a second standard and program the write data into the non-volatile memory cells.

[0179] According to embodiments, the method, device, and system may include a packet buffer circuit distinct from the at least one memory cell array. The at least one memory cell array may comprise non-volatile memory cells. In the alternate management mode, the memory controller circuit is further configured to store packet data received at the interface in the packet buffer circuit, analyze the stored packet data, determine an alternate write command and write data, decode the alternate write command according to a second standard, and program the write data into the non-volatile memory cells.

[0180] Methods, devices and systems according to embodiments may include packet buffer circuits comprising volatile memory cells.

[0181] In methods, devices, and systems according to embodiments, the first standard is compatible with the DDR standard and can include a host device coupled to the memory device by a memory bus, the host device being configurable to generate alternative command data that provides the same functionality as the serial interface standard.

[0182] It should be understood that throughout this specification, references to "one embodiment" or "embodiments" mean that the particular features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the invention. It should therefore be emphasized and recognized that two or more references to "an embodiment" or "one embodiment" or "alternative embodiments" in various parts of this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined as appropriate in one or more embodiments of the invention.

[0183] Similarly, in the exemplary embodiments of the invention described above, it should be understood that various features of the invention are sometimes grouped together in a single embodiment, drawing, or description to streamline the disclosure to aid in understanding one or more of the various inventive aspects. However, this method of disclosure should not be interpreted as reflecting an intention that the claims require more features than are expressly recited in each claim. Rather, inventive aspects may comprise less than all features of a single foregoing disclosed embodiment. Accordingly, the claims following the Detailed Description are expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of the invention.

[0184] While the present invention has been described with reference to illustrated embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrated embodiments, as well as other embodiments of the present invention, will become apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. In a method, the method comprises: The default mode for memory devices is Decoding command data received on a unidirectional command and address (CA) bus of the memory interface according to a first standard; in response to decoding a mode enter command according to the first standard, placing the memory device in an alternate management mode; Including, In the alternative management mode, receiving alternate command data on the CA bus; in response to receiving a command execution indication on the CA bus, decoding the alternate command data in accordance with a second standard and executing the alternate command; returning the memory device to the default mode in response to decoding a mode exit command received on the CA bus according to the first standard; Including, the memory interface comprises the CA bus and a data bus, the CA bus and the data bus comprising a plurality of parallel input connections; method.

2. In said default mode, storing memory device configuration data in configuration registers; In the alternate management mode, storing the alternate command data in the configuration register. The method of claim 1.

3. In the default mode, the configuration registers have a first register address space; In the alternate management mode, the configuration registers have a second register address space that is larger than the first register address space. The method of claim 2.

4. In the alternate management mode, the step of receiving alternate command data on the CA bus comprises: receiving on the CA bus a program command, a program address and program data configured to program non-volatile memory cells with write data; executing the alternate command includes programming the write data at the program address; The method of claim 1.

5. In the alternate management mode, the step of receiving alternate command data on the CA bus comprises: receiving a register read command and a register address on the CA bus; executing the alternative command includes providing register data to the register address as output data on the data bus; The method of claim 1.

6. In the alternative management mode, receiving the alternative command data in at least one data packet; responsive to receiving the command execution indication, parsing the at least one data packet to access the alternate command data; The method of claim 1.

7. The first standard is a double data rate (DDR) standard, the double data rate (DDR) standard comprising: Transmitting data on said data bus at DDR; Receives command and address data at a single data rate The second standard allows for the execution of commands having the functionality of a serial bus standard for transmitting commands, addresses and data values ​​over at least one serial line. The method of claim 1.

8. the first standard is a low power DDR standard; the serial bus standard is a Serial Peripheral Interface standard; The method according to claim 7.

9. at least one non-volatile memory cell array; an interface including a unidirectional command address (CA) bus with multiple CA inputs, a data bus with multiple data input / output (IO)s, and a timing clock input; A memory controller circuit; A memory device comprising: The memory controller circuit includes: In the default operating mode, Decoding command data received on the CA bus in accordance with a first standard; in response to decoding a mode enter command according to the first standard, placing the memory device in an alternate management mode; In the alternative management mode, receiving substitute command data on the CA bus; in response to receiving a command execution indication on the CA bus, decoding the alternate command data in accordance with a second standard and executing the alternate command; returning the memory device to a default mode in response to decoding a mode exit command received on the CA bus according to the first standard. It is configured as follows: Memory device.

10. the first standard being compatible with at least one double data rate standard; the second standard allows for the execution of commands having functions of at least one serial data communication standard; The memory device of claim 9.

11. the memory device further comprising a plurality of mode registers; The memory controller circuit includes: storing a mode configuration value in the mode register in response to decoding a mode access command according to the first standard, in the default mode of operation; storing the alternate command data in the mode register in the alternate management mode of operation; It is configured as follows: The memory device of claim 9.

12. the memory device further includes a packet buffer circuit; In the alternate management mode of operation, the memory controller circuit is configured to store received data packets in the packet buffer circuit, parse the data packets, and determine the alternate command data. The memory device of claim 9.

13. the alternative command data includes any one selected from the group consisting of a length value indicating the amount of data stored by the data packet, an error detection or correction code for the data contained within the data packet, and a security value for authenticating the sender of the data packet; The memory device of claim 12.

14. the data bus is unidirectional providing read-only output data from the memory devices; The memory device of claim 9.

15. the alternative command data comprises a program command, a target address and data to program; The memory device of claim 9.

16. A system comprising a memory device, The memory device comprises: an interface having a unidirectional command and address (CA) bus, a data bus, and a clock input configured to receive a clock; A memory controller circuit; Including, The memory controller circuit includes: In the default operating mode, Decoding command data received on the CA bus in accordance with a first standard; in response to decoding a mode enter command according to the first standard, placing the memory device in an alternate management mode; In the alternative management mode, receiving substitute command data on the CA bus; in response to receiving a command execution instruction on the CA bus, decoding the alternative command data and executing the alternative command; It is configured as follows: the first standard includes at least one read command, the at least one read command outputting read data stored in at least one memory cell array on the data bus at a double data rate relative to the clock; at least one alternative command includes a write command, the write command writing data into the at least one memory cell array, and the data to be written into the at least one memory cell array by the write command is received on the CA bus at a single data rate relative to the clock. system.

17. the at least one memory cell array comprises non-volatile memory cells; the write command is configured to program data received on the CA bus into the at least one memory cell array.

17. The system of claim 16.

18. The at least one alternative command is: a register write command configured to write write data received on the CA bus into a register of the memory device; a register read command configured to output data stored in a register of the memory device onto the data bus; Further comprising: the register of the memory device is distinct from the at least one memory cell array; 17. The system of claim 16.

19. the system further comprising a plurality of registers distinct from the at least one memory cell array; the at least one memory cell array comprises non-volatile memory cells; In the alternate management mode, the memory controller circuit Executing a register write command decoded according to the first standard and storing an alternative program command and write data in the register; Decoding a substitute write command according to a second standard and programming the write data into the non-volatile memory cells. further comprising:

17. The system of claim 16.

20. the system further comprising a packet buffer circuit distinct from the at least one memory cell array; the at least one memory cell array comprises non-volatile memory cells; In the alternate management mode, the memory controller circuit storing packet data received at said interface in said packet buffer circuit; Analyzing the stored packet data to determine alternative write commands and write data; Decoding a substitute write command according to a second standard and programming the write data into the non-volatile memory cells. further comprising:

17. The system of claim 16.

21. the packet buffer circuit comprises a volatile memory cell; 21. The system of claim 20.

22. the first standard is compatible with the Double Data Rate (DDR) standard; The system further includes a host device coupled to the memory device by a memory bus, the host device configured to generate alternative command data that provides the same functionality as a serial interface standard.

17. The system of claim 16.

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