Non-volatile memory device and method of operating same

Abstract

To provide a nonvolatile memory element and an operation method for the same.SOLUTION: A nonvolatile memory element may include a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain apart from each other on the resistance switching layer. The resistance switching layer can change the resistance value on the basis of the illumination of light delivered to the resistance switching layer and keep the changed resistance value.SELECTED DRAWING: Figure 7A

Description

[Technical field]

[0001] The present invention relates to a non-volatile memory device and a method for operating the same. [Background technology]

[0002] Non-volatile memory devices, which are semiconductor memory devices, retain information even when the power is turned off and can use the stored information again when power is turned on. Non-volatile memory devices can be used in mobile phones, digital cameras, personal digital assistants (PDAs), mobile computing devices, fixed computing devices, and other devices.

[0003] Recently, research is underway to use non-volatile memory elements in chips forming next-generation neuromorphic computing platforms or neural networks.

[0004] In particular, research into non-volatile memory devices having photoconductivity (PC) is currently in demand. Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a non-volatile memory device and an operating method thereof.

[0006] Another problem to be solved by the present invention is to provide a computer-readable recording medium having recorded thereon a program for causing a computer to execute the above-mentioned method.

[0007] The technical problems to be solved are not limited to those described above, and other technical problems may exist. [Means for solving the problem]

[0008] As a technical means for achieving the above-mentioned technical object, a first aspect of the present disclosure provides a nonvolatile memory element including a resistance switching layer having a resistance value, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain spaced apart from each other on the resistance switching layer, wherein the resistance switching layer changes its resistance value based on the illuminance of light irradiated to the resistance switching layer and holds the changed resistance value.

[0009] In addition, a non-volatile memory element may be provided in which the gate is a transparent conducting electrode (TCE) gate that is disposed on the resistance change layer and through which irradiated light passes.

[0010] In addition, a nonvolatile memory element may be provided in which the resistance change layer includes a 2D material, and the 2D material includes at least one of a transition metal dichalcogenide (TMD), silicene, black phosphorus, or graphene.

[0011] Moreover, it is possible to provide a nonvolatile memory element in which the resistance change layer is made of a single layer.

[0012] Moreover, it is possible to provide a nonvolatile memory element having a multi-layer variable resistance layer.

[0013] Also, a nonvolatile memory element can be provided, in which the resistance change layer includes a 3D material, and the 3D material includes at least one of germanium, silicon, a III-V semiconductor, or IGZO.

[0014] Also, a non-volatile memory element can be provided in which the gate oxide layer is multi-layered, including a charge trapping layer.

[0015] In addition, it is possible to provide a non-volatile memory device in which the resistance value of the variable resistance layer decreases as the illuminance of light irradiated onto the variable resistance layer increases with an off-voltage applied to the gate.

[0016] In addition, the resistance change layer can provide a non-volatile memory element that resets the resistance value when an on-voltage is applied to the gate.

[0017] A second aspect of the present disclosure may provide a method for performing an operation using a crossbar array including a plurality of nonvolatile memory elements, the method including: applying an off voltage to a gate of each of the plurality of nonvolatile memory elements; changing a resistance value of a resistive layer of each of the plurality of nonvolatile memory elements by irradiating the plurality of nonvolatile memory elements with light of an illuminance corresponding to a plurality of elements; and applying a gate off voltage to at least one row of the crossbar array to obtain a source current for each column of the crossbar array.

[0018] Also, the irradiating step may include a step of obtaining an image by applying a gate-off voltage to each row of the crossbar array and obtaining a source current to each column of the crossbar array, the irradiating step corresponding to a plurality of pixels included in the image, and the operation step may include a step of obtaining an image by applying a gate-off voltage to each row of the crossbar array and obtaining a source current to each column of the crossbar array.

[0019] In addition, the irradiated light corresponds to a plurality of pixels included in the image, and the irradiating step includes a step of sequentially arranging a plurality of color filters on the non-volatile memory elements and irradiating the light to each of the plurality of non-volatile memory elements, and the operation includes a step of applying a gate-off voltage for each row of the crossbar array and obtaining a source current for each column of the crossbar array to obtain an intermediate image corresponding to each of the plurality of color filters, and a step of combining the intermediate images to obtain a color image.

[0020] Also, the irradiating step may include a step of irradiating a plurality of non-volatile memory elements with light of illuminance corresponding to a plurality of weights including a specific layer of the neural network, and the operation may include a step of applying a gate-off voltage to at least one row of the crossbar array and obtaining a source current for each column of the crossbar array, thereby performing a vector matrix operation for the specific layer.

[0021] Also, the irradiating step may include a step of shifting a window by a stride interval on the image and irradiating light of an illuminance corresponding to a plurality of elements included in the window for each column of the crossbar array.

[0022] A third aspect of the present disclosure relates to a method for recognizing an image using a crossbar array including a plurality of nonvolatile memory elements, the method including: applying an off-voltage to a gate of each of the nonvolatile memory elements; shifting a window by a stride interval on the image and irradiating light of an intensity corresponding to the image included in the window for each column of the crossbar array; applying a gate off-voltage to at least one row of the crossbar array and acquiring a first source current for each column of the crossbar array, thereby performing a pooling operation; and applying an on-voltage to a gate of each of the nonvolatile memory elements to reset the nonvolatile memory elements. applying an off-voltage to a gate of each of the non-volatile memory elements that have been reset; irradiating the non-volatile memory elements with light having an illuminance corresponding to a plurality of weights including a specific layer of a neural network; applying a voltage corresponding to a first source current as a drain voltage to at least one row of the crossbar array and obtaining a second source current for each column of the crossbar array, thereby performing a fully-connected convolution operation; and recognizing an image based on the second source current.

[0023] A fourth aspect of the present disclosure can provide a computer-readable recording medium having recorded thereon a program for causing a computer to execute the method of the second aspect. Effect of the Invention

[0024] According to the above-mentioned solution of the problem of the present disclosure, the crossbar array including a plurality of non-volatile memory elements has photoconductive properties, and such properties can be used to utilize the crossbar array of the present disclosure in an image storage / acquisition process.

[0025] Furthermore, according to the above-described problem solving means of the present disclosure, the crossbar array performs vector-matrix operations, and such characteristics can be used to utilize the crossbar array of the present disclosure in the learning and inference processes of a neural network.

[0026] In addition, according to the above-described problem solving means of the present disclosure, the crossbar array used in the imaging mode (image storage / acquisition) can be reset and then used in the recognition mode (neural network learning / inference), thereby allowing the imaging mode and the recognition mode to be performed using one crossbar array. [Brief description of the drawings]

[0027] [Figure 1A] 1 is a diagram illustrating a method of operating a crossbar array including a plurality of non-volatile memory devices according to an embodiment. [Figure 1B] 1 is a diagram illustrating a method of operating a crossbar array including a plurality of non-volatile memory devices according to an embodiment. [Diagram 2] 1 is a diagram illustrating the architecture of a neural network according to an embodiment; [Diagram 3] 1 is a diagram illustrating a relationship between an input feature map and an output feature map in a neural network according to an embodiment. [Figure 4A] 1 is a diagram for comparing vector matrix multiplication according to one embodiment with operations performed in a crossbar array. [Figure 4B] 1 is a diagram for comparing vector matrix multiplication according to one embodiment with operations performed in a crossbar array. [Diagram 5] 1 is a diagram illustrating an example of a convolution operation performed in a crossbar array according to an embodiment. [Figure 6] 11 is a diagram illustrating an example in which a sub-feature map and a crossbar array are matched according to an embodiment. [Figure 7A] 1 is a side view illustrating a non-volatile memory device having a phototransistor and a memory characteristic according to an embodiment; [Figure 7B] 1 is a side view illustrating a non-volatile memory device having a phototransistor and a memory characteristic according to an embodiment; [Figure 8] 1 is a diagram illustrating a phenomenon in which a resistance value of a nonvolatile memory device according to an embodiment is different before and after light irradiation; [Figure 9A] 1 is an exemplary diagram illustrating a process of storing an image using a crossbar array including a plurality of non-volatile memory devices and acquiring the stored image according to an embodiment; [Figure 9B] 1 is an exemplary diagram illustrating a process of storing an image using a crossbar array including a plurality of non-volatile memory devices and acquiring the stored image according to an embodiment; [Figure 10] 1 is an exemplary diagram illustrating a process of performing a pooling operation of a neural network using a crossbar array including a plurality of non-volatile memory devices according to an embodiment; [Figure 11] 1 is an exemplary diagram illustrating a process of performing a convolution operation of a neural network using a crossbar array including a plurality of non-volatile memory devices according to an embodiment; [Figure 12] 1 is a flowchart illustrating a method of performing a predetermined operation using a crossbar array according to an embodiment. [Figure 13] 1 is a block diagram illustrating a memory system according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The appearances of the phrases "in some embodiments" or "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

[0029] Some embodiments of the present disclosure may be illustrated by functional block configurations and various processing steps. Some or all of such functional blocks may be embodied by various numbers of hardware and / or software configurations performing specific functions. For example, the functional blocks of the present disclosure may be embodied by one or more microprocessors or by circuit configurations for a given function. For example, the functional blocks of the present disclosure may be embodied in various programming or scripting languages. The functional blocks may be embodied by algorithms executed by one or more processors. The present disclosure may employ conventional techniques for electronic configuration, signal processing, and / or data processing. Terms such as "mechanism," "element," "means," and "configuration" are used broadly and are not limited to mechanical or physical configurations.

[0030] Furthermore, the connecting lines or connecting members between components shown in the drawings are merely illustrative of functional connections and / or physical or circuit connections, and in an actual device, connections between components may be represented by various alternative or additional functional connections, physical connections, or circuit connections.

[0031] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] 1A and 1B are diagrams illustrating a method of operating a crossbar array including a plurality of non-volatile memory devices according to an embodiment.

[0033] 1A, the crossbar array may include a plurality of presynaptic neurons 10, a plurality of postsynaptic neurons 20, and synapses 30 providing respective connections between the plurality of presynaptic neurons 10 and the plurality of postsynaptic neurons 20. The synapses 30 represent non-volatile memory elements.

[0034] In one embodiment, the crossbar array includes four presynaptic neurons 10, four postsynaptic neurons 20, and sixteen synapses 30, but the numbers can be varied in various ways. If the number of presynaptic neurons 10 is N (where N is a natural number equal to or greater than 2) and the number of postsynaptic neurons 20 is M (where M is a natural number equal to or greater than 2 and may be the same as or different from N), N*M synapses 30 are also arranged in a matrix.

[0035] Specifically, there may be provided wiring 12 connected to each of the presynaptic neurons 10 and extending in a first direction (e.g., horizontal direction), and wiring 22 connected to each of the postsynaptic neurons 20 and extending in a second direction (e.g., vertical direction) intersecting the first direction. Hereinafter, for convenience of explanation, the wiring 12 extending in the first direction may be referred to as a row line, and the wiring 22 extending in the second direction may be referred to as a column line. A plurality of synapses 30 may be disposed at each intersection of the row wiring 12 and the column wiring 22, and may connect the corresponding row wiring 12 and the corresponding column wiring 22 to each other.

[0036] The presynaptic neuron 10 generates a signal, for example, a signal corresponding to specific data, and transmits it to the row wiring 12, and the post-synaptic neuron 20 receives a synaptic signal that has passed through a synapse 30 through the column wiring 22 and processes it. The presynaptic neuron 10 corresponds to an axon, and the post-synaptic neuron 20 corresponds to a neuron. However, whether a neuron is a presynaptic neuron or a post-synaptic neuron may be determined based on a relative relationship with another neuron. For example, when the presynaptic neuron 10 receives a synaptic signal in relation to another neuron, it may function as a post-synaptic neuron. Similarly, when the post-synaptic neuron 20 transmits a signal in relation to another neuron, it may function as a presynaptic neuron. The presynaptic neuron 10 and the post-synaptic neuron 20 may be embodied as various circuits such as a CMOS.

[0037] The presynaptic neuron 10 and the postsynaptic neuron 20 are connected through a synapse 30. Here, the synapse 30 is an element whose electrical conductance or weight varies depending on an electrical pulse, such as a voltage or current, applied to both ends.

[0038] The synapse 30 may include, for example, a variable resistance element. The variable resistance element is an element that can be switched between different resistance states depending on a voltage or current applied across both ends, and may have a single-layer structure or a multi-layer structure including various materials having a plurality of resistance states, for example, transition metal oxides, metal oxides such as perovskite-based materials, phase-change materials such as chalcogenide-based materials, ferroelectric materials, ferromagnetic materials, etc. An operation in which the variable resistance element and / or the synapse 30 change from a relatively high resistance state (e.g., a high resistance state) to a relatively low resistance state (e.g., a low resistance state) is called a set operation, and an operation in which the variable resistance element and / or the synapse 30 change from a relatively high resistance state (e.g., a high resistance state) to a relatively low resistance state (e.g., a low resistance state) is called a reset operation.

[0039] However, the synapse 30 may be embodied to have various characteristics different from variable resistance elements used in memory devices, such as showing analog behavior in which the conductivity changes gradually depending on the number of input electrical pulses, without an abrupt resistance change during a set operation and a reset operation, unlike variable resistance elements used in memory devices such as RRAM, PRAM, FRAM, and MRAM.

[0040] The operation of the above-mentioned crossbar array will be described below with reference to Fig. 1B. For convenience of explanation, the row wires 12 will be referred to as the first row wire 12A, the second row wire 12B, the third row wire 12C, and the fourth row wire 12D from the top, and the column wires 22 will be referred to as the first column wire 22A, the second column wire 22B, the third column wire 22C, and the fourth column wire 22D from the left.

[0041] 1B, in an initial state, all of the synapses 30 may be in a relatively low conductivity state, i.e., a high resistance state. If at least some of the synapses 30 are in a low resistance state, an initialization operation to set them to a high resistance state may be further required. Each of the synapses 30 has a predetermined threshold value required for resistance and / or conductivity change. More specifically, if a voltage or current smaller than the predetermined threshold value is applied across each synapse 30, the conductance of the synapse 30 may not change, and if a voltage or current larger than the predetermined threshold value is applied to the synapse 30, the conductance of the synapse 30 may change.

[0042] In this state, an input signal corresponding to specific data may be input to the row wirings 12 to perform an operation of outputting the specific data as a result of the specific column wiring 22. In this case, the input signal may be represented as application of an electrical pulse to each of the row wirings 12. For example, when an input signal corresponding to data "0011" is input to the row wirings 12, no electrical pulse may be applied to the row wirings 12 corresponding to "0", for example, the first and second row wirings 12A and 12B, and only the row wirings 12 corresponding to "1", for example, the third and fourth row wirings 12C and 12D, may be applied with an electrical pulse. In this case, the column wirings 22 may be driven with an appropriate voltage or current for output.

[0043] As an example, when the column wiring 22 that outputs specific data has already been determined, the column wiring 22 is driven so that the synapse 30 located at the intersection with the row wiring 12 corresponding to "1" is applied with a voltage having a magnitude equal to or greater than the voltage required during the set operation (hereinafter, "set voltage"), and the remaining column wirings 22 can be driven so that the remaining synapses 30 are applied with a voltage smaller than the set voltage. For example, when the magnitude of the set voltage is Vset and the column wiring 22 that outputs data of "0011" is determined to be the third column wiring 22C, the magnitude of the electrical pulse applied to the third and fourth row wirings 12C and 12D is equal to or greater than Vset, and the voltage applied to the third column wiring 22C is also 0V, so that the first and second synapses 30A and 30B located at the intersection of the third column wiring 22C and the third and fourth row wirings 12C and 12D are applied with a voltage equal to or greater than Vset. As a result, the first and second synapses 30A and 30B are also in a low resistance state. The conductivity of the first and second synapses 30A, 30B in the low resistance state may gradually increase as the number of electrical pulses increases. The magnitude and width of the applied electrical pulses may also be substantially constant. The voltages applied to the remaining column wirings, i.e., the first, second and fourth column wirings 22A, 22B and 22D, may have a value between 0V and Vset, for example, 1 / 2Vset, so that the remaining synapses 30 other than the first and second synapses 30A, 30B are applied with a voltage smaller than Vset. Thereby, the resistance state of the remaining synapses 30 other than the first and second synapses 30A, 30B does not change. The flow of current or electrons in such a case is indicated by dotted arrows.

[0044] As another example, the column wire 22 that outputs the specific data may not be determined. In such a case, an electrical pulse corresponding to the specific data is applied to the row wires 12, and the current flowing through each column wire 22 is measured, and the column wire 22 that reaches the predetermined critical current earliest, for example, the third column wire 22C, becomes the column wire 22 that outputs the specific data.

[0045] In the manner described above, different data can be output to different column lines 22, respectively.

[0046] FIG. 2 is a diagram for explaining the architecture of a neural network according to an embodiment.

[0047] Referring to FIG. 2, the neural network 2 is also an architecture of a deep neural network (DNN) or n-layer neural networks. The DNN or n-layer neural network may be a convolutional neural network (CNN), a recurrent neural network (RNN), a deep belief network, a restricted Boltzman machine, or the like. For example, the neural network 2 may be embodied by a convolutional neural network (CNN), but is not limited thereto. In FIG. 2, some convolutional layers are illustrated in a convolutional neural network corresponding to an example of the neural network 2, but the convolutional neural network may further include a pooling layer, a fully connected layer, and the like in addition to the illustrated convolutional layers.

[0048] The neural network 2 may also be realized by an architecture having multiple layers including an input image, feature maps, and an output. In the neural network 2, the input image is convolved with a filter called a weight, and as a result, a feature map is output. At that time, the generated output feature map is convolved again with the weight as the input feature map, and a new feature map is output. As a result of such repeated convolution operations, a recognition result related to the features of the input image via the neural network 2 may finally be output.

[0049] For example, when an image of 24x24 pixels is input to the neural network 2 of FIG. 2, the input image may be output as a 4-channel feature map of 20x20 size through a convolution operation with the weights. The 20x20 feature map may then be reduced in size through repeated convolution operations with the weights, and finally a feature of 1x1 size may be output. The neural network 2 repeatedly performs convolution operations and subsampling (or pooling) operations in multiple layers to filter and output robust features representative of the entire image from the input image, and may derive a recognition result for the input image through the final output features.

[0050] FIG. 3 is a diagram illustrating a relationship between an input feature map and an output feature map in a neural network according to an embodiment.

[0051] Referring to FIG. 3, in one layer 3 of a neural network, a first feature map FM1 may correspond to an input feature map, and a second feature map FM2 may correspond to an output feature map. A feature map means a data set in which various features of input data are expressed. The feature maps FM1 and FM2 may have elements of a two-dimensional matrix or elements of a three-dimensional matrix, and a pixel value may be defined for each element. The feature maps FM1 and FM2 may have a width W (or referred to as a column), a height H (or referred to as a row), and a depth D. In this case, the depth D may correspond to the number of channels.

[0052] A convolution operation is performed on the first feature map FM1 and the weights, and as a result, a second feature map FM2 is generated. The weights filter the features of the first feature map FM1 by performing a convolution operation with the first feature map FM1. The weights perform a convolution operation with a window (also called a tile) of the first feature map FM1 while shifting the first feature map FM1 in a sliding window manner. During each shift, the weights may be multiplied and added with each pixel value of the overlapped window in the first feature map FM1. One channel of the second feature map FM2 is generated by convolving the first feature map FM1 with the weights. Although one weight is illustrated in FIG. 2, in reality, multiple weights are convolved with the first feature map FM1, respectively, to generate a second feature map FM2 of multiple channels.

[0053] Meanwhile, the second feature map FM2 may correspond to an input feature map of the next layer, for example, the second feature map FM2 may be an input feature map of a pooling (or subsampling) layer.

[0054] 2 and 3, for convenience of explanation, only a schematic architecture of the neural network 2 is illustrated. However, it will be understood by those of ordinary skill in the art that the neural network 2 may be embodied with a greater or lesser number of layers, feature maps, weights, etc., different from those illustrated, and that the size of the neural network 2 may be varied in various ways.

[0055] 4A and 4B are diagrams for comparing vector matrix multiplication according to one embodiment with operations performed in a crossbar array.

[0056] 4A, the convolution operation between the input feature map and the weights is performed using vector-matrix multiplication. For example, pixel data of the input feature map is represented by matrix X 410, and the weight values ​​are represented by matrix W 411. Pixel data of the output feature map is represented by matrix Y 412, which is a result of the multiplication operation between matrix X 410 and matrix W 411.

[0057] 4B, a vector multiplication operation is performed using non-volatile memory elements of a crossbar array. In comparison with FIG. 4A, pixel data of an input feature map is received as an input value of a non-volatile memory element, and the input value is also a voltage 420. In addition, weight values ​​are stored in synapses, i.e., memory cells, of the non-volatile memory element, and the weight values ​​stored in the memory cells are also a conductance 421. Therefore, an output value of the non-volatile memory element is represented by a current 422, which is a result of a multiplication operation of the voltage 420 and the conductance 421.

[0058] FIG. 5 is a diagram illustrating an example of a convolution operation performed in a crossbar array according to an embodiment.

[0059] The crossbar array 500 may receive pixel data of an input feature map 510. The crossbar array 500 may include a number of non-volatile memory elements.

[0060] In one embodiment, when the crossbar array 500 is a matrix of size NxM (N and M are natural numbers equal to or greater than 2), the number of pixel data of the input feature map 510 is less than or equal to the number of columns M of the crossbar array 500. The pixel data of the input feature map 510 is also a parameter in floating-point or fixed-point format. Meanwhile, in another embodiment, the number of pixel data of the input feature map 510 is more than the number of columns M of the crossbar array 500, which will be described in detail in FIG. 6.

[0061] A digital-to-analog converter (DAC) 520 may receive pixel data in the form of a digital signal and convert it into a voltage in the form of an analog signal. The pixel data of the input feature map 510 may have various bit resolution values ​​such as 1-bit, 4-bit, and 8-bit resolution. In one embodiment, the crossbar array 500 may convert the pixel data into a voltage using the DAC 520 and then receive the voltage 501 as an input value of the crossbar array 500.

[0062] Further, the learned weight values ​​are stored in each of the multiple nonvolatile memory elements included in the crossbar array 500. The weight values ​​are stored in memory cells of the nonvolatile memory elements, and the weight values ​​stored in the memory cells are also conductances 502. At this time, the crossbar array 500 calculates an output value by performing a vector multiplication operation of a voltage 501 and a conductance 502, and the output value is represented by a current 503. That is, the crossbar array 500 can output a result value that is the same as the result of a convolution operation between an input feature map and a weight, using multiple nonvolatile memory elements.

[0063] Since the current 503 output by the crossbar array 500 is an analog signal, an ADC (Analog Digital Converter) 530 can be used to use the current 503 as input data for another crossbar array 550. The current 503 output by the crossbar array 500 can be converted into a digital signal by the ADC 530. In one embodiment, the ADC 530 can be used to convert the current 503 into a digital signal having the same bit resolution as the pixel data of the input feature map 510. For example, if the pixel data of the input feature map 510 has 1-bit resolution, the ADC 530 can also convert the current 503 into a digital signal with 1-bit resolution.

[0064] The activation unit 540 can apply an activation function to the digital signal converted by the ADC 530. The activation function can be a Sigmoid function, a Tanh function, or a ReLU (Rectified Linear Unit) function, but the activation functions applicable to the digital signal are not limited thereto.

[0065] The digital signal to which the activation function is applied is used as an input value of another crossbar array 550. When the digital signal to which the activation function is applied is used as an input value of another crossbar array 550, the above-described process may be applied to the other crossbar array 550 in the same manner.

[0066] FIG. 6 is a diagram illustrating an example in which a sub-feature map and a crossbar array are matched according to an embodiment.

[0067] The input feature maps 610 used for training and inference can have various sizes, but because the size of the crossbar array 600 is limited, the number of pixel data in a single input feature map 610 is greater than the number of input values ​​that can be received by the crossbar array 600.

[0068] 6, the size of the input feature map 610 is 8x8, and the size of the crossbar array 600 is 16x16. In this case, the number of pixel data in the 8x8 input feature map 610 is 64 (=8x8), which is larger than the number of input values ​​that the crossbar array 600 can receive, that is, 16.

[0069] When the number of pixel data of the input feature map 610 is greater than the number of input values ​​of the crossbar array 600, i.e., the number of rows M, the input feature map 610 may be divided into sub-feature maps 611. The input feature map 610 may be divided into sub-feature maps 611 based on size information of the crossbar array 600.

[0070] Specifically, if the size of the input feature map 610 is 8x8 and the size of the crossbar array 600 is 16x16, the input feature map 610 is divided into four sub-feature maps such that the number of pixel data in each sub-feature map is 16. Each of the divided sub-feature maps may be matched to the crossbar array 600.

[0071] For example, the crossbar array 600 converts “aa” in the sub-feature map 610 into the first input value “V 1 ” and the “ab” of the sub-feature map 610 is received as the second input value “V 2 " and the "dd" of the sub-feature map 610 is received as the 16th input value "V 16 " can be received.

[0072] Meanwhile, as described above in FIG. 5, the pixel data of the sub-feature map 610 is also a digital signal (e.g., 1 bit, 4 bits, etc.), and the pixel data of the sub-feature map 610 passes through a DAC (Digital Analog Converter) to be converted into an analog voltage signal (V 1 Or V 16), which can then be input to the crossbar array 600.

[0073] In addition, the current I 1 ~I 16 is also an analog signal, and the current I 1 ~I 16 is passed through an ADC (Analog Digital Converter) and converted into a digital signal.

[0074] 7A and 7B are side views illustrating a non-volatile memory device having a phototransistor and memory characteristics according to an embodiment.

[0075] The nonvolatile memory elements 710 and 720 may include resistive change layers 715 and 725. Gates 713 and 723 may be located on the resistive change layers 715 and 725 (e.g., on the upper or lower parts of the resistive change layers 715 and 725). Gate oxide layers 714 and 724 may be formed between the resistive change layers 715 and 725 and the gates 713 and 723. In addition, sources 711 and 721 and drains 712 and 722 may be formed on the resistive change layers 715 and 725 and may be spaced apart from each other. The nonvolatile memory elements 710 and 720 may include a synapse 30 and may include gates 713 and 723 and drains 712 and 722 connected to the presynaptic neuron 10 and the postsynaptic neuron 20, respectively.

[0076] Hereinafter, it is assumed that an off-voltage is applied to the gates 713 and 723 when the resistance change layers 715 and 725 are irradiated with light, and a detailed description of this will be given later with reference to FIG.

[0077] The resistance values ​​of the resistance change layers 715 and 725 may be changed based on the illumination of light irradiated onto the resistance change layers 715 and 725, and may be maintained at the changed resistance values.

[0078] Specifically, when light is irradiated onto the variable resistance layers 715, 725, charges (electrons or holes) are trapped in defects inside the variable resistance layers 715, 725. When charges are trapped in the defects inside the variable resistance layers 715, 725, the resistance values ​​of the variable resistance layers 715, 725 are changed, and thereafter, even if the variable resistance layers 715, 725 are no longer irradiated with light, the resistance values ​​of the variable resistance layers 715, 725 are maintained at the changed value.

[0079] As the illuminance of light irradiated to the variable resistance layers 715, 725 increases, the amount of decrease in the resistance value of the variable resistance layers 715, 725 may increase. Specifically, as the illuminance of light irradiated to the variable resistance layers 715, 725 increases, the amount of charge trapped in defects inside the variable resistance layers 715, 725 may increase. As the amount of charge trapped inside the variable resistance layers 715, 725 increases, the resistance value of the variable resistance layers 715, 725 decreases.

[0080] In one embodiment, the light irradiated to the variable resistance layers 715, 725 is also light in the visible light range. The variable resistance layers 715, 725 are formed of a material described below, so that even if the variable resistance layers 715, 725 are irradiated with light in the visible light range, not high-energy light such as UV (ultra violet), the resistance values ​​of the variable resistance layers 715, 725 can be changed.

[0081] In one embodiment, the variable resistance layers 715 and 725 are formed of a 2D (2 Dimension) material. The variable resistance layers 715 and 725 may be formed of a single layer of a 2D material or a multi-layer of a 2D material. For example, the variable resistance layers 715 and 725 may include at least one of a Transition Metal Dichalcogenide (TMD), black phosphorus, silicene, and / or graphene. The TMD may be, for example, MoS 2 , MoSe 2 , MoTe 2 , W.S. 2 , WSe 2 , W.T.e. 2 , TaS2 , TaSe 2 , TiS 2 , TiSe 2 , ZrS 2 , ZrSe 2 , HfS 2 , HfSe 2 , SnS 2 , SnSe 2 , GeS 2 , GeSe 2 , GaS 2 , GaSe 2 , GaSe, GaTe, InSe, In 2 Se 3 , Bi 2 S 3 , Bi 2 Se 3 and Bi 2 Te 3 may include at least one of the following:

[0082] In another embodiment, the resistive layers 715 and 725 may be formed of a three-dimensional (3D) material, for example, the resistive layers 715 and 725 may include at least one of germanium, silicon, III-V semiconductors, and / or IGZO.

[0083] In one embodiment, the gate oxide layers 714, 724 are made of a single layer, for example, a single layer of Aluminum Oxide.

[0084] In another embodiment, the gate oxide layer 714, 724 is a multi-layer. The multi-layer gate oxide layer 714, 724 may include a charge trapping layer. For example, the multi-layer gate oxide layer 714, 724 may include a charge trapping layer between two aluminum oxide layers. The charge trapping layer may include, but is not limited to, hafnium oxide or silicon nitride.

[0085] 7A, a non-active memory element 710 using a back-gate 713 is illustrated. The back-gate 713 may be located below a resistive layer 715. For example, the back-gate 713 may be implemented using any suitable technology, such as a silicon on insulator (SOI) substrate.

[0086] The gate oxide layer 714 is located underneath the resistive change layer 715 and may be located between the resistive change layer 715 and the back gate 713 .

[0087] 7B, there is shown an inactive memory element 720 using a transparent conducting electrode (TCE) gate 723. The TCE gate 723 is located on top of a resistive layer 725. In FIGS. 7A and 7B, "top" and "bottom" refer to the location of the gate relative to a light source.

[0088] Light is irradiated onto the variable resistance layer 725 through the top of the variable resistance layer 725, so that the light hits the TCE gate 723 before the variable resistance layer 725. The inactive memory element 720 utilizes the TCE gate 723 through which light passes, so that the light reaches the variable resistance layer 725 through the top of the variable resistance layer 725.

[0089] A gate oxide layer 724 is located on top of the resistive change layer 725 and between the resistive change layer 725 and the TCE gate 723 .

[0090] FIG. 8 is a diagram illustrating a phenomenon in which the resistance value of a nonvolatile memory device according to an embodiment differs before and after light irradiation.

[0091] The non-volatile memory element may include a variable resistance layer. A gate is located on an upper or lower part of the variable resistance layer. A gate oxide layer is formed between the variable resistance layer and the gate. In addition, a source and a drain may be formed on the variable resistance layer and spaced apart from each other.

[0092] When an off voltage is applied to the gate of the nonvolatile memory device, the nonvolatile memory device operates as a phototransistor and an element having memory characteristics. In the following description, it is assumed that the nonvolatile memory device is an NMOS, but it is obvious to those skilled in the art that the nonvolatile memory device can be realized as various types of FETs (Field Effect Transistors).

[0093] A first graph 810 shows a gate voltage V G The current I detected from the source of the nonvolatile memory element by S Graph showing the above.

[0094] A second graph 820 shows the gate voltage V G The current I detected from the source of the nonvolatile memory element by S Graph showing the above.

[0095] In the first graph 810 and the second graph 820, a predetermined voltage V D is applied.

[0096] When charges are trapped in defects in the resistance change layer of a non-volatile memory element, the gate voltage V G Even if the off-state voltage is S can be detected.

[0097] When light is irradiated onto the variable resistance layer of the non-volatile memory device, more charges may be trapped in defects, thereby decreasing the resistance of the variable resistance layer. Even if light is no longer irradiated onto the variable resistance layer, the resistance of the variable resistance layer may be maintained at the decreased value.

[0098] Referring to the first graph 810, when an off voltage is applied to the gate of the nonvolatile memory device, the current detected from the source is I1 It is.

[0099] Referring to the second graph 820 showing the nonvolatile memory element after light is irradiated, when an off voltage is applied to the gate of the nonvolatile memory element, the current detected from the source is I 1 From I 2 When light is irradiated onto the variable resistance layer of the nonvolatile memory element, the resistance of the variable resistance layer decreases, and the current detected from the source of the nonvolatile memory element increases. Even if light is no longer irradiated onto the variable resistance layer of the nonvolatile memory element, the resistance of the variable resistance layer is maintained at the changed value, and when an off voltage is applied to the gate of the nonvolatile memory element, the current detected from the source also increases. 2 can be held in

[0100] In one embodiment, as the illuminance of light irradiated to the variable resistance layer of the non-volatile memory element increases, the charge trapped in the variable resistance layer increases, and the resistance value of the variable resistance layer decreases. As a result, the current detected from the source of the non-volatile memory element is I 2 It may increase even further.

[0101] Meanwhile, when an on-voltage equal to or greater than a critical value is applied to the gate of the nonvolatile memory device, the resistance value of the variable resistance layer of the nonvolatile memory device can be reset (rested). For example, to reset the resistance value of the variable resistance layer, a voltage of 7V is applied to the gate for 10 seconds.

[0102] Specifically, when light is irradiated onto the resistance change layer of the nonvolatile memory element, the source current becomes I 1 From I 2 If the gate of a non-volatile memory device is on-voltage above the critical value, the source current will be I 1 From I 2 may decrease again to

[0103] 9A and 9B are exemplary diagrams illustrating a process of storing an image using a crossbar array including a plurality of non-volatile memory devices and acquiring the stored image according to an embodiment.

[0104] In Figures 9A and 9B, it is assumed that the image 910 has a size of 4x4 and the crossbar array 900 has a size of 4x4, but a person of ordinary skill in the art would understand that the sizes of the image 910 and the crossbar array 900 can be varied in various ways.

[0105] 9A and 9B, the non-volatile memory elements are represented as synaptic positions a and b where rows and columns of the crossbar array 900 intersect.

[0106] Referring to FIG. 9A, a crossbar array 900 including multiple non-volatile memory elements can be used to store images.

[0107] To store an image using the crossbar array 900, an off voltage is applied to the gates of the non-volatile memory elements, and a drain voltage V D is applied.

[0108] In order to change the resistance value of the resistance change layer of each of the nonvolatile memory elements, light having an illuminance corresponding to the image 910 is irradiated onto each of the nonvolatile memory elements.

[0109] Specifically, a plurality of pixels P included in the image 910 11 ~P 14 , P 21 ~P 24 , P 31 ~P 34 , P 41 ~P 44 A light of a corresponding intensity is irradiated onto each of the non-volatile memory elements. 11The non-volatile memory element (1, 1) is irradiated with light of an intensity corresponding to P of the image 910. 21 The non-volatile memory element (2, 1) is irradiated with light of an intensity corresponding to P of the image 910. 32 The non-volatile memory element (3, 2) is irradiated with light of an intensity corresponding to P of the image 910. 44 The non-volatile memory element (4, 4) is irradiated with light having an illuminance corresponding to the above.

[0110] The brightness of each of the pixels included in the image 910 may be different from one another, and therefore the illuminance of the light irradiated to each of the nonvolatile memory elements may be different from one another. As a result, the degree to which the resistance value of the resistance change layer of each of the nonvolatile memory elements is changed may be different from one another. Even if the nonvolatile memory elements are no longer irradiated with light, the resistance value of the resistance change layer may be maintained at the changed value.

[0111] In other words, the resistance value of each of the non-volatile memory elements is changed depending on the brightness of each of the pixels included in the image 910, and the resistance values ​​of the non-volatile memory elements are maintained at the changed values ​​even if light is no longer irradiated, so that the image 910 is stored in the crossbar array 900.

[0112] On the other hand, R displayed on the crossbar array 900 11 ~R 14 , R 21 ~R 24 , R 31 ~R 34 , R 41 ~R 44 indicates the resistance value of each of the multiple nonvolatile memory elements.

[0113] Referring to FIG. 9B, a stored image can be obtained using a crossbar array 900 that includes a plurality of non-volatile memory devices.

[0114] In order to obtain an image stored in the crossbar array 900, a gate-off voltage may be applied to each row of the crossbar array 900. In the crossbar array 900 of FIG 9B, the non-volatile memory elements to which the gate-off voltage is applied are represented by circles.

[0115] Specifically, pixel P 11 ~P 14 To achieve this, a gate-off voltage may be applied to the first row 901a of the crossbar array 900. At this time, a gate-on voltage may be applied to the second through fourth rows 901b to 901d.

[0116] The source current I obtained by each column of the crossbar array 900 S11 ~I S14 The resistance values ​​R of the nonvolatile memory elements (1, 1) to (1, 4) are 11 ~R 14 On the other hand, the resistance value R of the non-volatile memory element is 11 ~R 14 is the pixel P in the first row of the image 910. 11 ~P 14 Therefore, the source current I obtained for each column of the crossbar array 900 is S11 ~I S14 Pixel P in the first row of image 910 is 11 ~P 14 can be obtained.

[0117] In a similar manner, the pixels in the second through fourth rows 901b-901d of the crossbar array 900 can be sequentially obtained by applying a gate-off voltage to each of the second through fourth rows 901b-901d and applying a gate-on voltage to the remaining rows.

[0118] In one embodiment, a color image can be obtained from the crossbar array 900 by sequentially disposing color filters on the crossbar array 900 .

[0119] For example, a color image can be obtained from the crossbar array 900 using three color filters: Red, Green, and Blue.

[0120] Specifically, a red color filter may be disposed on the crossbar array 900, and then light having an intensity corresponding to each of the pixels included in the color image may be irradiated onto each of the non-volatile memory elements. A gate-off voltage may be applied to each row of the crossbar array 900, and a source current may be obtained for each column of the crossbar array 900, thereby obtaining a red image.

[0121] After applying a gate-on voltage to the crossbar array 900 to reset it, the above-mentioned operation is repeated using the green and blue color filters to obtain a green image and a blue image. After the red, green, and blue images are obtained, the three images are synthesized to obtain a final color image.

[0122] The crossbar array 900 including multiple non-volatile memory elements according to the present disclosure has photoconductivity (PC) properties and can be utilized in an imaging mode (storing / capturing images) due to such properties.

[0123] FIG. 10 is an exemplary diagram illustrating a process of performing a pooling operation of a neural network using a crossbar array including a plurality of non-volatile memory devices according to an embodiment.

[0124] 10, it is assumed that the image 1010 has a size of 8x8 and the crossbar array 1000 has a size of 16x16, but it will be understood by those of ordinary skill in the art that the sizes of the image 1010 and the crossbar array 1000 can be variously changed. For example, the image 1010 may be an image representing any one of the numbers "1" to "9", but is not limited thereto.

[0125] In one embodiment, a window 1011 is shifted by a stride interval on the image 1010. For example, the stride is preset. The size of the window 1011 is determined based on the size of the crossbar array 1000. In one embodiment, the size of the window 1011 is determined based on the number of rows in the crossbar array 1000. For example, if the number of rows in the crossbar array 1000 is 16, the size of the window 1011 is also 4x4.

[0126] In the following, it is assumed that the window 1011 is shifted by a "1 stride" interval and the size of the window 1011 is 4 x 4. However, the shift interval and size of the window 1011 can be variously modified.

[0127] At each location on the image 1010, the window 1011 may include multiple pixels. For example, the window 1011 may include P 11 ~P 14 , P 21 ~P 24 , P 31 ~P 34 and P 41 ~P 44 The window 1011 may include pixels P 12 ~P 15 , P 22 ~P 25 , P 32 ~P 35 and P 42 ~P 45 The pixel may include pixels.

[0128] The pixels included in the window 1011 are irradiated with light of a corresponding intensity for each column of the crossbar array 1000. For example, the pixels P 11 ~P 14 , P 21 ~P 24 , P 31 ~P 34 and P 41 ~P 44 is irradiated onto the first column 1002a of the crossbar array 1000. That is, light with an illuminance corresponding to each of the 16 pixels included in the window 1011 at the first position is irradiated onto each of the 16 non-volatile memory elements included in the first column 1002a.

[0129] In a similar manner, light with an illuminance corresponding to a plurality of pixels contained in the window 1011 at the nth position is also irradiated onto the nth column of the crossbar array 1000 .

[0130] A gate-off voltage is applied to the first through sixteenth rows 1001a-1001p of the crossbar array 1000. In addition, drain voltages V0-V15 are applied to the first through sixteenth rows 1001a-1001p of the crossbar array 1000. The drain voltages V0-V15 are also masks used in a pooling operation.

[0131] A pooling operation is performed by acquiring source currents for each column of the crossbar array 1000. Specifically, a first-1 source current I S11 is a number of pixels P included in the window 1011 at the first position. 11 ~P 14 , P 21 ~P 24 , P 31 ~P 34 and P 41 ~P 44 This is also the pooling result for

[0132] In a similar manner, the first-second source current I 1002 b to the first-fifth source current I 1002 e are obtained from the second column 1002 b to the fifth column 1002 e. S12 ~I S15 is also the pooling result for multiple pixels included in the window 1011 at the first position to the fifth position.

[0133] Meanwhile, since the windows 1011 are located at a total of 25 positions on the image 1010, the pooling operation of the neural network can be completed by obtaining the pooling results for the multiple pixels contained in the windows 1011 at the first position to the 25th position through the above-mentioned method.

[0134] The crossbar array 1000 including multiple non-volatile memory elements according to the present disclosure performs vector-matrix operations (e.g., pooling operations), and using such characteristics, the crossbar array 1000 can be utilized for in-memory computing.

[0135] FIG. 11 is an exemplary diagram illustrating a process of performing a convolution operation of a neural network using a crossbar array including a plurality of non-volatile memory devices according to an embodiment.

[0136] A plurality of weights including a specific layer of a neural network are stored in the crossbar array 1000. A plurality of non-volatile memory elements of the crossbar array 1000 are irradiated with light having an illuminance corresponding to each of the plurality of weights including the specific layer, thereby storing the plurality of weights in the crossbar array 1000. A specific method is omitted here because it overlaps with the contents of FIG. 9A.

[0137] In one embodiment, a fully-connected convolution operation can be performed using the crossbar array 1000. In Fig. 11, a fully-connected convolution operation is performed to recognize the image 1010 of Fig. 10. For example, the crossbar array 1000 is used to perform a fully-connected convolution operation to determine which number among the numbers 1 to 9 the image 1010 corresponds to.

[0138] First, in order to perform a fully connected convolution operation, the crossbar array 1000 is reset.

[0139] The drain voltage of the crossbar array 1000 corresponds to the input value of the fully connected layer. The 1-1 source current to the 1-5 source current I S11 ~I S15 corresponds to the input value of the fully connected layer.

[0140] Specifically, the 1-1 source current to the 1-5 source current I S11 ~I S15 is the first drain voltage to the fifth drain voltage V D11 ~V D15 In addition, the first drain voltage to the fifth drain voltage V D11 ~V D15 They are applied to the first through fifth rows 1001A through 1001e, respectively.

[0141] An image 1010 is recognized by acquiring source currents for each column of the crossbar array 1000. Specifically, a 2-1 source current I 11 indicates the probability that the image 1010 corresponds to the digit "1." Also, the 2-2nd source current I 12 ~I 19 Each indicates the probability that the image 1010 corresponds to the digits "2" through "9."

[0142] On the other hand, the windows 1011 are located at a total of 25 positions on the image 1010, and the 2-1 source current to the 2-9 source current I 11 ~I 19 is merely the result of all the combination operations for the windows 1011 at the first position to the fifth position. In other words, by obtaining the results of all the combination operations for the windows 1011 at the remaining positions on the image 1010, the image 1010 can be finally recognized.

[0143] By repeating the above process, the 2-1st source current to the 2-9th source current I for the 1st column to the 9th column 1002A to 1002i are generated from the crossbar array 1000 based on the 25 source currents corresponding to the windows 1011 at the 1st position to the 25th position. 11 ~I 19 can be obtained.

[0144] The 2-1st source current to the 2-9th source current I obtained from the 1st column to the 9th column 1002a to 1002i of the crossbar array 1000 are 11 ~I 19 can indicate the probability that the image 1010 corresponds to the digits "1" to "9". The image 1010 is ultimately recognized as the digit with the highest probability value among the digits "1" to "9". For example, the 2-1st source current I 11 If the value of is the largest, then the image 1010 will also be finally recognized as the number "1."

[0145] Meanwhile, a plurality of weights included in a specific layer of a neural network are updated as the learning of the neural network progresses. When the weights are updated, the crossbar array 1000 is reset, and then light having an illumination intensity corresponding to each of the updated weights is irradiated onto each of the non-volatile memory elements, thereby storing the updated weights in the crossbar array 1000. The crossbar array 1000 can be widely used in the learning and inference processes of neural networks.

[0146] The crossbar array 1000 including a plurality of non-volatile memory elements according to the present disclosure performs vector-matrix operations, and using such characteristics, the crossbar array 1000 can also be utilized in learning and inference processes for image recognition.

[0147] In one embodiment, a crossbar array utilized in an imaging mode (image storage / acquisition) is reset and then utilized in a recognition mode (neural network training / inference), such that one crossbar array can be utilized in both the imaging mode and the recognition mode.

[0148] 12 is a flow chart illustrating a method of performing a predetermined operation using a crossbar array according to one embodiment. Since the method of performing a predetermined operation illustrated in FIG. 12 is related to the embodiment described in the drawings, the contents described above in the description of the drawings also apply to the method of FIG. 12 even if the contents are omitted below.

[0149] The crossbar array described below may include a plurality of non-volatile memory elements. The non-volatile memory elements may include a resistive layer. A gate is located on the top or bottom of the resistive layer. A gate oxide layer is formed between the resistive layer and the gate. In addition, a source and a drain may be formed on the resistive layer and spaced apart from each other.

[0150] Referring to FIG. 12, in operation 1210, the processor may apply an off voltage to a gate of each of a plurality of non-volatile memory elements.

[0151] When an off voltage is applied to the gate of the nonvolatile memory element, the nonvolatile memory element can operate as a phototransistor and an element having memory characteristics. The gate off voltage may be -6V, but is not limited thereto.

[0152] On the other hand, when an on-voltage is applied to the gate of the non-volatile memory device, the non-volatile memory device may be reset.

[0153] In step 1220, the processor may irradiate each of the plurality of non-volatile memory elements with light of an illumination intensity corresponding to each of the plurality of elements to change a resistance value of the resistive layer of each of the plurality of non-volatile memory elements.

[0154] The resistance value of the variable resistance layer may be changed based on the illuminance of light irradiated to the variable resistance layer and may be maintained at the changed resistance value. Specifically, when the variable resistance layer is irradiated with light, charges are trapped in defects within the variable resistance layer, changing the resistance value of the variable resistance layer. Thereafter, even if the variable resistance layer is no longer irradiated with light, the resistance value of the variable resistance layer may be maintained at the changed value.

[0155] The greater the illuminance of the light irradiated to the resistance change layer, the greater the decrease in the resistance value of the resistance change layer. Specifically, the greater the illuminance of the light irradiated to the resistance change layer, the greater the charge trapped in defects within the resistance change layer. As the charge trapped within the resistance change layer increases, the resistance value of the resistance change layer decreases.

[0156] In one embodiment, the resistance change layer may be formed of a 2D material, for example, the resistance change layer may be formed of at least one selected from the group consisting of Transition Metal Dichalcogenides (TMDs), black phosphorus, and graphene.

[0157] The variable resistance layer may be formed of a 3D material, for example, the variable resistance layer may include at least one selected from the group consisting of germanane, silicene, III-V, and IGZO.

[0158] In step 1230, the processor may perform a predetermined operation by applying a gate-off voltage to at least one row of the crossbar array and obtaining a source current by column of the crossbar array.

[0159] In one embodiment, the processor may control how to perform a given operation using the crossbar array described above. The processor may use the crossbar array to capture an image, where the elements are also pixels contained in the image.

[0160] Light having an intensity corresponding to each of a plurality of pixels included in an image is irradiated onto each of a plurality of non-volatile memory elements. The processor applies a gate-off voltage to each row of the crossbar array and obtains a source current to each column of the crossbar array, thereby obtaining an image.

[0161] Also, by sequentially arranging color filters on the crossbar array, a color image can be obtained from the crossbar array.

[0162] In one embodiment, the processor may use a crossbar array to perform the computation of a neural network, where the elements are also the weights included in a particular layer of the neural network.

[0163] A light having an illuminance corresponding to each of a plurality of weights included in a specific layer of the neural network is irradiated onto each of the plurality of non-volatile memory elements. The processor can perform a neural network operation by applying a gate-off voltage to at least one row of the crossbar array and acquiring a source current for each column of the crossbar array. For example, the neural network operation may include, but is not limited to, a pooling operation, a convolution operation, and a fully connected convolution operation.

[0164] In the present disclosure, the crossbar array can be used to store images or to obtain stored images from the crossbar array, and the crossbar array can be used to perform neural network operations to recognize images.

[0165] FIG. 13 is a block diagram illustrating a memory system according to one embodiment.

[0166] 13, memory system 1300 may include a processor 1310 and at least one crossbar array 1320. The processor 1310 performs control operations for the crossbar array 1320, and as an example, the processor 1310 may perform data storage, read, and erase operations for the crossbar array 1320 by providing an address ADD and a command CMD to the crossbar array 1320. In addition, data for storage and reading is transmitted and received between the processor 1310 and the crossbar array 1320.

[0167] The crossbar array 1321 may include a plurality of non-volatile memory elements disposed at intersections between a plurality of rows and a plurality of columns. In one embodiment, the non-volatile memory elements may include a resistive layer. A gate may be located on an upper or lower portion of the resistive layer. A gate oxide layer may be formed between the resistive layer and the gate. In addition, a source and a drain may be formed on the resistive layer and spaced apart from each other.

[0168] The processor 1310 may include a save / read control unit 1311, a voltage control unit 1312, and a data discrimination unit 1313. However, the components included in the processor 1310 are merely examples, and it will be obvious to those skilled in the art that some components may be removed or other components may be added.

[0169] The store / read controller 1311 may generate an address ADD and a command CMD for performing data store, read, and erase operations on the crossbar array 1321. In addition, the voltage controller 1312 may generate a voltage control signal for controlling at least one voltage level used in the crossbar array 1320. As an example, the voltage controller 1312 may generate a voltage control signal for controlling a voltage level applied to a row of the crossbar array 1321 in order to read data from the crossbar array 1321 or store data in the crossbar array 1321.

[0170] Meanwhile, the data discrimination unit 1313 performs a discrimination operation on data read from the crossbar array 1320. For example, the data discrimination unit 1313 discriminates data read from the crossbar array 1321 and discriminates whether each of the nonvolatile memory elements included in the crossbar array 1321 is in an on state or an off state. As an operation example, when data is stored in the crossbar array 1321, the data discrimination unit 1313 discriminates the data states of the nonvolatile memory elements included in the crossbar array 1321 using a predetermined read voltage, thereby discriminating whether data storage has been completed normally in the nonvolatile memory elements.

[0171] The present embodiment may also be embodied in the form of a recording medium including instructions executable by a computer, such as a program module executed by the computer. A computer-readable medium is any available medium that can be accessed by a computer, and includes both volatile and non-volatile media, and both separate and non-separate media. Also, a computer-readable medium includes both computer storage media and communication media. A computer recording medium includes both volatile and non-volatile, separate and non-separate media embodied by any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. A communication medium typically includes computer-readable instructions, data structures, other data in a modulated data signal, such as a program module, or other transmission mechanism, and includes any information transmission medium.

[0172] In this specification, a "unit" may be a hardware component such as a processor or a circuit, and / or a software component executed by a hardware component such as a processor.

[0173] The above description of the present specification is for illustrative purposes only, and a person having ordinary skill in the art to which the contents of the present specification belong will understand that the present invention can be easily modified into other specific forms without changing the technical idea or essential features of the present invention. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. For example, each component described as being a single type may be implemented in a distributed form, and similarly, each component described as being distributed may be implemented in a combined form.

[0174] The scope of the present embodiments is indicated by the claims set forth below rather than the above detailed description, and should be interpreted to include all modifications and variations derived from the meaning and scope of the claims and their equivalent concepts. [Explanation of symbols]

[0175] 2. Neural Networks 3. Layer 10 Presynaptic neurons 12 Row Wiring 12A~12D 1st row wiring~4th row wiring 20 Postsynaptic Neurons 22 Column wiring 22A~22D 1st column wiring~4th column wiring 30 Synapse 410 Matrix X 411 Matrix W 412 Matrix Y 420 Voltage 421 Conductance 422 Current 500 Crossbar Array 501 Voltage 502 Conductance 503 Current 510 Input feature maps 520 DAC(Digital Analog Converter) 530 ADC(Analog Digital Converter) 540 Activation Unit 550 Other Crossbar Arrays 600 Crossbar Array 610 Input feature maps 611 Subfeature Maps 710, 720 Non-volatile memory element 711, 721 Source 712, 722 Drain 713 Gate (Back Gate) 723 Gate (Transparent Conductive Electrode (TCE) Gate) 714, 724 Gate oxide layer 715, 725 Resistance change layer 810 Graph 1 820 Graph 2 900 Crossbar Array 901a~901d 1st~4th row 910 Images 1000 Crossbar Array 1001a~1001p 1st~16th row 1002a~1002i 1st~9th columns 1010 Images 1011 Window 1300 Memory System 1310 Processor 1311 Save / Read Control Unit 1312 Voltage control section 1313 Data discrimination section 1320, 1321 Crossbar Array FM1 1st feature map FM2 2nd Feature Map

Claims

1. A crossbar array for acquiring images, comprising: the crossbar array includes non-volatile memory elements; Each of the non-volatile memory elements comprises: A resistance switching layer having a resistance value; A gate on the resistance change layer; a gate oxide layer between the resistance change layer and the gate; a source and a drain spaced apart from each other on the resistance change layer; The resistance change layer of each of the nonvolatile memory elements changes the resistance value based on the illumination of light irradiated to the resistance change layer, and maintains the changed resistance value even when the light is not irradiated, the crossbar array is configured to acquire an image based on a resistance value of the resistance change layer according to an illuminance of light irradiated on the resistance change layer of each of the non-volatile memory elements; The illuminated light corresponds to a plurality of pixels contained in the image. A crossbar array.

2. The gate is The crossbar array of claim 1 , wherein the resistive change layer is provided with a transparent conducting electrode (TCE) gate on top of the resistive change layer through which the irradiated light passes.

3. The resistance change layer is The crossbar array of claim 1 , comprising 2D materials, the 2D materials comprising at least one of Transition Metal Dichalcogenides (TMD), silicene, black phosphorus, or graphene.

4. The crossbar array according to claim 3 , wherein the variable resistance layer is made of a single layer.

5. The crossbar array of claim 3 , wherein the variable resistance layer is made up of multiple layers.

6. The resistance change layer is The crossbar array of claim 1 , comprising a 3D material, the 3D material comprising at least one of germanane, silicon, a III-V semiconductor, or IGZO.

7. The crossbar array of claim 1 , wherein the gate oxide layer is a multi-layer including a charge trapping layer.

8. 2. The crossbar array of claim 1, wherein the resistance value of the variable resistance layer decreases as the illuminance of light irradiated onto the variable resistance layer increases when an off-voltage is applied to the gate.

9. The crossbar array of claim 1 , wherein the resistance change layer resets the resistance value when an on-voltage is applied to the gate.

10. 1. A method of performing an operation using a crossbar array including a plurality of non-volatile memory devices, comprising: applying an off voltage to a gate of each of the nonvolatile memory devices; changing a resistance value of each of the resistance change layers of the nonvolatile memory elements by irradiating the nonvolatile memory elements with light having an illuminance corresponding to a plurality of elements, and maintaining the changed resistance value even when the light is not irradiated; applying a gate-off voltage to at least one row of the crossbar array; obtaining a source current for each column of the crossbar array; the emitted light corresponds to a plurality of pixels in an image; The method further includes obtaining the image by applying a gate-off voltage to each row of the crossbar array and obtaining a source current to each column of the crossbar array.

11. The irradiating step includes: sequentially disposing a plurality of color filters on the non-volatile memory elements; and irradiating the light onto each of the non-volatile memory elements; The operation includes: obtaining intermediate images corresponding to the color filters by applying a gate-off voltage to each row of the crossbar array and obtaining source currents to each column of the crossbar array; and combining the intermediate images to obtain a color image.

12. The irradiating step includes: irradiating the non-volatile memory elements with light having an illuminance corresponding to a number of weights included in a specific layer of a neural network; The operation includes: and performing a vector matrix operation on the specific layer by applying a gate-off voltage to at least one row of the crossbar array and acquiring a source current by column of the crossbar array.

13. The irradiating step includes:

11. The method of claim 10, further comprising shifting a window by a stride interval on an image, and irradiating light of an illuminance corresponding to a plurality of elements included in the window by column of the crossbar array.

14. 1. A method for recognizing an image using a crossbar array including a plurality of non-volatile memory elements, comprising: applying an off voltage to a gate of each of the nonvolatile memory devices; shifting a window by a stride interval on the image and irradiating light of an illuminance corresponding to the image included in the window for each column of the crossbar array; applying a gate-off voltage to at least one row of the crossbar array and obtaining a first source current for each column of the crossbar array to perform a pooling operation; applying an on-voltage to a gate of each of the nonvolatile memory elements to reset the nonvolatile memory elements; applying an off voltage to a gate of each of the reset nonvolatile memory devices; changing a resistance value of each of the resistance change layers of the nonvolatile memory elements by irradiating the nonvolatile memory elements with light having an illuminance corresponding to a plurality of weights including a specific layer of a neural network, and maintaining the changed resistance value even when the light is not irradiated; applying a voltage corresponding to the first source current as a drain voltage to at least one row of the crossbar array, and obtaining a second source current for each column of the crossbar array; A step of performing a fully-connected convolution operation by and recognizing the image based on the second source current.

15. A computer-readable recording medium having recorded thereon a program for causing a computer to carry out the method according to any one of claims 10 to 13.

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